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11 * The above copyright notice and this permission notice (including the next
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24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded it's state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include <linux/err.h>
93 /* This is a HW constraint. The value below is the largest known requirement
94 * I've seen in a spec to date, and that was a workaround for a non-shipping
95 * part. It should be safe to decrease this, but it's more future proof as is.
97 #define CONTEXT_ALIGN (64<<10)
99 static struct i915_hw_context *
100 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
101 static int do_switch(struct i915_hw_context *to);
103 static int get_context_size(struct drm_device *dev)
105 struct drm_i915_private *dev_priv = dev->dev_private;
109 switch (INTEL_INFO(dev)->gen) {
111 reg = I915_READ(CXT_SIZE);
112 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
115 reg = I915_READ(GEN7_CXT_SIZE);
117 ret = HSW_CXT_TOTAL_SIZE(reg) * 64;
119 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
128 static void do_destroy(struct i915_hw_context *ctx)
131 idr_remove(&ctx->file_priv->context_idr, ctx->id);
133 drm_gem_object_unreference(&ctx->obj->base);
137 static struct i915_hw_context *
138 create_hw_context(struct drm_device *dev,
139 struct drm_i915_file_private *file_priv)
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 struct i915_hw_context *ctx;
145 ctx = kmalloc(sizeof(*ctx), M_DRM, M_WAITOK | M_ZERO);
147 return ERR_PTR(-ENOMEM);
149 ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size);
150 if (ctx->obj == NULL) {
152 DRM_DEBUG_DRIVER("Context object allocated failed\n");
153 return ERR_PTR(-ENOMEM);
156 if (INTEL_INFO(dev)->gen >= 7) {
157 ret = i915_gem_object_set_cache_level(ctx->obj,
163 /* The ring associated with the context object is handled by the normal
164 * object tracking code. We give an initial ring value simple to pass an
165 * assertion in the context switch code.
167 ctx->ring = &dev_priv->ring[RCS];
169 /* Default context will never have a file_priv */
170 if (file_priv == NULL)
173 ctx->file_priv = file_priv;
176 if (idr_pre_get(&file_priv->context_idr, GFP_KERNEL) == 0) {
178 DRM_DEBUG_DRIVER("idr allocation failed\n");
182 ret = idr_get_new_above(&file_priv->context_idr, ctx,
183 DEFAULT_CONTEXT_ID + 1, &id);
199 static inline bool is_default_context(struct i915_hw_context *ctx)
201 return (ctx == ctx->ring->default_context);
205 * The default context needs to exist per ring that uses contexts. It stores the
206 * context state of the GPU for applications that don't utilize HW contexts, as
207 * well as an idle case.
209 static int create_default_context(struct drm_i915_private *dev_priv)
211 struct i915_hw_context *ctx;
214 DRM_LOCK_ASSERT(dev_priv->dev);
216 ctx = create_hw_context(dev_priv->dev, NULL);
220 /* We may need to do things with the shrinker which require us to
221 * immediately switch back to the default context. This can cause a
222 * problem as pinning the default context also requires GTT space which
223 * may not be available. To avoid this we always pin the
226 dev_priv->ring[RCS].default_context = ctx;
227 ret = i915_gem_object_pin(ctx->obj, CONTEXT_ALIGN, false, false);
231 ret = do_switch(ctx);
235 DRM_DEBUG_DRIVER("Default HW context loaded\n");
239 i915_gem_object_unpin(ctx->obj);
245 void i915_gem_context_init(struct drm_device *dev)
247 struct drm_i915_private *dev_priv = dev->dev_private;
249 if (!HAS_HW_CONTEXTS(dev)) {
250 dev_priv->hw_contexts_disabled = true;
254 /* If called from reset, or thaw... we've been here already */
255 if (dev_priv->hw_contexts_disabled ||
256 dev_priv->ring[RCS].default_context)
259 dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
261 if (dev_priv->hw_context_size > (1<<20)) {
262 dev_priv->hw_contexts_disabled = true;
266 if (create_default_context(dev_priv)) {
267 dev_priv->hw_contexts_disabled = true;
271 DRM_DEBUG_DRIVER("HW context support initialized\n");
274 void i915_gem_context_fini(struct drm_device *dev)
276 struct drm_i915_private *dev_priv = dev->dev_private;
278 if (dev_priv->hw_contexts_disabled)
281 /* The only known way to stop the gpu from accessing the hw context is
282 * to reset it. Do this as the very last operation to avoid confusing
283 * other code, leading to spurious errors. */
284 intel_gpu_reset(dev);
286 i915_gem_object_unpin(dev_priv->ring[RCS].default_context->obj);
288 do_destroy(dev_priv->ring[RCS].default_context);
291 static int context_idr_cleanup(int id, void *p, void *data)
293 struct i915_hw_context *ctx = p;
295 BUG_ON(id == DEFAULT_CONTEXT_ID);
302 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
304 struct drm_i915_file_private *file_priv = file->driver_priv;
306 mutex_lock(&dev->struct_mutex);
307 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
308 idr_destroy(&file_priv->context_idr);
309 mutex_unlock(&dev->struct_mutex);
312 static struct i915_hw_context *
313 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
315 return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id);
319 mi_set_context(struct intel_ring_buffer *ring,
320 struct i915_hw_context *new_context,
325 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
326 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
327 * explicitly, so we rely on the value at ring init, stored in
328 * itlb_before_ctx_switch.
330 if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
331 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
336 ret = intel_ring_begin(ring, 6);
340 if (IS_GEN7(ring->dev))
341 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
343 intel_ring_emit(ring, MI_NOOP);
345 intel_ring_emit(ring, MI_NOOP);
346 intel_ring_emit(ring, MI_SET_CONTEXT);
347 intel_ring_emit(ring, new_context->obj->gtt_offset |
349 MI_SAVE_EXT_STATE_EN |
350 MI_RESTORE_EXT_STATE_EN |
352 /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */
353 intel_ring_emit(ring, MI_NOOP);
355 if (IS_GEN7(ring->dev))
356 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
358 intel_ring_emit(ring, MI_NOOP);
360 intel_ring_advance(ring);
365 static int do_switch(struct i915_hw_context *to)
367 struct intel_ring_buffer *ring = to->ring;
368 struct drm_i915_gem_object *from_obj = ring->last_context_obj;
372 BUG_ON(from_obj != NULL && from_obj->pin_count == 0);
374 if (from_obj == to->obj)
377 ret = i915_gem_object_pin(to->obj, CONTEXT_ALIGN, false, false);
381 /* Clear this page out of any CPU caches for coherent swap-in/out. Note
382 * that thanks to write = false in this call and us not setting any gpu
383 * write domains when putting a context object onto the active list
384 * (when switching away from it), this won't block.
385 * XXX: We need a real interface to do this instead of trickery. */
386 ret = i915_gem_object_set_to_gtt_domain(to->obj, false);
388 i915_gem_object_unpin(to->obj);
392 if (!to->obj->has_global_gtt_mapping)
393 i915_gem_gtt_bind_object(to->obj, to->obj->cache_level);
395 if (!to->is_initialized || is_default_context(to))
396 hw_flags |= MI_RESTORE_INHIBIT;
397 else if (WARN_ON_ONCE(from_obj == to->obj)) /* not yet expected */
398 hw_flags |= MI_FORCE_RESTORE;
400 ret = mi_set_context(ring, to, hw_flags);
402 i915_gem_object_unpin(to->obj);
406 /* The backing object for the context is done after switching to the
407 * *next* context. Therefore we cannot retire the previous context until
408 * the next context has already started running. In fact, the below code
409 * is a bit suboptimal because the retiring can occur simply after the
410 * MI_SET_CONTEXT instead of when the next seqno has completed.
412 if (from_obj != NULL) {
413 from_obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
414 i915_gem_object_move_to_active(from_obj, ring);
415 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
416 * whole damn pipeline, we don't need to explicitly mark the
417 * object dirty. The only exception is that the context must be
418 * correct in case the object gets swapped out. Ideally we'd be
419 * able to defer doing this until we know the object would be
420 * swapped, but there is no way to do that yet.
423 BUG_ON(from_obj->ring != ring);
424 i915_gem_object_unpin(from_obj);
426 drm_gem_object_unreference(&from_obj->base);
429 drm_gem_object_reference(&to->obj->base);
430 ring->last_context_obj = to->obj;
431 to->is_initialized = true;
437 * i915_switch_context() - perform a GPU context switch.
438 * @ring: ring for which we'll execute the context switch
439 * @file_priv: file_priv associated with the context, may be NULL
440 * @id: context id number
441 * @seqno: sequence number by which the new context will be switched to
444 * The context life cycle is simple. The context refcount is incremented and
445 * decremented by 1 and create and destroy. If the context is in use by the GPU,
446 * it will have a refoucnt > 1. This allows us to destroy the context abstract
447 * object while letting the normal object tracking destroy the backing BO.
449 int i915_switch_context(struct intel_ring_buffer *ring,
450 struct drm_file *file,
453 struct drm_i915_private *dev_priv = ring->dev->dev_private;
454 struct i915_hw_context *to;
456 if (dev_priv->hw_contexts_disabled)
459 if (ring != &dev_priv->ring[RCS])
462 if (to_id == DEFAULT_CONTEXT_ID) {
463 to = ring->default_context;
468 to = i915_gem_context_get(file->driver_priv, to_id);
473 return do_switch(to);
476 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
477 struct drm_file *file)
479 struct drm_i915_private *dev_priv = dev->dev_private;
480 struct drm_i915_gem_context_create *args = data;
481 struct drm_i915_file_private *file_priv = file->driver_priv;
482 struct i915_hw_context *ctx;
485 if (!(dev->driver->driver_features & DRIVER_GEM))
488 if (dev_priv->hw_contexts_disabled)
491 ret = i915_mutex_lock_interruptible(dev);
495 ctx = create_hw_context(dev, file_priv);
496 mutex_unlock(&dev->struct_mutex);
500 args->ctx_id = ctx->id;
501 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
506 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
507 struct drm_file *file)
509 struct drm_i915_gem_context_destroy *args = data;
510 struct drm_i915_file_private *file_priv = file->driver_priv;
511 struct i915_hw_context *ctx;
514 if (!(dev->driver->driver_features & DRIVER_GEM))
517 ret = i915_mutex_lock_interruptible(dev);
521 ctx = i915_gem_context_get(file_priv, args->ctx_id);
523 mutex_unlock(&dev->struct_mutex);
529 mutex_unlock(&dev->struct_mutex);
531 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);