1 /******************************************************************************
3 * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec)
5 *****************************************************************************/
7 /******************************************************************************
11 * Some or all of this work - Copyright (c) 1999 - 2020, Intel Corp.
12 * All rights reserved.
16 * 2.1. This is your license from Intel Corp. under its intellectual property
17 * rights. You may have additional license terms from the party that provided
18 * you this software, covering your right to use that party's intellectual
21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a
22 * copy of the source code appearing in this file ("Covered Code") an
23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the
24 * base code distributed originally by Intel ("Original Intel Code") to copy,
25 * make derivatives, distribute, use and display any portion of the Covered
26 * Code in any form, with the right to sublicense such rights; and
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
29 * license (with the right to sublicense), under only those claims of Intel
30 * patents that are infringed by the Original Intel Code, to make, use, sell,
31 * offer to sell, and import the Covered Code and derivative works thereof
32 * solely to the minimum extent necessary to exercise the above copyright
33 * license, and in no event shall the patent license extend to any additions
34 * to or modifications of the Original Intel Code. No other license or right
35 * is granted directly or by implication, estoppel or otherwise;
37 * The above copyright and patent license is granted only if the following
42 * 3.1. Redistribution of Source with Rights to Further Distribute Source.
43 * Redistribution of source code of any substantial portion of the Covered
44 * Code or modification with rights to further distribute source must include
45 * the above Copyright Notice, the above License, this list of Conditions,
46 * and the following Disclaimer and Export Compliance provision. In addition,
47 * Licensee must cause all Covered Code to which Licensee contributes to
48 * contain a file documenting the changes Licensee made to create that Covered
49 * Code and the date of any change. Licensee must include in that file the
50 * documentation of any changes made by any predecessor Licensee. Licensee
51 * must include a prominent statement that the modification is derived,
52 * directly or indirectly, from Original Intel Code.
54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source.
55 * Redistribution of source code of any substantial portion of the Covered
56 * Code or modification without rights to further distribute source must
57 * include the following Disclaimer and Export Compliance provision in the
58 * documentation and/or other materials provided with distribution. In
59 * addition, Licensee may not authorize further sublicense of source of any
60 * portion of the Covered Code, and must include terms to the effect that the
61 * license from Licensee to its licensee is limited to the intellectual
62 * property embodied in the software Licensee provides to its licensee, and
63 * not to intellectual property embodied in modifications its licensee may
66 * 3.3. Redistribution of Executable. Redistribution in executable form of any
67 * substantial portion of the Covered Code or modification must reproduce the
68 * above Copyright Notice, and the following Disclaimer and Export Compliance
69 * provision in the documentation and/or other materials provided with the
72 * 3.4. Intel retains all right, title, and interest in and to the Original
75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by
76 * Intel shall be used in advertising or otherwise to promote the sale, use or
77 * other dealings in products derived from or relating to the Covered Code
78 * without prior written authorization from Intel.
80 * 4. Disclaimer and Export Compliance
82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED
83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE
84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE,
85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT,
93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY
94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL
95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS
96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY
99 * 4.3. Licensee shall not export, either directly or indirectly, any of this
100 * software or system incorporating such software without first obtaining any
101 * required license or other approval from the U. S. Department of Commerce or
102 * any other agency or department of the United States Government. In the
103 * event Licensee exports any such software from the United States or
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
106 * compliance with all laws, regulations, orders, or other restrictions of the
107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor
108 * any of its subsidiaries will export/re-export any technical data, process,
109 * software, or service, directly or indirectly, to any country for which the
110 * United States government or any agency thereof requires an export license,
111 * other governmental approval, or letter of assurance, without first obtaining
112 * such license, approval or letter.
114 *****************************************************************************
116 * Alternatively, you may choose to be licensed under the terms of the
119 * Redistribution and use in source and binary forms, with or without
120 * modification, are permitted provided that the following conditions
122 * 1. Redistributions of source code must retain the above copyright
123 * notice, this list of conditions, and the following disclaimer,
124 * without modification.
125 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
126 * substantially similar to the "NO WARRANTY" disclaimer below
127 * ("Disclaimer") and any redistribution must be conditioned upon
128 * including a substantially similar Disclaimer requirement for further
129 * binary redistribution.
130 * 3. Neither the names of the above-listed copyright holders nor the names
131 * of any contributors may be used to endorse or promote products derived
132 * from this software without specific prior written permission.
134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
135 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
136 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
137 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
138 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
139 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
140 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
141 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
142 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
143 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
146 * Alternatively, you may choose to be licensed under the terms of the
147 * GNU General Public License ("GPL") version 2 as published by the Free
148 * Software Foundation.
150 *****************************************************************************/
156 /*******************************************************************************
158 * Additional ACPI Tables (2)
160 * These tables are not consumed directly by the ACPICA subsystem, but are
161 * included here to support device drivers and the AML disassembler.
163 ******************************************************************************/
167 * Values for description table header signatures for tables defined in this
168 * file. Useful because they make it more difficult to inadvertently type in
169 * the wrong signature.
171 #define ACPI_SIG_IORT "IORT" /* IO Remapping Table */
172 #define ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */
173 #define ACPI_SIG_LPIT "LPIT" /* Low Power Idle Table */
174 #define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */
175 #define ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */
176 #define ACPI_SIG_MCHI "MCHI" /* Management Controller Host Interface table */
177 #define ACPI_SIG_MPST "MPST" /* Memory Power State Table */
178 #define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table */
179 #define ACPI_SIG_MSDM "MSDM" /* Microsoft Data Management Table */
180 #define ACPI_SIG_MTMR "MTMR" /* MID Timer table */
181 #define ACPI_SIG_NFIT "NFIT" /* NVDIMM Firmware Interface Table */
182 #define ACPI_SIG_PCCT "PCCT" /* Platform Communications Channel Table */
183 #define ACPI_SIG_PDTT "PDTT" /* Platform Debug Trigger Table */
184 #define ACPI_SIG_PMTT "PMTT" /* Platform Memory Topology Table */
185 #define ACPI_SIG_PPTT "PPTT" /* Processor Properties Topology Table */
186 #define ACPI_SIG_RASF "RASF" /* RAS Feature table */
187 #define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */
188 #define ACPI_SIG_SDEI "SDEI" /* Software Delegated Exception Interface Table */
189 #define ACPI_SIG_SDEV "SDEV" /* Secure Devices table */
190 #define ACPI_SIG_NHLT "NHLT" /* Non-HDAudio Link Table */
194 * All tables must be byte-packed to match the ACPI specification, since
195 * the tables are provided by the system BIOS.
200 * Note: C bitfields are not used for this reason:
202 * "Bitfields are great and easy to read, but unfortunately the C language
203 * does not specify the layout of bitfields in memory, which means they are
204 * essentially useless for dealing with packed data in on-disk formats or
205 * binary wire protocols." (Or ACPI tables and buffers.) "If you ask me,
206 * this decision was a design error in C. Ritchie could have picked an order
207 * and stuck with it." Norman Ramsey.
208 * See http://stackoverflow.com/a/1053662/41661
212 /*******************************************************************************
214 * IORT - IO Remapping Table
216 * Conforms to "IO Remapping Table System Software on ARM Platforms",
217 * Document number: ARM DEN 0049D, March 2018
219 ******************************************************************************/
221 typedef struct acpi_table_iort
223 ACPI_TABLE_HEADER Header;
234 typedef struct acpi_iort_node
241 UINT32 MappingOffset;
246 /* Values for subtable Type above */
248 enum AcpiIortNodeType
250 ACPI_IORT_NODE_ITS_GROUP = 0x00,
251 ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
252 ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
253 ACPI_IORT_NODE_SMMU = 0x03,
254 ACPI_IORT_NODE_SMMU_V3 = 0x04,
255 ACPI_IORT_NODE_PMCG = 0x05
259 typedef struct acpi_iort_id_mapping
261 UINT32 InputBase; /* Lowest value in input range */
262 UINT32 IdCount; /* Number of IDs */
263 UINT32 OutputBase; /* Lowest value in output range */
264 UINT32 OutputReference; /* A reference to the output node */
267 } ACPI_IORT_ID_MAPPING;
269 /* Masks for Flags field above for IORT subtable */
271 #define ACPI_IORT_ID_SINGLE_MAPPING (1)
274 typedef struct acpi_iort_memory_access
276 UINT32 CacheCoherency;
281 } ACPI_IORT_MEMORY_ACCESS;
283 /* Values for CacheCoherency field above */
285 #define ACPI_IORT_NODE_COHERENT 0x00000001 /* The device node is fully coherent */
286 #define ACPI_IORT_NODE_NOT_COHERENT 0x00000000 /* The device node is not coherent */
288 /* Masks for Hints field above */
290 #define ACPI_IORT_HT_TRANSIENT (1)
291 #define ACPI_IORT_HT_WRITE (1<<1)
292 #define ACPI_IORT_HT_READ (1<<2)
293 #define ACPI_IORT_HT_OVERRIDE (1<<3)
295 /* Masks for MemoryFlags field above */
297 #define ACPI_IORT_MF_COHERENCY (1)
298 #define ACPI_IORT_MF_ATTRIBUTES (1<<1)
302 * IORT node specific subtables
304 typedef struct acpi_iort_its_group
307 UINT32 Identifiers[1]; /* GIC ITS identifier array */
309 } ACPI_IORT_ITS_GROUP;
312 typedef struct acpi_iort_named_component
315 UINT64 MemoryProperties; /* Memory access properties */
316 UINT8 MemoryAddressLimit; /* Memory address size limit */
317 char DeviceName[1]; /* Path of namespace object */
319 } ACPI_IORT_NAMED_COMPONENT;
321 /* Masks for Flags field above */
323 #define ACPI_IORT_NC_STALL_SUPPORTED (1)
324 #define ACPI_IORT_NC_PASID_BITS (31<<1)
326 typedef struct acpi_iort_root_complex
328 UINT64 MemoryProperties; /* Memory access properties */
330 UINT32 PciSegmentNumber;
331 UINT8 MemoryAddressLimit; /* Memory address size limit */
332 UINT8 Reserved[3]; /* Reserved, must be zero */
334 } ACPI_IORT_ROOT_COMPLEX;
336 /* Values for AtsAttribute field above */
338 #define ACPI_IORT_ATS_SUPPORTED 0x00000001 /* The root complex supports ATS */
339 #define ACPI_IORT_ATS_UNSUPPORTED 0x00000000 /* The root complex doesn't support ATS */
342 typedef struct acpi_iort_smmu
344 UINT64 BaseAddress; /* SMMU base address */
345 UINT64 Span; /* Length of memory range */
348 UINT32 GlobalInterruptOffset;
349 UINT32 ContextInterruptCount;
350 UINT32 ContextInterruptOffset;
351 UINT32 PmuInterruptCount;
352 UINT32 PmuInterruptOffset;
353 UINT64 Interrupts[1]; /* Interrupt array */
357 /* Values for Model field above */
359 #define ACPI_IORT_SMMU_V1 0x00000000 /* Generic SMMUv1 */
360 #define ACPI_IORT_SMMU_V2 0x00000001 /* Generic SMMUv2 */
361 #define ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002 /* ARM Corelink MMU-400 */
362 #define ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003 /* ARM Corelink MMU-500 */
363 #define ACPI_IORT_SMMU_CORELINK_MMU401 0x00000004 /* ARM Corelink MMU-401 */
364 #define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005 /* Cavium ThunderX SMMUv2 */
366 /* Masks for Flags field above */
368 #define ACPI_IORT_SMMU_DVM_SUPPORTED (1)
369 #define ACPI_IORT_SMMU_COHERENT_WALK (1<<1)
371 /* Global interrupt format */
373 typedef struct acpi_iort_smmu_gsi
378 UINT32 NSgCfgIrptFlags;
380 } ACPI_IORT_SMMU_GSI;
383 typedef struct acpi_iort_smmu_v3
385 UINT64 BaseAddress; /* SMMUv3 base address */
395 UINT32 IdMappingIndex;
399 /* Values for Model field above */
401 #define ACPI_IORT_SMMU_V3_GENERIC 0x00000000 /* Generic SMMUv3 */
402 #define ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001 /* HiSilicon Hi161x SMMUv3 */
403 #define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002 /* Cavium CN99xx SMMUv3 */
405 /* Masks for Flags field above */
407 #define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1)
408 #define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (3<<1)
409 #define ACPI_IORT_SMMU_V3_PXM_VALID (1<<3)
411 typedef struct acpi_iort_pmcg
413 UINT64 Page0BaseAddress;
415 UINT32 NodeReference;
416 UINT64 Page1BaseAddress;
421 /*******************************************************************************
423 * IVRS - I/O Virtualization Reporting Structure
426 * Conforms to "AMD I/O Virtualization Technology (IOMMU) Specification",
427 * Revision 1.26, February 2009.
429 ******************************************************************************/
431 typedef struct acpi_table_ivrs
433 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
434 UINT32 Info; /* Common virtualization info */
439 /* Values for Info field above */
441 #define ACPI_IVRS_PHYSICAL_SIZE 0x00007F00 /* 7 bits, physical address size */
442 #define ACPI_IVRS_VIRTUAL_SIZE 0x003F8000 /* 7 bits, virtual address size */
443 #define ACPI_IVRS_ATS_RESERVED 0x00400000 /* ATS address translation range reserved */
446 /* IVRS subtable header */
448 typedef struct acpi_ivrs_header
450 UINT8 Type; /* Subtable type */
452 UINT16 Length; /* Subtable length */
453 UINT16 DeviceId; /* ID of IOMMU */
457 /* Values for subtable Type above */
461 ACPI_IVRS_TYPE_HARDWARE1 = 0x10,
462 ACPI_IVRS_TYPE_HARDWARE2 = 0x11,
463 ACPI_IVRS_TYPE_MEMORY1 = 0x20,
464 ACPI_IVRS_TYPE_MEMORY2 = 0x21,
465 ACPI_IVRS_TYPE_MEMORY3 = 0x22
468 /* Masks for Flags field above for IVHD subtable */
470 #define ACPI_IVHD_TT_ENABLE (1)
471 #define ACPI_IVHD_PASS_PW (1<<1)
472 #define ACPI_IVHD_RES_PASS_PW (1<<2)
473 #define ACPI_IVHD_ISOC (1<<3)
474 #define ACPI_IVHD_IOTLB (1<<4)
476 /* Masks for Flags field above for IVMD subtable */
478 #define ACPI_IVMD_UNITY (1)
479 #define ACPI_IVMD_READ (1<<1)
480 #define ACPI_IVMD_WRITE (1<<2)
481 #define ACPI_IVMD_EXCLUSION_RANGE (1<<3)
485 * IVRS subtables, correspond to Type in ACPI_IVRS_HEADER
488 /* 0x10: I/O Virtualization Hardware Definition Block (IVHD) */
490 typedef struct acpi_ivrs_hardware_10
492 ACPI_IVRS_HEADER Header;
493 UINT16 CapabilityOffset; /* Offset for IOMMU control fields */
494 UINT64 BaseAddress; /* IOMMU control registers */
495 UINT16 PciSegmentGroup;
496 UINT16 Info; /* MSI number and unit ID */
497 UINT32 FeatureReporting;
499 } ACPI_IVRS_HARDWARE1;
501 /* 0x11: I/O Virtualization Hardware Definition Block (IVHD) */
503 typedef struct acpi_ivrs_hardware_11
505 ACPI_IVRS_HEADER Header;
506 UINT16 CapabilityOffset; /* Offset for IOMMU control fields */
507 UINT64 BaseAddress; /* IOMMU control registers */
508 UINT16 PciSegmentGroup;
509 UINT16 Info; /* MSI number and unit ID */
511 UINT64 EfrRegisterImage;
513 } ACPI_IVRS_HARDWARE2;
515 /* Masks for Info field above */
517 #define ACPI_IVHD_MSI_NUMBER_MASK 0x001F /* 5 bits, MSI message number */
518 #define ACPI_IVHD_UNIT_ID_MASK 0x1F00 /* 5 bits, UnitID */
522 * Device Entries for IVHD subtable, appear after ACPI_IVRS_HARDWARE structure.
523 * Upper two bits of the Type field are the (encoded) length of the structure.
524 * Currently, only 4 and 8 byte entries are defined. 16 and 32 byte entries
525 * are reserved for future use but not defined.
527 typedef struct acpi_ivrs_de_header
533 } ACPI_IVRS_DE_HEADER;
535 /* Length of device entry is in the top two bits of Type field above */
537 #define ACPI_IVHD_ENTRY_LENGTH 0xC0
539 /* Values for device entry Type field above */
541 enum AcpiIvrsDeviceEntryType
543 /* 4-byte device entries, all use ACPI_IVRS_DEVICE4 */
545 ACPI_IVRS_TYPE_PAD4 = 0,
546 ACPI_IVRS_TYPE_ALL = 1,
547 ACPI_IVRS_TYPE_SELECT = 2,
548 ACPI_IVRS_TYPE_START = 3,
549 ACPI_IVRS_TYPE_END = 4,
551 /* 8-byte device entries */
553 ACPI_IVRS_TYPE_PAD8 = 64,
554 ACPI_IVRS_TYPE_NOT_USED = 65,
555 ACPI_IVRS_TYPE_ALIAS_SELECT = 66, /* Uses ACPI_IVRS_DEVICE8A */
556 ACPI_IVRS_TYPE_ALIAS_START = 67, /* Uses ACPI_IVRS_DEVICE8A */
557 ACPI_IVRS_TYPE_EXT_SELECT = 70, /* Uses ACPI_IVRS_DEVICE8B */
558 ACPI_IVRS_TYPE_EXT_START = 71, /* Uses ACPI_IVRS_DEVICE8B */
559 ACPI_IVRS_TYPE_SPECIAL = 72 /* Uses ACPI_IVRS_DEVICE8C */
562 /* Values for Data field above */
564 #define ACPI_IVHD_INIT_PASS (1)
565 #define ACPI_IVHD_EINT_PASS (1<<1)
566 #define ACPI_IVHD_NMI_PASS (1<<2)
567 #define ACPI_IVHD_SYSTEM_MGMT (3<<4)
568 #define ACPI_IVHD_LINT0_PASS (1<<6)
569 #define ACPI_IVHD_LINT1_PASS (1<<7)
572 /* Types 0-4: 4-byte device entry */
574 typedef struct acpi_ivrs_device4
576 ACPI_IVRS_DE_HEADER Header;
580 /* Types 66-67: 8-byte device entry */
582 typedef struct acpi_ivrs_device8a
584 ACPI_IVRS_DE_HEADER Header;
589 } ACPI_IVRS_DEVICE8A;
591 /* Types 70-71: 8-byte device entry */
593 typedef struct acpi_ivrs_device8b
595 ACPI_IVRS_DE_HEADER Header;
598 } ACPI_IVRS_DEVICE8B;
600 /* Values for ExtendedData above */
602 #define ACPI_IVHD_ATS_DISABLED (1<<31)
604 /* Type 72: 8-byte device entry */
606 typedef struct acpi_ivrs_device8c
608 ACPI_IVRS_DE_HEADER Header;
613 } ACPI_IVRS_DEVICE8C;
615 /* Values for Variety field above */
617 #define ACPI_IVHD_IOAPIC 1
618 #define ACPI_IVHD_HPET 2
621 /* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition Block (IVMD) */
623 typedef struct acpi_ivrs_memory
625 ACPI_IVRS_HEADER Header;
634 /*******************************************************************************
636 * LPIT - Low Power Idle Table
638 * Conforms to "ACPI Low Power Idle Table (LPIT)" July 2014.
640 ******************************************************************************/
642 typedef struct acpi_table_lpit
644 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
649 /* LPIT subtable header */
651 typedef struct acpi_lpit_header
653 UINT32 Type; /* Subtable type */
654 UINT32 Length; /* Subtable length */
661 /* Values for subtable Type above */
665 ACPI_LPIT_TYPE_NATIVE_CSTATE = 0x00,
666 ACPI_LPIT_TYPE_RESERVED = 0x01 /* 1 and above are reserved */
669 /* Masks for Flags field above */
671 #define ACPI_LPIT_STATE_DISABLED (1)
672 #define ACPI_LPIT_NO_COUNTER (1<<1)
675 * LPIT subtables, correspond to Type in ACPI_LPIT_HEADER
678 /* 0x00: Native C-state instruction based LPI structure */
680 typedef struct acpi_lpit_native
682 ACPI_LPIT_HEADER Header;
683 ACPI_GENERIC_ADDRESS EntryTrigger;
686 ACPI_GENERIC_ADDRESS ResidencyCounter;
687 UINT64 CounterFrequency;
692 /*******************************************************************************
694 * MADT - Multiple APIC Description Table
697 ******************************************************************************/
699 typedef struct acpi_table_madt
701 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
702 UINT32 Address; /* Physical address of local APIC */
707 /* Masks for Flags field above */
709 #define ACPI_MADT_PCAT_COMPAT (1) /* 00: System also has dual 8259s */
711 /* Values for PCATCompat flag */
713 #define ACPI_MADT_DUAL_PIC 1
714 #define ACPI_MADT_MULTIPLE_APIC 0
717 /* Values for MADT subtable type in ACPI_SUBTABLE_HEADER */
721 ACPI_MADT_TYPE_LOCAL_APIC = 0,
722 ACPI_MADT_TYPE_IO_APIC = 1,
723 ACPI_MADT_TYPE_INTERRUPT_OVERRIDE = 2,
724 ACPI_MADT_TYPE_NMI_SOURCE = 3,
725 ACPI_MADT_TYPE_LOCAL_APIC_NMI = 4,
726 ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE = 5,
727 ACPI_MADT_TYPE_IO_SAPIC = 6,
728 ACPI_MADT_TYPE_LOCAL_SAPIC = 7,
729 ACPI_MADT_TYPE_INTERRUPT_SOURCE = 8,
730 ACPI_MADT_TYPE_LOCAL_X2APIC = 9,
731 ACPI_MADT_TYPE_LOCAL_X2APIC_NMI = 10,
732 ACPI_MADT_TYPE_GENERIC_INTERRUPT = 11,
733 ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR = 12,
734 ACPI_MADT_TYPE_GENERIC_MSI_FRAME = 13,
735 ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,
736 ACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15,
737 ACPI_MADT_TYPE_RESERVED = 16 /* 16 and greater are reserved */
742 * MADT Subtables, correspond to Type in ACPI_SUBTABLE_HEADER
745 /* 0: Processor Local APIC */
747 typedef struct acpi_madt_local_apic
749 ACPI_SUBTABLE_HEADER Header;
750 UINT8 ProcessorId; /* ACPI processor id */
751 UINT8 Id; /* Processor's local APIC id */
754 } ACPI_MADT_LOCAL_APIC;
759 typedef struct acpi_madt_io_apic
761 ACPI_SUBTABLE_HEADER Header;
762 UINT8 Id; /* I/O APIC ID */
763 UINT8 Reserved; /* Reserved - must be zero */
764 UINT32 Address; /* APIC physical address */
765 UINT32 GlobalIrqBase; /* Global system interrupt where INTI lines start */
770 /* 2: Interrupt Override */
772 typedef struct acpi_madt_interrupt_override
774 ACPI_SUBTABLE_HEADER Header;
775 UINT8 Bus; /* 0 - ISA */
776 UINT8 SourceIrq; /* Interrupt source (IRQ) */
777 UINT32 GlobalIrq; /* Global system interrupt */
780 } ACPI_MADT_INTERRUPT_OVERRIDE;
785 typedef struct acpi_madt_nmi_source
787 ACPI_SUBTABLE_HEADER Header;
789 UINT32 GlobalIrq; /* Global system interrupt */
791 } ACPI_MADT_NMI_SOURCE;
794 /* 4: Local APIC NMI */
796 typedef struct acpi_madt_local_apic_nmi
798 ACPI_SUBTABLE_HEADER Header;
799 UINT8 ProcessorId; /* ACPI processor id */
801 UINT8 Lint; /* LINTn to which NMI is connected */
803 } ACPI_MADT_LOCAL_APIC_NMI;
806 /* 5: Address Override */
808 typedef struct acpi_madt_local_apic_override
810 ACPI_SUBTABLE_HEADER Header;
811 UINT16 Reserved; /* Reserved, must be zero */
812 UINT64 Address; /* APIC physical address */
814 } ACPI_MADT_LOCAL_APIC_OVERRIDE;
819 typedef struct acpi_madt_io_sapic
821 ACPI_SUBTABLE_HEADER Header;
822 UINT8 Id; /* I/O SAPIC ID */
823 UINT8 Reserved; /* Reserved, must be zero */
824 UINT32 GlobalIrqBase; /* Global interrupt for SAPIC start */
825 UINT64 Address; /* SAPIC physical address */
827 } ACPI_MADT_IO_SAPIC;
832 typedef struct acpi_madt_local_sapic
834 ACPI_SUBTABLE_HEADER Header;
835 UINT8 ProcessorId; /* ACPI processor id */
836 UINT8 Id; /* SAPIC ID */
837 UINT8 Eid; /* SAPIC EID */
838 UINT8 Reserved[3]; /* Reserved, must be zero */
840 UINT32 Uid; /* Numeric UID - ACPI 3.0 */
841 char UidString[1]; /* String UID - ACPI 3.0 */
843 } ACPI_MADT_LOCAL_SAPIC;
846 /* 8: Platform Interrupt Source */
848 typedef struct acpi_madt_interrupt_source
850 ACPI_SUBTABLE_HEADER Header;
852 UINT8 Type; /* 1=PMI, 2=INIT, 3=corrected */
853 UINT8 Id; /* Processor ID */
854 UINT8 Eid; /* Processor EID */
855 UINT8 IoSapicVector; /* Vector value for PMI interrupts */
856 UINT32 GlobalIrq; /* Global system interrupt */
857 UINT32 Flags; /* Interrupt Source Flags */
859 } ACPI_MADT_INTERRUPT_SOURCE;
861 /* Masks for Flags field above */
863 #define ACPI_MADT_CPEI_OVERRIDE (1)
866 /* 9: Processor Local X2APIC (ACPI 4.0) */
868 typedef struct acpi_madt_local_x2apic
870 ACPI_SUBTABLE_HEADER Header;
871 UINT16 Reserved; /* Reserved - must be zero */
872 UINT32 LocalApicId; /* Processor x2APIC ID */
874 UINT32 Uid; /* ACPI processor UID */
876 } ACPI_MADT_LOCAL_X2APIC;
879 /* 10: Local X2APIC NMI (ACPI 4.0) */
881 typedef struct acpi_madt_local_x2apic_nmi
883 ACPI_SUBTABLE_HEADER Header;
885 UINT32 Uid; /* ACPI processor UID */
886 UINT8 Lint; /* LINTn to which NMI is connected */
887 UINT8 Reserved[3]; /* Reserved - must be zero */
889 } ACPI_MADT_LOCAL_X2APIC_NMI;
892 /* 11: Generic Interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 changes) */
894 typedef struct acpi_madt_generic_interrupt
896 ACPI_SUBTABLE_HEADER Header;
897 UINT16 Reserved; /* Reserved - must be zero */
898 UINT32 CpuInterfaceNumber;
901 UINT32 ParkingVersion;
902 UINT32 PerformanceInterrupt;
903 UINT64 ParkedAddress;
905 UINT64 GicvBaseAddress;
906 UINT64 GichBaseAddress;
907 UINT32 VgicInterrupt;
908 UINT64 GicrBaseAddress;
910 UINT8 EfficiencyClass;
912 UINT16 SpeInterrupt; /* ACPI 6.3 */
914 } ACPI_MADT_GENERIC_INTERRUPT;
916 /* Masks for Flags field above */
918 /* ACPI_MADT_ENABLED (1) Processor is usable if set */
919 #define ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1) /* 01: Performance Interrupt Mode */
920 #define ACPI_MADT_VGIC_IRQ_MODE (1<<2) /* 02: VGIC Maintenance Interrupt mode */
923 /* 12: Generic Distributor (ACPI 5.0 + ACPI 6.0 changes) */
925 typedef struct acpi_madt_generic_distributor
927 ACPI_SUBTABLE_HEADER Header;
928 UINT16 Reserved; /* Reserved - must be zero */
931 UINT32 GlobalIrqBase;
933 UINT8 Reserved2[3]; /* Reserved - must be zero */
935 } ACPI_MADT_GENERIC_DISTRIBUTOR;
937 /* Values for Version field above */
939 enum AcpiMadtGicVersion
941 ACPI_MADT_GIC_VERSION_NONE = 0,
942 ACPI_MADT_GIC_VERSION_V1 = 1,
943 ACPI_MADT_GIC_VERSION_V2 = 2,
944 ACPI_MADT_GIC_VERSION_V3 = 3,
945 ACPI_MADT_GIC_VERSION_V4 = 4,
946 ACPI_MADT_GIC_VERSION_RESERVED = 5 /* 5 and greater are reserved */
950 /* 13: Generic MSI Frame (ACPI 5.1) */
952 typedef struct acpi_madt_generic_msi_frame
954 ACPI_SUBTABLE_HEADER Header;
955 UINT16 Reserved; /* Reserved - must be zero */
962 } ACPI_MADT_GENERIC_MSI_FRAME;
964 /* Masks for Flags field above */
966 #define ACPI_MADT_OVERRIDE_SPI_VALUES (1)
969 /* 14: Generic Redistributor (ACPI 5.1) */
971 typedef struct acpi_madt_generic_redistributor
973 ACPI_SUBTABLE_HEADER Header;
974 UINT16 Reserved; /* reserved - must be zero */
978 } ACPI_MADT_GENERIC_REDISTRIBUTOR;
981 /* 15: Generic Translator (ACPI 6.0) */
983 typedef struct acpi_madt_generic_translator
985 ACPI_SUBTABLE_HEADER Header;
986 UINT16 Reserved; /* reserved - must be zero */
987 UINT32 TranslationId;
991 } ACPI_MADT_GENERIC_TRANSLATOR;
995 * Common flags fields for MADT subtables
998 /* MADT Local APIC flags */
1000 #define ACPI_MADT_ENABLED (1) /* 00: Processor is usable if set */
1002 /* MADT MPS INTI flags (IntiFlags) */
1004 #define ACPI_MADT_POLARITY_MASK (3) /* 00-01: Polarity of APIC I/O input signals */
1005 #define ACPI_MADT_TRIGGER_MASK (3<<2) /* 02-03: Trigger mode of APIC input signals */
1007 /* Values for MPS INTI flags */
1009 #define ACPI_MADT_POLARITY_CONFORMS 0
1010 #define ACPI_MADT_POLARITY_ACTIVE_HIGH 1
1011 #define ACPI_MADT_POLARITY_RESERVED 2
1012 #define ACPI_MADT_POLARITY_ACTIVE_LOW 3
1014 #define ACPI_MADT_TRIGGER_CONFORMS (0)
1015 #define ACPI_MADT_TRIGGER_EDGE (1<<2)
1016 #define ACPI_MADT_TRIGGER_RESERVED (2<<2)
1017 #define ACPI_MADT_TRIGGER_LEVEL (3<<2)
1020 /*******************************************************************************
1022 * MCFG - PCI Memory Mapped Configuration table and subtable
1025 * Conforms to "PCI Firmware Specification", Revision 3.0, June 20, 2005
1027 ******************************************************************************/
1029 typedef struct acpi_table_mcfg
1031 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1039 typedef struct acpi_mcfg_allocation
1041 UINT64 Address; /* Base address, processor-relative */
1042 UINT16 PciSegment; /* PCI segment group number */
1043 UINT8 StartBusNumber; /* Starting PCI Bus number */
1044 UINT8 EndBusNumber; /* Final PCI Bus number */
1047 } ACPI_MCFG_ALLOCATION;
1050 /*******************************************************************************
1052 * MCHI - Management Controller Host Interface Table
1055 * Conforms to "Management Component Transport Protocol (MCTP) Host
1056 * Interface Specification", Revision 1.0.0a, October 13, 2009
1058 ******************************************************************************/
1060 typedef struct acpi_table_mchi
1062 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1063 UINT8 InterfaceType;
1065 UINT64 ProtocolData;
1066 UINT8 InterruptType;
1068 UINT8 PciDeviceFlag;
1069 UINT32 GlobalInterrupt;
1070 ACPI_GENERIC_ADDRESS ControlRegister;
1079 /*******************************************************************************
1081 * MPST - Memory Power State Table (ACPI 5.0)
1084 ******************************************************************************/
1086 #define ACPI_MPST_CHANNEL_INFO \
1088 UINT8 Reserved1[3]; \
1089 UINT16 PowerNodeCount; \
1094 typedef struct acpi_table_mpst
1096 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1097 ACPI_MPST_CHANNEL_INFO /* Platform Communication Channel */
1102 /* Memory Platform Communication Channel Info */
1104 typedef struct acpi_mpst_channel
1106 ACPI_MPST_CHANNEL_INFO /* Platform Communication Channel */
1108 } ACPI_MPST_CHANNEL;
1111 /* Memory Power Node Structure */
1113 typedef struct acpi_mpst_power_node
1119 UINT64 RangeAddress;
1121 UINT32 NumPowerStates;
1122 UINT32 NumPhysicalComponents;
1124 } ACPI_MPST_POWER_NODE;
1126 /* Values for Flags field above */
1128 #define ACPI_MPST_ENABLED 1
1129 #define ACPI_MPST_POWER_MANAGED 2
1130 #define ACPI_MPST_HOT_PLUG_CAPABLE 4
1133 /* Memory Power State Structure (follows POWER_NODE above) */
1135 typedef struct acpi_mpst_power_state
1140 } ACPI_MPST_POWER_STATE;
1143 /* Physical Component ID Structure (follows POWER_STATE above) */
1145 typedef struct acpi_mpst_component
1149 } ACPI_MPST_COMPONENT;
1152 /* Memory Power State Characteristics Structure (follows all POWER_NODEs) */
1154 typedef struct acpi_mpst_data_hdr
1156 UINT16 CharacteristicsCount;
1159 } ACPI_MPST_DATA_HDR;
1161 typedef struct acpi_mpst_power_data
1166 UINT32 AveragePower;
1171 } ACPI_MPST_POWER_DATA;
1173 /* Values for Flags field above */
1175 #define ACPI_MPST_PRESERVE 1
1176 #define ACPI_MPST_AUTOENTRY 2
1177 #define ACPI_MPST_AUTOEXIT 4
1180 /* Shared Memory Region (not part of an ACPI table) */
1182 typedef struct acpi_mpst_shared
1187 UINT32 CommandRegister;
1188 UINT32 StatusRegister;
1189 UINT32 PowerStateId;
1191 UINT64 EnergyConsumed;
1192 UINT64 AveragePower;
1197 /*******************************************************************************
1199 * MSCT - Maximum System Characteristics Table (ACPI 4.0)
1202 ******************************************************************************/
1204 typedef struct acpi_table_msct
1206 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1207 UINT32 ProximityOffset; /* Location of proximity info struct(s) */
1208 UINT32 MaxProximityDomains;/* Max number of proximity domains */
1209 UINT32 MaxClockDomains; /* Max number of clock domains */
1210 UINT64 MaxAddress; /* Max physical address in system */
1215 /* Subtable - Maximum Proximity Domain Information. Version 1 */
1217 typedef struct acpi_msct_proximity
1221 UINT32 RangeStart; /* Start of domain range */
1222 UINT32 RangeEnd; /* End of domain range */
1223 UINT32 ProcessorCapacity;
1224 UINT64 MemoryCapacity; /* In bytes */
1226 } ACPI_MSCT_PROXIMITY;
1229 /*******************************************************************************
1231 * MSDM - Microsoft Data Management table
1233 * Conforms to "Microsoft Software Licensing Tables (SLIC and MSDM)",
1234 * November 29, 2011. Copyright 2011 Microsoft
1236 ******************************************************************************/
1238 /* Basic MSDM table is only the common ACPI header */
1240 typedef struct acpi_table_msdm
1242 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1247 /*******************************************************************************
1249 * MTMR - MID Timer Table
1252 * Conforms to "Simple Firmware Interface Specification",
1253 * Draft 0.8.2, Oct 19, 2010
1254 * NOTE: The ACPI MTMR is equivalent to the SFI MTMR table.
1256 ******************************************************************************/
1258 typedef struct acpi_table_mtmr
1260 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1266 typedef struct acpi_mtmr_entry
1268 ACPI_GENERIC_ADDRESS PhysicalAddress;
1275 /*******************************************************************************
1277 * NFIT - NVDIMM Interface Table (ACPI 6.0+)
1280 ******************************************************************************/
1282 typedef struct acpi_table_nfit
1284 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1285 UINT32 Reserved; /* Reserved, must be zero */
1289 /* Subtable header for NFIT */
1291 typedef struct acpi_nfit_header
1299 /* Values for subtable type in ACPI_NFIT_HEADER */
1303 ACPI_NFIT_TYPE_SYSTEM_ADDRESS = 0,
1304 ACPI_NFIT_TYPE_MEMORY_MAP = 1,
1305 ACPI_NFIT_TYPE_INTERLEAVE = 2,
1306 ACPI_NFIT_TYPE_SMBIOS = 3,
1307 ACPI_NFIT_TYPE_CONTROL_REGION = 4,
1308 ACPI_NFIT_TYPE_DATA_REGION = 5,
1309 ACPI_NFIT_TYPE_FLUSH_ADDRESS = 6,
1310 ACPI_NFIT_TYPE_CAPABILITIES = 7,
1311 ACPI_NFIT_TYPE_RESERVED = 8 /* 8 and greater are reserved */
1318 /* 0: System Physical Address Range Structure */
1320 typedef struct acpi_nfit_system_address
1322 ACPI_NFIT_HEADER Header;
1325 UINT32 Reserved; /* Reserved, must be zero */
1326 UINT32 ProximityDomain;
1327 UINT8 RangeGuid[16];
1330 UINT64 MemoryMapping;
1332 } ACPI_NFIT_SYSTEM_ADDRESS;
1336 #define ACPI_NFIT_ADD_ONLINE_ONLY (1) /* 00: Add/Online Operation Only */
1337 #define ACPI_NFIT_PROXIMITY_VALID (1<<1) /* 01: Proximity Domain Valid */
1339 /* Range Type GUIDs appear in the include/acuuid.h file */
1342 /* 1: Memory Device to System Address Range Map Structure */
1344 typedef struct acpi_nfit_memory_map
1346 ACPI_NFIT_HEADER Header;
1347 UINT32 DeviceHandle;
1353 UINT64 RegionOffset;
1355 UINT16 InterleaveIndex;
1356 UINT16 InterleaveWays;
1358 UINT16 Reserved; /* Reserved, must be zero */
1360 } ACPI_NFIT_MEMORY_MAP;
1364 #define ACPI_NFIT_MEM_SAVE_FAILED (1) /* 00: Last SAVE to Memory Device failed */
1365 #define ACPI_NFIT_MEM_RESTORE_FAILED (1<<1) /* 01: Last RESTORE from Memory Device failed */
1366 #define ACPI_NFIT_MEM_FLUSH_FAILED (1<<2) /* 02: Platform flush failed */
1367 #define ACPI_NFIT_MEM_NOT_ARMED (1<<3) /* 03: Memory Device is not armed */
1368 #define ACPI_NFIT_MEM_HEALTH_OBSERVED (1<<4) /* 04: Memory Device observed SMART/health events */
1369 #define ACPI_NFIT_MEM_HEALTH_ENABLED (1<<5) /* 05: SMART/health events enabled */
1370 #define ACPI_NFIT_MEM_MAP_FAILED (1<<6) /* 06: Mapping to SPA failed */
1373 /* 2: Interleave Structure */
1375 typedef struct acpi_nfit_interleave
1377 ACPI_NFIT_HEADER Header;
1378 UINT16 InterleaveIndex;
1379 UINT16 Reserved; /* Reserved, must be zero */
1382 UINT32 LineOffset[1]; /* Variable length */
1384 } ACPI_NFIT_INTERLEAVE;
1387 /* 3: SMBIOS Management Information Structure */
1389 typedef struct acpi_nfit_smbios
1391 ACPI_NFIT_HEADER Header;
1392 UINT32 Reserved; /* Reserved, must be zero */
1393 UINT8 Data[1]; /* Variable length */
1398 /* 4: NVDIMM Control Region Structure */
1400 typedef struct acpi_nfit_control_region
1402 ACPI_NFIT_HEADER Header;
1407 UINT16 SubsystemVendorId;
1408 UINT16 SubsystemDeviceId;
1409 UINT16 SubsystemRevisionId;
1411 UINT8 ManufacturingLocation;
1412 UINT16 ManufacturingDate;
1413 UINT8 Reserved[2]; /* Reserved, must be zero */
1414 UINT32 SerialNumber;
1418 UINT64 CommandOffset;
1420 UINT64 StatusOffset;
1423 UINT8 Reserved1[6]; /* Reserved, must be zero */
1425 } ACPI_NFIT_CONTROL_REGION;
1429 #define ACPI_NFIT_CONTROL_BUFFERED (1) /* Block Data Windows implementation is buffered */
1431 /* ValidFields bits */
1433 #define ACPI_NFIT_CONTROL_MFG_INFO_VALID (1) /* Manufacturing fields are valid */
1436 /* 5: NVDIMM Block Data Window Region Structure */
1438 typedef struct acpi_nfit_data_region
1440 ACPI_NFIT_HEADER Header;
1446 UINT64 StartAddress;
1448 } ACPI_NFIT_DATA_REGION;
1451 /* 6: Flush Hint Address Structure */
1453 typedef struct acpi_nfit_flush_address
1455 ACPI_NFIT_HEADER Header;
1456 UINT32 DeviceHandle;
1458 UINT8 Reserved[6]; /* Reserved, must be zero */
1459 UINT64 HintAddress[1]; /* Variable length */
1461 } ACPI_NFIT_FLUSH_ADDRESS;
1464 /* 7: Platform Capabilities Structure */
1466 typedef struct acpi_nfit_capabilities
1468 ACPI_NFIT_HEADER Header;
1469 UINT8 HighestCapability;
1470 UINT8 Reserved[3]; /* Reserved, must be zero */
1471 UINT32 Capabilities;
1474 } ACPI_NFIT_CAPABILITIES;
1476 /* Capabilities Flags */
1478 #define ACPI_NFIT_CAPABILITY_CACHE_FLUSH (1) /* 00: Cache Flush to NVDIMM capable */
1479 #define ACPI_NFIT_CAPABILITY_MEM_FLUSH (1<<1) /* 01: Memory Flush to NVDIMM capable */
1480 #define ACPI_NFIT_CAPABILITY_MEM_MIRRORING (1<<2) /* 02: Memory Mirroring capable */
1484 * NFIT/DVDIMM device handle support - used as the _ADR for each NVDIMM
1486 typedef struct nfit_device_handle
1490 } NFIT_DEVICE_HANDLE;
1492 /* Device handle construction and extraction macros */
1494 #define ACPI_NFIT_DIMM_NUMBER_MASK 0x0000000F
1495 #define ACPI_NFIT_CHANNEL_NUMBER_MASK 0x000000F0
1496 #define ACPI_NFIT_MEMORY_ID_MASK 0x00000F00
1497 #define ACPI_NFIT_SOCKET_ID_MASK 0x0000F000
1498 #define ACPI_NFIT_NODE_ID_MASK 0x0FFF0000
1500 #define ACPI_NFIT_DIMM_NUMBER_OFFSET 0
1501 #define ACPI_NFIT_CHANNEL_NUMBER_OFFSET 4
1502 #define ACPI_NFIT_MEMORY_ID_OFFSET 8
1503 #define ACPI_NFIT_SOCKET_ID_OFFSET 12
1504 #define ACPI_NFIT_NODE_ID_OFFSET 16
1506 /* Macro to construct a NFIT/NVDIMM device handle */
1508 #define ACPI_NFIT_BUILD_DEVICE_HANDLE(dimm, channel, memory, socket, node) \
1510 ((channel) << ACPI_NFIT_CHANNEL_NUMBER_OFFSET) | \
1511 ((memory) << ACPI_NFIT_MEMORY_ID_OFFSET) | \
1512 ((socket) << ACPI_NFIT_SOCKET_ID_OFFSET) | \
1513 ((node) << ACPI_NFIT_NODE_ID_OFFSET))
1515 /* Macros to extract individual fields from a NFIT/NVDIMM device handle */
1517 #define ACPI_NFIT_GET_DIMM_NUMBER(handle) \
1518 ((handle) & ACPI_NFIT_DIMM_NUMBER_MASK)
1520 #define ACPI_NFIT_GET_CHANNEL_NUMBER(handle) \
1521 (((handle) & ACPI_NFIT_CHANNEL_NUMBER_MASK) >> ACPI_NFIT_CHANNEL_NUMBER_OFFSET)
1523 #define ACPI_NFIT_GET_MEMORY_ID(handle) \
1524 (((handle) & ACPI_NFIT_MEMORY_ID_MASK) >> ACPI_NFIT_MEMORY_ID_OFFSET)
1526 #define ACPI_NFIT_GET_SOCKET_ID(handle) \
1527 (((handle) & ACPI_NFIT_SOCKET_ID_MASK) >> ACPI_NFIT_SOCKET_ID_OFFSET)
1529 #define ACPI_NFIT_GET_NODE_ID(handle) \
1530 (((handle) & ACPI_NFIT_NODE_ID_MASK) >> ACPI_NFIT_NODE_ID_OFFSET)
1533 /*******************************************************************************
1535 * PCCT - Platform Communications Channel Table (ACPI 5.0)
1536 * Version 2 (ACPI 6.2)
1538 ******************************************************************************/
1540 typedef struct acpi_table_pcct
1542 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1548 /* Values for Flags field above */
1550 #define ACPI_PCCT_DOORBELL 1
1552 /* Values for subtable type in ACPI_SUBTABLE_HEADER */
1556 ACPI_PCCT_TYPE_GENERIC_SUBSPACE = 0,
1557 ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE = 1,
1558 ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE_TYPE2 = 2, /* ACPI 6.1 */
1559 ACPI_PCCT_TYPE_EXT_PCC_MASTER_SUBSPACE = 3, /* ACPI 6.2 */
1560 ACPI_PCCT_TYPE_EXT_PCC_SLAVE_SUBSPACE = 4, /* ACPI 6.2 */
1561 ACPI_PCCT_TYPE_RESERVED = 5 /* 5 and greater are reserved */
1565 * PCCT Subtables, correspond to Type in ACPI_SUBTABLE_HEADER
1568 /* 0: Generic Communications Subspace */
1570 typedef struct acpi_pcct_subspace
1572 ACPI_SUBTABLE_HEADER Header;
1576 ACPI_GENERIC_ADDRESS DoorbellRegister;
1577 UINT64 PreserveMask;
1580 UINT32 MaxAccessRate;
1581 UINT16 MinTurnaroundTime;
1583 } ACPI_PCCT_SUBSPACE;
1586 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */
1588 typedef struct acpi_pcct_hw_reduced
1590 ACPI_SUBTABLE_HEADER Header;
1591 UINT32 PlatformInterrupt;
1596 ACPI_GENERIC_ADDRESS DoorbellRegister;
1597 UINT64 PreserveMask;
1600 UINT32 MaxAccessRate;
1601 UINT16 MinTurnaroundTime;
1603 } ACPI_PCCT_HW_REDUCED;
1606 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */
1608 typedef struct acpi_pcct_hw_reduced_type2
1610 ACPI_SUBTABLE_HEADER Header;
1611 UINT32 PlatformInterrupt;
1616 ACPI_GENERIC_ADDRESS DoorbellRegister;
1617 UINT64 PreserveMask;
1620 UINT32 MaxAccessRate;
1621 UINT16 MinTurnaroundTime;
1622 ACPI_GENERIC_ADDRESS PlatformAckRegister;
1623 UINT64 AckPreserveMask;
1624 UINT64 AckWriteMask;
1626 } ACPI_PCCT_HW_REDUCED_TYPE2;
1629 /* 3: Extended PCC Master Subspace Type 3 (ACPI 6.2) */
1631 typedef struct acpi_pcct_ext_pcc_master
1633 ACPI_SUBTABLE_HEADER Header;
1634 UINT32 PlatformInterrupt;
1639 ACPI_GENERIC_ADDRESS DoorbellRegister;
1640 UINT64 PreserveMask;
1643 UINT32 MaxAccessRate;
1644 UINT32 MinTurnaroundTime;
1645 ACPI_GENERIC_ADDRESS PlatformAckRegister;
1646 UINT64 AckPreserveMask;
1649 ACPI_GENERIC_ADDRESS CmdCompleteRegister;
1650 UINT64 CmdCompleteMask;
1651 ACPI_GENERIC_ADDRESS CmdUpdateRegister;
1652 UINT64 CmdUpdatePreserveMask;
1653 UINT64 CmdUpdateSetMask;
1654 ACPI_GENERIC_ADDRESS ErrorStatusRegister;
1655 UINT64 ErrorStatusMask;
1657 } ACPI_PCCT_EXT_PCC_MASTER;
1660 /* 4: Extended PCC Slave Subspace Type 4 (ACPI 6.2) */
1662 typedef struct acpi_pcct_ext_pcc_slave
1664 ACPI_SUBTABLE_HEADER Header;
1665 UINT32 PlatformInterrupt;
1670 ACPI_GENERIC_ADDRESS DoorbellRegister;
1671 UINT64 PreserveMask;
1674 UINT32 MaxAccessRate;
1675 UINT32 MinTurnaroundTime;
1676 ACPI_GENERIC_ADDRESS PlatformAckRegister;
1677 UINT64 AckPreserveMask;
1680 ACPI_GENERIC_ADDRESS CmdCompleteRegister;
1681 UINT64 CmdCompleteMask;
1682 ACPI_GENERIC_ADDRESS CmdUpdateRegister;
1683 UINT64 CmdUpdatePreserveMask;
1684 UINT64 CmdUpdateSetMask;
1685 ACPI_GENERIC_ADDRESS ErrorStatusRegister;
1686 UINT64 ErrorStatusMask;
1688 } ACPI_PCCT_EXT_PCC_SLAVE;
1691 /* Values for doorbell flags above */
1693 #define ACPI_PCCT_INTERRUPT_POLARITY (1)
1694 #define ACPI_PCCT_INTERRUPT_MODE (1<<1)
1698 * PCC memory structures (not part of the ACPI table)
1701 /* Shared Memory Region */
1703 typedef struct acpi_pcct_shared_memory
1709 } ACPI_PCCT_SHARED_MEMORY;
1712 /* Extended PCC Subspace Shared Memory Region (ACPI 6.2) */
1714 typedef struct acpi_pcct_ext_pcc_shared_memory
1721 } ACPI_PCCT_EXT_PCC_SHARED_MEMORY;
1724 /*******************************************************************************
1726 * PDTT - Platform Debug Trigger Table (ACPI 6.2)
1729 ******************************************************************************/
1731 typedef struct acpi_table_pdtt
1733 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1742 * PDTT Communication Channel Identifier Structure.
1743 * The number of these structures is defined by TriggerCount above,
1744 * starting at ArrayOffset.
1746 typedef struct acpi_pdtt_channel
1751 } ACPI_PDTT_CHANNEL;
1753 /* Flags for above */
1755 #define ACPI_PDTT_RUNTIME_TRIGGER (1)
1756 #define ACPI_PDTT_WAIT_COMPLETION (1<<1)
1757 #define ACPI_PDTT_TRIGGER_ORDER (1<<2)
1760 /*******************************************************************************
1762 * PMTT - Platform Memory Topology Table (ACPI 5.0)
1765 ******************************************************************************/
1767 typedef struct acpi_table_pmtt
1769 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1775 /* Common header for PMTT subtables that follow main table */
1777 typedef struct acpi_pmtt_header
1787 /* Values for Type field above */
1789 #define ACPI_PMTT_TYPE_SOCKET 0
1790 #define ACPI_PMTT_TYPE_CONTROLLER 1
1791 #define ACPI_PMTT_TYPE_DIMM 2
1792 #define ACPI_PMTT_TYPE_RESERVED 3 /* 0x03-0xFF are reserved */
1794 /* Values for Flags field above */
1796 #define ACPI_PMTT_TOP_LEVEL 0x0001
1797 #define ACPI_PMTT_PHYSICAL 0x0002
1798 #define ACPI_PMTT_MEMORY_TYPE 0x000C
1802 * PMTT subtables, correspond to Type in acpi_pmtt_header
1806 /* 0: Socket Structure */
1808 typedef struct acpi_pmtt_socket
1810 ACPI_PMTT_HEADER Header;
1817 /* 1: Memory Controller subtable */
1819 typedef struct acpi_pmtt_controller
1821 ACPI_PMTT_HEADER Header;
1823 UINT32 WriteLatency;
1824 UINT32 ReadBandwidth;
1825 UINT32 WriteBandwidth;
1831 } ACPI_PMTT_CONTROLLER;
1833 /* 1a: Proximity Domain substructure */
1835 typedef struct acpi_pmtt_domain
1837 UINT32 ProximityDomain;
1842 /* 2: Physical Component Identifier (DIMM) */
1844 typedef struct acpi_pmtt_physical_component
1846 ACPI_PMTT_HEADER Header;
1852 } ACPI_PMTT_PHYSICAL_COMPONENT;
1855 /*******************************************************************************
1857 * PPTT - Processor Properties Topology Table (ACPI 6.2)
1860 ******************************************************************************/
1862 typedef struct acpi_table_pptt
1864 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1868 /* Values for Type field above */
1872 ACPI_PPTT_TYPE_PROCESSOR = 0,
1873 ACPI_PPTT_TYPE_CACHE = 1,
1874 ACPI_PPTT_TYPE_ID = 2,
1875 ACPI_PPTT_TYPE_RESERVED = 3
1879 /* 0: Processor Hierarchy Node Structure */
1881 typedef struct acpi_pptt_processor
1883 ACPI_SUBTABLE_HEADER Header;
1887 UINT32 AcpiProcessorId;
1888 UINT32 NumberOfPrivResources;
1890 } ACPI_PPTT_PROCESSOR;
1894 #define ACPI_PPTT_PHYSICAL_PACKAGE (1)
1895 #define ACPI_PPTT_ACPI_PROCESSOR_ID_VALID (1<<1)
1896 #define ACPI_PPTT_ACPI_PROCESSOR_IS_THREAD (1<<2) /* ACPI 6.3 */
1897 #define ACPI_PPTT_ACPI_LEAF_NODE (1<<3) /* ACPI 6.3 */
1898 #define ACPI_PPTT_ACPI_IDENTICAL (1<<4) /* ACPI 6.3 */
1901 /* 1: Cache Type Structure */
1903 typedef struct acpi_pptt_cache
1905 ACPI_SUBTABLE_HEADER Header;
1908 UINT32 NextLevelOfCache;
1910 UINT32 NumberOfSets;
1911 UINT8 Associativity;
1919 #define ACPI_PPTT_SIZE_PROPERTY_VALID (1) /* Physical property valid */
1920 #define ACPI_PPTT_NUMBER_OF_SETS_VALID (1<<1) /* Number of sets valid */
1921 #define ACPI_PPTT_ASSOCIATIVITY_VALID (1<<2) /* Associativity valid */
1922 #define ACPI_PPTT_ALLOCATION_TYPE_VALID (1<<3) /* Allocation type valid */
1923 #define ACPI_PPTT_CACHE_TYPE_VALID (1<<4) /* Cache type valid */
1924 #define ACPI_PPTT_WRITE_POLICY_VALID (1<<5) /* Write policy valid */
1925 #define ACPI_PPTT_LINE_SIZE_VALID (1<<6) /* Line size valid */
1927 /* Masks for Attributes */
1929 #define ACPI_PPTT_MASK_ALLOCATION_TYPE (0x03) /* Allocation type */
1930 #define ACPI_PPTT_MASK_CACHE_TYPE (0x0C) /* Cache type */
1931 #define ACPI_PPTT_MASK_WRITE_POLICY (0x10) /* Write policy */
1933 /* Attributes describing cache */
1934 #define ACPI_PPTT_CACHE_READ_ALLOCATE (0x0) /* Cache line is allocated on read */
1935 #define ACPI_PPTT_CACHE_WRITE_ALLOCATE (0x01) /* Cache line is allocated on write */
1936 #define ACPI_PPTT_CACHE_RW_ALLOCATE (0x02) /* Cache line is allocated on read and write */
1937 #define ACPI_PPTT_CACHE_RW_ALLOCATE_ALT (0x03) /* Alternate representation of above */
1939 #define ACPI_PPTT_CACHE_TYPE_DATA (0x0) /* Data cache */
1940 #define ACPI_PPTT_CACHE_TYPE_INSTR (1<<2) /* Instruction cache */
1941 #define ACPI_PPTT_CACHE_TYPE_UNIFIED (2<<2) /* Unified I & D cache */
1942 #define ACPI_PPTT_CACHE_TYPE_UNIFIED_ALT (3<<2) /* Alternate representation of above */
1944 #define ACPI_PPTT_CACHE_POLICY_WB (0x0) /* Cache is write back */
1945 #define ACPI_PPTT_CACHE_POLICY_WT (1<<4) /* Cache is write through */
1947 /* 2: ID Structure */
1949 typedef struct acpi_pptt_id
1951 ACPI_SUBTABLE_HEADER Header;
1963 /*******************************************************************************
1965 * RASF - RAS Feature Table (ACPI 5.0)
1968 ******************************************************************************/
1970 typedef struct acpi_table_rasf
1972 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1973 UINT8 ChannelId[12];
1977 /* RASF Platform Communication Channel Shared Memory Region */
1979 typedef struct acpi_rasf_shared_memory
1985 UINT8 Capabilities[16];
1986 UINT8 SetCapabilities[16];
1987 UINT16 NumParameterBlocks;
1988 UINT32 SetCapabilitiesStatus;
1990 } ACPI_RASF_SHARED_MEMORY;
1992 /* RASF Parameter Block Structure Header */
1994 typedef struct acpi_rasf_parameter_block
2000 } ACPI_RASF_PARAMETER_BLOCK;
2002 /* RASF Parameter Block Structure for PATROL_SCRUB */
2004 typedef struct acpi_rasf_patrol_scrub_parameter
2006 ACPI_RASF_PARAMETER_BLOCK Header;
2007 UINT16 PatrolScrubCommand;
2008 UINT64 RequestedAddressRange[2];
2009 UINT64 ActualAddressRange[2];
2011 UINT8 RequestedSpeed;
2013 } ACPI_RASF_PATROL_SCRUB_PARAMETER;
2015 /* Masks for Flags and Speed fields above */
2017 #define ACPI_RASF_SCRUBBER_RUNNING 1
2018 #define ACPI_RASF_SPEED (7<<1)
2019 #define ACPI_RASF_SPEED_SLOW (0<<1)
2020 #define ACPI_RASF_SPEED_MEDIUM (4<<1)
2021 #define ACPI_RASF_SPEED_FAST (7<<1)
2023 /* Channel Commands */
2025 enum AcpiRasfCommands
2027 ACPI_RASF_EXECUTE_RASF_COMMAND = 1
2030 /* Platform RAS Capabilities */
2032 enum AcpiRasfCapabiliities
2034 ACPI_HW_PATROL_SCRUB_SUPPORTED = 0,
2035 ACPI_SW_PATROL_SCRUB_EXPOSED = 1
2038 /* Patrol Scrub Commands */
2040 enum AcpiRasfPatrolScrubCommands
2042 ACPI_RASF_GET_PATROL_PARAMETERS = 1,
2043 ACPI_RASF_START_PATROL_SCRUBBER = 2,
2044 ACPI_RASF_STOP_PATROL_SCRUBBER = 3
2047 /* Channel Command flags */
2049 #define ACPI_RASF_GENERATE_SCI (1<<15)
2055 ACPI_RASF_SUCCESS = 0,
2056 ACPI_RASF_NOT_VALID = 1,
2057 ACPI_RASF_NOT_SUPPORTED = 2,
2059 ACPI_RASF_FAILED = 4,
2060 ACPI_RASF_ABORTED = 5,
2061 ACPI_RASF_INVALID_DATA = 6
2066 #define ACPI_RASF_COMMAND_COMPLETE (1)
2067 #define ACPI_RASF_SCI_DOORBELL (1<<1)
2068 #define ACPI_RASF_ERROR (1<<2)
2069 #define ACPI_RASF_STATUS (0x1F<<3)
2072 /*******************************************************************************
2074 * SBST - Smart Battery Specification Table
2077 ******************************************************************************/
2079 typedef struct acpi_table_sbst
2081 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
2082 UINT32 WarningLevel;
2084 UINT32 CriticalLevel;
2089 /*******************************************************************************
2091 * SDEI - Software Delegated Exception Interface Descriptor Table
2093 * Conforms to "Software Delegated Exception Interface (SDEI)" ARM DEN0054A,
2094 * May 8th, 2017. Copyright 2017 ARM Ltd.
2096 ******************************************************************************/
2098 typedef struct acpi_table_sdei
2100 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
2105 /*******************************************************************************
2107 * SDEV - Secure Devices Table (ACPI 6.2)
2110 ******************************************************************************/
2112 typedef struct acpi_table_sdev
2114 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
2119 typedef struct acpi_sdev_header
2128 /* Values for subtable type above */
2132 ACPI_SDEV_TYPE_NAMESPACE_DEVICE = 0,
2133 ACPI_SDEV_TYPE_PCIE_ENDPOINT_DEVICE = 1,
2134 ACPI_SDEV_TYPE_RESERVED = 2 /* 2 and greater are reserved */
2137 /* Values for flags above */
2139 #define ACPI_SDEV_HANDOFF_TO_UNSECURE_OS (1)
2145 /* 0: Namespace Device Based Secure Device Structure */
2147 typedef struct acpi_sdev_namespace
2149 ACPI_SDEV_HEADER Header;
2150 UINT16 DeviceIdOffset;
2151 UINT16 DeviceIdLength;
2152 UINT16 VendorDataOffset;
2153 UINT16 VendorDataLength;
2155 } ACPI_SDEV_NAMESPACE;
2157 /* 1: PCIe Endpoint Device Based Device Structure */
2159 typedef struct acpi_sdev_pcie
2161 ACPI_SDEV_HEADER Header;
2166 UINT16 VendorDataOffset;
2167 UINT16 VendorDataLength;
2171 /* 1a: PCIe Endpoint path entry */
2173 typedef struct acpi_sdev_pcie_path
2178 } ACPI_SDEV_PCIE_PATH;
2181 /* Reset to default packing */
2185 #endif /* __ACTBL2_H__ */