2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
8 * This code is derived from software contributed to Berkeley by
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
43 //#include "use_npx.h"
45 #include "opt_compat.h"
48 #include "opt_directio.h"
51 #include "opt_msgbuf.h"
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/sysproto.h>
57 #include <sys/signalvar.h>
58 #include <sys/kernel.h>
59 #include <sys/linker.h>
60 #include <sys/malloc.h>
64 #include <sys/reboot.h>
66 #include <sys/msgbuf.h>
67 #include <sys/sysent.h>
68 #include <sys/sysctl.h>
69 #include <sys/vmmeter.h>
71 #include <sys/usched.h>
74 #include <sys/ctype.h>
75 #include <sys/serialize.h>
76 #include <sys/systimer.h>
79 #include <vm/vm_param.h>
81 #include <vm/vm_kern.h>
82 #include <vm/vm_object.h>
83 #include <vm/vm_page.h>
84 #include <vm/vm_map.h>
85 #include <vm/vm_pager.h>
86 #include <vm/vm_extern.h>
88 #include <sys/thread2.h>
89 #include <sys/mplock2.h>
90 #include <sys/mutex2.h>
98 #include <machine/cpu.h>
99 #include <machine/clock.h>
100 #include <machine/specialreg.h>
102 #include <machine/bootinfo.h>
104 #include <machine/md_var.h>
105 #include <machine/metadata.h>
106 #include <machine/pc/bios.h>
107 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
108 #include <machine/globaldata.h> /* CPU_prvspace */
109 #include <machine/smp.h>
111 #include <machine/perfmon.h>
113 #include <machine/cputypes.h>
114 #include <machine/intr_machdep.h>
117 #include <bus/isa/isa_device.h>
119 #include <machine_base/isa/isa_intr.h>
120 #include <bus/isa/rtc.h>
121 #include <sys/random.h>
122 #include <sys/ptrace.h>
123 #include <machine/sigframe.h>
125 #include <sys/machintr.h>
126 #include <machine_base/icu/icu_abi.h>
127 #include <machine_base/icu/elcr_var.h>
128 #include <machine_base/apic/lapic.h>
129 #include <machine_base/apic/ioapic.h>
130 #include <machine_base/apic/ioapic_abi.h>
131 #include <machine/mptable.h>
133 #define PHYSMAP_ENTRIES 10
135 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
137 extern void printcpuinfo(void); /* XXX header file */
138 extern void identify_cpu(void);
140 extern void finishidentcpu(void);
142 extern void panicifcpuunsupported(void);
144 static void cpu_startup(void *);
145 static void pic_finish(void *);
146 static void cpu_finish(void *);
148 #ifndef CPU_DISABLE_SSE
149 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
150 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
151 #endif /* CPU_DISABLE_SSE */
153 extern void ffs_rawread_setup(void);
154 #endif /* DIRECTIO */
155 static void init_locks(void);
157 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
158 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
159 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
162 extern vm_offset_t ksym_start, ksym_end;
165 struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */
167 int _udatasel, _ucodesel, _ucode32sel;
169 int64_t tsc_offsets[MAXCPU];
171 int cpu_mwait_halt; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */
173 #if defined(SWTCH_OPTIM_STATS)
174 extern int swtch_optim_stats;
175 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
176 CTLFLAG_RD, &swtch_optim_stats, 0, "");
177 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
178 CTLFLAG_RD, &tlb_flush_count, 0, "");
180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt,
181 CTLFLAG_RW, &cpu_mwait_halt, 0, "");
183 #define CPU_MWAIT_C1 1
184 #define CPU_MWAIT_C2 2
185 #define CPU_MWAIT_C3 3
186 #define CPU_MWAIT_CX_MAX 8
188 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */
189 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */
191 SYSCTL_NODE(_machdep, 0, mwait, CTLFLAG_RW, 0, "MWAIT features");
192 SYSCTL_NODE(_machdep_mwait, 0, CX, CTLFLAG_RW, 0, "MWAIT Cx settings");
194 struct cpu_mwait_cx {
197 struct sysctl_ctx_list sysctl_ctx;
198 struct sysctl_oid *sysctl_tree;
200 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX];
201 static char cpu_mwait_cx_supported[256];
203 static int cpu_mwait_hints_cnt;
204 static int *cpu_mwait_hints;
206 static int cpu_mwait_deep_hints_cnt;
207 static int *cpu_mwait_deep_hints;
209 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1
210 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2
212 static int cpu_mwait_c3_preamble =
213 CPU_MWAIT_C3_PREAMBLE_BM_ARB |
214 CPU_MWAIT_C3_PREAMBLE_BM_STS;
216 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD,
217 cpu_mwait_cx_supported, 0, "MWAIT supported C states");
219 static struct lwkt_serialize cpu_mwait_cx_slize = LWKT_SERIALIZE_INITIALIZER;
220 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS,
222 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS);
223 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS);
225 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW,
226 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", "");
227 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW,
228 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", "");
232 u_long ebda_addr = 0;
234 int imcr_present = 0;
236 int naps = 0; /* # of Applications processors */
239 struct mtx dt_lock; /* lock for GDT and LDT */
242 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
244 u_long pmem = ctob(physmem);
246 int error = sysctl_handle_long(oidp, &pmem, 0, req);
250 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
251 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
254 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
256 int error = sysctl_handle_int(oidp, 0,
257 ctob(physmem - vmstats.v_wire_count), req);
261 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
262 0, 0, sysctl_hw_usermem, "IU", "");
265 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
267 int error = sysctl_handle_int(oidp, 0,
268 x86_64_btop(avail_end - avail_start), req);
272 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
273 0, 0, sysctl_hw_availpages, "I", "");
279 * The number of PHYSMAP entries must be one less than the number of
280 * PHYSSEG entries because the PHYSMAP entry that spans the largest
281 * physical address that is accessible by ISA DMA is split into two
284 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
286 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
287 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
289 /* must be 2 less so 0 0 can signal end of chunks */
290 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
291 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
293 static vm_offset_t buffer_sva, buffer_eva;
294 vm_offset_t clean_sva, clean_eva;
295 static vm_offset_t pager_sva, pager_eva;
296 static struct trapframe proc0_tf;
299 cpu_startup(void *dummy)
303 vm_offset_t firstaddr;
306 * Good {morning,afternoon,evening,night}.
308 kprintf("%s", version);
311 panicifcpuunsupported();
315 kprintf("real memory = %ju (%ju MB)\n",
317 (intmax_t)Realmem / 1024 / 1024);
319 * Display any holes after the first chunk of extended memory.
324 kprintf("Physical memory chunk(s):\n");
325 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
326 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
328 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
329 (intmax_t)phys_avail[indx],
330 (intmax_t)phys_avail[indx + 1] - 1,
332 (intmax_t)(size1 / PAGE_SIZE));
337 * Allocate space for system data structures.
338 * The first available kernel virtual address is in "v".
339 * As pages of kernel virtual memory are allocated, "v" is incremented.
340 * As pages of memory are allocated and cleared,
341 * "firstaddr" is incremented.
342 * An index into the kernel page table corresponding to the
343 * virtual memory address maintained in "v" is kept in "mapaddr".
347 * Make two passes. The first pass calculates how much memory is
348 * needed and allocates it. The second pass assigns virtual
349 * addresses to the various data structures.
353 v = (caddr_t)firstaddr;
355 #define valloc(name, type, num) \
356 (name) = (type *)v; v = (caddr_t)((name)+(num))
357 #define valloclim(name, type, num, lim) \
358 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
361 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
362 * For the first 64MB of ram nominally allocate sufficient buffers to
363 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
364 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
365 * the buffer cache we limit the eventual kva reservation to
368 * factor represents the 1/4 x ram conversion.
371 long factor = 4 * BKVASIZE / 1024;
372 long kbytes = physmem * (PAGE_SIZE / 1024);
376 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
378 nbuf += (kbytes - 65536) * 2 / (factor * 5);
379 if (maxbcache && nbuf > maxbcache / BKVASIZE)
380 nbuf = maxbcache / BKVASIZE;
384 * Do not allow the buffer_map to be more then 1/2 the size of the
387 if (nbuf > (virtual_end - virtual_start +
388 virtual2_end - virtual2_start) / (BKVASIZE * 2)) {
389 nbuf = (virtual_end - virtual_start +
390 virtual2_end - virtual2_start) / (BKVASIZE * 2);
391 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
395 * Do not allow the buffer_map to use more than 50% of available
396 * physical-equivalent memory. Since the VM pages which back
397 * individual buffers are typically wired, having too many bufs
398 * can prevent the system from paging properly.
400 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) {
401 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2);
402 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
406 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
407 * the valloc space which is just the virtual_end - virtual_start
408 * section. We use valloc() to allocate the buf header array.
410 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
411 nbuf = (virtual_end - virtual_start) /
412 sizeof(struct buf) / 2;
413 kprintf("Warning: nbufs capped at %ld due to valloc "
414 "considerations", nbuf);
417 nswbuf = lmax(lmin(nbuf / 4, 256), 16);
419 if (nswbuf < NSWBUF_MIN)
426 valloc(swbuf, struct buf, nswbuf);
427 valloc(buf, struct buf, nbuf);
430 * End of first pass, size has been calculated so allocate memory
432 if (firstaddr == 0) {
433 size = (vm_size_t)(v - firstaddr);
434 firstaddr = kmem_alloc(&kernel_map, round_page(size));
436 panic("startup: no room for tables");
441 * End of second pass, addresses have been assigned
443 * nbuf is an int, make sure we don't overflow the field.
445 * On 64-bit systems we always reserve maximal allocations for
446 * buffer cache buffers and there are no fragmentation issues,
447 * so the KVA segment does not have to be excessively oversized.
449 if ((vm_size_t)(v - firstaddr) != size)
450 panic("startup: table size inconsistency");
452 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
453 ((vm_offset_t)(nbuf + 16) * BKVASIZE) +
454 (nswbuf * MAXPHYS) + pager_map_size);
455 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
456 ((vm_offset_t)(nbuf + 16) * BKVASIZE));
457 buffer_map.system_map = 1;
458 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
459 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size);
460 pager_map.system_map = 1;
462 #if defined(USERCONFIG)
464 cninit(); /* the preferred console may have changed */
467 kprintf("avail memory = %ju (%ju MB)\n",
468 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
469 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
473 struct cpu_idle_stat {
478 u_long mwait_cx[CPU_MWAIT_CX_MAX];
481 #define CPU_IDLE_STAT_HALT -1
482 #define CPU_IDLE_STAT_SPIN -2
484 static struct cpu_idle_stat cpu_idle_stats[MAXCPU];
487 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS)
489 int idx = arg2, cpu, error;
492 if (idx == CPU_IDLE_STAT_HALT) {
493 for (cpu = 0; cpu < ncpus; ++cpu)
494 val += cpu_idle_stats[cpu].halt;
495 } else if (idx == CPU_IDLE_STAT_SPIN) {
496 for (cpu = 0; cpu < ncpus; ++cpu)
497 val += cpu_idle_stats[cpu].spin;
499 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
500 ("invalid index %d", idx));
501 for (cpu = 0; cpu < ncpus; ++cpu)
502 val += cpu_idle_stats[cpu].mwait_cx[idx];
505 error = sysctl_handle_quad(oidp, &val, 0, req);
506 if (error || req->newptr == NULL)
509 if (idx == CPU_IDLE_STAT_HALT) {
510 for (cpu = 0; cpu < ncpus; ++cpu)
511 cpu_idle_stats[cpu].halt = 0;
512 cpu_idle_stats[0].halt = val;
513 } else if (idx == CPU_IDLE_STAT_SPIN) {
514 for (cpu = 0; cpu < ncpus; ++cpu)
515 cpu_idle_stats[cpu].spin = 0;
516 cpu_idle_stats[0].spin = val;
518 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
519 ("invalid index %d", idx));
520 for (cpu = 0; cpu < ncpus; ++cpu)
521 cpu_idle_stats[cpu].mwait_cx[idx] = 0;
522 cpu_idle_stats[0].mwait_cx[idx] = val;
528 cpu_finish(void *dummy __unused)
534 if ((cpu_feature2 & CPUID2_MON) &&
535 (cpu_mwait_feature & CPUID_MWAIT_EXT)) {
539 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
540 (CPUID_TO_FAMILY(cpu_id) > 0xf ||
541 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
542 CPUID_TO_MODEL(cpu_id) >= 0xf))) {
543 atomic_clear_int(&cpu_mwait_c3_preamble,
544 CPU_MWAIT_C3_PREAMBLE_BM_ARB);
547 sbuf_new(&sb, cpu_mwait_cx_supported,
548 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN);
550 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) {
551 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i];
554 ksnprintf(cx->name, sizeof(cx->name), "C%d", i);
556 sysctl_ctx_init(&cx->sysctl_ctx);
557 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx,
558 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO,
559 cx->name, CTLFLAG_RW, NULL, "Cx control/info");
560 if (cx->sysctl_tree == NULL)
563 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i);
564 SYSCTL_ADD_INT(&cx->sysctl_ctx,
565 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
566 "subcnt", CTLFLAG_RD, &cx->subcnt, 0,
568 SYSCTL_ADD_PROC(&cx->sysctl_ctx,
569 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
570 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0,
571 i, sysctl_cpu_idle_cnt, "Q", "# of times entered");
573 for (sub = 0; sub < cx->subcnt; ++sub)
574 sbuf_printf(&sb, "C%d/%d ", i, sub);
582 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i)
583 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt;
584 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt,
588 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) {
591 subcnt = cpu_mwait_cx_info[i].subcnt;
592 for (j = 0; j < subcnt; ++j) {
593 KASSERT(hint_idx < cpu_mwait_hints_cnt,
594 ("invalid mwait hint index %d", hint_idx));
595 cpu_mwait_hints[hint_idx] =
596 MWAIT_EAX_HINT(i, j);
600 KASSERT(hint_idx == cpu_mwait_hints_cnt,
601 ("mwait hint count %d != index %d",
602 cpu_mwait_hints_cnt, hint_idx));
605 kprintf("MWAIT hints:\n");
606 for (i = 0; i < cpu_mwait_hints_cnt; ++i) {
607 int hint = cpu_mwait_hints[i];
609 kprintf(" C%d/%d hint 0x%04x\n",
610 MWAIT_EAX_TO_CX(hint),
611 MWAIT_EAX_TO_CX_SUB(hint), hint);
618 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i)
619 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt;
620 cpu_mwait_deep_hints =
621 kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt,
625 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) {
628 subcnt = cpu_mwait_cx_info[i].subcnt;
629 for (j = 0; j < subcnt; ++j) {
630 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt,
631 ("invalid mwait deep hint index %d",
633 cpu_mwait_deep_hints[hint_idx] =
634 MWAIT_EAX_HINT(i, j);
638 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt,
639 ("mwait deep hint count %d != index %d",
640 cpu_mwait_deep_hints_cnt, hint_idx));
643 kprintf("MWAIT deep hints:\n");
644 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) {
645 int hint = cpu_mwait_deep_hints[i];
647 kprintf(" C%d/%d hint 0x%04x\n",
648 MWAIT_EAX_TO_CX(hint),
649 MWAIT_EAX_TO_CX_SUB(hint), hint);
656 pic_finish(void *dummy __unused)
658 /* Log ELCR information */
661 /* Log MPTABLE information */
662 mptable_pci_int_dump();
665 MachIntrABI.finalize();
669 * Send an interrupt to process.
671 * Stack is set up to allow sigcode stored
672 * at top to call routine, followed by kcall
673 * to sigreturn routine below. After sigreturn
674 * resets the signal mask, the stack, and the
675 * frame pointer, it returns to the user
679 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
681 struct lwp *lp = curthread->td_lwp;
682 struct proc *p = lp->lwp_proc;
683 struct trapframe *regs;
684 struct sigacts *psp = p->p_sigacts;
685 struct sigframe sf, *sfp;
689 regs = lp->lwp_md.md_regs;
690 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
692 /* Save user context */
693 bzero(&sf, sizeof(struct sigframe));
694 sf.sf_uc.uc_sigmask = *mask;
695 sf.sf_uc.uc_stack = lp->lwp_sigstk;
696 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
697 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
698 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
700 /* Make the size of the saved context visible to userland */
701 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
703 /* Allocate and validate space for the signal handler context. */
704 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
705 SIGISMEMBER(psp->ps_sigonstack, sig)) {
706 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
707 sizeof(struct sigframe));
708 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
710 /* We take red zone into account */
711 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
715 * XXX AVX needs 64-byte alignment but sigframe has other fields and
716 * the embedded ucontext is not at the front, so aligning this won't
717 * help us. Fortunately we bcopy in/out of the sigframe, so the
720 * The problem though is if userland winds up trying to use the
723 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
725 /* Translate the signal is appropriate */
726 if (p->p_sysent->sv_sigtbl) {
727 if (sig <= p->p_sysent->sv_sigsize)
728 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
732 * Build the argument list for the signal handler.
734 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
736 regs->tf_rdi = sig; /* argument 1 */
737 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
739 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
741 * Signal handler installed with SA_SIGINFO.
743 * action(signo, siginfo, ucontext)
745 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
746 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
747 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
749 /* fill siginfo structure */
750 sf.sf_si.si_signo = sig;
751 sf.sf_si.si_code = code;
752 sf.sf_si.si_addr = (void *)regs->tf_addr;
755 * Old FreeBSD-style arguments.
757 * handler (signo, code, [uc], addr)
759 regs->tf_rsi = (register_t)code; /* argument 2 */
760 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
761 sf.sf_ahu.sf_handler = catcher;
765 * If we're a vm86 process, we want to save the segment registers.
766 * We also change eflags to be our emulated eflags, not the actual
770 if (regs->tf_eflags & PSL_VM) {
771 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
772 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
774 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
775 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
776 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
777 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
779 if (vm86->vm86_has_vme == 0)
780 sf.sf_uc.uc_mcontext.mc_eflags =
781 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
782 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
785 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
786 * syscalls made by the signal handler. This just avoids
787 * wasting time for our lazy fixup of such faults. PSL_NT
788 * does nothing in vm86 mode, but vm86 programs can set it
789 * almost legitimately in probes for old cpu types.
791 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
796 * Save the FPU state and reinit the FP unit
798 npxpush(&sf.sf_uc.uc_mcontext);
801 * Copy the sigframe out to the user's stack.
803 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
805 * Something is wrong with the stack pointer.
806 * ...Kill the process.
811 regs->tf_rsp = (register_t)sfp;
812 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
815 * i386 abi specifies that the direction flag must be cleared
818 regs->tf_rflags &= ~(PSL_T|PSL_D);
821 * 64 bit mode has a code and stack selector but
822 * no data or extra selector. %fs and %gs are not
825 regs->tf_cs = _ucodesel;
826 regs->tf_ss = _udatasel;
831 * Sanitize the trapframe for a virtual kernel passing control to a custom
832 * VM context. Remove any items that would otherwise create a privilage
835 * XXX at the moment we allow userland to set the resume flag. Is this a
839 cpu_sanitize_frame(struct trapframe *frame)
841 frame->tf_cs = _ucodesel;
842 frame->tf_ss = _udatasel;
843 /* XXX VM (8086) mode not supported? */
844 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
845 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
851 * Sanitize the tls so loading the descriptor does not blow up
852 * on us. For x86_64 we don't have to do anything.
855 cpu_sanitize_tls(struct savetls *tls)
861 * sigreturn(ucontext_t *sigcntxp)
863 * System call to cleanup state after a signal
864 * has been taken. Reset signal mask and
865 * stack state from context left by sendsig (above).
866 * Return to previous pc and psl as specified by
867 * context left by sendsig. Check carefully to
868 * make sure that the user has not modified the
869 * state to gain improper privileges.
873 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
874 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
877 sys_sigreturn(struct sigreturn_args *uap)
879 struct lwp *lp = curthread->td_lwp;
880 struct trapframe *regs;
888 * We have to copy the information into kernel space so userland
889 * can't modify it while we are sniffing it.
891 regs = lp->lwp_md.md_regs;
892 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
896 rflags = ucp->uc_mcontext.mc_rflags;
898 /* VM (8086) mode not supported */
899 rflags &= ~PSL_VM_UNSUPP;
902 if (eflags & PSL_VM) {
903 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
904 struct vm86_kernel *vm86;
907 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
908 * set up the vm86 area, and we can't enter vm86 mode.
910 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
912 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
913 if (vm86->vm86_inited == 0)
916 /* go back to user mode if both flags are set */
917 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
918 trapsignal(lp, SIGBUS, 0);
920 if (vm86->vm86_has_vme) {
921 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
922 (eflags & VME_USERCHANGE) | PSL_VM;
924 vm86->vm86_eflags = eflags; /* save VIF, VIP */
925 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
926 (eflags & VM_USERCHANGE) | PSL_VM;
928 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
929 tf->tf_eflags = eflags;
930 tf->tf_vm86_ds = tf->tf_ds;
931 tf->tf_vm86_es = tf->tf_es;
932 tf->tf_vm86_fs = tf->tf_fs;
933 tf->tf_vm86_gs = tf->tf_gs;
934 tf->tf_ds = _udatasel;
935 tf->tf_es = _udatasel;
936 tf->tf_fs = _udatasel;
937 tf->tf_gs = _udatasel;
942 * Don't allow users to change privileged or reserved flags.
945 * XXX do allow users to change the privileged flag PSL_RF.
946 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
947 * should sometimes set it there too. tf_eflags is kept in
948 * the signal context during signal handling and there is no
949 * other place to remember it, so the PSL_RF bit may be
950 * corrupted by the signal handler without us knowing.
951 * Corruption of the PSL_RF bit at worst causes one more or
952 * one less debugger trap, so allowing it is fairly harmless.
954 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
955 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
960 * Don't allow users to load a valid privileged %cs. Let the
961 * hardware check for invalid selectors, excess privilege in
962 * other selectors, invalid %eip's and invalid %esp's.
964 cs = ucp->uc_mcontext.mc_cs;
965 if (!CS_SECURE(cs)) {
966 kprintf("sigreturn: cs = 0x%x\n", cs);
967 trapsignal(lp, SIGBUS, T_PROTFLT);
970 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
974 * Restore the FPU state from the frame
977 npxpop(&ucp->uc_mcontext);
979 if (ucp->uc_mcontext.mc_onstack & 1)
980 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
982 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
984 lp->lwp_sigmask = ucp->uc_sigmask;
985 SIG_CANTMASK(lp->lwp_sigmask);
992 * Machine dependent boot() routine
994 * I haven't seen anything to put here yet
995 * Possibly some stuff might be grafted back here from boot()
1003 * Shutdown the CPU as much as possible
1009 __asm__ __volatile("hlt");
1013 * cpu_idle() represents the idle LWKT. You cannot return from this function
1014 * (unless you want to blow things up!). Instead we look for runnable threads
1015 * and loop or halt as appropriate. Giant is not held on entry to the thread.
1017 * The main loop is entered with a critical section held, we must release
1018 * the critical section before doing anything else. lwkt_switch() will
1019 * check for pending interrupts due to entering and exiting its own
1022 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
1023 * However, there are cases where the idlethread will be entered with
1024 * the possibility that no IPI will occur and in such cases
1025 * lwkt_switch() sets TDF_IDLE_NOHLT.
1027 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
1028 * must occur before it starts using ACPI halt.
1030 static int cpu_idle_hlt = 2;
1031 static u_int cpu_idle_repeat = 750;
1032 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
1033 &cpu_idle_hlt, 0, "Idle loop HLT enable");
1034 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
1035 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
1037 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1038 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts");
1039 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1040 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins");
1043 cpu_idle_default_hook(void)
1046 * We must guarentee that hlt is exactly the instruction
1047 * following the sti.
1049 __asm __volatile("sti; hlt");
1052 /* Other subsystems (e.g., ACPI) can hook this later. */
1053 void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
1056 cpu_mwait_cx_hint(struct cpu_idle_stat *stat)
1061 if (cpu_mwait_halt >= 0) {
1062 hint = cpu_mwait_halt;
1066 idx = (stat->repeat + stat->repeat_last) >> 1;
1067 if (cpu_mwait_halt == CPU_MWAIT_HINT_AUTODEEP) {
1068 if (idx >= cpu_mwait_deep_hints_cnt)
1069 idx = cpu_mwait_deep_hints_cnt - 1;
1070 hint = cpu_mwait_deep_hints[idx];
1072 if (idx >= cpu_mwait_hints_cnt)
1073 idx = cpu_mwait_hints_cnt - 1;
1074 hint = cpu_mwait_hints[idx];
1077 cx_idx = MWAIT_EAX_TO_CX(hint);
1078 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX)
1079 stat->mwait_cx[cx_idx]++;
1086 globaldata_t gd = mycpu;
1087 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid];
1088 struct thread *td __debugvar = gd->gd_curthread;
1093 KKASSERT(td->td_critcount == 0);
1096 * See if there are any LWKTs ready to go.
1101 * When halting inside a cli we must check for reqflags
1102 * races, particularly [re]schedule requests. Running
1103 * splz() does the job.
1106 * 0 Never halt, just spin
1108 * 1 Always use HLT (or MONITOR/MWAIT if avail).
1109 * This typically eats more power than the
1112 * 2 Use HLT/MONITOR/MWAIT up to a point and then
1113 * use the ACPI halt (default). This is a hybrid
1114 * approach. See machdep.cpu_idle_repeat.
1116 * 3 Always use the ACPI halt. This typically
1117 * eats the least amount of power but the cpu
1118 * will be slow waking up. Slows down e.g.
1119 * compiles and other pipe/event oriented stuff.
1121 * NOTE: Interrupts are enabled and we are not in a critical
1124 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1125 * don't bother capping gd_idle_repeat, it is ok if
1128 if (gd->gd_idle_repeat == 0) {
1129 stat->repeat = (stat->repeat + stat->repeat_last) >> 1;
1130 stat->repeat_last = 0;
1132 ++stat->repeat_last;
1133 ++gd->gd_idle_repeat;
1134 reqflags = gd->gd_reqflags;
1135 quick = (cpu_idle_hlt == 1) ||
1136 (cpu_idle_hlt < 3 &&
1137 gd->gd_idle_repeat < cpu_idle_repeat);
1139 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
1140 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1142 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags,
1143 cpu_mwait_cx_hint(stat), 0);
1145 } else if (cpu_idle_hlt) {
1146 __asm __volatile("cli");
1148 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1150 cpu_idle_default_hook();
1154 __asm __volatile("sti");
1158 __asm __volatile("sti");
1165 * This routine is called if a spinlock has been held through the
1166 * exponential backoff period and is seriously contested. On a real cpu
1170 cpu_spinlock_contested(void)
1176 * Clear registers on exec
1179 exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1181 struct thread *td = curthread;
1182 struct lwp *lp = td->td_lwp;
1183 struct pcb *pcb = td->td_pcb;
1184 struct trapframe *regs = lp->lwp_md.md_regs;
1186 /* was i386_user_cleanup() in NetBSD */
1190 bzero((char *)regs, sizeof(struct trapframe));
1191 regs->tf_rip = entry;
1192 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1193 regs->tf_rdi = stack; /* argv */
1194 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1195 regs->tf_ss = _udatasel;
1196 regs->tf_cs = _ucodesel;
1197 regs->tf_rbx = ps_strings;
1200 * Reset the hardware debug registers if they were in use.
1201 * They won't have any meaning for the newly exec'd process.
1203 if (pcb->pcb_flags & PCB_DBREGS) {
1209 pcb->pcb_dr7 = 0; /* JG set bit 10? */
1210 if (pcb == td->td_pcb) {
1212 * Clear the debug registers on the running
1213 * CPU, otherwise they will end up affecting
1214 * the next process we switch to.
1218 pcb->pcb_flags &= ~PCB_DBREGS;
1222 * Initialize the math emulator (if any) for the current process.
1223 * Actually, just clear the bit that says that the emulator has
1224 * been initialized. Initialization is delayed until the process
1225 * traps to the emulator (if it is done at all) mainly because
1226 * emulators don't provide an entry point for initialization.
1228 pcb->pcb_flags &= ~FP_SOFTFP;
1231 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1232 * gd_npxthread. Otherwise a preemptive interrupt thread
1233 * may panic in npxdna().
1236 load_cr0(rcr0() | CR0_MP);
1239 * NOTE: The MSR values must be correct so we can return to
1240 * userland. gd_user_fs/gs must be correct so the switch
1241 * code knows what the current MSR values are.
1243 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
1244 pcb->pcb_gsbase = 0;
1245 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1246 mdcpu->gd_user_gs = 0;
1247 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1248 wrmsr(MSR_KGSBASE, 0);
1250 /* Initialize the npx (if any) for the current process. */
1251 npxinit(__INITIAL_FPUCW__);
1254 pcb->pcb_ds = _udatasel;
1255 pcb->pcb_es = _udatasel;
1256 pcb->pcb_fs = _udatasel;
1257 pcb->pcb_gs = _udatasel;
1266 cr0 |= CR0_NE; /* Done by npxinit() */
1267 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1268 cr0 |= CR0_WP | CR0_AM;
1274 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1277 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1279 if (!error && req->newptr)
1284 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1285 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1287 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1288 CTLFLAG_RW, &disable_rtc_set, 0, "");
1291 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1292 CTLFLAG_RD, &bootinfo, bootinfo, "");
1295 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1296 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1298 extern u_long bootdev; /* not a cdev_t - encoding is different */
1299 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1300 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1303 * Initialize 386 and configure to run kernel
1307 * Initialize segments & interrupt table
1311 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1312 struct gate_descriptor idt_arr[MAXCPU][NIDT];
1314 union descriptor ldt[NLDT]; /* local descriptor table */
1317 /* table descriptors - used to load tables by cpu */
1318 struct region_descriptor r_gdt;
1319 struct region_descriptor r_idt_arr[MAXCPU];
1321 /* JG proc0paddr is a virtual address */
1324 char proc0paddr_buff[LWKT_THREAD_STACK];
1327 /* software prototypes -- in more palatable form */
1328 struct soft_segment_descriptor gdt_segs[] = {
1329 /* GNULL_SEL 0 Null Descriptor */
1330 { 0x0, /* segment base address */
1332 0, /* segment type */
1333 0, /* segment descriptor priority level */
1334 0, /* segment descriptor present */
1336 0, /* default 32 vs 16 bit size */
1337 0 /* limit granularity (byte/page units)*/ },
1338 /* GCODE_SEL 1 Code Descriptor for kernel */
1339 { 0x0, /* segment base address */
1340 0xfffff, /* length - all address space */
1341 SDT_MEMERA, /* segment type */
1342 SEL_KPL, /* segment descriptor priority level */
1343 1, /* segment descriptor present */
1345 0, /* default 32 vs 16 bit size */
1346 1 /* limit granularity (byte/page units)*/ },
1347 /* GDATA_SEL 2 Data Descriptor for kernel */
1348 { 0x0, /* segment base address */
1349 0xfffff, /* length - all address space */
1350 SDT_MEMRWA, /* segment type */
1351 SEL_KPL, /* segment descriptor priority level */
1352 1, /* segment descriptor present */
1354 0, /* default 32 vs 16 bit size */
1355 1 /* limit granularity (byte/page units)*/ },
1356 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1357 { 0x0, /* segment base address */
1358 0xfffff, /* length - all address space */
1359 SDT_MEMERA, /* segment type */
1360 SEL_UPL, /* segment descriptor priority level */
1361 1, /* segment descriptor present */
1363 1, /* default 32 vs 16 bit size */
1364 1 /* limit granularity (byte/page units)*/ },
1365 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1366 { 0x0, /* segment base address */
1367 0xfffff, /* length - all address space */
1368 SDT_MEMRWA, /* segment type */
1369 SEL_UPL, /* segment descriptor priority level */
1370 1, /* segment descriptor present */
1372 1, /* default 32 vs 16 bit size */
1373 1 /* limit granularity (byte/page units)*/ },
1374 /* GUCODE_SEL 5 64 bit Code Descriptor for user */
1375 { 0x0, /* segment base address */
1376 0xfffff, /* length - all address space */
1377 SDT_MEMERA, /* segment type */
1378 SEL_UPL, /* segment descriptor priority level */
1379 1, /* segment descriptor present */
1381 0, /* default 32 vs 16 bit size */
1382 1 /* limit granularity (byte/page units)*/ },
1383 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1385 0x0, /* segment base address */
1386 sizeof(struct x86_64tss)-1,/* length - all address space */
1387 SDT_SYSTSS, /* segment type */
1388 SEL_KPL, /* segment descriptor priority level */
1389 1, /* segment descriptor present */
1391 0, /* unused - default 32 vs 16 bit size */
1392 0 /* limit granularity (byte/page units)*/ },
1393 /* Actually, the TSS is a system descriptor which is double size */
1394 { 0x0, /* segment base address */
1396 0, /* segment type */
1397 0, /* segment descriptor priority level */
1398 0, /* segment descriptor present */
1400 0, /* default 32 vs 16 bit size */
1401 0 /* limit granularity (byte/page units)*/ },
1402 /* GUGS32_SEL 8 32 bit GS Descriptor for user */
1403 { 0x0, /* segment base address */
1404 0xfffff, /* length - all address space */
1405 SDT_MEMRWA, /* segment type */
1406 SEL_UPL, /* segment descriptor priority level */
1407 1, /* segment descriptor present */
1409 1, /* default 32 vs 16 bit size */
1410 1 /* limit granularity (byte/page units)*/ },
1414 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
1418 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1419 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1421 ip->gd_looffset = (uintptr_t)func;
1422 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1428 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1433 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1435 struct gate_descriptor *ip;
1437 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
1439 ip = &idt_arr[cpu][idx];
1440 ip->gd_looffset = (uintptr_t)func;
1441 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1447 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1450 #define IDTVEC(name) __CONCAT(X,name)
1453 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1454 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1455 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1456 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1457 IDTVEC(xmm), IDTVEC(dblfault),
1458 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1460 #ifdef DEBUG_INTERRUPTS
1461 extern inthand_t *Xrsvdary[256];
1465 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1467 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1468 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1469 ssd->ssd_type = sd->sd_type;
1470 ssd->ssd_dpl = sd->sd_dpl;
1471 ssd->ssd_p = sd->sd_p;
1472 ssd->ssd_def32 = sd->sd_def32;
1473 ssd->ssd_gran = sd->sd_gran;
1477 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1480 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1481 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1482 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1483 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1484 sd->sd_type = ssd->ssd_type;
1485 sd->sd_dpl = ssd->ssd_dpl;
1486 sd->sd_p = ssd->ssd_p;
1487 sd->sd_long = ssd->ssd_long;
1488 sd->sd_def32 = ssd->ssd_def32;
1489 sd->sd_gran = ssd->ssd_gran;
1493 ssdtosyssd(struct soft_segment_descriptor *ssd,
1494 struct system_segment_descriptor *sd)
1497 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1498 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1499 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1500 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1501 sd->sd_type = ssd->ssd_type;
1502 sd->sd_dpl = ssd->ssd_dpl;
1503 sd->sd_p = ssd->ssd_p;
1504 sd->sd_gran = ssd->ssd_gran;
1508 * Populate the (physmap) array with base/bound pairs describing the
1509 * available physical memory in the system, then test this memory and
1510 * build the phys_avail array describing the actually-available memory.
1512 * If we cannot accurately determine the physical memory map, then use
1513 * value from the 0xE801 call, and failing that, the RTC.
1515 * Total memory size may be set by the kernel environment variable
1516 * hw.physmem or the compile-time define MAXMEM.
1518 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1519 * of PAGE_SIZE. This also greatly reduces the memory test time
1520 * which would otherwise be excessive on machines with > 8G of ram.
1522 * XXX first should be vm_paddr_t.
1525 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1526 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1529 getmemsize(caddr_t kmdp, u_int64_t first)
1531 int off, physmap_idx, pa_indx, da_indx;
1533 vm_paddr_t physmap[PHYSMAP_SIZE];
1535 vm_paddr_t msgbuf_size;
1536 u_long physmem_tunable;
1538 struct bios_smap *smapbase, *smap, *smapend;
1540 quad_t dcons_addr, dcons_size;
1542 bzero(physmap, sizeof(physmap));
1546 * get memory map from INT 15:E820, kindly supplied by the loader.
1548 * subr_module.c says:
1549 * "Consumer may safely assume that size value precedes data."
1550 * ie: an int32_t immediately precedes smap.
1552 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1553 MODINFO_METADATA | MODINFOMD_SMAP);
1554 if (smapbase == NULL)
1555 panic("No BIOS smap info from loader!");
1557 smapsize = *((u_int32_t *)smapbase - 1);
1558 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1560 for (smap = smapbase; smap < smapend; smap++) {
1561 if (boothowto & RB_VERBOSE)
1562 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1563 smap->type, smap->base, smap->length);
1565 if (smap->type != SMAP_TYPE_MEMORY)
1568 if (smap->length == 0)
1571 for (i = 0; i <= physmap_idx; i += 2) {
1572 if (smap->base < physmap[i + 1]) {
1573 if (boothowto & RB_VERBOSE) {
1574 kprintf("Overlapping or non-monotonic "
1575 "memory region, ignoring "
1581 if (i <= physmap_idx)
1584 Realmem += smap->length;
1586 if (smap->base == physmap[physmap_idx + 1]) {
1587 physmap[physmap_idx + 1] += smap->length;
1592 if (physmap_idx == PHYSMAP_SIZE) {
1593 kprintf("Too many segments in the physical "
1594 "address map, giving up\n");
1597 physmap[physmap_idx] = smap->base;
1598 physmap[physmap_idx + 1] = smap->base + smap->length;
1601 base_memory = physmap[1] / 1024;
1602 /* make hole for AP bootstrap code */
1603 physmap[1] = mp_bootaddress(base_memory);
1605 /* Save EBDA address, if any */
1606 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1610 * Maxmem isn't the "maximum memory", it's one larger than the
1611 * highest page of the physical address space. It should be
1612 * called something like "Maxphyspage". We may adjust this
1613 * based on ``hw.physmem'' and the results of the memory test.
1615 Maxmem = atop(physmap[physmap_idx + 1]);
1618 Maxmem = MAXMEM / 4;
1621 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1622 Maxmem = atop(physmem_tunable);
1625 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1628 if (Maxmem > atop(physmap[physmap_idx + 1]))
1629 Maxmem = atop(physmap[physmap_idx + 1]);
1632 * Blowing out the DMAP will blow up the system.
1634 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1635 kprintf("Limiting Maxmem due to DMAP size\n");
1636 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1639 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1640 (boothowto & RB_VERBOSE)) {
1641 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
1645 * Call pmap initialization to make new kernel address space
1649 pmap_bootstrap(&first);
1650 physmap[0] = PAGE_SIZE;
1653 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1656 for (i = j = 0; i <= physmap_idx; i += 2) {
1657 if (physmap[i+1] > ptoa(Maxmem))
1658 physmap[i+1] = ptoa(Maxmem);
1659 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1660 ~PHYSMAP_ALIGN_MASK;
1661 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1663 physmap[j] = physmap[i];
1664 physmap[j+1] = physmap[i+1];
1666 if (physmap[i] < physmap[i+1])
1669 physmap_idx = j - 2;
1672 * Align anything else used in the validation loop.
1674 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1677 * Size up each available chunk of physical memory.
1681 phys_avail[pa_indx++] = physmap[0];
1682 phys_avail[pa_indx] = physmap[0];
1683 dump_avail[da_indx] = physmap[0];
1687 * Get dcons buffer address
1689 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1690 kgetenv_quad("dcons.size", &dcons_size) == 0)
1694 * Validate the physical memory. The physical memory segments
1695 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1698 for (i = 0; i <= physmap_idx; i += 2) {
1701 end = physmap[i + 1];
1703 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
1704 int tmp, page_bad, full;
1705 int *ptr = (int *)CADDR1;
1709 * block out kernel memory as not available.
1711 if (pa >= 0x200000 && pa < first)
1715 * block out dcons buffer
1718 && pa >= trunc_page(dcons_addr)
1719 && pa < dcons_addr + dcons_size) {
1726 * map page into kernel: valid, read/write,non-cacheable
1729 kernel_pmap.pmap_bits[PG_V_IDX] |
1730 kernel_pmap.pmap_bits[PG_RW_IDX] |
1731 kernel_pmap.pmap_bits[PG_N_IDX];
1736 * Test for alternating 1's and 0's
1738 *(volatile int *)ptr = 0xaaaaaaaa;
1740 if (*(volatile int *)ptr != 0xaaaaaaaa)
1743 * Test for alternating 0's and 1's
1745 *(volatile int *)ptr = 0x55555555;
1747 if (*(volatile int *)ptr != 0x55555555)
1752 *(volatile int *)ptr = 0xffffffff;
1754 if (*(volatile int *)ptr != 0xffffffff)
1759 *(volatile int *)ptr = 0x0;
1761 if (*(volatile int *)ptr != 0x0)
1764 * Restore original value.
1769 * Adjust array of valid/good pages.
1771 if (page_bad == TRUE)
1774 * If this good page is a continuation of the
1775 * previous set of good pages, then just increase
1776 * the end pointer. Otherwise start a new chunk.
1777 * Note that "end" points one higher than end,
1778 * making the range >= start and < end.
1779 * If we're also doing a speculative memory
1780 * test and we at or past the end, bump up Maxmem
1781 * so that we keep going. The first bad page
1782 * will terminate the loop.
1784 if (phys_avail[pa_indx] == pa) {
1785 phys_avail[pa_indx] += PHYSMAP_ALIGN;
1788 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1790 "Too many holes in the physical address space, giving up\n");
1795 phys_avail[pa_indx++] = pa;
1796 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
1798 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
1800 if (dump_avail[da_indx] == pa) {
1801 dump_avail[da_indx] += PHYSMAP_ALIGN;
1804 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1808 dump_avail[da_indx++] = pa;
1809 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
1820 * The last chunk must contain at least one page plus the message
1821 * buffer to avoid complicating other code (message buffer address
1822 * calculation, etc.).
1824 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1826 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1827 msgbuf_size >= phys_avail[pa_indx]) {
1828 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1829 phys_avail[pa_indx--] = 0;
1830 phys_avail[pa_indx--] = 0;
1833 Maxmem = atop(phys_avail[pa_indx]);
1835 /* Trim off space for the message buffer. */
1836 phys_avail[pa_indx] -= msgbuf_size;
1838 avail_end = phys_avail[pa_indx];
1840 /* Map the message buffer. */
1841 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1842 pmap_kenter((vm_offset_t)msgbufp + off,
1843 phys_avail[pa_indx] + off);
1847 struct machintr_abi MachIntrABI;
1858 * 7 Device Not Available (x87)
1860 * 9 Coprocessor Segment overrun (unsupported, reserved)
1862 * 11 Segment not present
1864 * 13 General Protection
1867 * 16 x87 FP Exception pending
1868 * 17 Alignment Check
1870 * 19 SIMD floating point
1872 * 32-255 INTn/external sources
1875 hammer_time(u_int64_t modulep, u_int64_t physfree)
1878 int gsel_tss, x, cpu;
1880 int metadata_missing, off;
1882 struct mdglobaldata *gd;
1886 * Prevent lowering of the ipl if we call tsleep() early.
1888 gd = &CPU_prvspace[0].mdglobaldata;
1889 bzero(gd, sizeof(*gd));
1892 * Note: on both UP and SMP curthread must be set non-NULL
1893 * early in the boot sequence because the system assumes
1894 * that 'curthread' is never NULL.
1897 gd->mi.gd_curthread = &thread0;
1898 thread0.td_gd = &gd->mi;
1900 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1903 metadata_missing = 0;
1904 if (bootinfo.bi_modulep) {
1905 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1906 preload_bootstrap_relocate(KERNBASE);
1908 metadata_missing = 1;
1910 if (bootinfo.bi_envp)
1911 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1914 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1915 preload_bootstrap_relocate(PTOV_OFFSET);
1916 kmdp = preload_search_by_type("elf kernel");
1918 kmdp = preload_search_by_type("elf64 kernel");
1919 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1920 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1922 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1923 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1926 if (boothowto & RB_VERBOSE)
1930 * Default MachIntrABI to ICU
1932 MachIntrABI = MachIntrABI_ICU;
1935 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1936 * and ncpus_fit_mask remain 0.
1941 /* Init basic tunables, hz etc */
1945 * make gdt memory segments
1947 gdt_segs[GPROC0_SEL].ssd_base =
1948 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
1950 gd->mi.gd_prvspace = &CPU_prvspace[0];
1952 for (x = 0; x < NGDT; x++) {
1953 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
1954 ssdtosd(&gdt_segs[x], &gdt[x]);
1956 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1957 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
1959 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1960 r_gdt.rd_base = (long) gdt;
1963 wrmsr(MSR_FSBASE, 0); /* User value */
1964 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
1965 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1967 mi_gdinit(&gd->mi, 0);
1969 proc0paddr = proc0paddr_buff;
1970 mi_proc0init(&gd->mi, proc0paddr);
1971 safepri = TDPRI_MAX;
1973 /* spinlocks and the BGL */
1977 for (x = 0; x < NIDT; x++)
1978 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
1979 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
1980 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
1981 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
1982 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
1983 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
1984 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
1985 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
1986 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
1987 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
1988 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
1989 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
1990 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
1991 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
1992 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
1993 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
1994 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
1995 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
1996 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
1997 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
1999 for (cpu = 0; cpu < MAXCPU; ++cpu) {
2000 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
2001 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
2004 lidt(&r_idt_arr[0]);
2007 * Initialize the console before we print anything out.
2012 if (metadata_missing)
2013 kprintf("WARNING: loader(8) metadata is missing!\n");
2023 * Initialize IRQ mapping
2026 * SHOULD be after elcr_probe()
2028 MachIntrABI_ICU.initmap();
2029 MachIntrABI_IOAPIC.initmap();
2033 if (boothowto & RB_KDB)
2034 Debugger("Boot flags requested debugger");
2038 finishidentcpu(); /* Final stage of CPU initialization */
2039 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2040 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2042 identify_cpu(); /* Final stage of CPU initialization */
2043 initializecpu(0); /* Initialize CPU registers */
2045 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
2046 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2047 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
2050 * Some of the virtual machines do not work w/ I/O APIC
2051 * enabled. If the user does not explicitly enable or
2052 * disable the I/O APIC (ioapic_enable < 0), then we
2053 * disable I/O APIC on all virtual machines.
2056 * This must be done after identify_cpu(), which sets
2059 if (ioapic_enable < 0) {
2060 if (cpu_feature2 & CPUID2_VMM)
2066 /* make an initial tss so cpu can get interrupt stack on syscall! */
2067 gd->gd_common_tss.tss_rsp0 =
2068 (register_t)(thread0.td_kstack +
2069 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
2070 /* Ensure the stack is aligned to 16 bytes */
2071 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
2073 /* double fault stack */
2074 gd->gd_common_tss.tss_ist1 =
2075 (long)&gd->mi.gd_prvspace->idlestack[
2076 sizeof(gd->mi.gd_prvspace->idlestack)];
2078 /* Set the IO permission bitmap (empty due to tss seg limit) */
2079 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
2081 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
2082 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
2083 gd->gd_common_tssd = *gd->gd_tss_gdt;
2086 /* Set up the fast syscall stuff */
2087 msr = rdmsr(MSR_EFER) | EFER_SCE;
2088 wrmsr(MSR_EFER, msr);
2089 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
2090 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
2091 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
2092 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
2093 wrmsr(MSR_STAR, msr);
2094 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
2096 getmemsize(kmdp, physfree);
2097 init_param2(physmem);
2099 /* now running on new page tables, configured,and u/iom is accessible */
2101 /* Map the message buffer. */
2103 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2104 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2107 msgbufinit(msgbufp, MSGBUF_SIZE);
2110 /* transfer to user mode */
2112 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2113 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2114 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
2120 /* setup proc 0's pcb */
2121 thread0.td_pcb->pcb_flags = 0;
2122 thread0.td_pcb->pcb_cr3 = KPML4phys;
2123 thread0.td_pcb->pcb_ext = NULL;
2124 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
2126 /* Location of kernel stack for locore */
2127 return ((u_int64_t)thread0.td_pcb);
2131 * Initialize machine-dependant portions of the global data structure.
2132 * Note that the global data area and cpu0's idlestack in the private
2133 * data space were allocated in locore.
2135 * Note: the idlethread's cpl is 0
2137 * WARNING! Called from early boot, 'mycpu' may not work yet.
2140 cpu_gdinit(struct mdglobaldata *gd, int cpu)
2143 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
2145 lwkt_init_thread(&gd->mi.gd_idlethread,
2146 gd->mi.gd_prvspace->idlestack,
2147 sizeof(gd->mi.gd_prvspace->idlestack),
2149 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2150 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2151 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2152 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2156 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2158 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2159 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2162 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2168 globaldata_find(int cpu)
2170 KKASSERT(cpu >= 0 && cpu < ncpus);
2171 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2175 ptrace_set_pc(struct lwp *lp, unsigned long addr)
2177 lp->lwp_md.md_regs->tf_rip = addr;
2182 ptrace_single_step(struct lwp *lp)
2184 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
2189 fill_regs(struct lwp *lp, struct reg *regs)
2191 struct trapframe *tp;
2193 if ((tp = lp->lwp_md.md_regs) == NULL)
2195 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs));
2200 set_regs(struct lwp *lp, struct reg *regs)
2202 struct trapframe *tp;
2204 tp = lp->lwp_md.md_regs;
2205 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
2206 !CS_SECURE(regs->r_cs))
2208 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs));
2213 #ifndef CPU_DISABLE_SSE
2215 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2217 struct env87 *penv_87 = &sv_87->sv_env;
2218 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2221 /* FPU control/status */
2222 penv_87->en_cw = penv_xmm->en_cw;
2223 penv_87->en_sw = penv_xmm->en_sw;
2224 penv_87->en_tw = penv_xmm->en_tw;
2225 penv_87->en_fip = penv_xmm->en_fip;
2226 penv_87->en_fcs = penv_xmm->en_fcs;
2227 penv_87->en_opcode = penv_xmm->en_opcode;
2228 penv_87->en_foo = penv_xmm->en_foo;
2229 penv_87->en_fos = penv_xmm->en_fos;
2232 for (i = 0; i < 8; ++i)
2233 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2237 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2239 struct env87 *penv_87 = &sv_87->sv_env;
2240 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2243 /* FPU control/status */
2244 penv_xmm->en_cw = penv_87->en_cw;
2245 penv_xmm->en_sw = penv_87->en_sw;
2246 penv_xmm->en_tw = penv_87->en_tw;
2247 penv_xmm->en_fip = penv_87->en_fip;
2248 penv_xmm->en_fcs = penv_87->en_fcs;
2249 penv_xmm->en_opcode = penv_87->en_opcode;
2250 penv_xmm->en_foo = penv_87->en_foo;
2251 penv_xmm->en_fos = penv_87->en_fos;
2254 for (i = 0; i < 8; ++i)
2255 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2257 #endif /* CPU_DISABLE_SSE */
2260 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2262 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2264 #ifndef CPU_DISABLE_SSE
2266 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2267 (struct save87 *)fpregs);
2270 #endif /* CPU_DISABLE_SSE */
2271 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2276 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2278 #ifndef CPU_DISABLE_SSE
2280 set_fpregs_xmm((struct save87 *)fpregs,
2281 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2284 #endif /* CPU_DISABLE_SSE */
2285 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2290 fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2295 dbregs->dr[0] = rdr0();
2296 dbregs->dr[1] = rdr1();
2297 dbregs->dr[2] = rdr2();
2298 dbregs->dr[3] = rdr3();
2299 dbregs->dr[4] = rdr4();
2300 dbregs->dr[5] = rdr5();
2301 dbregs->dr[6] = rdr6();
2302 dbregs->dr[7] = rdr7();
2305 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2307 dbregs->dr[0] = pcb->pcb_dr0;
2308 dbregs->dr[1] = pcb->pcb_dr1;
2309 dbregs->dr[2] = pcb->pcb_dr2;
2310 dbregs->dr[3] = pcb->pcb_dr3;
2313 dbregs->dr[6] = pcb->pcb_dr6;
2314 dbregs->dr[7] = pcb->pcb_dr7;
2319 set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2322 load_dr0(dbregs->dr[0]);
2323 load_dr1(dbregs->dr[1]);
2324 load_dr2(dbregs->dr[2]);
2325 load_dr3(dbregs->dr[3]);
2326 load_dr4(dbregs->dr[4]);
2327 load_dr5(dbregs->dr[5]);
2328 load_dr6(dbregs->dr[6]);
2329 load_dr7(dbregs->dr[7]);
2332 struct ucred *ucred;
2334 uint64_t mask1, mask2;
2337 * Don't let an illegal value for dr7 get set. Specifically,
2338 * check for undefined settings. Setting these bit patterns
2339 * result in undefined behaviour and can lead to an unexpected
2342 /* JG this loop looks unreadable */
2343 /* Check 4 2-bit fields for invalid patterns.
2344 * These fields are R/Wi, for i = 0..3
2346 /* Is 10 in LENi allowed when running in compatibility mode? */
2347 /* Pattern 10 in R/Wi might be used to indicate
2348 * breakpoint on I/O. Further analysis should be
2349 * carried to decide if it is safe and useful to
2350 * provide access to that capability
2352 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2353 i++, mask1 <<= 4, mask2 <<= 4)
2354 if ((dbregs->dr[7] & mask1) == mask2)
2357 pcb = lp->lwp_thread->td_pcb;
2358 ucred = lp->lwp_proc->p_ucred;
2361 * Don't let a process set a breakpoint that is not within the
2362 * process's address space. If a process could do this, it
2363 * could halt the system by setting a breakpoint in the kernel
2364 * (if ddb was enabled). Thus, we need to check to make sure
2365 * that no breakpoints are being enabled for addresses outside
2366 * process's address space, unless, perhaps, we were called by
2369 * XXX - what about when the watched area of the user's
2370 * address space is written into from within the kernel
2371 * ... wouldn't that still cause a breakpoint to be generated
2372 * from within kernel mode?
2375 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
2376 if (dbregs->dr[7] & 0x3) {
2377 /* dr0 is enabled */
2378 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
2382 if (dbregs->dr[7] & (0x3<<2)) {
2383 /* dr1 is enabled */
2384 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
2388 if (dbregs->dr[7] & (0x3<<4)) {
2389 /* dr2 is enabled */
2390 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
2394 if (dbregs->dr[7] & (0x3<<6)) {
2395 /* dr3 is enabled */
2396 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
2401 pcb->pcb_dr0 = dbregs->dr[0];
2402 pcb->pcb_dr1 = dbregs->dr[1];
2403 pcb->pcb_dr2 = dbregs->dr[2];
2404 pcb->pcb_dr3 = dbregs->dr[3];
2405 pcb->pcb_dr6 = dbregs->dr[6];
2406 pcb->pcb_dr7 = dbregs->dr[7];
2408 pcb->pcb_flags |= PCB_DBREGS;
2415 * Return > 0 if a hardware breakpoint has been hit, and the
2416 * breakpoint was in user space. Return 0, otherwise.
2419 user_dbreg_trap(void)
2421 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2422 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2423 int nbp; /* number of breakpoints that triggered */
2424 caddr_t addr[4]; /* breakpoint addresses */
2428 if ((dr7 & 0xff) == 0) {
2430 * all GE and LE bits in the dr7 register are zero,
2431 * thus the trap couldn't have been caused by the
2432 * hardware debug registers
2443 * None of the breakpoint bits are set meaning this
2444 * trap was not caused by any of the debug registers
2450 * at least one of the breakpoints were hit, check to see
2451 * which ones and if any of them are user space addresses
2455 addr[nbp++] = (caddr_t)rdr0();
2458 addr[nbp++] = (caddr_t)rdr1();
2461 addr[nbp++] = (caddr_t)rdr2();
2464 addr[nbp++] = (caddr_t)rdr3();
2467 for (i=0; i<nbp; i++) {
2469 (caddr_t)VM_MAX_USER_ADDRESS) {
2471 * addr[i] is in user space
2478 * None of the breakpoints are in user space.
2486 Debugger(const char *msg)
2488 kprintf("Debugger(\"%s\") called.\n", msg);
2495 * Provide inb() and outb() as functions. They are normally only
2496 * available as macros calling inlined functions, thus cannot be
2497 * called inside DDB.
2499 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2505 /* silence compiler warnings */
2507 void outb(u_int, u_char);
2514 * We use %%dx and not %1 here because i/o is done at %dx and not at
2515 * %edx, while gcc generates inferior code (movw instead of movl)
2516 * if we tell it to load (u_short) port.
2518 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2523 outb(u_int port, u_char data)
2527 * Use an unnecessary assignment to help gcc's register allocator.
2528 * This make a large difference for gcc-1.40 and a tiny difference
2529 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2530 * best results. gcc-2.6.0 can't handle this.
2533 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2541 * initialize all the SMP locks
2544 /* critical region when masking or unmasking interupts */
2545 struct spinlock_deprecated imen_spinlock;
2547 /* critical region for old style disable_intr/enable_intr */
2548 struct spinlock_deprecated mpintr_spinlock;
2550 /* critical region around INTR() routines */
2551 struct spinlock_deprecated intr_spinlock;
2553 /* lock region used by kernel profiling */
2554 struct spinlock_deprecated mcount_spinlock;
2556 /* locks com (tty) data/hardware accesses: a FASTINTR() */
2557 struct spinlock_deprecated com_spinlock;
2559 /* lock regions around the clock hardware */
2560 struct spinlock_deprecated clock_spinlock;
2566 * Get the initial mplock with a count of 1 for the BSP.
2567 * This uses a LOGICAL cpu ID, ie BSP == 0.
2569 cpu_get_initial_mplock();
2571 spin_lock_init(&mcount_spinlock);
2572 spin_lock_init(&intr_spinlock);
2573 spin_lock_init(&mpintr_spinlock);
2574 spin_lock_init(&imen_spinlock);
2575 spin_lock_init(&com_spinlock);
2576 spin_lock_init(&clock_spinlock);
2578 /* our token pool needs to work early */
2579 lwkt_token_pool_init();
2583 cpu_mwait_hint_valid(uint32_t hint)
2587 cx_idx = MWAIT_EAX_TO_CX(hint);
2588 if (cx_idx >= CPU_MWAIT_CX_MAX)
2591 sub = MWAIT_EAX_TO_CX_SUB(hint);
2592 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2599 cpu_mwait_cx_no_bmsts(void)
2601 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS);
2605 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0,
2606 boolean_t allow_auto)
2608 int error, cx_idx, old_cx_idx, sub = 0, hint;
2609 char name[16], *ptr, *start;
2613 old_cx_idx = MWAIT_EAX_TO_CX(hint);
2614 sub = MWAIT_EAX_TO_CX_SUB(hint);
2615 } else if (hint == CPU_MWAIT_HINT_AUTO) {
2616 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX;
2617 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) {
2618 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX;
2620 old_cx_idx = CPU_MWAIT_CX_MAX;
2623 if ((cpu_feature2 & CPUID2_MON) == 0 ||
2624 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
2625 strlcpy(name, "NONE", sizeof(name));
2626 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO)
2627 strlcpy(name, "AUTO", sizeof(name));
2628 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP)
2629 strlcpy(name, "AUTODEEP", sizeof(name));
2630 else if (old_cx_idx >= CPU_MWAIT_CX_MAX ||
2631 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt)
2632 strlcpy(name, "INVALID", sizeof(name));
2634 ksnprintf(name, sizeof(name), "C%d/%d", old_cx_idx, sub);
2636 error = sysctl_handle_string(oidp, name, sizeof(name), req);
2637 if (error != 0 || req->newptr == NULL)
2640 if ((cpu_feature2 & CPUID2_MON) == 0 ||
2641 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
2644 if (allow_auto && strcmp(name, "AUTO") == 0) {
2645 hint = CPU_MWAIT_HINT_AUTO;
2646 cx_idx = CPU_MWAIT_C2;
2649 if (allow_auto && strcmp(name, "AUTODEEP") == 0) {
2650 hint = CPU_MWAIT_HINT_AUTODEEP;
2651 cx_idx = CPU_MWAIT_C3;
2655 if (strlen(name) < 4 || toupper(name[0]) != 'C')
2660 cx_idx = strtol(start, &ptr, 10);
2661 if (ptr == start || *ptr != '/')
2663 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX)
2669 sub = strtol(start, &ptr, 10);
2672 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2675 hint = MWAIT_EAX_HINT(cx_idx, sub);
2677 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble)
2679 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) {
2680 error = cputimer_intr_powersave_addreq();
2683 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) {
2684 cputimer_intr_powersave_remreq();
2692 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS)
2696 lwkt_serialize_enter(&cpu_mwait_cx_slize);
2697 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2698 &cpu_mwait_halt, TRUE);
2699 lwkt_serialize_exit(&cpu_mwait_cx_slize);
2704 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS)
2708 lwkt_serialize_enter(&cpu_mwait_cx_slize);
2709 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2710 &cpu_mwait_spin, FALSE);
2711 lwkt_serialize_exit(&cpu_mwait_cx_slize);