sys/dev/netif/wx/if_wx.c

   1 /* $FreeBSD: src/sys/pci/if_wx.c,v 1.5.2.12 2003/03/05 18:42:34 njl Exp $ */
   2 /* $DragonFly: src/sys/dev/netif/wx/Attic/if_wx.c,v 1.6 2004/01/06 01:40:50 dillon Exp $ */
   3 /*
   4  * Principal Author: Matthew Jacob <mjacob@feral.com>
   5  * Copyright (c) 1999, 2001 by Traakan Software
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice unmodified, this list of conditions, and the following
  13  *    disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * Additional Copyright (c) 2001 by Parag Patel
  31  * under same licence for MII PHY code.
  32  */
  33
  34 /*
  35  * Intel Gigabit Ethernet (82452/82453) Driver.
  36  * Inspired by fxp driver by David Greenman for FreeBSD, and by
  37  * Bill Paul's work in other FreeBSD network drivers.
  38  */
  39
  40 /*
  41  * Many bug fixes gratefully acknowledged from:
  42  *
  43  *      The folks at Sitara Networks
  44  */
  45
  46 /*
  47  * Options
  48  */
  49
  50 /*
  51  * Use only every other 16 byte receive descriptor, leaving the ones
  52  * in between empty. This card is most efficient at reading/writing
  53  * 32 byte cache lines, so avoid all the (not working for early rev
  54  * cards) MWI and/or READ/MODIFY/WRITE cycles updating one descriptor
  55  * would have you do.
  56  *
  57  * This isn't debugged yet.
  58  */
  59 /* #define      PADDED_CELL     1 */
  60
  61 /*
  62  * Since the includes are a mess, they'll all be in if_wxvar.h
  63  */
  64
  65 #include "if_wxvar.h"
  66
  67 #ifdef __alpha__
  68 #undef vtophys
  69 #define vtophys(va)     alpha_XXX_dmamap((vm_offset_t)(va))
  70 #endif /* __alpha__ */
  71
  72 /*
  73  * Function Prototpes, yadda yadda...
  74  */
  75
  76 static int wx_intr(void *);
  77 static void wx_handle_link_intr(wx_softc_t *);
  78 static void wx_check_link(wx_softc_t *);
  79 static void wx_handle_rxint(wx_softc_t *);
  80 static void wx_gc(wx_softc_t *);
  81 static void wx_start(struct ifnet *);
  82 static int wx_ioctl(struct ifnet *, IOCTL_CMD_TYPE, caddr_t);
  83 static int wx_ifmedia_upd(struct ifnet *);
  84 static void wx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  85 static int wx_init(void *);
  86 static void wx_hw_stop(wx_softc_t *);
  87 static void wx_set_addr(wx_softc_t *, int, u_int8_t *);
  88 static int wx_hw_initialize(wx_softc_t *);
  89 static void wx_stop(wx_softc_t *);
  90 static void wx_txwatchdog(struct ifnet *);
  91 static int wx_get_rbuf(wx_softc_t *, rxpkt_t *);
  92 static void wx_rxdma_map(wx_softc_t *, rxpkt_t *, struct mbuf *);
  93
  94 static INLINE void wx_eeprom_raise_clk(wx_softc_t *, u_int32_t);
  95 static INLINE void wx_eeprom_lower_clk(wx_softc_t *, u_int32_t);
  96 static INLINE void wx_eeprom_sobits(wx_softc_t *, u_int16_t, u_int16_t);
  97 static INLINE u_int16_t wx_eeprom_sibits(wx_softc_t *);
  98 static INLINE void wx_eeprom_cleanup(wx_softc_t *);
  99 static INLINE u_int16_t wx_read_eeprom_word(wx_softc_t *, int);
 100 static void wx_read_eeprom(wx_softc_t *, u_int16_t *, int, int);
 101
 102 static int wx_attach_common(wx_softc_t *);
 103 static void wx_watchdog(void *);
 104
 105 static INLINE void wx_mwi_whackon(wx_softc_t *);
 106 static INLINE void wx_mwi_unwhack(wx_softc_t *);
 107 static int wx_dring_setup(wx_softc_t *);
 108 static void wx_dring_teardown(wx_softc_t *);
 109
 110 static int wx_attach_phy(wx_softc_t *);
 111 static int wx_miibus_readreg(void *, int, int);
 112 static int wx_miibus_writereg(void *, int, int, int);
 113 static void wx_miibus_statchg(void *);
 114 static void wx_miibus_mediainit(void *);
 115
 116 static u_int32_t wx_mii_shift_in(wx_softc_t *);
 117 static void wx_mii_shift_out(wx_softc_t *, u_int32_t, u_int32_t);
 118
 119 #define WX_DISABLE_INT(sc)      WRITE_CSR(sc, WXREG_IMCLR, WXDISABLE)
 120 #define WX_ENABLE_INT(sc)       WRITE_CSR(sc, WXREG_IMASK, sc->wx_ienable)
 121
 122 /*
 123  * Until we do a bit more work, we can get no bigger than MCLBYTES
 124  */
 125 #if     0
 126 #define WX_MAXMTU       (WX_MAX_PKT_SIZE_JUMBO - sizeof (struct ether_header))
 127 #else
 128 #define WX_MAXMTU       (MCLBYTES - sizeof (struct ether_header))
 129 #endif
 130
 131 #define DPRINTF(sc, x)  if (sc->wx_debug) printf x
 132 #define IPRINTF(sc, x)  if (sc->wx_verbose) printf x
 133
 134 static const char ldn[] = "%s: link down\n";
 135 static const char lup[] = "%s: link up\n";
 136 static const char sqe[] = "%s: receive sequence error\n";
 137 static const char ane[] = "%s: /C/ ordered sets seen- enabling ANE\n";
 138 static const char inane[] = "%s: no /C/ ordered sets seen- disabling ANE\n";
 139
 140 static int wx_txint_delay = 5000;       /* ~5ms */
 141 TUNABLE_INT("hw.wx.txint_delay", &wx_txint_delay);
 142
 143 SYSCTL_NODE(_hw, OID_AUTO, wx, CTLFLAG_RD, 0, "WX driver parameters");
 144 SYSCTL_INT(_hw_wx, OID_AUTO, txint_delay, CTLFLAG_RW,
 145         &wx_txint_delay, 0, "");
 146 static int wx_dump_stats = -1;
 147 SYSCTL_INT(_hw_wx, OID_AUTO, dump_stats, CTLFLAG_RW,
 148         &wx_dump_stats, 0, "");
 149 static int wx_clr_stats = -1;
 150 SYSCTL_INT(_hw_wx, OID_AUTO, clear_stats, CTLFLAG_RW,
 151         &wx_clr_stats, 0, "");
 152
 153 /*
 154  * Program multicast addresses.
 155  *
 156  * This function must be called at splimp, but it may sleep.
 157  */
 158 static int
 159 wx_mc_setup(wx_softc_t *sc)
 160 {
 161         struct ifnet *ifp = &sc->wx_if;
 162         struct ifmultiaddr *ifma;
 163
 164         /*
 165          * XXX: drain TX queue
 166          */
 167         if (sc->tactive) {
 168                 return (EBUSY);
 169         }
 170
 171         wx_stop(sc);
 172
 173         if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) {
 174                 sc->all_mcasts = 1;
 175                 return (wx_init(sc));
 176         }
 177
 178         sc->wx_nmca = 0;
 179         for (ifma = ifp->if_multiaddrs.lh_first, sc->wx_nmca = 0;
 180             ifma != NULL; ifma = ifma->ifma_link.le_next) {
 181
 182                 if (ifma->ifma_addr->sa_family != AF_LINK) {
 183                         continue;
 184                 }
 185                 if (sc->wx_nmca >= WX_RAL_TAB_SIZE-1) {
 186                         sc->wx_nmca = 0;
 187                         sc->all_mcasts = 1;
 188                         break;
 189                 }
 190                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 191                     (void *) &sc->wx_mcaddr[sc->wx_nmca++][0], 6);
 192         }
 193         return (wx_init(sc));
 194 }
 195
 196 /*
 197  * Return identification string if this is device is ours.
 198  */
 199 static int
 200 wx_probe(device_t dev)
 201 {
 202         if (pci_get_vendor(dev) != WX_VENDOR_INTEL) {
 203                 return (ENXIO);
 204         }
 205         switch (pci_get_device(dev)) {
 206         case WX_PRODUCT_82452:
 207                 device_set_desc(dev, "Intel PRO/1000 Gigabit (WISEMAN)");
 208                 break;
 209         case WX_PRODUCT_LIVENGOOD:
 210                 device_set_desc(dev, "Intel PRO/1000 (LIVENGOOD)");
 211                 break;
 212         case WX_PRODUCT_82452_SC:
 213                 device_set_desc(dev, "Intel PRO/1000 F Gigabit Ethernet");
 214                 break;
 215         case WX_PRODUCT_82543:
 216                 device_set_desc(dev, "Intel PRO/1000 T Gigabit Ethernet");
 217                 break;
 218         default:
 219                 return (ENXIO);
 220         }
 221         return (0);
 222 }
 223
 224 static int
 225 wx_attach(device_t dev)
 226 {
 227         int error = 0;
 228         wx_softc_t *sc = device_get_softc(dev);
 229         struct ifnet *ifp;
 230         u_int32_t val;
 231         int rid;
 232
 233         bzero(sc, sizeof (wx_softc_t));
 234
 235         callout_handle_init(&sc->w.sch);
 236         sc->w.dev = dev;
 237
 238         if (bootverbose)
 239                 sc->wx_verbose = 1;
 240
 241         if (getenv_int ("wx_debug", &rid)) {
 242                 if (rid & (1 << device_get_unit(dev))) {
 243                         sc->wx_debug = 1;
 244                 }
 245         }
 246
 247         if (getenv_int("wx_no_ilos", &rid)) {
 248                 if (rid & (1 << device_get_unit(dev))) {
 249                         sc->wx_no_ilos = 1;
 250                 }
 251         }
 252
 253         if (getenv_int("wx_ilos", &rid)) {
 254                 if (rid & (1 << device_get_unit(dev))) {
 255                         sc->wx_ilos = 1;
 256                 }
 257         }
 258
 259         if (getenv_int("wx_no_flow", &rid)) {
 260                 if (rid & (1 << device_get_unit(dev))) {
 261                         sc->wx_no_flow = 1;
 262                 }
 263         }
 264
 265 #ifdef  SMPNG
 266         mtx_init(&sc->wx_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
 267 #endif
 268         WX_LOCK(sc);
 269         /*
 270          * get revision && id...
 271          */
 272         sc->wx_idnrev = (pci_get_device(dev) << 16) | (pci_get_revid(dev));
 273
 274         /*
 275          * Enable bus mastering, make sure that the cache line size is right.
 276          */
 277         pci_enable_busmaster(dev);
 278         pci_enable_io(dev, SYS_RES_MEMORY);
 279         val = pci_read_config(dev, PCIR_COMMAND, 4);
 280         if ((val & PCIM_CMD_MEMEN) == 0) {
 281                 device_printf(dev, "failed to enable memory mapping\n");
 282                 error = ENXIO;
 283                 goto out;
 284         }
 285
 286         /*
 287          * Let the BIOS do it's job- but check for sanity.
 288          */
 289         val = pci_read_config(dev, PCIR_CACHELNSZ, 1);
 290         if (val < 4 || val > 32) {
 291                 pci_write_config(dev, PCIR_CACHELNSZ, 8, 1);
 292         }
 293
 294         /*
 295          * Map control/status registers.
 296          */
 297         rid = WX_MMBA;
 298         sc->w.mem = bus_alloc_resource(dev, SYS_RES_MEMORY,
 299             &rid, 0, ~0, 1, RF_ACTIVE);
 300         if (!sc->w.mem) {
 301                 device_printf(dev, "could not map memory\n");
 302                 error = ENXIO;
 303                 goto out;
 304         }
 305         sc->w.st = rman_get_bustag(sc->w.mem);
 306         sc->w.sh = rman_get_bushandle(sc->w.mem);
 307
 308         rid = 0;
 309         sc->w.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 310             &rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 311         if (sc->w.irq == NULL) {
 312                 device_printf(dev, "could not map interrupt\n");
 313                 error = ENXIO;
 314                 goto out;
 315         }
 316         error = bus_setup_intr(dev, sc->w.irq, INTR_TYPE_NET,
 317             (void (*)(void *))wx_intr, sc, &sc->w.ih);
 318         if (error) {
 319                 device_printf(dev, "could not setup irq\n");
 320                 goto out;
 321         }
 322         (void) snprintf(sc->wx_name, sizeof (sc->wx_name) - 1, "wx%d",
 323             device_get_unit(dev));
 324         if (wx_attach_common(sc)) {
 325                 bus_teardown_intr(dev, sc->w.irq, sc->w.ih);
 326                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->w.irq);
 327                 bus_release_resource(dev, SYS_RES_MEMORY, WX_MMBA, sc->w.mem);
 328                 error = ENXIO;
 329                 goto out;
 330         }
 331         device_printf(dev, "Ethernet address %02x:%02x:%02x:%02x:%02x:%02x\n",
 332             sc->w.arpcom.ac_enaddr[0], sc->w.arpcom.ac_enaddr[1],
 333             sc->w.arpcom.ac_enaddr[2], sc->w.arpcom.ac_enaddr[3],
 334             sc->w.arpcom.ac_enaddr[4], sc->w.arpcom.ac_enaddr[5]);
 335
 336         ifp = &sc->w.arpcom.ac_if;
 337         if_initname(ifp, "wx", device_get_unit(dev));
 338         ifp->if_mtu = ETHERMTU; /* we always start at ETHERMTU size */
 339         ifp->if_output = ether_output;
 340         ifp->if_baudrate = 1000000000;
 341         ifp->if_init = (void (*)(void *))wx_init;
 342         ifp->if_softc = sc;
 343         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 344         ifp->if_ioctl = wx_ioctl;
 345         ifp->if_start = wx_start;
 346         ifp->if_watchdog = wx_txwatchdog;
 347         ifp->if_snd.ifq_maxlen = WX_MAX_TDESC - 1;
 348         ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
 349 out:
 350         WX_UNLOCK(sc);
 351         return (error);
 352 }
 353
 354 static int
 355 wx_attach_phy(wx_softc_t *sc)
 356 {
 357         if (mii_phy_probe(sc->w.dev, &sc->w.miibus, wx_ifmedia_upd,
 358             wx_ifmedia_sts)) {
 359                 printf("%s: no PHY probed!\n", sc->wx_name);
 360                 return (-1);
 361         }
 362         sc->wx_mii = 1;
 363         return 0;
 364 }
 365
 366 static int
 367 wx_detach(device_t dev)
 368 {
 369         wx_softc_t *sc = device_get_softc(dev);
 370
 371         WX_LOCK(sc);
 372         wx_stop(sc);
 373
 374         ether_ifdetach(&sc->w.arpcom.ac_if, ETHER_BPF_SUPPORTED);
 375         if (sc->w.miibus) {
 376                 bus_generic_detach(dev);
 377                 device_delete_child(dev, sc->w.miibus);
 378         } else {
 379                 ifmedia_removeall(&sc->wx_media);
 380         }
 381         bus_teardown_intr(dev, sc->w.irq, sc->w.ih);
 382         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->w.irq);
 383         bus_release_resource(dev, SYS_RES_MEMORY, WX_MMBA, sc->w.mem);
 384
 385         wx_dring_teardown(sc);
 386         if (sc->rbase) {
 387                 WXFREE(sc->rbase);
 388                 sc->rbase = NULL;
 389         }
 390         if (sc->tbase) {
 391                 WXFREE(sc->tbase);
 392                 sc->tbase = NULL;
 393         }
 394         WX_UNLOCK(sc);
 395 #ifdef  SMPNG
 396         mtx_destroy(&sc->wx_mtx);
 397 #endif
 398         return (0);
 399 }
 400
 401 static int
 402 wx_shutdown(device_t dev)
 403 {
 404         wx_hw_stop((wx_softc_t *) device_get_softc(dev));
 405         return (0);
 406 }
 407
 408 static INLINE void
 409 wx_mwi_whackon(wx_softc_t *sc)
 410 {
 411         sc->wx_cmdw = pci_read_config(sc->w.dev, PCIR_COMMAND, 2);
 412         pci_write_config(sc->w.dev, PCIR_COMMAND, sc->wx_cmdw & ~MWI, 2);
 413 }
 414
 415 static INLINE void
 416 wx_mwi_unwhack(wx_softc_t *sc)
 417 {
 418         if (sc->wx_cmdw & MWI) {
 419                 pci_write_config(sc->w.dev, PCIR_COMMAND, sc->wx_cmdw, 2);
 420         }
 421 }
 422
 423 static int
 424 wx_dring_setup(wx_softc_t *sc)
 425 {
 426         size_t len;
 427
 428         len = sizeof (wxrd_t) * WX_MAX_RDESC;
 429         sc->rdescriptors = (wxrd_t *)
 430             contigmalloc(len, M_DEVBUF, M_NOWAIT, 0, ~0, 4096, 0);
 431         if (sc->rdescriptors == NULL) {
 432                 printf("%s: could not allocate rcv descriptors\n", sc->wx_name);
 433                 return (-1);
 434         }
 435         if (((intptr_t)sc->rdescriptors) & 0xfff) {
 436                 contigfree(sc->rdescriptors, len, M_DEVBUF);
 437                 sc->rdescriptors = NULL;
 438                 printf("%s: rcv descriptors not 4KB aligned\n", sc->wx_name);
 439                 return (-1);
 440         }
 441         bzero(sc->rdescriptors, len);
 442
 443         len = sizeof (wxtd_t) * WX_MAX_TDESC;
 444         sc->tdescriptors = (wxtd_t *)
 445             contigmalloc(len, M_DEVBUF, M_NOWAIT, 0, ~0, 4096, 0);
 446         if (sc->tdescriptors == NULL) {
 447                 contigfree(sc->rdescriptors,
 448                     sizeof (wxrd_t) * WX_MAX_RDESC, M_DEVBUF);
 449                 sc->rdescriptors = NULL;
 450                 printf("%s: could not allocate xmt descriptors\n", sc->wx_name);
 451                 return (-1);
 452         }
 453         if (((intptr_t)sc->tdescriptors) & 0xfff) {
 454                 contigfree(sc->rdescriptors,
 455                     sizeof (wxrd_t) * WX_MAX_RDESC, M_DEVBUF);
 456                 contigfree(sc->tdescriptors, len, M_DEVBUF);
 457                 sc->rdescriptors = NULL;
 458                 sc->tdescriptors = NULL;
 459                 printf("%s: xmt descriptors not 4KB aligned\n", sc->wx_name);
 460                 return (-1);
 461         }
 462         bzero(sc->tdescriptors, len);
 463         return (0);
 464 }
 465
 466 static void
 467 wx_dring_teardown(wx_softc_t *sc)
 468 {
 469         if (sc->rdescriptors) {
 470                 contigfree(sc->rdescriptors,
 471                     sizeof (wxrd_t) * WX_MAX_RDESC, M_DEVBUF);
 472                 sc->rdescriptors = NULL;
 473         }
 474         if (sc->tdescriptors) {
 475                 contigfree(sc->tdescriptors,
 476                     sizeof (wxtd_t) * WX_MAX_TDESC, M_DEVBUF);
 477                 sc->tdescriptors = NULL;
 478         }
 479 }
 480
 481 static device_method_t wx_methods[] = {
 482         /* Device interface */
 483         DEVMETHOD(device_probe,         wx_probe),
 484         DEVMETHOD(device_attach,        wx_attach),
 485         DEVMETHOD(device_detach,        wx_detach),
 486         DEVMETHOD(device_shutdown,      wx_shutdown),
 487
 488         /* bus interface */
 489         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 490         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 491
 492         /* MII interface */
 493         DEVMETHOD(miibus_readreg,       wx_miibus_readreg),
 494         DEVMETHOD(miibus_writereg,      wx_miibus_writereg),
 495         DEVMETHOD(miibus_statchg,       wx_miibus_statchg),
 496         DEVMETHOD(miibus_mediainit,     wx_miibus_mediainit),
 497
 498         { 0, 0 }
 499 };
 500
 501 static driver_t wx_driver = {
 502         "wx", wx_methods, sizeof(wx_softc_t),
 503 };
 504 static devclass_t wx_devclass;
 505
 506 DECLARE_DUMMY_MODULE(if_wx);
 507 MODULE_DEPEND(if_wx, miibus, 1, 1, 1);
 508 DRIVER_MODULE(if_wx, pci, wx_driver, wx_devclass, 0, 0);
 509 DRIVER_MODULE(miibus, wx, miibus_driver, miibus_devclass, 0, 0);
 510
 511 /*
 512  * Do generic parts of attach. Our registers have been mapped
 513  * and our interrupt registered.
 514  */
 515 static int
 516 wx_attach_common(wx_softc_t *sc)
 517 {
 518         size_t len;
 519         u_int32_t tmp;
 520         int ll = 0;
 521
 522         /*
 523          * First, check for revision support.
 524          */
 525         if (sc->wx_idnrev < WX_WISEMAN_2_0) {
 526                 printf("%s: cannot support ID 0x%x, revision %d chips\n",
 527                     sc->wx_name, sc->wx_idnrev >> 16, sc->wx_idnrev & 0xffff);
 528                 return (ENXIO);
 529         }
 530
 531         /*
 532          * Second, reset the chip.
 533          */
 534         wx_hw_stop(sc);
 535
 536         /*
 537          * Third, validate our EEPROM.
 538          */
 539
 540         /* TBD */
 541
 542         /*
 543          * Fourth, read eeprom for our MAC address and other things.
 544          */
 545         wx_read_eeprom(sc, (u_int16_t *)sc->wx_enaddr, WX_EEPROM_MAC_OFF, 3);
 546
 547         /*
 548          * Fifth, establish some adapter parameters.
 549          */
 550         sc->wx_dcr = 0;
 551
 552         if (IS_LIVENGOOD_CU(sc)) {
 553
 554                 /* settings to talk to PHY */
 555                 sc->wx_dcr |= WXDCR_FRCSPD | WXDCR_FRCDPX | WXDCR_SLU;
 556                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
 557
 558                 /*
 559                  * Raise the PHY's reset line to make it operational.
 560                  */
 561                 tmp = READ_CSR(sc, WXREG_EXCT);
 562                 tmp |= WXPHY_RESET_DIR4;
 563                 WRITE_CSR(sc, WXREG_EXCT, tmp);
 564                 DELAY(20*1000);
 565
 566                 tmp = READ_CSR(sc, WXREG_EXCT);
 567                 tmp &= ~WXPHY_RESET4;
 568                 WRITE_CSR(sc, WXREG_EXCT, tmp);
 569                 DELAY(20*1000);
 570
 571                 tmp = READ_CSR(sc, WXREG_EXCT);
 572                 tmp |= WXPHY_RESET4;
 573                 WRITE_CSR(sc, WXREG_EXCT, tmp);
 574                 DELAY(20*1000);
 575
 576                 if (wx_attach_phy(sc)) {
 577                         goto fail;
 578                 }
 579         } else {
 580                 ifmedia_init(&sc->wx_media, IFM_IMASK,
 581                     wx_ifmedia_upd, wx_ifmedia_sts);
 582
 583                 ifmedia_add(&sc->wx_media, IFM_ETHER|IFM_1000_SX, 0, NULL);
 584                 ifmedia_add(&sc->wx_media,
 585                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
 586                 ifmedia_set(&sc->wx_media, IFM_ETHER|IFM_1000_SX|IFM_FDX);
 587
 588                 sc->wx_media.ifm_media = sc->wx_media.ifm_cur->ifm_media;
 589         }
 590
 591         /*
 592          * Sixth, establish a default device control register word.
 593          */
 594         ll += 1;
 595         if (sc->wx_cfg1 & WX_EEPROM_CTLR1_FD)
 596                 sc->wx_dcr |= WXDCR_FD;
 597         if (sc->wx_cfg1 & WX_EEPROM_CTLR1_ILOS)
 598                 sc->wx_dcr |= WXDCR_ILOS;
 599
 600         tmp = (sc->wx_cfg1 >> WX_EEPROM_CTLR1_SWDPIO_SHIFT) & WXDCR_SWDPIO_MASK;
 601         sc->wx_dcr |= (tmp << WXDCR_SWDPIO_SHIFT);
 602
 603         if (sc->wx_no_ilos)
 604                 sc->wx_dcr &= ~WXDCR_ILOS;
 605         if (sc->wx_ilos)
 606                 sc->wx_dcr |= WXDCR_ILOS;
 607         if (sc->wx_no_flow == 0)
 608                 sc->wx_dcr |= WXDCR_RFCE | WXDCR_TFCE;
 609
 610         /*
 611          * Seventh, allocate various sw structures...
 612          */
 613         len = sizeof (rxpkt_t) * WX_MAX_RDESC;
 614         sc->rbase = (rxpkt_t *) WXMALLOC(len);
 615         if (sc->rbase == NULL) {
 616                 goto fail;
 617         }
 618         bzero(sc->rbase, len);
 619         ll += 1;
 620
 621         len = sizeof (txpkt_t) * WX_MAX_TDESC;
 622         sc->tbase = (txpkt_t *) WXMALLOC(len);
 623         if (sc->tbase == NULL) {
 624                 goto fail;
 625         }
 626         bzero(sc->tbase, len);
 627         ll += 1;
 628
 629         /*
 630          * Eighth, allocate and dma map (platform dependent) descriptor rings.
 631          * They have to be aligned on a 4KB boundary.
 632          */
 633         if (wx_dring_setup(sc) == 0) {
 634                 return (0);
 635         }
 636
 637 fail:
 638         printf("%s: failed to do common attach (%d)\n", sc->wx_name, ll);
 639         wx_dring_teardown(sc);
 640         if (sc->rbase) {
 641                 WXFREE(sc->rbase);
 642                 sc->rbase = NULL;
 643         }
 644         if (sc->tbase) {
 645                 WXFREE(sc->tbase);
 646                 sc->tbase = NULL;
 647         }
 648         return (ENOMEM);
 649 }
 650
 651 /*
 652  * EEPROM functions.
 653  */
 654
 655 static INLINE void
 656 wx_eeprom_raise_clk(wx_softc_t *sc, u_int32_t regval)
 657 {
 658         WRITE_CSR(sc, WXREG_EECDR, regval | WXEECD_SK);
 659         DELAY(50);
 660 }
 661
 662 static INLINE void
 663 wx_eeprom_lower_clk(wx_softc_t *sc, u_int32_t regval)
 664 {
 665         WRITE_CSR(sc, WXREG_EECDR, regval & ~WXEECD_SK);
 666         DELAY(50);
 667 }
 668
 669 static INLINE void
 670 wx_eeprom_sobits(wx_softc_t *sc, u_int16_t data, u_int16_t count)
 671 {
 672         u_int32_t regval, mask;
 673
 674         mask = 1 << (count - 1);
 675         regval = READ_CSR(sc, WXREG_EECDR) & ~(WXEECD_DI|WXEECD_DO);
 676
 677         do {
 678                 if (data & mask)
 679                         regval |= WXEECD_DI;
 680                 else
 681                         regval &= ~WXEECD_DI;
 682                 WRITE_CSR(sc, WXREG_EECDR, regval); DELAY(50);
 683                 wx_eeprom_raise_clk(sc, regval);
 684                 wx_eeprom_lower_clk(sc, regval);
 685                 mask >>= 1;
 686         } while (mask != 0);
 687         WRITE_CSR(sc, WXREG_EECDR, regval & ~WXEECD_DI);
 688 }
 689
 690 static INLINE u_int16_t
 691 wx_eeprom_sibits(wx_softc_t *sc)
 692 {
 693         unsigned int regval, i;
 694         u_int16_t data;
 695
 696         data = 0;
 697         regval = READ_CSR(sc, WXREG_EECDR) & ~(WXEECD_DI|WXEECD_DO);
 698         for (i = 0; i != 16; i++) {
 699                 data <<= 1;
 700                 wx_eeprom_raise_clk(sc, regval);
 701                 regval = READ_CSR(sc, WXREG_EECDR) & ~WXEECD_DI;
 702                 if (regval & WXEECD_DO) {
 703                         data |= 1;
 704                 }
 705                 wx_eeprom_lower_clk(sc, regval);
 706         }
 707         return (data);
 708 }
 709
 710 static INLINE void
 711 wx_eeprom_cleanup(wx_softc_t *sc)
 712 {
 713         u_int32_t regval;
 714         regval = READ_CSR(sc, WXREG_EECDR) & ~(WXEECD_DI|WXEECD_CS);
 715         WRITE_CSR(sc, WXREG_EECDR, regval); DELAY(50);
 716         wx_eeprom_raise_clk(sc, regval);
 717         wx_eeprom_lower_clk(sc, regval);
 718 }
 719
 720 static u_int16_t INLINE
 721 wx_read_eeprom_word(wx_softc_t *sc, int offset)
 722 {
 723         u_int16_t       data;
 724         WRITE_CSR(sc, WXREG_EECDR, WXEECD_CS);
 725         wx_eeprom_sobits(sc, EEPROM_READ_OPCODE, 3);
 726         wx_eeprom_sobits(sc, offset, 6);
 727         data = wx_eeprom_sibits(sc);
 728         wx_eeprom_cleanup(sc);
 729         return (data);
 730 }
 731
 732 static void
 733 wx_read_eeprom(wx_softc_t *sc, u_int16_t *data, int offset, int words)
 734 {
 735         int i;
 736         for (i = 0; i < words; i++) {
 737                 *data++ = wx_read_eeprom_word(sc, offset++);
 738         }
 739         sc->wx_cfg1 = wx_read_eeprom_word(sc, WX_EEPROM_CTLR1_OFF);
 740 }
 741
 742 /*
 743  * Start packet transmission on the interface.
 744  */
 745
 746 static void
 747 wx_start(struct ifnet *ifp)
 748 {
 749         wx_softc_t *sc = SOFTC_IFP(ifp);
 750         u_int16_t widx = WX_MAX_TDESC, cidx, nactv;
 751
 752         WX_LOCK(sc);
 753         DPRINTF(sc, ("%s: wx_start\n", sc->wx_name));
 754         nactv = sc->tactive;
 755         while (nactv < WX_MAX_TDESC - 1) {
 756                 int ndesc, plen;
 757                 int gctried = 0;
 758                 struct mbuf *m, *mb_head;
 759
 760                 IF_DEQUEUE(&ifp->if_snd, mb_head);
 761                 if (mb_head == NULL) {
 762                         break;
 763                 }
 764                 sc->wx_xmitwanted++;
 765
 766                 /*
 767                  * If we have a packet less than ethermin, pad it out.
 768                  */
 769                 if (mb_head->m_pkthdr.len < WX_MIN_RPKT_SIZE) {
 770                         if (mb_head->m_next == NULL) {
 771                                 mb_head->m_len = WX_MIN_RPKT_SIZE;
 772                         } else {
 773                                 MGETHDR(m, M_DONTWAIT, MT_DATA);
 774                                 if (m == NULL) {
 775                                         m_freem(mb_head);
 776                                         break;
 777                                 }
 778                                 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
 779                                     mtod(m, caddr_t));
 780                                 m->m_pkthdr.len = m->m_len = WX_MIN_RPKT_SIZE;
 781                                 bzero(mtod(m, char *) + mb_head->m_pkthdr.len,
 782                                      WX_MIN_RPKT_SIZE - mb_head->m_pkthdr.len);
 783                                 sc->wx_xmitpullup++;
 784                                 m_freem(mb_head);
 785                                 mb_head = m;
 786                         }
 787                 }
 788         again:
 789                 cidx = sc->tnxtfree;
 790                 nactv = sc->tactive;
 791
 792
 793                 /*
 794                  * Go through each of the mbufs in the chain and initialize
 795                  * the transmit buffer descriptors with the physical address
 796                  * and size of that mbuf. If we have a length less than our
 797                  * minimum transmit size, we bail (to do a pullup). If we run
 798                  * out of descriptors, we also bail and try and do a pullup.
 799                  */
 800                 for (plen = ndesc = 0, m = mb_head; m != NULL; m = m->m_next) {
 801                         vm_offset_t vptr;
 802                         wxtd_t *td;
 803
 804                         /*
 805                          * If this mbuf has no data, skip it.
 806                          */
 807                         if (m->m_len == 0) {
 808                                 continue;
 809                         }
 810
 811                         /*
 812                          * This appears to be a bogus check the PRO1000T.
 813                          * I think they meant that the minimum packet size
 814                          * is in fact WX_MIN_XPKT_SIZE (all data loaded)
 815                          */
 816 #if     0
 817                         /*
 818                          * If this mbuf is too small for the chip's minimum,
 819                          * break out to cluster it.
 820                          */
 821                         if (m->m_len < WX_MIN_XPKT_SIZE) {
 822                                 sc->wx_xmitrunt++;
 823                                 break;
 824                         }
 825 #endif
 826
 827                         /*
 828                          * Do we have a descriptor available for this mbuf?
 829                          */
 830                         if (++nactv == WX_MAX_TDESC) {
 831                                 if (gctried++ == 0) {
 832                                         sc->wx_xmitgc++;
 833                                         wx_gc(sc);
 834                                         goto again;
 835                                 }
 836                                 break;
 837                         }
 838                         sc->tbase[cidx].dptr = m;
 839                         td = &sc->tdescriptors[cidx];
 840                         td->length = m->m_len;
 841                         plen += m->m_len;
 842
 843                         vptr = mtod(m, vm_offset_t);
 844                         td->address.highpart = 0;
 845                         td->address.lowpart = vtophys(vptr);
 846
 847                         td->cso = 0;
 848                         td->status = 0;
 849                         td->special = 0;
 850                         td->cmd = 0;
 851                         td->css = 0;
 852
 853                         if (sc->wx_debug) {
 854                                 printf("%s: XMIT[%d] %p vptr %lx (length %d "
 855                                     "DMA addr %x) idx %d\n", sc->wx_name,
 856                                     ndesc, m, (long) vptr, td->length,
 857                                     td->address.lowpart, cidx);
 858                         }
 859                         ndesc++;
 860                         cidx = T_NXT_IDX(cidx);
 861                 }
 862
 863                 /*
 864                  * If we get here and m is NULL, we can send
 865                  * the the packet chain described by mb_head.
 866                  */
 867                 if (m == NULL) {
 868                         /*
 869                          * Mark the last descriptor with EOP and tell the
 870                          * chip to insert a final checksum.
 871                          */
 872                         wxtd_t *td = &sc->tdescriptors[T_PREV_IDX(cidx)];
 873                         td->cmd = TXCMD_EOP|TXCMD_IFCS;
 874                         /*
 875                          * Set up a delayed interrupt when this packet
 876                          * is sent and the descriptor written back.
 877                          * Additional packets completing will cause
 878                          * interrupt to be delayed further. Therefore,
 879                          * after the *last* packet is sent, after the delay
 880                          * period in TIDV, an interrupt will be generated
 881                          * which will cause us to garbage collect.
 882                          */
 883                         td->cmd |= TXCMD_IDE|TXCMD_RPS;
 884
 885                         /*
 886                          * Don't xmit odd length packets.
 887                          * We're okay with bumping things
 888                          * up as long as our mbuf allocation
 889                          * is always larger than our MTU
 890                          * by a comfortable amount.
 891                          *
 892                          * Yes, it's a hole to run past the end
 893                          * of a packet.
 894                          */
 895                         if (plen & 0x1) {
 896                                 sc->wx_oddpkt++;
 897                                 td->length++;
 898                         }
 899
 900                         sc->tbase[sc->tnxtfree].sidx = sc->tnxtfree;
 901                         sc->tbase[sc->tnxtfree].eidx = cidx;
 902                         sc->tbase[sc->tnxtfree].next = NULL;
 903                         if (sc->tbsyf) {
 904                                 sc->tbsyl->next = &sc->tbase[sc->tnxtfree];
 905                         } else {
 906                                 sc->tbsyf = &sc->tbase[sc->tnxtfree];
 907                         }
 908                         sc->tbsyl = &sc->tbase[sc->tnxtfree];
 909                         sc->tnxtfree = cidx;
 910                         sc->tactive = nactv;
 911                         ifp->if_timer = 10;
 912                         if (ifp->if_bpf)
 913                                 bpf_mtap(WX_BPFTAP_ARG(ifp), mb_head);
 914                         /* defer xmit until we've got them all */
 915                         widx = cidx;
 916                         continue;
 917                 }
 918
 919                 /*
 920                  * Otherwise, we couldn't send this packet for some reason.
 921                  *
 922                  * If don't have a descriptor available, and this is a
 923                  * single mbuf packet, freeze output so that later we
 924                  * can restart when we have more room. Otherwise, we'll
 925                  * try and cluster the request. We've already tried to
 926                  * garbage collect completed descriptors.
 927                  */
 928                 if (nactv == WX_MAX_TDESC && mb_head->m_next == NULL) {
 929                         sc->wx_xmitputback++;
 930                         ifp->if_flags |= IFF_OACTIVE;
 931                         IF_PREPEND(&ifp->if_snd, mb_head);
 932                         break;
 933                 }
 934
 935                 /*
 936                  * Otherwise, it's either a fragment length somewhere in the
 937                  * chain that isn't at least WX_MIN_XPKT_SIZE in length or
 938                  * the number of fragments exceeds the number of descriptors
 939                  * available.
 940                  *
 941                  * We could try a variety of strategies here- if this is
 942                  * a length problem for single mbuf packet or a length problem
 943                  * for the last mbuf in a chain (we could just try and adjust
 944                  * it), but it's just simpler to try and cluster it.
 945                  */
 946                 MGETHDR(m, M_DONTWAIT, MT_DATA);
 947                 if (m == NULL) {
 948                         m_freem(mb_head);
 949                         break;
 950                 }
 951                 MCLGET(m, M_DONTWAIT);
 952                 if ((m->m_flags & M_EXT) == 0) {
 953                         m_freem(m);
 954                         m_freem(mb_head);
 955                         break;
 956                 }
 957                 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, mtod(m, caddr_t));
 958                 m->m_pkthdr.len = m->m_len = mb_head->m_pkthdr.len;
 959                 m_freem(mb_head);
 960                 mb_head = m;
 961                 sc->wx_xmitcluster++;
 962                 goto again;
 963         }
 964
 965         if (widx < WX_MAX_TDESC) {
 966                 if (IS_WISEMAN(sc)) {
 967                         WRITE_CSR(sc, WXREG_TDT, widx);
 968                 } else {
 969                         WRITE_CSR(sc, WXREG_TDT_LIVENGOOD, widx);
 970                 }
 971         }
 972
 973         if (sc->tactive == WX_MAX_TDESC - 1) {
 974                 sc->wx_xmitgc++;
 975                 wx_gc(sc);
 976                 if (sc->tactive >= WX_MAX_TDESC - 1) {
 977                         sc->wx_xmitblocked++;
 978                         ifp->if_flags |= IFF_OACTIVE;
 979                 }
 980         }
 981
 982         /* used SW LED to indicate transmission active */
 983         if (sc->tactive > 0 && sc->wx_mii) {
 984                 WRITE_CSR(sc, WXREG_DCR,
 985                     READ_CSR(sc, WXREG_DCR) | (WXDCR_SWDPIO0|WXDCR_SWDPIN0));
 986         }
 987         WX_UNLOCK(sc);
 988 }
 989
 990 /*
 991  * Process interface interrupts.
 992  */
 993 static int
 994 wx_intr(void *arg)
 995 {
 996         wx_softc_t *sc = arg;
 997         int claimed = 0;
 998
 999         WX_ILOCK(sc);
1000         /*
1001          * Read interrupt cause register. Reading it clears bits.
1002          */
1003         sc->wx_icr = READ_CSR(sc, WXREG_ICR);
1004         if (sc->wx_icr) {
1005                 claimed++;
1006                 WX_DISABLE_INT(sc);
1007                 sc->wx_intr++;
1008                 if (sc->wx_icr & (WXISR_LSC|WXISR_RXSEQ|WXISR_GPI_EN1)) {
1009                         sc->wx_linkintr++;
1010                         wx_handle_link_intr(sc);
1011                 }
1012                 wx_handle_rxint(sc);
1013                 if (sc->wx_icr & WXISR_TXDW) {
1014                         sc->wx_txqe++;
1015                         wx_gc(sc);
1016                 }
1017 #if     0
1018                 if (sc->wx_icr & WXISR_TXQE) {
1019                         sc->wx_txqe++;
1020                         wx_gc(sc);
1021                 }
1022 #endif
1023                 if (sc->wx_if.if_snd.ifq_head != NULL) {
1024                         wx_start(&sc->wx_if);
1025                 }
1026                 WX_ENABLE_INT(sc);
1027         }
1028         WX_IUNLK(sc);
1029         return (claimed);
1030 }
1031
1032 static void
1033 wx_handle_link_intr(wx_softc_t *sc)
1034 {
1035         u_int32_t txcw, rxcw, dcr, dsr;
1036
1037
1038         dcr = READ_CSR(sc, WXREG_DCR);
1039         DPRINTF(sc, ("%s: handle_link_intr: icr=%#x dcr=%#x\n",
1040             sc->wx_name, sc->wx_icr, dcr));
1041         if (sc->wx_mii) {
1042                 mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
1043                 mii_pollstat(mii);
1044                 if (mii->mii_media_status & IFM_ACTIVE) {
1045                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE) {
1046                                 IPRINTF(sc, (ldn, sc->wx_name));
1047                                 sc->linkup = 0;
1048                         } else {
1049                                 IPRINTF(sc, (lup, sc->wx_name));
1050                                 sc->linkup = 1;
1051                         }
1052                         WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1053                 } else if (sc->wx_icr & WXISR_RXSEQ) {
1054                         DPRINTF(sc, (sqe, sc->wx_name));
1055                 }
1056                 return;
1057         }
1058
1059         txcw = READ_CSR(sc, WXREG_XMIT_CFGW);
1060         rxcw = READ_CSR(sc, WXREG_RECV_CFGW);
1061         dsr = READ_CSR(sc, WXREG_DSR);
1062
1063         /*
1064          * If we have LOS or are now receiving Ordered Sets and are not
1065          * doing auto-negotiation, restore autonegotiation.
1066          */
1067
1068         if (((dcr & WXDCR_SWDPIN1) || (rxcw & WXRXCW_C)) &&
1069             ((txcw & WXTXCW_ANE) == 0)) {
1070                 DPRINTF(sc, (ane, sc->wx_name));
1071                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT);
1072                 sc->wx_dcr &= ~WXDCR_SLU;
1073                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1074                 sc->ane_failed = 0;
1075         }
1076
1077         if (sc->wx_icr & WXISR_LSC) {
1078                 if (READ_CSR(sc, WXREG_DSR) & WXDSR_LU) {
1079                         IPRINTF(sc, (lup, sc->wx_name));
1080                         sc->linkup = 1;
1081                         sc->wx_dcr |= (WXDCR_SWDPIO0|WXDCR_SWDPIN0);
1082                 } else {
1083                         IPRINTF(sc, (ldn, sc->wx_name));
1084                         sc->linkup = 0;
1085                         sc->wx_dcr &= ~(WXDCR_SWDPIO0|WXDCR_SWDPIN0);
1086                 }
1087                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1088         } else {
1089                 DPRINTF(sc, (sqe, sc->wx_name));
1090         }
1091 }
1092
1093 static void
1094 wx_check_link(wx_softc_t *sc)
1095 {
1096         u_int32_t rxcw, dcr, dsr;
1097
1098         if (sc->wx_mii) {
1099                 mii_pollstat(WX_MII_FROM_SOFTC(sc));
1100                 return;
1101         }
1102
1103         rxcw = READ_CSR(sc, WXREG_RECV_CFGW);
1104         dcr = READ_CSR(sc, WXREG_DCR);
1105         dsr = READ_CSR(sc, WXREG_DSR);
1106
1107         if ((dsr & WXDSR_LU) == 0 && (dcr & WXDCR_SWDPIN1) == 0 &&
1108             (rxcw & WXRXCW_C) == 0) {
1109                 if (sc->ane_failed == 0) {
1110                         sc->ane_failed = 1;
1111                         return;
1112                 }
1113                 DPRINTF(sc, (inane, sc->wx_name));
1114                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT & ~WXTXCW_ANE);
1115                 if (sc->wx_idnrev < WX_WISEMAN_2_1)
1116                         sc->wx_dcr &= ~WXDCR_TFCE;
1117                 sc->wx_dcr |= WXDCR_SLU;
1118                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1119         } else if ((rxcw & WXRXCW_C) != 0 && (dcr & WXDCR_SLU) != 0) {
1120                 DPRINTF(sc, (ane, sc->wx_name));
1121                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT);
1122                 sc->wx_dcr &= ~WXDCR_SLU;
1123                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1124         }
1125 }
1126
1127 static void
1128 wx_handle_rxint(wx_softc_t *sc)
1129 {
1130         struct ether_header *eh;
1131         struct mbuf *m0, *mb, *pending[WX_MAX_RDESC];
1132         struct ifnet *ifp = &sc->wx_if;
1133         int npkts, ndesc, lidx, idx, tlen;
1134
1135         DPRINTF(sc, ("%s: wx_handle_rxint\n", sc->wx_name));
1136
1137         for (m0 = sc->rpending, tlen = ndesc = npkts = 0, idx = sc->rnxt,
1138             lidx = R_PREV_IDX(idx); ndesc < WX_MAX_RDESC;
1139             ndesc++, lidx = idx, idx = R_NXT_IDX(idx)) {
1140                 wxrd_t *rd;
1141                 rxpkt_t *rxpkt;
1142                 int length, offset, lastframe;
1143
1144                 rd = &sc->rdescriptors[idx];
1145                 /*
1146                  * XXX: DMA Flush descriptor
1147                  */
1148                 if ((rd->status & RDSTAT_DD) == 0) {
1149                         if (m0) {
1150                                 if (sc->rpending == NULL) {
1151                                         m0->m_pkthdr.len = tlen;
1152                                         sc->rpending = m0;
1153                                 } else {
1154                                         m_freem(m0);
1155                                 }
1156                                 m0 = NULL;
1157                         }
1158                         DPRINTF(sc, ("%s: WXRX: ndesc %d idx %d lidx %d\n",
1159                             sc->wx_name, ndesc, idx, lidx));
1160                         break;
1161                 }
1162
1163                 if (rd->errors != 0) {
1164                         printf("%s: packet with errors (%x)\n",
1165                             sc->wx_name, rd->errors);
1166                         rd->status = 0;
1167                         ifp->if_ierrors++;
1168                         if (m0) {
1169                                 m_freem(m0);
1170                                 m0 = NULL;
1171                                 if (sc->rpending) {
1172                                         m_freem(sc->rpending);
1173                                         sc->rpending = NULL;
1174                                 }
1175                         }
1176                         continue;
1177                 }
1178
1179
1180                 rxpkt = &sc->rbase[idx];
1181                 mb = rxpkt->dptr;
1182                 if (mb == NULL) {
1183                         printf("%s: receive descriptor with no mbuf\n",
1184                             sc->wx_name);
1185                         (void) wx_get_rbuf(sc, rxpkt);
1186                         rd->status = 0;
1187                         ifp->if_ierrors++;
1188                         if (m0) {
1189                                 m_freem(m0);
1190                                 m0 = NULL;
1191                                 if (sc->rpending) {
1192                                         m_freem(sc->rpending);
1193                                         sc->rpending = NULL;
1194                                 }
1195                         }
1196                         continue;
1197                 }
1198
1199                 /* XXX: Flush DMA for rxpkt */
1200
1201                 if (wx_get_rbuf(sc, rxpkt)) {
1202                         sc->wx_rxnobuf++;
1203                         wx_rxdma_map(sc, rxpkt, mb);
1204                         ifp->if_ierrors++;
1205                         rd->status = 0;
1206                         if (m0) {
1207                                 m_freem(m0);
1208                                 m0 = NULL;
1209                                 if (sc->rpending) {
1210                                         m_freem(sc->rpending);
1211                                         sc->rpending = NULL;
1212                                 }
1213                         }
1214                         continue;
1215                 }
1216
1217                 /*
1218                  * Save the completing packet's offset value and length
1219                  * and install the new one into the descriptor.
1220                  */
1221                 lastframe = (rd->status & RDSTAT_EOP) != 0;
1222                 length = rd->length;
1223                 offset = rd->address.lowpart & 0xff;
1224                 bzero (rd, sizeof (*rd));
1225                 rd->address.lowpart = rxpkt->dma_addr + WX_RX_OFFSET_VALUE;
1226
1227                 mb->m_len = length;
1228                 mb->m_data += offset;
1229                 mb->m_next = NULL;
1230                 if (m0 == NULL) {
1231                         m0 = mb;
1232                         tlen = length;
1233                 } else if (m0 == sc->rpending) {
1234                         /*
1235                          * Pick up where we left off before. If
1236                          * we have an offset (we're assuming the
1237                          * first frame has an offset), then we've
1238                          * lost sync somewhere along the line.
1239                          */
1240                         if (offset) {
1241                                 printf("%s: lost sync with partial packet\n",
1242                                     sc->wx_name);
1243                                 m_freem(sc->rpending);
1244                                 sc->rpending = NULL;
1245                                 m0 = mb;
1246                                 tlen = length;
1247                         } else {
1248                                 sc->rpending = NULL;
1249                                 tlen = m0->m_pkthdr.len;
1250                         }
1251                 } else {
1252                         tlen += length;
1253                 }
1254
1255                 DPRINTF(sc, ("%s: RDESC[%d] len %d off %d lastframe %d\n",
1256                     sc->wx_name, idx, mb->m_len, offset, lastframe));
1257                 if (m0 != mb)
1258                         m_cat(m0, mb);
1259                 if (lastframe == 0) {
1260                         continue;
1261                 }
1262                 m0->m_pkthdr.rcvif = ifp;
1263                 m0->m_pkthdr.len = tlen - WX_CRC_LENGTH;
1264                 mb->m_len -= WX_CRC_LENGTH;
1265
1266                 eh = mtod(m0, struct ether_header *);
1267                 /*
1268                  * No need to check for promiscous mode since
1269                  * the decision to keep or drop the packet is
1270                  * handled by ether_input()
1271                  */
1272                 pending[npkts++] = m0;
1273                 m0 = NULL;
1274                 tlen = 0;
1275         }
1276
1277         if (ndesc) {
1278                 if (IS_WISEMAN(sc)) {
1279                         WRITE_CSR(sc, WXREG_RDT0, lidx);
1280                 } else {
1281                         WRITE_CSR(sc, WXREG_RDT0_LIVENGOOD, lidx);
1282                 }
1283                 sc->rnxt = idx;
1284         }
1285
1286         if (npkts) {
1287                 sc->wx_rxintr++;
1288         }
1289
1290         for (idx = 0; idx < npkts; idx++) {
1291                 mb = pending[idx];
1292                 if (ifp->if_bpf) {
1293                         bpf_mtap(WX_BPFTAP_ARG(ifp), mb);
1294                 }
1295                 ifp->if_ipackets++;
1296                 DPRINTF(sc, ("%s: RECV packet length %d\n",
1297                     sc->wx_name, mb->m_pkthdr.len));
1298                 eh = mtod(mb, struct ether_header *);
1299                 m_adj(mb, sizeof (struct ether_header));
1300                 ether_input(ifp, eh, mb);
1301         }
1302 }
1303
1304 static void
1305 wx_gc(wx_softc_t *sc)
1306 {
1307         struct ifnet *ifp = &sc->wx_if;
1308         txpkt_t *txpkt;
1309         u_int32_t tdh;
1310
1311         WX_LOCK(sc);
1312         txpkt = sc->tbsyf;
1313         if (IS_WISEMAN(sc)) {
1314                 tdh = READ_CSR(sc, WXREG_TDH);
1315         } else {
1316                 tdh = READ_CSR(sc, WXREG_TDH_LIVENGOOD);
1317         }
1318         while (txpkt != NULL) {
1319                 u_int32_t end = txpkt->eidx, cidx = tdh;
1320
1321                 /*
1322                  * Normalize start..end indices to 2 *
1323                  * WX_MAX_TDESC range to eliminate wrap.
1324                  */
1325                 if (txpkt->eidx < txpkt->sidx) {
1326                         end += WX_MAX_TDESC;
1327                 }
1328
1329                 /*
1330                  * Normalize current chip index to 2 *
1331                  * WX_MAX_TDESC range to eliminate wrap.
1332                  */
1333                 if (cidx < txpkt->sidx) {
1334                         cidx += WX_MAX_TDESC;
1335                 }
1336
1337                 /*
1338                  * If the current chip index is between low and
1339                  * high indices for this packet, it's not finished
1340                  * transmitting yet. Because transmits are done FIFO,
1341                  * this means we're done garbage collecting too.
1342                  */
1343
1344                 if (txpkt->sidx <= cidx && cidx < txpkt->eidx) {
1345                         DPRINTF(sc, ("%s: TXGC %d..%d TDH %d\n", sc->wx_name,
1346                             txpkt->sidx, txpkt->eidx, tdh));
1347                         break;
1348                 }
1349                 ifp->if_opackets++;
1350
1351                 if (txpkt->dptr) {
1352                         (void) m_freem(txpkt->dptr);
1353                 } else {
1354                         printf("%s: null mbuf in gc\n", sc->wx_name);
1355                 }
1356
1357                 for (cidx = txpkt->sidx; cidx != txpkt->eidx;
1358                     cidx = T_NXT_IDX(cidx)) {
1359                         txpkt_t *tmp;
1360                         wxtd_t *td;
1361
1362                         td = &sc->tdescriptors[cidx];
1363                         if (td->status & TXSTS_EC) {
1364                                 IPRINTF(sc, ("%s: excess collisions\n",
1365                                     sc->wx_name));
1366                                 ifp->if_collisions++;
1367                                 ifp->if_oerrors++;
1368                         }
1369                         if (td->status & TXSTS_LC) {
1370                                 IPRINTF(sc,
1371                                     ("%s: lost carrier\n", sc->wx_name));
1372                                 ifp->if_oerrors++;
1373                         }
1374                         tmp = &sc->tbase[cidx];
1375                         DPRINTF(sc, ("%s: TXGC[%d] %p %d..%d done nact %d "
1376                             "TDH %d\n", sc->wx_name, cidx, tmp->dptr,
1377                             txpkt->sidx, txpkt->eidx, sc->tactive, tdh));
1378                         tmp->dptr = NULL;
1379                         if (sc->tactive == 0) {
1380                                 printf("%s: nactive < 0?\n", sc->wx_name);
1381                         } else {
1382                                 sc->tactive -= 1;
1383                         }
1384                         bzero(td, sizeof (*td));
1385                 }
1386                 sc->tbsyf = txpkt->next;
1387                 txpkt = sc->tbsyf;
1388         }
1389         if (sc->tactive < WX_MAX_TDESC - 1) {
1390                 ifp->if_timer = 0;
1391                 ifp->if_flags &= ~IFF_OACTIVE;
1392         }
1393
1394         /* used SW LED to indicate transmission not active */
1395         if (sc->tactive == 0 && sc->wx_mii) {
1396                 WRITE_CSR(sc, WXREG_DCR,
1397                     READ_CSR(sc, WXREG_DCR) & ~(WXDCR_SWDPIO0|WXDCR_SWDPIN0));
1398         }
1399         WX_UNLOCK(sc);
1400 }
1401
1402 /*
1403  * Periodic timer to update packet in/out/collision statistics,
1404  * and, more importantly, garbage collect completed transmissions
1405  * and to handle link status changes.
1406  */
1407 #define WX_PRT_STATS(sc, y)     printf("\t" # y " = %u\n", ((sc)->y))
1408 #define WX_CLR_STATS(sc, y)     ((sc)->y  = 0)
1409
1410 static void
1411 wx_watchdog(void *arg)
1412 {
1413         wx_softc_t *sc = arg;
1414
1415         WX_LOCK(sc);
1416         if (sc->wx_needreinit) {
1417                 WX_UNLOCK(sc);
1418                 if (wx_init(sc) == 0) {
1419                         WX_LOCK(sc);
1420                         sc->wx_needreinit = 0;
1421                 } else {
1422                         WX_LOCK(sc);
1423                 }
1424         } else {
1425                 wx_gc(sc);
1426                 wx_check_link(sc);
1427         }
1428         if (wx_dump_stats == device_get_unit(sc->w.dev)) {
1429                 printf("%s: current statistics\n", sc->wx_name);
1430                 WX_PRT_STATS(sc, wx_intr);
1431                 WX_PRT_STATS(sc, wx_linkintr);
1432                 WX_PRT_STATS(sc, wx_rxintr);
1433                 WX_PRT_STATS(sc, wx_txqe);
1434                 WX_PRT_STATS(sc, wx_xmitgc);
1435                 WX_PRT_STATS(sc, wx_xmitpullup);
1436                 WX_PRT_STATS(sc, wx_xmitcluster);
1437                 WX_PRT_STATS(sc, wx_xmitputback);
1438                 WX_PRT_STATS(sc, wx_xmitwanted);
1439                 WX_PRT_STATS(sc, wx_xmitblocked);
1440                 WX_PRT_STATS(sc, wx_xmitrunt);
1441                 WX_PRT_STATS(sc, wx_rxnobuf);
1442                 WX_PRT_STATS(sc, wx_oddpkt);
1443                 wx_dump_stats = -1;
1444         }
1445         if (wx_clr_stats == device_get_unit(sc->w.dev)) {
1446                 printf("%s: statistics cleared\n", sc->wx_name);
1447                 WX_CLR_STATS(sc, wx_intr);
1448                 WX_CLR_STATS(sc, wx_linkintr);
1449                 WX_CLR_STATS(sc, wx_rxintr);
1450                 WX_CLR_STATS(sc, wx_txqe);
1451                 WX_CLR_STATS(sc, wx_xmitgc);
1452                 WX_CLR_STATS(sc, wx_xmitpullup);
1453                 WX_CLR_STATS(sc, wx_xmitcluster);
1454                 WX_CLR_STATS(sc, wx_xmitputback);
1455                 WX_CLR_STATS(sc, wx_xmitwanted);
1456                 WX_CLR_STATS(sc, wx_xmitblocked);
1457                 WX_CLR_STATS(sc, wx_xmitrunt);
1458                 WX_CLR_STATS(sc, wx_rxnobuf);
1459                 WX_CLR_STATS(sc, wx_oddpkt);
1460                 wx_clr_stats = -1;
1461         }
1462         WX_UNLOCK(sc);
1463
1464         /*
1465          * Schedule another timeout one second from now.
1466          */
1467         TIMEOUT(sc, wx_watchdog, sc, hz);
1468 }
1469
1470 /*
1471  * Stop and reinitialize the hardware
1472  */
1473 static void
1474 wx_hw_stop(wx_softc_t *sc)
1475 {
1476         u_int32_t icr;
1477         DPRINTF(sc, ("%s: wx_hw_stop\n", sc->wx_name));
1478         WX_DISABLE_INT(sc);
1479         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1480                 wx_mwi_whackon(sc);
1481         }
1482         WRITE_CSR(sc, WXREG_DCR, WXDCR_RST);
1483         DELAY(20 * 1000);
1484         icr = READ_CSR(sc, WXREG_ICR);
1485         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1486                 wx_mwi_unwhack(sc);
1487         }
1488 }
1489
1490 static void
1491 wx_set_addr(wx_softc_t *sc, int idx, u_int8_t *mac)
1492 {
1493         u_int32_t t0, t1;
1494         DPRINTF(sc, ("%s: wx_set_addr\n", sc->wx_name));
1495         t0 = (mac[0]) | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
1496         t1 = (mac[4] << 0) | (mac[5] << 8);
1497         t1 |= WX_RAL_AV;
1498         WRITE_CSR(sc, WXREG_RAL_LO(idx), t0);
1499         WRITE_CSR(sc, WXREG_RAL_HI(idx), t1);
1500 }
1501
1502 static int
1503 wx_hw_initialize(wx_softc_t *sc)
1504 {
1505         int i;
1506
1507         DPRINTF(sc, ("%s: wx_hw_initialize\n", sc->wx_name));
1508
1509         WRITE_CSR(sc, WXREG_VET, 0);
1510         for (i = 0; i < (WX_VLAN_TAB_SIZE << 2); i += 4) {
1511                 WRITE_CSR(sc, (WXREG_VFTA + i), 0);
1512         }
1513         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1514                 wx_mwi_whackon(sc);
1515                 WRITE_CSR(sc, WXREG_RCTL, WXRCTL_RST);
1516                 DELAY(5 * 1000);
1517         }
1518         /*
1519          * Load the first receiver address with our MAC address,
1520          * and load as many multicast addresses as can fit into
1521          * the receive address array.
1522          */
1523         wx_set_addr(sc, 0, sc->wx_enaddr);
1524         for (i = 1; i <= sc->wx_nmca; i++) {
1525                 if (i >= WX_RAL_TAB_SIZE) {
1526                         break;
1527                 } else {
1528                         wx_set_addr(sc, i, sc->wx_mcaddr[i-1]);
1529                 }
1530         }
1531
1532         while (i < WX_RAL_TAB_SIZE) {
1533                 WRITE_CSR(sc, WXREG_RAL_LO(i), 0);
1534                 WRITE_CSR(sc, WXREG_RAL_HI(i), 0);
1535                 i++;
1536         }
1537
1538         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1539                 WRITE_CSR(sc, WXREG_RCTL, 0);
1540                 DELAY(1 * 1000);
1541                 wx_mwi_unwhack(sc);
1542         }
1543
1544         /*
1545          * Clear out the hashed multicast table array.
1546          */
1547         for (i = 0; i < WX_MC_TAB_SIZE; i++) {
1548                 WRITE_CSR(sc, WXREG_MTA + (sizeof (u_int32_t) * 4), 0);
1549         }
1550
1551         if (IS_LIVENGOOD_CU(sc)) {
1552                 /*
1553                  * has a PHY - raise its reset line to make it operational
1554                  */
1555                 u_int32_t tmp = READ_CSR(sc, WXREG_EXCT);
1556                 tmp |= WXPHY_RESET_DIR4;
1557                 WRITE_CSR(sc, WXREG_EXCT, tmp);
1558                 DELAY(20*1000);
1559
1560                 tmp = READ_CSR(sc, WXREG_EXCT);
1561                 tmp &= ~WXPHY_RESET4;
1562                 WRITE_CSR(sc, WXREG_EXCT, tmp);
1563                 DELAY(20*1000);
1564
1565                 tmp = READ_CSR(sc, WXREG_EXCT);
1566                 tmp |= WXPHY_RESET4;
1567                 WRITE_CSR(sc, WXREG_EXCT, tmp);
1568                 DELAY(20*1000);
1569         } else if (IS_LIVENGOOD(sc)) {
1570                 u_int16_t tew;
1571
1572                 /*
1573                  * Handle link control
1574                  */
1575                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr | WXDCR_LRST);
1576                 DELAY(50 * 1000);
1577
1578                 wx_read_eeprom(sc, &tew, WX_EEPROM_CTLR2_OFF, 1);
1579                 tew = (tew & WX_EEPROM_CTLR2_SWDPIO) << WX_EEPROM_EXT_SHIFT;
1580                 WRITE_CSR(sc, WXREG_EXCT, (u_int32_t)tew);
1581         }
1582
1583         if (sc->wx_dcr & (WXDCR_RFCE|WXDCR_TFCE)) {
1584                 WRITE_CSR(sc, WXREG_FCAL, FC_FRM_CONST_LO);
1585                 WRITE_CSR(sc, WXREG_FCAH, FC_FRM_CONST_HI);
1586                 WRITE_CSR(sc, WXREG_FCT, FC_TYP_CONST);
1587         } else {
1588                 WRITE_CSR(sc, WXREG_FCAL, 0);
1589                 WRITE_CSR(sc, WXREG_FCAH, 0);
1590                 WRITE_CSR(sc, WXREG_FCT, 0);
1591         }
1592         WRITE_CSR(sc, WXREG_FLOW_XTIMER, WX_XTIMER_DFLT);
1593
1594         if (IS_WISEMAN(sc)) {
1595                 if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1596                         WRITE_CSR(sc, WXREG_FLOW_RCV_HI, 0);
1597                         WRITE_CSR(sc, WXREG_FLOW_RCV_LO, 0);
1598                         sc->wx_dcr &= ~(WXDCR_RFCE|WXDCR_TFCE);
1599                 } else {
1600                         WRITE_CSR(sc, WXREG_FLOW_RCV_HI, WX_RCV_FLOW_HI_DFLT);
1601                         WRITE_CSR(sc, WXREG_FLOW_RCV_LO, WX_RCV_FLOW_LO_DFLT);
1602                 }
1603         } else {
1604                 WRITE_CSR(sc, WXREG_FLOW_RCV_HI_LIVENGOOD, WX_RCV_FLOW_HI_DFLT);
1605                 WRITE_CSR(sc, WXREG_FLOW_RCV_LO_LIVENGOOD, WX_RCV_FLOW_LO_DFLT);
1606         }
1607
1608         if (!IS_LIVENGOOD_CU(sc))
1609                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT);
1610
1611         WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1612         DELAY(50 * 1000);
1613
1614         if (!IS_LIVENGOOD_CU(sc)) {
1615                 /*
1616                  * The pin stuff is all FM from the Linux driver.
1617                  */
1618                 if ((READ_CSR(sc, WXREG_DCR) & WXDCR_SWDPIN1) == 0) {
1619                         for (i = 0; i < (WX_LINK_UP_TIMEOUT/10); i++) {
1620                                 DELAY(10 * 1000);
1621                                 if (READ_CSR(sc, WXREG_DSR) & WXDSR_LU) {
1622                                         sc->linkup = 1;
1623                                         break;
1624                                 }
1625                         }
1626                         if (sc->linkup == 0) {
1627                                 sc->ane_failed = 1;
1628                                 wx_check_link(sc);
1629                         }
1630                         sc->ane_failed = 0;
1631                 } else {
1632                         printf("%s: SWDPIO1 did not clear- check for reversed "
1633                                 "or disconnected cable\n", sc->wx_name);
1634                         /* but return okay anyway */
1635                 }
1636         }
1637
1638         sc->wx_ienable = WXIENABLE_DEFAULT;
1639         return (0);
1640 }
1641
1642 /*
1643  * Stop the interface. Cancels the statistics updater and resets the interface.
1644  */
1645 static void
1646 wx_stop(wx_softc_t *sc)
1647 {
1648         txpkt_t *txp;
1649         rxpkt_t *rxp;
1650         struct ifnet *ifp = &sc->wx_if;
1651
1652         DPRINTF(sc, ("%s: wx_stop\n", sc->wx_name));
1653         /*
1654          * Cancel stats updater.
1655          */
1656         UNTIMEOUT(wx_watchdog, sc, sc);
1657
1658         /*
1659          * Reset the chip
1660          */
1661         wx_hw_stop(sc);
1662
1663         /*
1664          * Release any xmit buffers.
1665          */
1666         for (txp = sc->tbase; txp && txp < &sc->tbase[WX_MAX_TDESC]; txp++) {
1667                 if (txp->dptr) {
1668                         m_free(txp->dptr);
1669                         txp->dptr = NULL;
1670                 }
1671         }
1672
1673         /*
1674          * Free all the receive buffers.
1675          */
1676         for (rxp = sc->rbase; rxp && rxp < &sc->rbase[WX_MAX_RDESC]; rxp++) {
1677                 if (rxp->dptr) {
1678                         m_free(rxp->dptr);
1679                         rxp->dptr = NULL;
1680                 }
1681         }
1682
1683         if (sc->rpending) {
1684                 m_freem(sc->rpending);
1685                 sc->rpending = NULL;
1686         }
1687
1688         /*
1689          * And we're outta here...
1690          */
1691
1692         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1693         ifp->if_timer = 0;
1694 }
1695
1696 /*
1697  * Transmit Watchdog
1698  */
1699 static void
1700 wx_txwatchdog(struct ifnet *ifp)
1701 {
1702         wx_softc_t *sc = SOFTC_IFP(ifp);
1703         printf("%s: device timeout\n", sc->wx_name);
1704         ifp->if_oerrors++;
1705         if (wx_init(sc)) {
1706                 printf("%s: could not re-init device\n", sc->wx_name);
1707                 sc->wx_needreinit = 1;
1708         }
1709 }
1710
1711 static int
1712 wx_init(void *xsc)
1713 {
1714         struct ifmedia *ifm;
1715         wx_softc_t *sc = xsc;
1716         struct ifnet *ifp = &sc->wx_if;
1717         rxpkt_t *rxpkt;
1718         wxrd_t *rd;
1719         size_t len;
1720         int i, bflags;
1721
1722         DPRINTF(sc, ("%s: wx_init\n", sc->wx_name));
1723         WX_LOCK(sc);
1724
1725         /*
1726          * Cancel any pending I/O by resetting things.
1727          * wx_stop will free any allocated mbufs.
1728          */
1729         wx_stop(sc);
1730
1731         /*
1732          * Reset the hardware. All network addresses loaded here, but
1733          * neither the receiver nor the transmitter are enabled.
1734          */
1735
1736         if (wx_hw_initialize(sc)) {
1737                 DPRINTF(sc, ("%s: wx_hw_initialize failed\n", sc->wx_name));
1738                 WX_UNLOCK(sc);
1739                 return (EIO);
1740         }
1741
1742         /*
1743          * Set up the receive ring stuff.
1744          */
1745         len = sizeof (wxrd_t) * WX_MAX_RDESC;
1746         bzero(sc->rdescriptors, len);
1747         for (rxpkt = sc->rbase, i = 0; rxpkt != NULL && i < WX_MAX_RDESC;
1748             i += RXINCR, rxpkt++) {
1749                 rd = &sc->rdescriptors[i];
1750                 if (wx_get_rbuf(sc, rxpkt)) {
1751                         break;
1752                 }
1753                 rd->address.lowpart = rxpkt->dma_addr + WX_RX_OFFSET_VALUE;
1754         }
1755         if (i != WX_MAX_RDESC) {
1756                 printf("%s: could not set up rbufs\n", sc->wx_name);
1757                 wx_stop(sc);
1758                 WX_UNLOCK(sc);
1759                 return (ENOMEM);
1760         }
1761
1762         /*
1763          * Set up transmit parameters and enable the transmitter.
1764          */
1765         sc->tnxtfree = sc->tactive = 0;
1766         sc->tbsyf = sc->tbsyl = NULL;
1767         WRITE_CSR(sc, WXREG_TCTL, 0);
1768         DELAY(5 * 1000);
1769         if (IS_WISEMAN(sc)) {
1770                 WRITE_CSR(sc, WXREG_TDBA_LO,
1771                         vtophys((vm_offset_t)&sc->tdescriptors[0]));
1772                 WRITE_CSR(sc, WXREG_TDBA_HI, 0);
1773                 WRITE_CSR(sc, WXREG_TDLEN, WX_MAX_TDESC * sizeof (wxtd_t));
1774                 WRITE_CSR(sc, WXREG_TDH, 0);
1775                 WRITE_CSR(sc, WXREG_TDT, 0);
1776                 WRITE_CSR(sc, WXREG_TQSA_HI, 0);
1777                 WRITE_CSR(sc, WXREG_TQSA_LO, 0);
1778                 WRITE_CSR(sc, WXREG_TIPG, WX_WISEMAN_TIPG_DFLT);
1779                 WRITE_CSR(sc, WXREG_TIDV, wx_txint_delay);
1780         } else {
1781                 WRITE_CSR(sc, WXREG_TDBA_LO_LIVENGOOD,
1782                         vtophys((vm_offset_t)&sc->tdescriptors[0]));
1783                 WRITE_CSR(sc, WXREG_TDBA_HI_LIVENGOOD, 0);
1784                 WRITE_CSR(sc, WXREG_TDLEN_LIVENGOOD,
1785                         WX_MAX_TDESC * sizeof (wxtd_t));
1786                 WRITE_CSR(sc, WXREG_TDH_LIVENGOOD, 0);
1787                 WRITE_CSR(sc, WXREG_TDT_LIVENGOOD, 0);
1788                 WRITE_CSR(sc, WXREG_TQSA_HI, 0);
1789                 WRITE_CSR(sc, WXREG_TQSA_LO, 0);
1790                 WRITE_CSR(sc, WXREG_TIPG, WX_LIVENGOOD_TIPG_DFLT);
1791                 WRITE_CSR(sc, WXREG_TIDV_LIVENGOOD, wx_txint_delay);
1792         }
1793         WRITE_CSR(sc, WXREG_TCTL, (WXTCTL_CT(WX_COLLISION_THRESHOLD) |
1794             WXTCTL_COLD(WX_FDX_COLLISION_DX) | WXTCTL_EN));
1795         /*
1796          * Set up receive parameters and enable the receiver.
1797          */
1798
1799         sc->rnxt = 0;
1800         WRITE_CSR(sc, WXREG_RCTL, 0);
1801         DELAY(5 * 1000);
1802         if (IS_WISEMAN(sc)) {
1803                 WRITE_CSR(sc, WXREG_RDTR0, WXRDTR_FPD);
1804                 WRITE_CSR(sc, WXREG_RDBA0_LO,
1805                     vtophys((vm_offset_t)&sc->rdescriptors[0]));
1806                 WRITE_CSR(sc, WXREG_RDBA0_HI, 0);
1807                 WRITE_CSR(sc, WXREG_RDLEN0, WX_MAX_RDESC * sizeof (wxrd_t));
1808                 WRITE_CSR(sc, WXREG_RDH0, 0);
1809                 WRITE_CSR(sc, WXREG_RDT0, (WX_MAX_RDESC - RXINCR));
1810         } else {
1811                 /*
1812                  * The delay should yield ~10us receive interrupt delay
1813                  */
1814                 WRITE_CSR(sc, WXREG_RDTR0_LIVENGOOD, WXRDTR_FPD | 0x40);
1815                 WRITE_CSR(sc, WXREG_RDBA0_LO_LIVENGOOD,
1816                     vtophys((vm_offset_t)&sc->rdescriptors[0]));
1817                 WRITE_CSR(sc, WXREG_RDBA0_HI_LIVENGOOD, 0);
1818                 WRITE_CSR(sc, WXREG_RDLEN0_LIVENGOOD,
1819                     WX_MAX_RDESC * sizeof (wxrd_t));
1820                 WRITE_CSR(sc, WXREG_RDH0_LIVENGOOD, 0);
1821                 WRITE_CSR(sc, WXREG_RDT0_LIVENGOOD, (WX_MAX_RDESC - RXINCR));
1822         }
1823         WRITE_CSR(sc, WXREG_RDTR1, 0);
1824         WRITE_CSR(sc, WXREG_RDBA1_LO, 0);
1825         WRITE_CSR(sc, WXREG_RDBA1_HI, 0);
1826         WRITE_CSR(sc, WXREG_RDLEN1, 0);
1827         WRITE_CSR(sc, WXREG_RDH1, 0);
1828         WRITE_CSR(sc, WXREG_RDT1, 0);
1829
1830         if (ifp->if_mtu > ETHERMTU) {
1831                 bflags = WXRCTL_EN | WXRCTL_LPE | WXRCTL_2KRBUF;
1832         } else {
1833                 bflags = WXRCTL_EN | WXRCTL_2KRBUF;
1834         }
1835
1836         WRITE_CSR(sc, WXREG_RCTL, bflags |
1837             ((ifp->if_flags & IFF_BROADCAST) ? WXRCTL_BAM : 0) |
1838             ((ifp->if_flags & IFF_PROMISC) ? WXRCTL_UPE : 0) |
1839             ((sc->all_mcasts) ? WXRCTL_MPE : 0));
1840
1841         /*
1842          * Enable Interrupts
1843          */
1844         WX_ENABLE_INT(sc);
1845
1846         if (sc->wx_mii) {
1847                 mii_mediachg(WX_MII_FROM_SOFTC(sc));
1848         } else {
1849                 ifm = &sc->wx_media;
1850                 i = ifm->ifm_media;
1851                 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1852                 wx_ifmedia_upd(ifp);
1853                 ifm->ifm_media = i;
1854         }
1855
1856         /*
1857          * Mark that we're up and running...
1858          */
1859         ifp->if_flags |= IFF_RUNNING;
1860         ifp->if_flags &= ~IFF_OACTIVE;
1861
1862
1863         /*
1864          * Start stats updater.
1865          */
1866         TIMEOUT(sc, wx_watchdog, sc, hz);
1867
1868         WX_UNLOCK(sc);
1869         /*
1870          * And we're outta here...
1871          */
1872         return (0);
1873 }
1874
1875 /*
1876  * Get a receive buffer for our use (and dma map the data area).
1877  *
1878  * The Wiseman chip can have buffers be 256, 512, 1024 or 2048 bytes in size.
1879  * The LIVENGOOD chip can go higher (up to 16K), but what's the point as
1880  * we aren't doing non-MCLGET memory management.
1881  *
1882  * It wants them aligned on 256 byte boundaries, but can actually cope
1883  * with an offset in the first 255 bytes of the head of a receive frame.
1884  *
1885  * We'll allocate a MCLBYTE sized cluster but *not* adjust the data pointer
1886  * by any alignment value. Instead, we'll tell the chip to offset by any
1887  * alignment and we'll catch the alignment on the backend at interrupt time.
1888  */
1889 static void
1890 wx_rxdma_map(wx_softc_t *sc, rxpkt_t *rxpkt, struct mbuf *mb)
1891 {
1892         rxpkt->dptr = mb;
1893         rxpkt->dma_addr = vtophys(mtod(mb, vm_offset_t));
1894 }
1895
1896 static int
1897 wx_get_rbuf(wx_softc_t *sc, rxpkt_t *rxpkt)
1898 {
1899         struct mbuf *mb;
1900         MGETHDR(mb, M_DONTWAIT, MT_DATA);
1901         if (mb == NULL) {
1902                 rxpkt->dptr = NULL;
1903                 return (-1);
1904         }
1905         MCLGET(mb, M_DONTWAIT);
1906         if ((mb->m_flags & M_EXT) == 0) {
1907                 m_freem(mb);
1908                 rxpkt->dptr = NULL;
1909                 return (-1);
1910         }
1911         wx_rxdma_map(sc, rxpkt, mb);
1912         return (0);
1913 }
1914
1915 static int
1916 wx_ioctl(struct ifnet *ifp, IOCTL_CMD_TYPE command, caddr_t data)
1917 {
1918         wx_softc_t *sc = SOFTC_IFP(ifp);
1919         struct ifreq *ifr = (struct ifreq *) data;
1920         int error = 0;
1921
1922         WX_LOCK(sc);
1923         switch (command) {
1924         case SIOCSIFADDR:
1925         case SIOCGIFADDR:
1926                 error = ether_ioctl(ifp, command, data);
1927                 break;
1928         case SIOCSIFMTU:
1929                 if (ifr->ifr_mtu > WX_MAXMTU || ifr->ifr_mtu < ETHERMIN) {
1930                         error = EINVAL;
1931                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
1932                         ifp->if_mtu = ifr->ifr_mtu;
1933                         error = wx_init(sc);
1934                 }
1935                 break;
1936         case SIOCSIFFLAGS:
1937                 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1938
1939                 /*
1940                  * If interface is marked up and not running, then start it.
1941                  * If it is marked down and running, stop it.
1942                  * If it's up then re-initialize it. This is so flags
1943                  * such as IFF_PROMISC are handled.
1944                  */
1945                 if (ifp->if_flags & IFF_UP) {
1946                         if ((ifp->if_flags & IFF_RUNNING) == 0) {
1947                                 error = wx_init(sc);
1948                         }
1949                 } else {
1950                         if (ifp->if_flags & IFF_RUNNING) {
1951                                 wx_stop(sc);
1952                         }
1953                 }
1954                 break;
1955
1956         case SIOCADDMULTI:
1957         case SIOCDELMULTI:
1958                 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1959                 error = wx_mc_setup(sc);
1960                 break;
1961         case SIOCGIFMEDIA:
1962         case SIOCSIFMEDIA:
1963                 DPRINTF(sc, ("%s: ioctl SIOC[GS]IFMEDIA: command=%#lx\n",
1964                     sc->wx_name, command));
1965                 if (sc->wx_mii) {
1966                         mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
1967                         error = ifmedia_ioctl(ifp, ifr,
1968                             &mii->mii_media, command);
1969                 } else {
1970                         error = ifmedia_ioctl(ifp, ifr, &sc->wx_media, command);
1971                 }
1972
1973                 break;
1974         default:
1975                 error = EINVAL;
1976         }
1977
1978         WX_UNLOCK(sc);
1979         return (error);
1980 }
1981
1982 static int
1983 wx_ifmedia_upd(struct ifnet *ifp)
1984 {
1985         struct wx_softc *sc = SOFTC_IFP(ifp);
1986         struct ifmedia *ifm;
1987
1988         DPRINTF(sc, ("%s: ifmedia_upd\n", sc->wx_name));
1989
1990         if (sc->wx_mii) {
1991                 mii_mediachg(WX_MII_FROM_SOFTC(sc));
1992                 return 0;
1993         }
1994
1995         ifm = &sc->wx_media;
1996
1997         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1998                 return (EINVAL);
1999         }
2000
2001         return (0);
2002 }
2003
2004 static void
2005 wx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2006 {
2007         u_int32_t dsr;
2008         struct wx_softc *sc = SOFTC_IFP(ifp);
2009
2010         DPRINTF(sc, ("%s: ifmedia_sts: ", sc->wx_name));
2011
2012         if (sc->wx_mii) {
2013                 mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
2014                 mii_pollstat(mii);
2015                 ifmr->ifm_active = mii->mii_media_active;
2016                 ifmr->ifm_status = mii->mii_media_status;
2017                 DPRINTF(sc, ("active=%#x status=%#x\n",
2018                     ifmr->ifm_active, ifmr->ifm_status));
2019                 return;
2020         }
2021
2022         DPRINTF(sc, ("\n"));
2023         ifmr->ifm_status = IFM_AVALID;
2024         ifmr->ifm_active = IFM_ETHER;
2025
2026         if (sc->linkup == 0)
2027                 return;
2028
2029         ifmr->ifm_status |= IFM_ACTIVE;
2030         dsr = READ_CSR(sc, WXREG_DSR);
2031         if (IS_LIVENGOOD(sc)) {
2032                 if (dsr &  WXDSR_1000BT) {
2033                         if (IS_LIVENGOOD_CU(sc)) {
2034                                 ifmr->ifm_status |= IFM_1000_TX;
2035                         }
2036                         else {
2037                                 ifmr->ifm_status |= IFM_1000_SX;
2038                         }
2039                 } else if (dsr & WXDSR_100BT) {
2040                         ifmr->ifm_status |= IFM_100_FX; /* ?? */
2041                 } else {
2042                         ifmr->ifm_status |= IFM_10_T;   /* ?? */
2043                 }
2044         } else {
2045                 ifmr->ifm_status |= IFM_1000_SX;
2046         }
2047         if (dsr & WXDSR_FD) {
2048                 ifmr->ifm_active |= IFM_FDX;
2049         }
2050 }
2051
2052
2053 #define RAISE_CLOCK(sc, dcr)    \
2054                 WRITE_CSR(sc, WXREG_DCR, (dcr) | WXPHY_MDC), DELAY(2)
2055
2056 #define LOWER_CLOCK(sc, dcr)    \
2057                 WRITE_CSR(sc, WXREG_DCR, (dcr) & ~WXPHY_MDC), DELAY(2)
2058
2059 static u_int32_t
2060 wx_mii_shift_in(wx_softc_t *sc)
2061 {
2062         u_int32_t dcr, i;
2063         u_int32_t data = 0;
2064
2065         dcr = READ_CSR(sc, WXREG_DCR);
2066         dcr &= ~(WXPHY_MDIO_DIR | WXPHY_MDIO);
2067         WRITE_CSR(sc, WXREG_DCR, dcr);
2068         RAISE_CLOCK(sc, dcr);
2069         LOWER_CLOCK(sc, dcr);
2070
2071         for (i = 0; i < 16; i++) {
2072                 data <<= 1;
2073                 RAISE_CLOCK(sc, dcr);
2074                 dcr = READ_CSR(sc, WXREG_DCR);
2075
2076                 if (dcr & WXPHY_MDIO)
2077                         data |= 1;
2078
2079                 LOWER_CLOCK(sc, dcr);
2080         }
2081
2082         RAISE_CLOCK(sc, dcr);
2083         LOWER_CLOCK(sc, dcr);
2084         return (data);
2085 }
2086
2087 static void
2088 wx_mii_shift_out(wx_softc_t *sc, u_int32_t data, u_int32_t count)
2089 {
2090         u_int32_t dcr, mask;
2091
2092         dcr = READ_CSR(sc, WXREG_DCR);
2093         dcr |= WXPHY_MDIO_DIR | WXPHY_MDC_DIR;
2094
2095         for (mask = (1 << (count - 1)); mask; mask >>= 1) {
2096                 if (data & mask)
2097                         dcr |= WXPHY_MDIO;
2098                 else
2099                         dcr &= ~WXPHY_MDIO;
2100
2101                 WRITE_CSR(sc, WXREG_DCR, dcr);
2102                 DELAY(2);
2103                 RAISE_CLOCK(sc, dcr);
2104                 LOWER_CLOCK(sc, dcr);
2105         }
2106 }
2107
2108 static int
2109 wx_miibus_readreg(void *arg, int phy, int reg)
2110 {
2111         wx_softc_t *sc = WX_SOFTC_FROM_MII_ARG(arg);
2112         unsigned int data = 0;
2113
2114         if (!IS_LIVENGOOD_CU(sc)) {
2115                 return 0;
2116         }
2117         wx_mii_shift_out(sc, WXPHYC_PREAMBLE, WXPHYC_PREAMBLE_LEN);
2118         wx_mii_shift_out(sc, reg | (phy << 5) | (WXPHYC_READ << 10) |
2119             (WXPHYC_SOF << 12), 14);
2120         data = wx_mii_shift_in(sc);
2121         return (data & WXMDIC_DATA_MASK);
2122 }
2123
2124 static int
2125 wx_miibus_writereg(void *arg, int phy, int reg, int data)
2126 {
2127         wx_softc_t *sc = WX_SOFTC_FROM_MII_ARG(arg);
2128         if (!IS_LIVENGOOD_CU(sc)) {
2129                 return 0;
2130         }
2131         wx_mii_shift_out(sc, WXPHYC_PREAMBLE, WXPHYC_PREAMBLE_LEN);
2132         wx_mii_shift_out(sc, (u_int32_t)data | (WXPHYC_TURNAROUND << 16) |
2133             (reg << 18) | (phy << 23) | (WXPHYC_WRITE << 28) |
2134             (WXPHYC_SOF << 30), 32);
2135         return (0);
2136 }
2137
2138 static void
2139 wx_miibus_statchg(void *arg)
2140 {
2141         wx_softc_t *sc = WX_SOFTC_FROM_MII_ARG(arg);
2142         mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
2143         u_int32_t dcr, tctl;
2144
2145         if (mii == NULL)
2146                 return;
2147
2148         dcr = sc->wx_dcr;
2149         tctl = READ_CSR(sc, WXREG_TCTL);
2150         DPRINTF(sc, ("%s: statchg dcr=%#x tctl=%#x", sc->wx_name, dcr, tctl));
2151
2152         dcr |= WXDCR_FRCSPD | WXDCR_FRCDPX | WXDCR_SLU;
2153         dcr &= ~(WXDCR_SPEED_MASK | WXDCR_ASDE /* | WXDCR_ILOS */);
2154
2155         if (mii->mii_media_status & IFM_ACTIVE) {
2156                 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE) {
2157                         DPRINTF(sc, (" link-down\n"));
2158                         sc->linkup = 0;
2159                         return;
2160                 }
2161
2162                 sc->linkup = 1;
2163         }
2164
2165         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) {
2166                 DPRINTF(sc, (" 1000TX"));
2167                 dcr |= WXDCR_1000BT;
2168         } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2169                 DPRINTF(sc, (" 100TX"));
2170                 dcr |= WXDCR_100BT;
2171         } else  /* assume IFM_10_TX */ {
2172                 DPRINTF(sc, (" 10TX"));
2173                 dcr |= WXDCR_10BT;
2174         }
2175
2176         if (mii->mii_media_active & IFM_FDX) {
2177                 DPRINTF(sc, ("-FD"));
2178                 tctl = WXTCTL_CT(WX_COLLISION_THRESHOLD) |
2179                     WXTCTL_COLD(WX_FDX_COLLISION_DX) | WXTCTL_EN;
2180                 dcr |= WXDCR_FD;
2181         } else {
2182                 DPRINTF(sc, ("-HD"));
2183                 tctl = WXTCTL_CT(WX_COLLISION_THRESHOLD) |
2184                     WXTCTL_COLD(WX_HDX_COLLISION_DX) | WXTCTL_EN;
2185                 dcr &= ~WXDCR_FD;
2186         }
2187
2188         /* FLAG0==rx-flow-control FLAG1==tx-flow-control */
2189         if (mii->mii_media_active & IFM_FLAG0) {
2190                 dcr |= WXDCR_RFCE;
2191         } else {
2192                 dcr &= ~WXDCR_RFCE;
2193         }
2194
2195         if (mii->mii_media_active & IFM_FLAG1) {
2196                 dcr |= WXDCR_TFCE;
2197         } else {
2198                 dcr &= ~WXDCR_TFCE;
2199         }
2200
2201         if (dcr & (WXDCR_RFCE|WXDCR_TFCE)) {
2202                 WRITE_CSR(sc, WXREG_FCAL, FC_FRM_CONST_LO);
2203                 WRITE_CSR(sc, WXREG_FCAH, FC_FRM_CONST_HI);
2204                 WRITE_CSR(sc, WXREG_FCT, FC_TYP_CONST);
2205         } else {
2206                 WRITE_CSR(sc, WXREG_FCAL, 0);
2207                 WRITE_CSR(sc, WXREG_FCAH, 0);
2208                 WRITE_CSR(sc, WXREG_FCT, 0);
2209         }
2210
2211         DPRINTF(sc, (" dcr=%#x tctl=%#x\n", dcr, tctl));
2212         WRITE_CSR(sc, WXREG_TCTL, tctl);
2213         sc->wx_dcr = dcr;
2214         WRITE_CSR(sc, WXREG_DCR, dcr);
2215 }
2216
2217 static void
2218 wx_miibus_mediainit(void *arg)
2219 {
2220 }