2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/param.h>
36 #include <sys/bitops.h>
37 #include <sys/endian.h>
38 #include <sys/kernel.h>
40 #include <sys/interrupt.h>
41 #include <sys/malloc.h>
44 #include <sys/serialize.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
52 #include <net/if_arp.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/ifq_var.h>
57 #include <netproto/802_11/ieee80211_radiotap.h>
58 #include <netproto/802_11/ieee80211_var.h>
59 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
61 #include <bus/pci/pcireg.h>
62 #include <bus/pci/pcivar.h>
65 #include <dev/netif/bwi/if_bwireg.h>
66 #include <dev/netif/bwi/if_bwivar.h>
67 #include <dev/netif/bwi/bwimac.h>
68 #include <dev/netif/bwi/bwirf.h>
70 struct bwi_clock_freq {
75 struct bwi_myaddr_bssid {
76 uint8_t myaddr[IEEE80211_ADDR_LEN];
77 uint8_t bssid[IEEE80211_ADDR_LEN];
80 static int bwi_probe(device_t);
81 static int bwi_attach(device_t);
82 static int bwi_detach(device_t);
83 static int bwi_shutdown(device_t);
85 static void bwi_init(void *);
86 static int bwi_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
87 static void bwi_start(struct ifnet *, struct ifaltq_subque *);
88 static void bwi_watchdog(struct ifnet *);
89 static int bwi_newstate(struct ieee80211com *, enum ieee80211_state, int);
90 static void bwi_updateslot(struct ifnet *);
91 static int bwi_media_change(struct ifnet *);
92 static void *bwi_ratectl_attach(struct ieee80211com *, u_int);
94 static void bwi_next_scan(void *);
95 static void bwi_calibrate(void *);
97 static void bwi_newstate_begin(struct bwi_softc *, enum ieee80211_state);
98 static void bwi_init_statechg(struct bwi_softc *, int);
99 static int bwi_stop(struct bwi_softc *, int);
100 static int bwi_newbuf(struct bwi_softc *, int, int);
101 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
102 struct ieee80211_node **, int);
104 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
105 bus_addr_t, int, int);
106 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
108 static int bwi_init_tx_ring32(struct bwi_softc *, int);
109 static int bwi_init_rx_ring32(struct bwi_softc *);
110 static int bwi_init_txstats32(struct bwi_softc *);
111 static void bwi_free_tx_ring32(struct bwi_softc *, int);
112 static void bwi_free_rx_ring32(struct bwi_softc *);
113 static void bwi_free_txstats32(struct bwi_softc *);
114 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
115 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
116 int, bus_addr_t, int);
117 static int bwi_rxeof32(struct bwi_softc *);
118 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
119 static void bwi_txeof_status32(struct bwi_softc *);
121 static int bwi_init_tx_ring64(struct bwi_softc *, int);
122 static int bwi_init_rx_ring64(struct bwi_softc *);
123 static int bwi_init_txstats64(struct bwi_softc *);
124 static void bwi_free_tx_ring64(struct bwi_softc *, int);
125 static void bwi_free_rx_ring64(struct bwi_softc *);
126 static void bwi_free_txstats64(struct bwi_softc *);
127 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
128 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
129 int, bus_addr_t, int);
130 static int bwi_rxeof64(struct bwi_softc *);
131 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
132 static void bwi_txeof_status64(struct bwi_softc *);
134 static void bwi_intr(void *);
135 static int bwi_rxeof(struct bwi_softc *, int);
136 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
137 static void bwi_txeof(struct bwi_softc *);
138 static void bwi_txeof_status(struct bwi_softc *, int);
139 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
140 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
141 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
142 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
143 struct bwi_rxbuf_hdr *, const void *, int, int);
145 static int bwi_dma_alloc(struct bwi_softc *);
146 static void bwi_dma_free(struct bwi_softc *);
147 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
148 struct bwi_ring_data *, bus_size_t,
150 static int bwi_dma_mbuf_create(struct bwi_softc *);
151 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
152 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
153 static void bwi_dma_txstats_free(struct bwi_softc *);
154 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
155 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
158 static void bwi_power_on(struct bwi_softc *, int);
159 static int bwi_power_off(struct bwi_softc *, int);
160 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
161 static int bwi_set_clock_delay(struct bwi_softc *);
162 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
163 static int bwi_get_pwron_delay(struct bwi_softc *sc);
164 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
166 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
167 static int bwi_set_chan(struct bwi_softc *, struct ieee80211_channel *);
169 static void bwi_get_card_flags(struct bwi_softc *);
170 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
172 static int bwi_bus_attach(struct bwi_softc *);
173 static int bwi_bbp_attach(struct bwi_softc *);
174 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
175 static void bwi_bbp_power_off(struct bwi_softc *);
177 static const char *bwi_regwin_name(const struct bwi_regwin *);
178 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
179 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
180 static int bwi_regwin_select(struct bwi_softc *, int);
182 static void bwi_led_attach(struct bwi_softc *);
183 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
184 static void bwi_led_event(struct bwi_softc *, int);
185 static void bwi_led_blink_start(struct bwi_softc *, int, int);
186 static void bwi_led_blink_next(void *);
187 static void bwi_led_blink_end(void *);
189 static const struct bwi_dev {
194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4301,
195 "Broadcom BCM4301 802.11 Wireless Lan" },
197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4307,
198 "Broadcom BCM4307 802.11 Wireless Lan" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4311,
201 "Broadcom BCM4311 802.11 Wireless Lan" },
203 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4312,
204 "Broadcom BCM4312 802.11 Wireless Lan" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_1,
207 "Broadcom BCM4306 802.11 Wireless Lan" },
209 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_2,
210 "Broadcom BCM4306 802.11 Wireless Lan" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_3,
213 "Broadcom BCM4306 802.11 Wireless Lan" },
215 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4309,
216 "Broadcom BCM4309 802.11 Wireless Lan" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4318,
219 "Broadcom BCM4318 802.11 Wireless Lan" },
221 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4319,
222 "Broadcom BCM4319 802.11 Wireless Lan" }
225 static device_method_t bwi_methods[] = {
226 DEVMETHOD(device_probe, bwi_probe),
227 DEVMETHOD(device_attach, bwi_attach),
228 DEVMETHOD(device_detach, bwi_detach),
229 DEVMETHOD(device_shutdown, bwi_shutdown),
231 DEVMETHOD(device_suspend, bwi_suspend),
232 DEVMETHOD(device_resume, bwi_resume),
237 static driver_t bwi_driver = {
240 sizeof(struct bwi_softc)
243 static devclass_t bwi_devclass;
245 DRIVER_MODULE(bwi, pci, bwi_driver, bwi_devclass, NULL, NULL);
246 DRIVER_MODULE(bwi, cardbus, bwi_driver, bwi_devclass, NULL, NULL);
248 MODULE_DEPEND(bwi, wlan, 1, 1, 1);
249 MODULE_DEPEND(bwi, wlan_ratectl_onoe, 1, 1, 1);
251 MODULE_DEPEND(bwi, wlan_ratectl_amrr, 1, 1, 1);
253 MODULE_DEPEND(bwi, pci, 1, 1, 1);
254 MODULE_DEPEND(bwi, cardbus, 1, 1, 1);
256 static const struct {
260 } bwi_bbpid_map[] = {
261 { 0x4301, 0x4301, 0x4301 },
262 { 0x4305, 0x4307, 0x4307 },
263 { 0x4403, 0x4403, 0x4402 },
264 { 0x4610, 0x4615, 0x4610 },
265 { 0x4710, 0x4715, 0x4710 },
266 { 0x4720, 0x4725, 0x4309 }
269 static const struct {
272 } bwi_regwin_count[] = {
285 #define CLKSRC(src) \
286 [BWI_CLKSRC_ ## src] = { \
287 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
288 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
291 static const struct {
294 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
302 #define VENDOR_LED_ACT(vendor) \
304 .vid = PCI_VENDOR_##vendor, \
305 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
308 static const struct {
310 uint8_t led_act[BWI_LED_MAX];
311 } bwi_vendor_led_act[] = {
312 VENDOR_LED_ACT(COMPAQ),
313 VENDOR_LED_ACT(LINKSYS)
316 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
317 { BWI_VENDOR_LED_ACT_DEFAULT };
319 #undef VENDOR_LED_ACT
321 static const struct {
324 } bwi_led_duration[109] = {
341 #ifdef BWI_DEBUG_VERBOSE
342 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
344 static uint32_t bwi_debug;
346 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
347 #endif /* BWI_DEBUG */
349 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
351 static const struct ieee80211_rateset bwi_rateset_11b =
352 { 4, { 2, 4, 11, 22 } };
353 static const struct ieee80211_rateset bwi_rateset_11g =
354 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
357 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
359 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
363 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
364 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
367 struct bwi_desc32 *desc = &desc_array[desc_idx];
368 uint32_t ctrl, addr, addr_hi, addr_lo;
370 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
371 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
373 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
374 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
376 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
377 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
378 if (desc_idx == ndesc - 1)
379 ctrl |= BWI_DESC32_C_EOR;
382 ctrl |= BWI_DESC32_C_FRAME_START |
383 BWI_DESC32_C_FRAME_END |
387 desc->addr = htole32(addr);
388 desc->ctrl = htole32(ctrl);
391 /* XXX does not belong here */
393 bwi_rate2plcp(uint8_t rate)
395 rate &= IEEE80211_RATE_VAL;
400 case 11: return 0x37;
401 case 22: return 0x6e;
402 case 44: return 0xdc;
411 case 108: return 0xc;
414 panic("unsupported rate %u", rate);
418 /* XXX does not belong here */
419 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
420 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
423 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
427 plcp = __SHIFTIN(bwi_rate2plcp(rate), IEEE80211_OFDM_PLCP_RATE_MASK) |
428 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
429 *plcp0 = htole32(plcp);
432 /* XXX does not belong here */
433 struct ieee80211_ds_plcp_hdr {
440 #define IEEE80211_DS_PLCP_SERVICE_LOCKED 0x04
441 #define IEEE80211_DS_PLCL_SERVICE_PBCC 0x08
442 #define IEEE80211_DS_PLCP_SERVICE_LENEXT5 0x20
443 #define IEEE80211_DS_PLCP_SERVICE_LENEXT6 0x40
444 #define IEEE80211_DS_PLCP_SERVICE_LENEXT7 0x80
447 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
450 int len, service, pkt_bitlen;
452 pkt_bitlen = pkt_len * NBBY;
453 len = howmany(pkt_bitlen * 2, rate);
455 service = IEEE80211_DS_PLCP_SERVICE_LOCKED;
456 if (rate == (11 * 2)) {
460 * PLCP service field needs to be adjusted,
461 * if TX rate is 11Mbytes/s
463 pkt_bitlen1 = len * 11;
464 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
465 service |= IEEE80211_DS_PLCP_SERVICE_LENEXT7;
468 plcp->i_signal = bwi_rate2plcp(rate);
469 plcp->i_service = service;
470 plcp->i_length = htole16(len);
471 /* NOTE: do NOT touch i_crc */
475 bwi_plcp_header(void *plcp, int pkt_len, uint8_t rate)
477 enum ieee80211_modtype modtype;
480 * Assume caller has zeroed 'plcp'
483 modtype = ieee80211_rate2modtype(rate);
484 if (modtype == IEEE80211_MODTYPE_OFDM)
485 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
486 else if (modtype == IEEE80211_MODTYPE_DS)
487 bwi_ds_plcp_header(plcp, pkt_len, rate);
489 panic("unsupport modulation type %u", modtype);
492 static __inline uint8_t
493 bwi_ofdm_plcp2rate(const uint32_t *plcp0)
498 plcp = le32toh(*plcp0);
499 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);
500 return ieee80211_plcp2rate(plcp_rate, 1);
503 static __inline uint8_t
504 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr)
506 return ieee80211_plcp2rate(hdr->i_signal, 0);
510 bwi_probe(device_t dev)
512 const struct bwi_dev *b;
515 did = pci_get_device(dev);
516 vid = pci_get_vendor(dev);
518 for (b = bwi_devices; b->desc != NULL; ++b) {
519 if (b->did == did && b->vid == vid) {
520 device_set_desc(dev, b->desc);
528 bwi_attach(device_t dev)
530 struct bwi_softc *sc = device_get_softc(dev);
531 struct ieee80211com *ic = &sc->sc_ic;
532 struct ifnet *ifp = &ic->ic_if;
535 char ethstr[ETHER_ADDRSTRLEN + 1];
538 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
542 * Initialize sysctl variables
544 sc->sc_fw_version = BWI_FW_VERSION3;
545 sc->sc_dwell_time = 200;
546 sc->sc_led_idle = (2350 * hz) / 1000;
547 sc->sc_led_blink = 1;
548 sc->sc_txpwr_calib = 1;
550 sc->sc_debug = bwi_debug;
553 callout_init(&sc->sc_scan_ch);
554 callout_init(&sc->sc_calib_ch);
557 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
560 /* XXX Save more PCIR */
561 irq = pci_read_config(dev, PCIR_INTLINE, 4);
562 mem = pci_read_config(dev, BWI_PCIR_BAR, 4);
564 device_printf(dev, "chip is in D%d power mode "
565 "-- setting to D0\n", pci_get_powerstate(dev));
567 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
569 pci_write_config(dev, PCIR_INTLINE, irq, 4);
570 pci_write_config(dev, BWI_PCIR_BAR, mem, 4);
572 #endif /* !BURN_BRIDGE */
574 pci_enable_busmaster(dev);
576 /* Get more PCI information */
577 sc->sc_pci_revid = pci_get_revid(dev);
578 sc->sc_pci_subvid = pci_get_subvendor(dev);
579 sc->sc_pci_subdid = pci_get_subdevice(dev);
584 sc->sc_mem_rid = BWI_PCIR_BAR;
585 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
586 &sc->sc_mem_rid, RF_ACTIVE);
587 if (sc->sc_mem_res == NULL) {
588 device_printf(dev, "can't allocate IO memory\n");
591 sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res);
592 sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res);
598 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
600 RF_SHAREABLE | RF_ACTIVE);
601 if (sc->sc_irq_res == NULL) {
602 device_printf(dev, "can't allocate irq\n");
610 sysctl_ctx_init(&sc->sc_sysctl_ctx);
611 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
612 SYSCTL_STATIC_CHILDREN(_hw),
614 device_get_nameunit(dev),
616 if (sc->sc_sysctl_tree == NULL) {
617 device_printf(dev, "can't add sysctl node\n");
622 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
623 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
624 "dwell_time", CTLFLAG_RW, &sc->sc_dwell_time, 0,
625 "Channel dwell time during scan (msec)");
626 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
627 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
628 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
630 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
631 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
632 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
633 "# ticks before LED enters idle state");
634 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
635 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
636 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
637 "Allow LED to blink");
638 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
639 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
640 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
641 "Enable software TX power calibration");
643 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
644 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
645 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
650 error = bwi_bbp_attach(sc);
654 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
658 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
659 error = bwi_set_clock_delay(sc);
663 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
667 error = bwi_get_pwron_delay(sc);
672 error = bwi_bus_attach(sc);
676 bwi_get_card_flags(sc);
680 for (i = 0; i < sc->sc_nmac; ++i) {
681 struct bwi_regwin *old;
683 mac = &sc->sc_mac[i];
684 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
688 error = bwi_mac_lateattach(mac);
692 error = bwi_regwin_switch(sc, old, NULL);
698 * XXX First MAC is known to exist
701 mac = &sc->sc_mac[0];
704 bwi_bbp_power_off(sc);
706 error = bwi_dma_alloc(sc);
711 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
712 ifp->if_init = bwi_init;
713 ifp->if_ioctl = bwi_ioctl;
714 ifp->if_start = bwi_start;
715 ifp->if_watchdog = bwi_watchdog;
716 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
718 ifq_set_ready(&ifp->if_snd);
722 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
723 BWI_SPROM_CARD_INFO_LOCALE);
724 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
727 * Setup ratesets, phytype, channels and get MAC address
729 if (phy->phy_mode == IEEE80211_MODE_11B ||
730 phy->phy_mode == IEEE80211_MODE_11G) {
733 ic->ic_sup_rates[IEEE80211_MODE_11B] = bwi_rateset_11b;
735 if (phy->phy_mode == IEEE80211_MODE_11B) {
736 chan_flags = IEEE80211_CHAN_B;
737 ic->ic_phytype = IEEE80211_T_DS;
739 chan_flags = IEEE80211_CHAN_CCK |
740 IEEE80211_CHAN_OFDM |
743 ic->ic_phytype = IEEE80211_T_OFDM;
744 ic->ic_sup_rates[IEEE80211_MODE_11G] =
748 /* XXX depend on locale */
749 for (i = 1; i <= 14; ++i) {
750 ic->ic_channels[i].ic_freq =
751 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
752 ic->ic_channels[i].ic_flags = chan_flags;
755 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_myaddr);
756 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
757 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_myaddr);
758 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
759 device_printf(dev, "invalid MAC address: "
760 "%s\n", kether_ntoa(ic->ic_myaddr, ethstr));
763 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
768 panic("unknown phymode %d", phy->phy_mode);
771 ic->ic_caps = IEEE80211_C_SHSLOT |
772 IEEE80211_C_SHPREAMBLE |
775 ic->ic_state = IEEE80211_S_INIT;
776 ic->ic_opmode = IEEE80211_M_STA;
778 IEEE80211_ONOE_PARAM_SETUP(&sc->sc_onoe_param);
779 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE;
780 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE;
781 ic->ic_ratectl.rc_st_attach = bwi_ratectl_attach;
783 ic->ic_updateslot = bwi_updateslot;
785 ieee80211_ifattach(ic);
787 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
788 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;
790 sc->sc_newstate = ic->ic_newstate;
791 ic->ic_newstate = bwi_newstate;
793 ieee80211_media_init(ic, bwi_media_change, ieee80211_media_status);
798 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
799 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
802 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(uint32_t));
803 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
804 sc->sc_tx_th.wt_ihdr.it_present = htole32(BWI_TX_RADIOTAP_PRESENT);
806 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(uint32_t));
807 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
808 sc->sc_rx_th.wr_ihdr.it_present = htole32(BWI_RX_RADIOTAP_PRESENT);
810 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq_res));
812 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, bwi_intr, sc,
813 &sc->sc_irq_handle, ifp->if_serializer);
815 device_printf(dev, "can't setup intr\n");
817 ieee80211_ifdetach(ic);
822 ieee80211_announce(ic);
831 bwi_detach(device_t dev)
833 struct bwi_softc *sc = device_get_softc(dev);
835 if (device_is_attached(dev)) {
836 struct ifnet *ifp = &sc->sc_ic.ic_if;
839 lwkt_serialize_enter(ifp->if_serializer);
841 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
842 lwkt_serialize_exit(ifp->if_serializer);
845 ieee80211_ifdetach(&sc->sc_ic);
847 for (i = 0; i < sc->sc_nmac; ++i)
848 bwi_mac_detach(&sc->sc_mac[i]);
851 if (sc->sc_sysctl_tree != NULL)
852 sysctl_ctx_free(&sc->sc_sysctl_ctx);
854 if (sc->sc_irq_res != NULL) {
855 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
859 if (sc->sc_mem_res != NULL) {
860 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
870 bwi_shutdown(device_t dev)
872 struct bwi_softc *sc = device_get_softc(dev);
873 struct ifnet *ifp = &sc->sc_ic.ic_if;
875 lwkt_serialize_enter(ifp->if_serializer);
877 lwkt_serialize_exit(ifp->if_serializer);
882 bwi_power_on(struct bwi_softc *sc, int with_pll)
884 uint32_t gpio_in, gpio_out, gpio_en;
887 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
888 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
891 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
892 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
894 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
895 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
897 /* Turn off PLL first */
898 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
899 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
902 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
903 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
908 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
909 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
914 /* Clear "Signaled Target Abort" */
915 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
916 status &= ~PCIM_STATUS_STABORT;
917 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
921 bwi_power_off(struct bwi_softc *sc, int with_pll)
923 uint32_t gpio_out, gpio_en;
925 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
926 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
927 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
929 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
930 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
932 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
933 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
936 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
937 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
942 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
943 struct bwi_regwin **old_rw)
950 if (!BWI_REGWIN_EXIST(rw))
953 if (sc->sc_cur_regwin != rw) {
954 error = bwi_regwin_select(sc, rw->rw_id);
956 if_printf(&sc->sc_ic.ic_if, "can't select regwin %d\n",
963 *old_rw = sc->sc_cur_regwin;
964 sc->sc_cur_regwin = rw;
969 bwi_regwin_select(struct bwi_softc *sc, int id)
971 uint32_t win = BWI_PCIM_REGWIN(id);
975 for (i = 0; i < RETRY_MAX; ++i) {
976 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
977 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
987 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
991 val = CSR_READ_4(sc, BWI_ID_HI);
992 *type = BWI_ID_HI_REGWIN_TYPE(val);
993 *rev = BWI_ID_HI_REGWIN_REV(val);
995 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
996 "vendor 0x%04x\n", *type, *rev,
997 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
1001 bwi_bbp_attach(struct bwi_softc *sc)
1003 uint16_t bbp_id, rw_type;
1006 int error, nregwin, i;
1009 * Get 0th regwin information
1010 * NOTE: 0th regwin should exist
1012 error = bwi_regwin_select(sc, 0);
1014 device_printf(sc->sc_dev, "can't select regwin 0\n");
1017 bwi_regwin_info(sc, &rw_type, &rw_rev);
1024 if (rw_type == BWI_REGWIN_T_COM) {
1025 info = CSR_READ_4(sc, BWI_INFO);
1026 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
1028 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
1030 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
1032 uint16_t did = pci_get_device(sc->sc_dev);
1033 uint8_t revid = pci_get_revid(sc->sc_dev);
1035 for (i = 0; i < NELEM(bwi_bbpid_map); ++i) {
1036 if (did >= bwi_bbpid_map[i].did_min &&
1037 did <= bwi_bbpid_map[i].did_max) {
1038 bbp_id = bwi_bbpid_map[i].bbp_id;
1043 device_printf(sc->sc_dev, "no BBP id for device id "
1048 info = __SHIFTIN(revid, BWI_INFO_BBPREV_MASK) |
1049 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
1053 * Find out number of regwins
1056 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
1057 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
1059 for (i = 0; i < NELEM(bwi_regwin_count); ++i) {
1060 if (bwi_regwin_count[i].bbp_id == bbp_id) {
1061 nregwin = bwi_regwin_count[i].nregwin;
1066 device_printf(sc->sc_dev, "no number of win for "
1067 "BBP id 0x%04x\n", bbp_id);
1072 /* Record BBP id/rev for later using */
1073 sc->sc_bbp_id = bbp_id;
1074 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
1075 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
1076 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
1077 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
1079 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
1080 nregwin, sc->sc_cap);
1083 * Create rest of the regwins
1086 /* Don't re-create common regwin, if it is already created */
1087 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
1089 for (; i < nregwin; ++i) {
1091 * Get regwin information
1093 error = bwi_regwin_select(sc, i);
1095 device_printf(sc->sc_dev,
1096 "can't select regwin %d\n", i);
1099 bwi_regwin_info(sc, &rw_type, &rw_rev);
1103 * 1) Bus (PCI/PCIE) regwin
1105 * Ignore rest types of regwin
1107 if (rw_type == BWI_REGWIN_T_BUSPCI ||
1108 rw_type == BWI_REGWIN_T_BUSPCIE) {
1109 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1110 device_printf(sc->sc_dev,
1111 "bus regwin already exists\n");
1113 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
1116 } else if (rw_type == BWI_REGWIN_T_MAC) {
1117 /* XXX ignore return value */
1118 bwi_mac_attach(sc, i, rw_rev);
1122 /* At least one MAC shold exist */
1123 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
1124 device_printf(sc->sc_dev, "no MAC was found\n");
1127 KKASSERT(sc->sc_nmac > 0);
1129 /* Bus regwin must exist */
1130 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1131 device_printf(sc->sc_dev, "no bus regwin was found\n");
1135 /* Start with first MAC */
1136 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
1144 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
1146 struct bwi_regwin *old, *bus;
1150 bus = &sc->sc_bus_regwin;
1151 KKASSERT(sc->sc_cur_regwin == &mac->mac_regwin);
1154 * Tell bus to generate requested interrupts
1156 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1158 * NOTE: Read BWI_FLAGS from MAC regwin
1160 val = CSR_READ_4(sc, BWI_FLAGS);
1162 error = bwi_regwin_switch(sc, bus, &old);
1166 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
1170 mac_mask = 1 << mac->mac_id;
1172 error = bwi_regwin_switch(sc, bus, &old);
1176 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
1177 val |= mac_mask << 8;
1178 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
1181 if (sc->sc_flags & BWI_F_BUS_INITED)
1184 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1186 * Enable prefetch and burst
1188 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
1189 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
1191 if (bus->rw_rev < 5) {
1192 struct bwi_regwin *com = &sc->sc_com_regwin;
1195 * Configure timeouts for bus operation
1199 * Set service timeout and request timeout
1201 CSR_SETBITS_4(sc, BWI_CONF_LO,
1202 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
1203 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
1206 * If there is common regwin, we switch to that regwin
1207 * and switch back to bus regwin once we have done.
1209 if (BWI_REGWIN_EXIST(com)) {
1210 error = bwi_regwin_switch(sc, com, NULL);
1215 /* Let bus know what we have changed */
1216 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
1217 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
1218 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
1219 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1221 if (BWI_REGWIN_EXIST(com)) {
1222 error = bwi_regwin_switch(sc, bus, NULL);
1226 } else if (bus->rw_rev >= 11) {
1228 * Enable memory read multiple
1230 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
1236 sc->sc_flags |= BWI_F_BUS_INITED;
1238 return bwi_regwin_switch(sc, old, NULL);
1242 bwi_get_card_flags(struct bwi_softc *sc)
1244 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1245 if (sc->sc_card_flags == 0xffff)
1246 sc->sc_card_flags = 0;
1248 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1249 sc->sc_pci_subdid == 0x4e && /* XXX */
1250 sc->sc_pci_revid > 0x40)
1251 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1253 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1257 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1261 for (i = 0; i < 3; ++i) {
1262 *((uint16_t *)eaddr + i) =
1263 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1268 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1270 struct bwi_regwin *com;
1275 bzero(freq, sizeof(*freq));
1276 com = &sc->sc_com_regwin;
1278 KKASSERT(BWI_REGWIN_EXIST(com));
1279 KKASSERT(sc->sc_cur_regwin == com);
1280 KKASSERT(sc->sc_cap & BWI_CAP_CLKMODE);
1283 * Calculate clock frequency
1287 if (com->rw_rev < 6) {
1288 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1289 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1290 src = BWI_CLKSRC_PCI;
1293 src = BWI_CLKSRC_CS_OSC;
1296 } else if (com->rw_rev < 10) {
1297 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1299 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1300 if (src == BWI_CLKSRC_LP_OSC) {
1303 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1305 /* Unknown source */
1306 if (src >= BWI_CLKSRC_MAX)
1307 src = BWI_CLKSRC_CS_OSC;
1310 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1312 src = BWI_CLKSRC_CS_OSC;
1313 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1316 KKASSERT(src >= 0 && src < BWI_CLKSRC_MAX);
1319 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1320 src == BWI_CLKSRC_PCI ? "PCI" :
1321 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1323 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1324 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1326 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1327 freq->clkfreq_min, freq->clkfreq_max);
1331 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1333 struct bwi_regwin *old, *com;
1334 uint32_t clk_ctrl, clk_src;
1335 int error, pwr_off = 0;
1337 com = &sc->sc_com_regwin;
1338 if (!BWI_REGWIN_EXIST(com))
1341 if (com->rw_rev >= 10 || com->rw_rev < 6)
1345 * For common regwin whose rev is [6, 10), the chip
1346 * must be capable to change clock mode.
1348 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1351 error = bwi_regwin_switch(sc, com, &old);
1355 if (clk_mode == BWI_CLOCK_MODE_FAST)
1356 bwi_power_on(sc, 0); /* Don't turn on PLL */
1358 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1359 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1362 case BWI_CLOCK_MODE_FAST:
1363 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1364 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1366 case BWI_CLOCK_MODE_SLOW:
1367 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1369 case BWI_CLOCK_MODE_DYN:
1370 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1371 BWI_CLOCK_CTRL_IGNPLL |
1372 BWI_CLOCK_CTRL_NODYN);
1373 if (clk_src != BWI_CLKSRC_CS_OSC) {
1374 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1379 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1382 bwi_power_off(sc, 0); /* Leave PLL as it is */
1384 return bwi_regwin_switch(sc, old, NULL);
1388 bwi_set_clock_delay(struct bwi_softc *sc)
1390 struct bwi_regwin *old, *com;
1393 com = &sc->sc_com_regwin;
1394 if (!BWI_REGWIN_EXIST(com))
1397 error = bwi_regwin_switch(sc, com, &old);
1401 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1402 if (sc->sc_bbp_rev == 0)
1403 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1404 else if (sc->sc_bbp_rev == 1)
1405 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1408 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1409 if (com->rw_rev >= 10) {
1410 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1412 struct bwi_clock_freq freq;
1414 bwi_get_clock_freq(sc, &freq);
1415 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1416 howmany(freq.clkfreq_max * 150, 1000000));
1417 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1418 howmany(freq.clkfreq_max * 15, 1000000));
1422 return bwi_regwin_switch(sc, old, NULL);
1428 bwi_init_statechg(xsc, 1);
1432 bwi_init_statechg(struct bwi_softc *sc, int statechg)
1434 struct ieee80211com *ic = &sc->sc_ic;
1435 struct ifnet *ifp = &ic->ic_if;
1436 struct bwi_mac *mac;
1439 ASSERT_SERIALIZED(ifp->if_serializer);
1441 error = bwi_stop(sc, statechg);
1443 if_printf(ifp, "can't stop\n");
1447 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1451 mac = &sc->sc_mac[0];
1452 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1456 error = bwi_mac_init(mac);
1460 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1462 bcopy(IF_LLADDR(ifp), ic->ic_myaddr, sizeof(ic->ic_myaddr));
1464 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1465 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, ic->ic_myaddr);
1467 bwi_mac_reset_hwkeys(mac);
1469 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1474 * Drain any possible pending TX status
1476 for (i = 0; i < NRETRY; ++i) {
1477 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1478 BWI_TXSTATUS0_VALID) == 0)
1480 CSR_READ_4(sc, BWI_TXSTATUS1);
1483 if_printf(ifp, "can't drain TX status\n");
1487 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1488 bwi_mac_updateslot(mac, 1);
1491 error = bwi_mac_start(mac);
1496 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1498 ifp->if_flags |= IFF_RUNNING;
1499 ifq_clr_oactive(&ifp->if_snd);
1502 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1503 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
1504 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1506 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1509 ieee80211_new_state(ic, ic->ic_state, -1);
1519 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t req, struct ucred *cr)
1521 struct bwi_softc *sc = ifp->if_softc;
1524 ASSERT_SERIALIZED(ifp->if_serializer);
1528 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1529 (IFF_UP | IFF_RUNNING)) {
1530 struct bwi_mac *mac;
1533 KKASSERT(sc->sc_cur_regwin->rw_type ==
1535 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1537 if ((ifp->if_flags & IFF_PROMISC) &&
1538 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1540 sc->sc_flags |= BWI_F_PROMISC;
1541 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1542 (sc->sc_flags & BWI_F_PROMISC)) {
1544 sc->sc_flags &= ~BWI_F_PROMISC;
1548 bwi_mac_set_promisc(mac, promisc);
1551 if (ifp->if_flags & IFF_UP) {
1552 if ((ifp->if_flags & IFF_RUNNING) == 0)
1555 if (ifp->if_flags & IFF_RUNNING)
1560 error = ieee80211_ioctl(&sc->sc_ic, cmd, req, cr);
1564 if (error == ENETRESET) {
1565 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1566 (IFF_UP | IFF_RUNNING))
1574 bwi_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1576 struct bwi_softc *sc = ifp->if_softc;
1577 struct ieee80211com *ic = &sc->sc_ic;
1578 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1581 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1582 ASSERT_SERIALIZED(ifp->if_serializer);
1584 if (ifq_is_oactive(&ifp->if_snd) || (ifp->if_flags & IFF_RUNNING) == 0)
1590 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1591 struct ieee80211_frame *wh;
1592 struct ieee80211_node *ni;
1596 if (!IF_QEMPTY(&ic->ic_mgtq)) {
1597 IF_DEQUEUE(&ic->ic_mgtq, m);
1599 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1600 m->m_pkthdr.rcvif = NULL;
1603 } else if (!ifq_is_empty(&ifp->if_snd)) {
1604 struct ether_header *eh;
1606 if (ic->ic_state != IEEE80211_S_RUN) {
1607 ifq_purge(&ifp->if_snd);
1611 m = ifq_dequeue(&ifp->if_snd);
1615 if (m->m_len < sizeof(*eh)) {
1616 m = m_pullup(m, sizeof(*eh));
1618 IFNET_STAT_INC(ifp, oerrors, 1);
1622 eh = mtod(m, struct ether_header *);
1624 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1627 IFNET_STAT_INC(ifp, oerrors, 1);
1635 m = ieee80211_encap(ic, m, ni);
1637 ieee80211_free_node(ni);
1638 IFNET_STAT_INC(ifp, oerrors, 1);
1645 if (ic->ic_rawbpf != NULL)
1646 bpf_mtap(ic->ic_rawbpf, m);
1648 wh = mtod(m, struct ieee80211_frame *);
1649 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1650 if (ieee80211_crypto_encap(ic, ni, m) == NULL) {
1651 ieee80211_free_node(ni);
1653 IFNET_STAT_INC(ifp, oerrors, 1);
1657 wh = NULL; /* Catch any invalid use */
1659 if (bwi_encap(sc, idx, m, &ni, mgt_pkt) != 0) {
1660 /* 'm' is freed in bwi_encap() if we reach here */
1662 ieee80211_free_node(ni);
1663 IFNET_STAT_INC(ifp, oerrors, 1);
1669 idx = (idx + 1) % BWI_TX_NDESC;
1671 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
1672 ifq_set_oactive(&ifp->if_snd);
1679 sc->sc_tx_timer = 5;
1684 bwi_watchdog(struct ifnet *ifp)
1686 struct bwi_softc *sc = ifp->if_softc;
1688 ASSERT_SERIALIZED(ifp->if_serializer);
1692 if ((ifp->if_flags & IFF_RUNNING) == 0)
1695 if (sc->sc_tx_timer) {
1696 if (--sc->sc_tx_timer == 0) {
1697 if_printf(ifp, "watchdog timeout\n");
1698 IFNET_STAT_INC(ifp, oerrors, 1);
1704 ieee80211_watchdog(&sc->sc_ic);
1708 bwi_stop(struct bwi_softc *sc, int state_chg)
1710 struct ieee80211com *ic = &sc->sc_ic;
1711 struct ifnet *ifp = &ic->ic_if;
1712 struct bwi_mac *mac;
1713 int i, error, pwr_off = 0;
1715 ASSERT_SERIALIZED(ifp->if_serializer);
1718 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1720 bwi_newstate_begin(sc, IEEE80211_S_INIT);
1722 if (ifp->if_flags & IFF_RUNNING) {
1723 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1724 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1726 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1727 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1731 for (i = 0; i < sc->sc_nmac; ++i) {
1732 struct bwi_regwin *old_rw;
1734 mac = &sc->sc_mac[i];
1735 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1738 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1742 bwi_mac_shutdown(mac);
1745 bwi_regwin_switch(sc, old_rw, NULL);
1749 bwi_bbp_power_off(sc);
1751 sc->sc_tx_timer = 0;
1753 ifp->if_flags &= ~IFF_RUNNING;
1754 ifq_clr_oactive(&ifp->if_snd);
1761 struct bwi_softc *sc = xsc;
1762 struct bwi_mac *mac;
1763 struct ifnet *ifp = &sc->sc_ic.ic_if;
1764 uint32_t intr_status;
1765 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1766 int i, txrx_error, tx = 0, rx_data = -1;
1768 ASSERT_SERIALIZED(ifp->if_serializer);
1770 if ((ifp->if_flags & IFF_RUNNING) == 0)
1774 * Get interrupt status
1776 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1777 if (intr_status == 0xffffffff) /* Not for us */
1780 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1782 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1783 if (intr_status == 0) /* Nothing is interesting */
1786 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1787 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1790 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1791 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1794 if (BWI_TXRX_IS_RX(i))
1795 mask = BWI_TXRX_RX_INTRS;
1797 mask = BWI_TXRX_TX_INTRS;
1799 txrx_intr_status[i] =
1800 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1802 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1803 i, txrx_intr_status[i]);
1805 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1806 if_printf(ifp, "intr fatal TX/RX (%d) error 0x%08x\n",
1807 i, txrx_intr_status[i]);
1811 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1814 * Acknowledge interrupt
1816 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1818 for (i = 0; i < BWI_TXRX_NRING; ++i)
1819 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1821 /* Disable all interrupts */
1822 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1824 if (intr_status & BWI_INTR_PHY_TXERR) {
1825 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1826 if_printf(ifp, "intr PHY TX error\n");
1827 /* XXX to netisr0? */
1828 bwi_init_statechg(sc, 0);
1834 /* TODO: reset device */
1837 if (intr_status & BWI_INTR_TBTT)
1838 bwi_mac_config_ps(mac);
1840 if (intr_status & BWI_INTR_EO_ATIM)
1841 if_printf(ifp, "EO_ATIM\n");
1843 if (intr_status & BWI_INTR_PMQ) {
1845 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1848 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1851 if (intr_status & BWI_INTR_NOISE)
1852 if_printf(ifp, "intr noise\n");
1854 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX)
1855 rx_data = sc->sc_rxeof(sc);
1857 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1858 sc->sc_txeof_status(sc);
1862 if (intr_status & BWI_INTR_TX_DONE) {
1867 /* Re-enable interrupts */
1868 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1870 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1871 int evt = BWI_LED_EVENT_NONE;
1873 if (tx && rx_data > 0) {
1874 if (sc->sc_rx_rate > sc->sc_tx_rate)
1875 evt = BWI_LED_EVENT_RX;
1877 evt = BWI_LED_EVENT_TX;
1879 evt = BWI_LED_EVENT_TX;
1880 } else if (rx_data > 0) {
1881 evt = BWI_LED_EVENT_RX;
1882 } else if (rx_data == 0) {
1883 evt = BWI_LED_EVENT_POLL;
1886 if (evt != BWI_LED_EVENT_NONE)
1887 bwi_led_event(sc, evt);
1892 bwi_newstate_begin(struct bwi_softc *sc, enum ieee80211_state nstate)
1894 callout_stop(&sc->sc_scan_ch);
1895 callout_stop(&sc->sc_calib_ch);
1897 ieee80211_ratectl_newstate(&sc->sc_ic, nstate);
1898 bwi_led_newstate(sc, nstate);
1900 if (nstate == IEEE80211_S_INIT)
1901 sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1905 bwi_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1907 struct bwi_softc *sc = ic->ic_if.if_softc;
1908 struct ifnet *ifp = &ic->ic_if;
1911 ASSERT_SERIALIZED(ifp->if_serializer);
1913 bwi_newstate_begin(sc, nstate);
1915 if (nstate == IEEE80211_S_INIT)
1918 error = bwi_set_chan(sc, ic->ic_curchan);
1920 if_printf(ifp, "can't set channel to %u\n",
1921 ieee80211_chan2ieee(ic, ic->ic_curchan));
1925 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1927 } else if (nstate == IEEE80211_S_RUN) {
1928 struct bwi_mac *mac;
1930 bwi_set_bssid(sc, ic->ic_bss->ni_bssid);
1932 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1933 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1935 /* Initial TX power calibration */
1936 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1938 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1940 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1943 bwi_set_bssid(sc, bwi_zero_addr);
1947 error = sc->sc_newstate(ic, nstate, arg);
1949 if (nstate == IEEE80211_S_SCAN) {
1950 callout_reset(&sc->sc_scan_ch,
1951 (sc->sc_dwell_time * hz) / 1000,
1953 } else if (nstate == IEEE80211_S_RUN) {
1954 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
1960 bwi_media_change(struct ifnet *ifp)
1964 ASSERT_SERIALIZED(ifp->if_serializer);
1966 error = ieee80211_media_change(ifp);
1967 if (error != ENETRESET)
1970 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
1971 bwi_init(ifp->if_softc);
1976 bwi_dma_alloc(struct bwi_softc *sc)
1978 int error, i, has_txstats;
1979 bus_addr_t lowaddr = 0;
1980 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1981 uint32_t txrx_ctrl_step = 0;
1984 for (i = 0; i < sc->sc_nmac; ++i) {
1985 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1991 switch (sc->sc_bus_space) {
1992 case BWI_BUS_SPACE_30BIT:
1993 case BWI_BUS_SPACE_32BIT:
1994 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1995 lowaddr = BWI_BUS_SPACE_MAXADDR;
1997 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1998 desc_sz = sizeof(struct bwi_desc32);
1999 txrx_ctrl_step = 0x20;
2001 sc->sc_init_tx_ring = bwi_init_tx_ring32;
2002 sc->sc_free_tx_ring = bwi_free_tx_ring32;
2003 sc->sc_init_rx_ring = bwi_init_rx_ring32;
2004 sc->sc_free_rx_ring = bwi_free_rx_ring32;
2005 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
2006 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
2007 sc->sc_rxeof = bwi_rxeof32;
2008 sc->sc_start_tx = bwi_start_tx32;
2010 sc->sc_init_txstats = bwi_init_txstats32;
2011 sc->sc_free_txstats = bwi_free_txstats32;
2012 sc->sc_txeof_status = bwi_txeof_status32;
2016 case BWI_BUS_SPACE_64BIT:
2017 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
2018 desc_sz = sizeof(struct bwi_desc64);
2019 txrx_ctrl_step = 0x40;
2021 sc->sc_init_tx_ring = bwi_init_tx_ring64;
2022 sc->sc_free_tx_ring = bwi_free_tx_ring64;
2023 sc->sc_init_rx_ring = bwi_init_rx_ring64;
2024 sc->sc_free_rx_ring = bwi_free_rx_ring64;
2025 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
2026 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
2027 sc->sc_rxeof = bwi_rxeof64;
2028 sc->sc_start_tx = bwi_start_tx64;
2030 sc->sc_init_txstats = bwi_init_txstats64;
2031 sc->sc_free_txstats = bwi_free_txstats64;
2032 sc->sc_txeof_status = bwi_txeof_status64;
2037 KKASSERT(lowaddr != 0);
2038 KKASSERT(desc_sz != 0);
2039 KKASSERT(txrx_ctrl_step != 0);
2041 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
2042 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
2045 * Create top level DMA tag
2047 error = bus_dma_tag_create(NULL, BWI_ALIGN, 0,
2048 lowaddr, BUS_SPACE_MAXADDR,
2051 BUS_SPACE_UNRESTRICTED,
2052 BUS_SPACE_MAXSIZE_32BIT,
2053 0, &sc->sc_parent_dtag);
2055 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
2059 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
2062 * Create TX ring DMA stuffs
2064 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2065 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2067 tx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2068 0, &sc->sc_txring_dtag);
2070 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
2074 for (i = 0; i < BWI_TX_NRING; ++i) {
2075 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
2076 &sc->sc_tx_rdata[i], tx_ring_sz,
2079 device_printf(sc->sc_dev, "%dth TX ring "
2080 "DMA alloc failed\n", i);
2086 * Create RX ring DMA stuffs
2088 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2089 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2091 rx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2092 0, &sc->sc_rxring_dtag);
2094 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
2098 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
2099 rx_ring_sz, TXRX_CTRL(0));
2101 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
2106 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
2108 device_printf(sc->sc_dev,
2109 "TX stats DMA alloc failed\n");
2116 return bwi_dma_mbuf_create(sc);
2120 bwi_dma_free(struct bwi_softc *sc)
2122 if (sc->sc_txring_dtag != NULL) {
2125 for (i = 0; i < BWI_TX_NRING; ++i) {
2126 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
2128 if (rd->rdata_desc != NULL) {
2129 bus_dmamap_unload(sc->sc_txring_dtag,
2131 bus_dmamem_free(sc->sc_txring_dtag,
2136 bus_dma_tag_destroy(sc->sc_txring_dtag);
2139 if (sc->sc_rxring_dtag != NULL) {
2140 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2142 if (rd->rdata_desc != NULL) {
2143 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2144 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2147 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2150 bwi_dma_txstats_free(sc);
2151 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2153 if (sc->sc_parent_dtag != NULL)
2154 bus_dma_tag_destroy(sc->sc_parent_dtag);
2158 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2159 struct bwi_ring_data *rd, bus_size_t size,
2164 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2165 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2168 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2172 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2173 bwi_dma_ring_addr, &rd->rdata_paddr,
2176 device_printf(sc->sc_dev, "can't load DMA mem\n");
2177 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2178 rd->rdata_desc = NULL;
2182 rd->rdata_txrx_ctrl = txrx_ctrl;
2187 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2190 struct bwi_txstats_data *st;
2191 bus_size_t dma_size;
2194 st = kmalloc(sizeof(*st), M_DEVBUF, M_WAITOK | M_ZERO);
2195 sc->sc_txstats = st;
2198 * Create TX stats descriptor DMA stuffs
2200 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2202 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2203 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2205 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2206 0, &st->stats_ring_dtag);
2208 device_printf(sc->sc_dev, "can't create txstats ring "
2213 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2214 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2215 &st->stats_ring_dmap);
2217 device_printf(sc->sc_dev, "can't allocate txstats ring "
2219 bus_dma_tag_destroy(st->stats_ring_dtag);
2220 st->stats_ring_dtag = NULL;
2224 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2225 st->stats_ring, dma_size,
2226 bwi_dma_ring_addr, &st->stats_ring_paddr,
2229 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2230 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2231 st->stats_ring_dmap);
2232 bus_dma_tag_destroy(st->stats_ring_dtag);
2233 st->stats_ring_dtag = NULL;
2238 * Create TX stats DMA stuffs
2240 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2243 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_ALIGN, 0,
2244 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2246 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2247 0, &st->stats_dtag);
2249 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2253 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2254 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2257 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2258 bus_dma_tag_destroy(st->stats_dtag);
2259 st->stats_dtag = NULL;
2263 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2264 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2267 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2268 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2269 bus_dma_tag_destroy(st->stats_dtag);
2270 st->stats_dtag = NULL;
2274 st->stats_ctrl_base = ctrl_base;
2279 bwi_dma_txstats_free(struct bwi_softc *sc)
2281 struct bwi_txstats_data *st;
2283 if (sc->sc_txstats == NULL)
2285 st = sc->sc_txstats;
2287 if (st->stats_ring_dtag != NULL) {
2288 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2289 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2290 st->stats_ring_dmap);
2291 bus_dma_tag_destroy(st->stats_ring_dtag);
2294 if (st->stats_dtag != NULL) {
2295 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2296 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2297 bus_dma_tag_destroy(st->stats_dtag);
2300 kfree(st, M_DEVBUF);
2304 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2306 KASSERT(nseg == 1, ("too many segments"));
2307 *((bus_addr_t *)arg) = seg->ds_addr;
2311 bwi_dma_mbuf_create(struct bwi_softc *sc)
2313 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2314 int i, j, k, ntx, error;
2317 * Create TX/RX mbuf DMA tag
2319 error = bus_dma_tag_create(sc->sc_parent_dtag, 1, 0,
2320 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2321 NULL, NULL, MCLBYTES, 1,
2322 BUS_SPACE_MAXSIZE_32BIT,
2323 0, &sc->sc_buf_dtag);
2325 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2332 * Create TX mbuf DMA map
2334 for (i = 0; i < BWI_TX_NRING; ++i) {
2335 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2337 for (j = 0; j < BWI_TX_NDESC; ++j) {
2338 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2339 &tbd->tbd_buf[j].tb_dmap);
2341 device_printf(sc->sc_dev, "can't create "
2342 "%dth tbd, %dth DMA map\n", i, j);
2345 for (k = 0; k < j; ++k) {
2346 bus_dmamap_destroy(sc->sc_buf_dtag,
2347 tbd->tbd_buf[k].tb_dmap);
2356 * Create RX mbuf DMA map and a spare DMA map
2358 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2359 &rbd->rbd_tmp_dmap);
2361 device_printf(sc->sc_dev,
2362 "can't create spare RX buf DMA map\n");
2366 for (j = 0; j < BWI_RX_NDESC; ++j) {
2367 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2368 &rbd->rbd_buf[j].rb_dmap);
2370 device_printf(sc->sc_dev, "can't create %dth "
2371 "RX buf DMA map\n", j);
2373 for (k = 0; k < j; ++k) {
2374 bus_dmamap_destroy(sc->sc_buf_dtag,
2375 rbd->rbd_buf[j].rb_dmap);
2377 bus_dmamap_destroy(sc->sc_buf_dtag,
2385 bwi_dma_mbuf_destroy(sc, ntx, 0);
2390 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2394 if (sc->sc_buf_dtag == NULL)
2397 for (i = 0; i < ntx; ++i) {
2398 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2400 for (j = 0; j < BWI_TX_NDESC; ++j) {
2401 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2403 if (tb->tb_mbuf != NULL) {
2404 bus_dmamap_unload(sc->sc_buf_dtag,
2406 m_freem(tb->tb_mbuf);
2408 if (tb->tb_ni != NULL)
2409 ieee80211_free_node(tb->tb_ni);
2410 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2415 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2417 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2418 for (j = 0; j < BWI_RX_NDESC; ++j) {
2419 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2421 if (rb->rb_mbuf != NULL) {
2422 bus_dmamap_unload(sc->sc_buf_dtag,
2424 m_freem(rb->rb_mbuf);
2426 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2430 bus_dma_tag_destroy(sc->sc_buf_dtag);
2431 sc->sc_buf_dtag = NULL;
2435 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2437 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2441 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2443 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2447 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2449 struct bwi_ring_data *rd;
2450 struct bwi_txbuf_data *tbd;
2451 uint32_t val, addr_hi, addr_lo;
2453 KKASSERT(ring_idx < BWI_TX_NRING);
2454 rd = &sc->sc_tx_rdata[ring_idx];
2455 tbd = &sc->sc_tx_bdata[ring_idx];
2460 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2461 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2462 BUS_DMASYNC_PREWRITE);
2464 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2465 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2467 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2468 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2469 BWI_TXRX32_RINGINFO_FUNC_MASK);
2470 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2472 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2473 BWI_TXRX32_CTRL_ENABLE;
2474 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2480 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2481 bus_addr_t paddr, int hdr_size, int ndesc)
2483 uint32_t val, addr_hi, addr_lo;
2485 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2486 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2488 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2489 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2490 BWI_TXRX32_RINGINFO_FUNC_MASK);
2491 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2493 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2494 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2495 BWI_TXRX32_CTRL_ENABLE;
2496 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2498 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2499 (ndesc - 1) * sizeof(struct bwi_desc32));
2503 bwi_init_rx_ring32(struct bwi_softc *sc)
2505 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2508 sc->sc_rx_bdata.rbd_idx = 0;
2510 for (i = 0; i < BWI_RX_NDESC; ++i) {
2511 error = bwi_newbuf(sc, i, 1);
2513 if_printf(&sc->sc_ic.ic_if,
2514 "can't allocate %dth RX buffer\n", i);
2518 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2519 BUS_DMASYNC_PREWRITE);
2521 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2522 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2527 bwi_init_txstats32(struct bwi_softc *sc)
2529 struct bwi_txstats_data *st = sc->sc_txstats;
2530 bus_addr_t stats_paddr;
2533 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2534 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2538 stats_paddr = st->stats_paddr;
2539 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2540 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2541 stats_paddr, sizeof(struct bwi_txstats), 0);
2542 stats_paddr += sizeof(struct bwi_txstats);
2544 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2545 BUS_DMASYNC_PREWRITE);
2547 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2548 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2553 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2556 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2558 KKASSERT(buf_idx < BWI_RX_NDESC);
2559 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2564 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2565 int buf_idx, bus_addr_t paddr, int buf_len)
2567 KKASSERT(buf_idx < BWI_TX_NDESC);
2568 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2573 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2580 bwi_init_rx_ring64(struct bwi_softc *sc)
2587 bwi_init_txstats64(struct bwi_softc *sc)
2594 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2601 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2602 int buf_idx, bus_addr_t paddr, int buf_len)
2608 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2609 bus_size_t mapsz __unused, int error)
2612 KASSERT(nseg == 1, ("too many segments(%d)", nseg));
2613 *((bus_addr_t *)arg) = seg->ds_addr;
2618 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2620 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2621 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2622 struct bwi_rxbuf_hdr *hdr;
2628 KKASSERT(buf_idx < BWI_RX_NDESC);
2630 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2635 * If the NIC is up and running, we need to:
2636 * - Clear RX buffer's header.
2637 * - Restore RX descriptor settings.
2644 m->m_len = m->m_pkthdr.len = MCLBYTES;
2647 * Try to load RX buf into temporary DMA map
2649 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2650 bwi_dma_buf_addr, &paddr,
2651 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2656 * See the comment above
2665 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2667 rxbuf->rb_paddr = paddr;
2670 * Swap RX buf's DMA map with the loaded temporary one
2672 map = rxbuf->rb_dmap;
2673 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2674 rbd->rbd_tmp_dmap = map;
2678 * Clear RX buf header
2680 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2681 bzero(hdr, sizeof(*hdr));
2682 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2685 * Setup RX buf descriptor
2687 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2688 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2693 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2694 const uint8_t *addr)
2698 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2699 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2701 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2704 addr_val = (uint16_t)addr[i * 2] |
2705 (((uint16_t)addr[(i * 2) + 1]) << 8);
2706 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2711 bwi_set_chan(struct bwi_softc *sc, struct ieee80211_channel *c)
2713 struct ieee80211com *ic = &sc->sc_ic;
2715 struct ifnet *ifp = &ic->ic_if;
2717 struct bwi_mac *mac;
2721 ASSERT_SERIALIZED(ifp->if_serializer);
2723 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2724 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2726 chan = ieee80211_chan2ieee(ic, c);
2728 bwi_rf_set_chan(mac, chan, 0);
2731 * Setup radio tap channel freq and flags
2733 if (IEEE80211_IS_CHAN_G(c))
2734 flags = IEEE80211_CHAN_G;
2736 flags = IEEE80211_CHAN_B;
2738 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
2739 htole16(c->ic_freq);
2740 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
2747 bwi_next_scan(void *xsc)
2749 struct bwi_softc *sc = xsc;
2750 struct ieee80211com *ic = &sc->sc_ic;
2751 struct ifnet *ifp = &ic->ic_if;
2753 lwkt_serialize_enter(ifp->if_serializer);
2755 if (ic->ic_state == IEEE80211_S_SCAN)
2756 ieee80211_next_scan(ic);
2758 lwkt_serialize_exit(ifp->if_serializer);
2762 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2764 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2765 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2766 struct ieee80211com *ic = &sc->sc_ic;
2767 struct ifnet *ifp = &ic->ic_if;
2768 int idx, rx_data = 0;
2771 while (idx != end_idx) {
2772 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2773 struct bwi_rxbuf_hdr *hdr;
2774 struct ieee80211_frame_min *wh;
2775 struct ieee80211_node *ni;
2779 int buflen, wh_ofs, hdr_extra, rssi, type, rate;
2782 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2783 BUS_DMASYNC_POSTREAD);
2785 if (bwi_newbuf(sc, idx, 0)) {
2786 IFNET_STAT_INC(ifp, ierrors, 1);
2790 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2791 flags2 = le16toh(hdr->rxh_flags2);
2794 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2796 wh_ofs = hdr_extra + 6; /* XXX magic number */
2798 buflen = le16toh(hdr->rxh_buflen);
2799 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2800 if_printf(ifp, "short frame %d, hdr_extra %d\n",
2802 IFNET_STAT_INC(ifp, ierrors, 1);
2807 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra);
2808 rssi = bwi_calc_rssi(sc, hdr);
2810 m->m_pkthdr.rcvif = ifp;
2811 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2812 m_adj(m, sizeof(*hdr) + wh_ofs);
2814 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2815 rate = bwi_ofdm_plcp2rate(plcp);
2817 rate = bwi_ds_plcp2rate(plcp);
2820 if (sc->sc_drvbpf != NULL)
2821 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi);
2823 m_adj(m, -IEEE80211_CRC_LEN);
2825 wh = mtod(m, struct ieee80211_frame_min *);
2826 ni = ieee80211_find_rxnode(ic, wh);
2828 type = ieee80211_input(ic, m, ni, rssi - BWI_NOISE_FLOOR,
2829 le16toh(hdr->rxh_tsf));
2830 ieee80211_free_node(ni);
2832 if (type == IEEE80211_FC0_TYPE_DATA) {
2834 sc->sc_rx_rate = rate;
2837 idx = (idx + 1) % BWI_RX_NDESC;
2841 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2842 BUS_DMASYNC_PREWRITE);
2847 bwi_rxeof32(struct bwi_softc *sc)
2849 uint32_t val, rx_ctrl;
2850 int end_idx, rx_data;
2852 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2854 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2855 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2856 sizeof(struct bwi_desc32);
2858 rx_data = bwi_rxeof(sc, end_idx);
2860 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2861 end_idx * sizeof(struct bwi_desc32));
2867 bwi_rxeof64(struct bwi_softc *sc)
2874 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2878 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2882 for (i = 0; i < NRETRY; ++i) {
2885 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2886 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2887 BWI_RX32_STATUS_STATE_DISABLED)
2893 if_printf(&sc->sc_ic.ic_if, "reset rx ring timedout\n");
2897 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2901 bwi_free_txstats32(struct bwi_softc *sc)
2903 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2907 bwi_free_rx_ring32(struct bwi_softc *sc)
2909 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2910 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2913 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2915 for (i = 0; i < BWI_RX_NDESC; ++i) {
2916 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2918 if (rb->rb_mbuf != NULL) {
2919 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2920 m_freem(rb->rb_mbuf);
2927 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2929 struct bwi_ring_data *rd;
2930 struct bwi_txbuf_data *tbd;
2931 struct ifnet *ifp = &sc->sc_ic.ic_if;
2932 uint32_t state, val;
2935 KKASSERT(ring_idx < BWI_TX_NRING);
2936 rd = &sc->sc_tx_rdata[ring_idx];
2937 tbd = &sc->sc_tx_bdata[ring_idx];
2941 for (i = 0; i < NRETRY; ++i) {
2942 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2943 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2944 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2945 state == BWI_TX32_STATUS_STATE_IDLE ||
2946 state == BWI_TX32_STATUS_STATE_STOPPED)
2952 if_printf(ifp, "wait for TX ring(%d) stable timed out\n",
2956 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2957 for (i = 0; i < NRETRY; ++i) {
2958 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2959 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2960 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2966 if_printf(ifp, "reset TX ring (%d) timed out\n", ring_idx);
2972 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2974 for (i = 0; i < BWI_TX_NDESC; ++i) {
2975 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2977 if (tb->tb_mbuf != NULL) {
2978 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2979 m_freem(tb->tb_mbuf);
2982 if (tb->tb_ni != NULL) {
2983 ieee80211_free_node(tb->tb_ni);
2990 bwi_free_txstats64(struct bwi_softc *sc)
2996 bwi_free_rx_ring64(struct bwi_softc *sc)
3002 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
3008 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
3009 struct ieee80211_node **ni0, int mgt_pkt)
3011 struct ieee80211com *ic = &sc->sc_ic;
3012 struct ieee80211_node *ni = *ni0;
3013 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
3014 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
3015 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3016 struct bwi_mac *mac;
3017 struct bwi_txbuf_hdr *hdr;
3018 struct ieee80211_frame *wh;
3019 uint8_t rate, rate_fb;
3023 int pkt_len, error, mcast_pkt = 0;
3029 KKASSERT(ni != NULL);
3030 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3031 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3033 wh = mtod(m, struct ieee80211_frame *);
3035 /* Get 802.11 frame len before prepending TX header */
3036 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3041 bzero(tb->tb_rateidx, sizeof(tb->tb_rateidx));
3043 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
3046 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3049 if (ic->ic_fixed_rate >= 1)
3050 idx = ic->ic_fixed_rate - 1;
3053 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates, idx);
3055 tb->tb_rateidx_cnt = ieee80211_ratectl_findrate(ni,
3056 m->m_pkthdr.len, tb->tb_rateidx, BWI_NTXRATE);
3058 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3060 if (tb->tb_rateidx_cnt == BWI_NTXRATE) {
3061 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates,
3066 tb->tb_buflen = m->m_pkthdr.len;
3069 /* Fixed at 1Mbits/s for mgt frames */
3070 rate = rate_fb = (1 * 2);
3073 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3074 rate = rate_fb = ic->ic_mcast_rate;
3078 if (rate == 0 || rate_fb == 0) {
3079 /* XXX this should not happen */
3080 if_printf(&ic->ic_if, "invalid rate %u or fallback rate %u",
3082 rate = rate_fb = (1 * 2); /* Force 1Mbits/s */
3084 sc->sc_tx_rate = rate;
3089 if (sc->sc_drvbpf != NULL) {
3090 sc->sc_tx_th.wt_flags = 0;
3091 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3092 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3093 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_DS &&
3094 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3096 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3098 sc->sc_tx_th.wt_rate = rate;
3100 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_tx_th, sc->sc_tx_th_len);
3104 * Setup the embedded TX header
3106 M_PREPEND(m, sizeof(*hdr), MB_DONTWAIT);
3108 if_printf(&ic->ic_if, "prepend TX header failed\n");
3111 hdr = mtod(m, struct bwi_txbuf_hdr *);
3113 bzero(hdr, sizeof(*hdr));
3115 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3116 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3122 ack_rate = ieee80211_ack_rate(ni, rate_fb);
3123 dur = ieee80211_txtime(ni,
3124 sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN,
3125 ack_rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
3127 hdr->txh_fb_duration = htole16(dur);
3130 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3131 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3133 bwi_plcp_header(hdr->txh_plcp, pkt_len, rate);
3134 bwi_plcp_header(hdr->txh_fb_plcp, pkt_len, rate_fb);
3136 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3137 BWI_TXH_PHY_C_ANTMODE_MASK);
3138 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_OFDM)
3139 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3140 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3141 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3143 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3144 if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
3145 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3146 if (ieee80211_rate2modtype(rate_fb) == IEEE80211_MODTYPE_OFDM)
3147 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3149 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3150 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3152 /* Catch any further usage */
3157 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3158 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3159 if (error && error != EFBIG) {
3160 if_printf(&ic->ic_if, "can't load TX buffer (1) %d\n", error);
3164 if (error) { /* error == EFBIG */
3167 m_new = m_defrag(m, MB_DONTWAIT);
3168 if (m_new == NULL) {
3169 if_printf(&ic->ic_if, "can't defrag TX buffer\n");
3176 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3177 bwi_dma_buf_addr, &paddr,
3180 if_printf(&ic->ic_if, "can't load TX buffer (2) %d\n",
3187 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3189 if (mgt_pkt || mcast_pkt) {
3190 /* Don't involve mcast/mgt packets into TX rate control */
3191 ieee80211_free_node(ni);
3198 p = mtod(m, const uint8_t *);
3199 for (i = 0; i < m->m_pkthdr.len; ++i) {
3200 if (i != 0 && i % 8 == 0)
3202 kprintf("%02x ", p[i]);
3207 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3208 idx, pkt_len, m->m_pkthdr.len);
3210 /* Setup TX descriptor */
3211 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3212 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3213 BUS_DMASYNC_PREWRITE);
3216 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3225 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3227 idx = (idx + 1) % BWI_TX_NDESC;
3228 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3229 idx * sizeof(struct bwi_desc32));
3233 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3239 bwi_txeof_status32(struct bwi_softc *sc)
3241 struct ifnet *ifp = &sc->sc_ic.ic_if;
3242 uint32_t val, ctrl_base;
3245 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3247 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3248 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3249 sizeof(struct bwi_desc32);
3251 bwi_txeof_status(sc, end_idx);
3253 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3254 end_idx * sizeof(struct bwi_desc32));
3256 if (!ifq_is_oactive(&ifp->if_snd))
3261 bwi_txeof_status64(struct bwi_softc *sc)
3267 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3269 struct ifnet *ifp = &sc->sc_ic.ic_if;
3270 struct bwi_txbuf_data *tbd;
3271 struct bwi_txbuf *tb;
3272 int ring_idx, buf_idx;
3275 if_printf(ifp, "zero tx id\n");
3279 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3280 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3282 KKASSERT(ring_idx == BWI_TX_DATA_RING);
3283 KKASSERT(buf_idx < BWI_TX_NDESC);
3285 tbd = &sc->sc_tx_bdata[ring_idx];
3286 KKASSERT(tbd->tbd_used > 0);
3289 tb = &tbd->tbd_buf[buf_idx];
3291 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3292 "acked %d, data_txcnt %d, ni %p\n",
3293 buf_idx, acked, data_txcnt, tb->tb_ni);
3295 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3296 m_freem(tb->tb_mbuf);
3299 if (tb->tb_ni != NULL) {
3300 struct ieee80211_ratectl_res res[BWI_NTXRATE];
3303 if (data_txcnt <= BWI_SHRETRY_FB || tb->tb_rateidx_cnt == 1) {
3305 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3306 res[0].rc_res_tries = data_txcnt;
3308 res_len = BWI_NTXRATE;
3309 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3310 res[0].rc_res_tries = BWI_SHRETRY_FB;
3311 res[1].rc_res_rateidx = tb->tb_rateidx[1];
3312 res[1].rc_res_tries = data_txcnt - BWI_SHRETRY_FB;
3316 IFNET_STAT_INC(ifp, opackets, 1);
3317 retry = data_txcnt > 0 ? data_txcnt - 1 : 0;
3319 IFNET_STAT_INC(ifp, oerrors, 1);
3323 ieee80211_ratectl_tx_complete(tb->tb_ni, tb->tb_buflen,
3324 res, res_len, retry, 0, !acked);
3326 ieee80211_free_node(tb->tb_ni);
3329 /* XXX mgt packet error */
3330 IFNET_STAT_INC(ifp, opackets, 1);
3333 if (tbd->tbd_used == 0)
3334 sc->sc_tx_timer = 0;
3336 ifq_clr_oactive(&ifp->if_snd);
3340 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3342 struct bwi_txstats_data *st = sc->sc_txstats;
3345 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3347 idx = st->stats_idx;
3348 while (idx != end_idx) {
3349 const struct bwi_txstats *stats = &st->stats[idx];
3351 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3354 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3355 BWI_TXS_TXCNT_DATA);
3356 _bwi_txeof(sc, le16toh(stats->txs_id),
3357 stats->txs_flags & BWI_TXS_F_ACKED,
3360 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3362 st->stats_idx = idx;
3366 bwi_txeof(struct bwi_softc *sc)
3368 struct ifnet *ifp = &sc->sc_ic.ic_if;
3371 uint32_t tx_status0, tx_status1;
3375 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3376 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3378 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3380 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3381 data_txcnt = __SHIFTOUT(tx_status0,
3382 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3384 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3387 _bwi_txeof(sc, tx_id, tx_status0 & BWI_TXSTATUS0_ACKED,
3391 if (!ifq_is_oactive(&ifp->if_snd))
3396 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3398 bwi_power_on(sc, 1);
3399 return bwi_set_clock_mode(sc, clk_mode);
3403 bwi_bbp_power_off(struct bwi_softc *sc)
3405 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3406 bwi_power_off(sc, 1);
3410 bwi_get_pwron_delay(struct bwi_softc *sc)
3412 struct bwi_regwin *com, *old;
3413 struct bwi_clock_freq freq;
3417 com = &sc->sc_com_regwin;
3418 KKASSERT(BWI_REGWIN_EXIST(com));
3420 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3423 error = bwi_regwin_switch(sc, com, &old);
3427 bwi_get_clock_freq(sc, &freq);
3429 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3430 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3431 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3433 return bwi_regwin_switch(sc, old, NULL);
3437 bwi_bus_attach(struct bwi_softc *sc)
3439 struct bwi_regwin *bus, *old;
3442 bus = &sc->sc_bus_regwin;
3444 error = bwi_regwin_switch(sc, bus, &old);
3448 if (!bwi_regwin_is_enabled(sc, bus))
3449 bwi_regwin_enable(sc, bus, 0);
3451 /* Disable interripts */
3452 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3454 return bwi_regwin_switch(sc, old, NULL);
3458 bwi_regwin_name(const struct bwi_regwin *rw)
3460 switch (rw->rw_type) {
3461 case BWI_REGWIN_T_COM:
3463 case BWI_REGWIN_T_BUSPCI:
3465 case BWI_REGWIN_T_MAC:
3467 case BWI_REGWIN_T_BUSPCIE:
3470 panic("unknown regwin type 0x%04x", rw->rw_type);
3475 bwi_regwin_disable_bits(struct bwi_softc *sc)
3479 /* XXX cache this */
3480 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3481 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3482 "bus rev %u\n", busrev);
3484 if (busrev == BWI_BUSREV_0)
3485 return BWI_STATE_LO_DISABLE1;
3486 else if (busrev == BWI_BUSREV_1)
3487 return BWI_STATE_LO_DISABLE2;
3489 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3493 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3495 uint32_t val, disable_bits;
3497 disable_bits = bwi_regwin_disable_bits(sc);
3498 val = CSR_READ_4(sc, BWI_STATE_LO);
3500 if ((val & (BWI_STATE_LO_CLOCK |
3501 BWI_STATE_LO_RESET |
3502 disable_bits)) == BWI_STATE_LO_CLOCK) {
3503 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3504 bwi_regwin_name(rw));
3507 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3508 bwi_regwin_name(rw));
3514 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3516 uint32_t state_lo, disable_bits;
3519 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3522 * If current regwin is in 'reset' state, it was already disabled.
3524 if (state_lo & BWI_STATE_LO_RESET) {
3525 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3526 "%s was already disabled\n", bwi_regwin_name(rw));
3530 disable_bits = bwi_regwin_disable_bits(sc);
3533 * Disable normal clock
3535 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3536 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3539 * Wait until normal clock is disabled
3542 for (i = 0; i < NRETRY; ++i) {
3543 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3544 if (state_lo & disable_bits)
3549 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3550 bwi_regwin_name(rw));
3553 for (i = 0; i < NRETRY; ++i) {
3556 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3557 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3562 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3563 bwi_regwin_name(rw));
3568 * Reset and disable regwin with gated clock
3570 state_lo = BWI_STATE_LO_RESET | disable_bits |
3571 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3572 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3573 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3575 /* Flush pending bus write */
3576 CSR_READ_4(sc, BWI_STATE_LO);
3579 /* Reset and disable regwin */
3580 state_lo = BWI_STATE_LO_RESET | disable_bits |
3581 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3582 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3584 /* Flush pending bus write */
3585 CSR_READ_4(sc, BWI_STATE_LO);
3590 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3592 uint32_t state_lo, state_hi, imstate;
3594 bwi_regwin_disable(sc, rw, flags);
3596 /* Reset regwin with gated clock */
3597 state_lo = BWI_STATE_LO_RESET |
3598 BWI_STATE_LO_CLOCK |
3599 BWI_STATE_LO_GATED_CLOCK |
3600 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3601 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3603 /* Flush pending bus write */
3604 CSR_READ_4(sc, BWI_STATE_LO);
3607 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3608 if (state_hi & BWI_STATE_HI_SERROR)
3609 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3611 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3612 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3613 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3614 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3617 /* Enable regwin with gated clock */
3618 state_lo = BWI_STATE_LO_CLOCK |
3619 BWI_STATE_LO_GATED_CLOCK |
3620 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3621 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3623 /* Flush pending bus write */
3624 CSR_READ_4(sc, BWI_STATE_LO);
3627 /* Enable regwin with normal clock */
3628 state_lo = BWI_STATE_LO_CLOCK |
3629 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3630 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3632 /* Flush pending bus write */
3633 CSR_READ_4(sc, BWI_STATE_LO);
3638 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3640 struct ieee80211com *ic = &sc->sc_ic;
3641 struct bwi_mac *mac;
3642 struct bwi_myaddr_bssid buf;
3647 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3648 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3650 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3652 bcopy(ic->ic_myaddr, buf.myaddr, sizeof(buf.myaddr));
3653 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3655 n = sizeof(buf) / sizeof(val);
3656 p = (const uint8_t *)&buf;
3657 for (i = 0; i < n; ++i) {
3661 for (j = 0; j < sizeof(val); ++j)
3662 val |= ((uint32_t)(*p++)) << (j * 8);
3664 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3669 bwi_updateslot(struct ifnet *ifp)
3671 struct bwi_softc *sc = ifp->if_softc;
3672 struct ieee80211com *ic = &sc->sc_ic;
3673 struct bwi_mac *mac;
3675 if ((ifp->if_flags & IFF_RUNNING) == 0)
3678 ASSERT_SERIALIZED(ifp->if_serializer);
3680 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3682 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3683 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3685 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3689 bwi_calibrate(void *xsc)
3691 struct bwi_softc *sc = xsc;
3692 struct ieee80211com *ic = &sc->sc_ic;
3693 struct ifnet *ifp = &ic->ic_if;
3695 lwkt_serialize_enter(ifp->if_serializer);
3697 if (ic->ic_state == IEEE80211_S_RUN) {
3698 struct bwi_mac *mac;
3700 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3701 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3703 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
3704 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3705 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3708 /* XXX 15 seconds */
3709 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3712 lwkt_serialize_exit(ifp->if_serializer);
3716 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3718 struct bwi_mac *mac;
3720 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3721 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3723 return bwi_rf_calc_rssi(mac, hdr);
3727 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3728 struct bwi_rxbuf_hdr *hdr, const void *plcp,
3731 const struct ieee80211_frame_min *wh;
3733 KKASSERT(sc->sc_drvbpf != NULL);
3735 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3736 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3737 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3739 wh = mtod(m, const struct ieee80211_frame_min *);
3740 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3741 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3743 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */
3744 sc->sc_rx_th.wr_rate = rate;
3745 sc->sc_rx_th.wr_antsignal = rssi;
3746 sc->sc_rx_th.wr_antnoise = BWI_NOISE_FLOOR;
3748 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_rx_th, sc->sc_rx_th_len);
3752 bwi_led_attach(struct bwi_softc *sc)
3754 const uint8_t *led_act = NULL;
3755 uint16_t gpio, val[BWI_LED_MAX];
3758 for (i = 0; i < NELEM(bwi_vendor_led_act); ++i) {
3759 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3760 led_act = bwi_vendor_led_act[i].led_act;
3764 if (led_act == NULL)
3765 led_act = bwi_default_led_act;
3767 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3768 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3769 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3771 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3772 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3773 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3775 for (i = 0; i < BWI_LED_MAX; ++i) {
3776 struct bwi_led *led = &sc->sc_leds[i];
3778 if (val[i] == 0xff) {
3779 led->l_act = led_act[i];
3781 if (val[i] & BWI_LED_ACT_LOW)
3782 led->l_flags |= BWI_LED_F_ACTLOW;
3783 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3785 led->l_mask = (1 << i);
3787 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3788 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3789 led->l_act == BWI_LED_ACT_BLINK) {
3790 led->l_flags |= BWI_LED_F_BLINK;
3791 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3792 led->l_flags |= BWI_LED_F_POLLABLE;
3793 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3794 led->l_flags |= BWI_LED_F_SLOW;
3796 if (sc->sc_blink_led == NULL) {
3797 sc->sc_blink_led = led;
3798 if (led->l_flags & BWI_LED_F_SLOW)
3799 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3803 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3804 "%dth led, act %d, lowact %d\n", i,
3805 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3807 callout_init(&sc->sc_led_blink_ch);
3810 static __inline uint16_t
3811 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3813 if (led->l_flags & BWI_LED_F_ACTLOW)
3818 val &= ~led->l_mask;
3823 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3825 struct ieee80211com *ic = &sc->sc_ic;
3829 if (nstate == IEEE80211_S_INIT) {
3830 callout_stop(&sc->sc_led_blink_ch);
3831 sc->sc_led_blinking = 0;
3834 if ((ic->ic_if.if_flags & IFF_RUNNING) == 0)
3837 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3838 for (i = 0; i < BWI_LED_MAX; ++i) {
3839 struct bwi_led *led = &sc->sc_leds[i];
3842 if (led->l_act == BWI_LED_ACT_UNKN ||
3843 led->l_act == BWI_LED_ACT_NULL)
3846 if ((led->l_flags & BWI_LED_F_BLINK) &&
3847 nstate != IEEE80211_S_INIT)
3850 switch (led->l_act) {
3851 case BWI_LED_ACT_ON: /* Always on */
3854 case BWI_LED_ACT_OFF: /* Always off */
3855 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3861 case IEEE80211_S_INIT:
3864 case IEEE80211_S_RUN:
3865 if (led->l_act == BWI_LED_ACT_11G &&
3866 ic->ic_curmode != IEEE80211_MODE_11G)
3870 if (led->l_act == BWI_LED_ACT_ASSOC)
3877 val = bwi_led_onoff(led, val, on);
3879 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3883 bwi_led_event(struct bwi_softc *sc, int event)
3885 struct bwi_led *led = sc->sc_blink_led;
3888 if (event == BWI_LED_EVENT_POLL) {
3889 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3891 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3895 sc->sc_led_ticks = ticks;
3896 if (sc->sc_led_blinking)
3900 case BWI_LED_EVENT_RX:
3901 rate = sc->sc_rx_rate;
3903 case BWI_LED_EVENT_TX:
3904 rate = sc->sc_tx_rate;
3906 case BWI_LED_EVENT_POLL:
3910 panic("unknown LED event %d", event);
3913 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3914 bwi_led_duration[rate].off_dur);
3918 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
3920 struct bwi_led *led = sc->sc_blink_led;
3923 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3924 val = bwi_led_onoff(led, val, 1);
3925 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3927 if (led->l_flags & BWI_LED_F_SLOW) {
3928 BWI_LED_SLOWDOWN(on_dur);
3929 BWI_LED_SLOWDOWN(off_dur);
3932 sc->sc_led_blinking = 1;
3933 sc->sc_led_blink_offdur = off_dur;
3935 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
3939 bwi_led_blink_next(void *xsc)
3941 struct bwi_softc *sc = xsc;
3944 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3945 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
3946 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3948 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
3949 bwi_led_blink_end, sc);
3953 bwi_led_blink_end(void *xsc)
3955 struct bwi_softc *sc = xsc;
3957 sc->sc_led_blinking = 0;
3961 bwi_ratectl_attach(struct ieee80211com *ic, u_int rc)
3963 struct bwi_softc *sc = ic->ic_if.if_softc;
3966 case IEEE80211_RATECTL_ONOE:
3967 return &sc->sc_onoe_param;
3968 case IEEE80211_RATECTL_NONE:
3969 /* This could only happen during detaching */
3972 panic("unknown rate control algo %u", rc);