2 * Copyright (c) 1996, Javier MartÃn Rueda (jmrueda@diatel.upm.es)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/ex/if_exreg.h,v 1.1.10.2 2001/03/05 05:33:20 imp Exp $
28 * $DragonFly: src/sys/dev/netif/ex/if_exreg.h,v 1.2 2003/06/17 04:28:25 dillon Exp $
32 * Intel EtherExpress Pro/10 Ethernet driver
39 #define CARD_TYPE_EX_10 1
40 #define CARD_TYPE_EX_10_PLUS 2
42 /* Length of an ethernet address. */
43 #define ETHER_ADDR_LEN 6
44 /* Default RAM size in board. */
45 #define CARD_RAM_SIZE 0x8000
46 /* Number of I/O ports used. */
50 * Intel EtherExpress Pro (i82595 based) registers
53 /* Common registers to all banks. */
72 /* Definitions for command register (CMD_REG). */
74 #define Switch_Bank_CMD 0
75 #define MC_Setup_CMD 3
76 #define Transmit_CMD 4
77 #define Diagnose_CMD 7
78 #define Rcv_Enable_CMD 8
81 #define Resume_XMT_List_CMD 28
82 #define Sel_Reset_CMD 30
84 #define Bank0_Sel 0x00
85 #define Bank1_Sel 0x40
86 #define Bank2_Sel 0x80
88 /* Bank 0 specific registers. */
94 #define Counter_bits 0xc0
99 #define Rx_Stp_Int 0x01
104 #define RCV_STOP_REG 6
106 #define HOST_ADDR_REG 12 /* 16-bit register */
107 #define IO_PORT_REG 14 /* 16-bit register */
109 /* Bank 1 specific registers. */
111 #define TriST_INT 0x80
113 #define RCV_LOWER_LIMIT_REG 8
114 #define RCV_UPPER_LIMIT_REG 9
115 #define XMT_LOWER_LIMIT_REG 10
116 #define XMT_UPPER_LIMIT_REG 11
118 /* Bank 2 specific registers. */
120 #define Disc_Bad_Fr 0x80
121 #define Tx_Chn_ErStp 0x40
122 #define Tx_Chn_Int_Md 0x20
123 #define No_SA_Ins 0x10
124 #define RX_CRC_InMem 0x04
127 #define I_ADDR_REG0 4
128 #define EEPROM_REG 10
129 #define Trnoff_Enable 0x10
131 /* EEPROM memory positions (16-bit wide). */
134 # define EE_W0_PNP 0x0001
135 # define EE_W0_BUS16 0x0004
136 # define EE_W0_FLASH_ADDR_MASK 0x0038
137 # define EE_W0_FLASH_ADDR_SHIFT 3
138 # define EE_W0_AUTO_IO 0x0040
139 # define EE_W0_FLASH 0x0100
140 # define EE_W0_AUTO_NEG 0x0200
141 # define EE_W0_IO_MASK 0xFC00
142 # define EE_W0_IO_SHIFT 10
145 #define IRQ_No_Mask 0x07
148 # define EE_W1_INT_SEL 0x0007
149 # define EE_W1_NO_LINK_INT 0x0008 /* Link Integrity Off */
150 # define EE_W1_NO_POLARITY 0x0010 /* Polarity Correction Off */
151 # define EE_W1_TPE_AUI 0x0020 /* 1 = TPE, 0 = AUI */
152 # define EE_W1_NO_JABBER_PREV 0x0040 /* Jabber prevention Off */
153 # define EE_W1_NO_AUTO_SELECT 0x0080 /* Auto Port Selection Off */
154 # define EE_W1_SMOUT 0x0100 /* SMout Pin Control 0= Input */
155 # define EE_W1_PROM 0x0200 /* Flash = 0, PROM = 1 */
156 # define EE_W1_ALT_READY 0x2000 /* Alternate Ready, 0=normal */
157 # define EE_W1_FULL_DUPLEX 0x8000
163 #define EE_Eth_Addr_Lo 2
164 #define EE_Eth_Addr_Mid 3
165 #define EE_Eth_Addr_Hi 4
168 # define EE_W5_BNC_TPE 0x0001 /* 0 = TPE, 1 = BNC */
169 # define EE_W5_BOOT_IPX 0x0002
170 # define EE_W5_BOOT_ODI 0x0004
171 # define EE_W5_BOOT_NDIS (EE_W5_BOOT_IPX|EE_W5_BOOT_ODI)
172 # define EE_W5_NUM_CONN 0x0008 /* 0 = 2, 1 = 3 */
173 # define EE_W5_NOFLASH 0x0010 /* No flash socket present */
174 # define EE_W5_PORT_TPE 0x0020 /* TPE present */
175 # define EE_W5_PORT_BNC 0x0040 /* BNC present */
176 # define EE_W5_PORT_AUI 0x0080 /* AUI present */
177 # define EE_W5_PWR_MGT 0x0100 /* Power Management */
178 # define EE_W5_CP 0x0200 /* COncurrent Processing */
181 # define EE_W6_STEP_MASK 0x000F
182 # define EE_W6_BOARD_MASK 0xFFF0
183 # define EE_W6_BOARD_SHIFT 4
185 /* EEPROM serial interface. */
191 #define EE_READ_CMD (6 << 6)
193 /* Frame chain constants. */
195 /* Transmit header length (in board's ring buffer). */
196 #define XMT_HEADER_LEN 8
197 #define XMT_Chain_Point 4
198 #define XMT_Byte_Count 6
199 #define Done_bit 0x0080
200 #define Ch_bit 0x8000
201 /* Transmit result bits. */
202 #define No_Collisions_bits 0x000f
203 #define TX_OK_bit 0x2000
204 /* Receive result bits. */
206 #define RCV_OK_bit 0x2000