2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jmereg.h,v 1.1 2008/05/27 01:42:01 yongari Exp $
28 * $DragonFly: src/sys/dev/netif/jme/if_jmereg.h,v 1.6 2008/11/26 11:55:18 sephe Exp $
34 /* FM/ECO revision. FM revision is in the upper 4bits. */
35 #define JME_REV1_A1 0x10
36 #define JME_REV1_A2 0x11 /* JMC250A2 */
38 #define JME_REV2_2 0x22
39 #define JME_REV3_1 0x31
40 #define JME_REV3_2 0x32
42 #define JME_REV5_1 0x51
43 #define JME_REV5_3 0x53
46 /* JMC250 PCI configuration register. */
47 #define JME_PCIR_BAR PCIR_BAR(0)
49 #define JME_PCI_EROM 0x30
51 #define JME_PCI_DBG 0x9C
53 #define JME_PCI_SPI 0xB0
55 #define SPI_ENB 0x00000010
56 #define SPI_SO_STATUS 0x00000008
57 #define SPI_SI_CTRL 0x00000004
58 #define SPI_SCK_CTRL 0x00000002
59 #define SPI_CS_N_CTRL 0x00000001
61 #define JME_PCI_PHYCFG0 0xC0
63 #define JME_PCI_PHYCFG1 0xC4
65 #define JME_PCI_PHYCFG2 0xC8
67 #define JME_PCI_PHYCFG3 0xCC
69 #define JME_PCI_PIPECTL1 0xD0
71 #define JME_PCI_PIPECTL2 0xD4
73 /* PCIe link error/status. */
74 #define JME_PCI_LES 0xD8
76 /* propeietary register 0. */
77 #define JME_PCI_PE0 0xE0
78 #define PE0_SPI_EXIST 0x00200000
79 #define PE0_PME_D0 0x00100000
80 #define PE0_PME_D3H 0x00080000
81 #define PE0_PME_SPI_PAD 0x00040000
82 #define PE0_MASK_ASPM 0x00020000
83 #define PE0_EEPROM_RW_DIS 0x00008000
84 #define PE0_PCI_INTA 0x00001000
85 #define PE0_PCI_INTB 0x00002000
86 #define PE0_PCI_INTC 0x00003000
87 #define PE0_PCI_INTD 0x00004000
88 #define PE0_PCI_SVSSID_WR_ENB 0x00000800
89 #define PE0_MSIX_SIZE_8 0x00000700
90 #define PE0_MSIX_SIZE_7 0x00000600
91 #define PE0_MSIX_SIZE_6 0x00000500
92 #define PE0_MSIX_SIZE_5 0x00000400
93 #define PE0_MSIX_SIZE_4 0x00000300
94 #define PE0_MSIX_SIZE_3 0x00000200
95 #define PE0_MSIX_SIZE_2 0x00000100
96 #define PE0_MSIX_SIZE_1 0x00000000
97 #define PE0_MSIX_SIZE_DEF 0x00000700
98 #define PE0_MSIX_CAP_DIS 0x00000080
99 #define PE0_MSI_PVMC_ENB 0x00000040
100 #define PE0_LCAP_EXIT_LAT_MASK 0x00000038
101 #define PE0_LCAP_EXIT_LAT_DEF 0x00000038
102 #define PE0_PM_AUXC_MASK 0x00000007
103 #define PE0_PM_AUXC_DEF 0x00000007
105 #define JME_PCI_PE1 0xE4
106 #define PE1_GPREG0_PHYBG 0x0000C000
107 #define PE1_GPREG0_ENBG 0x00000000
108 #define PE1_GPREG0_PDD3COLD 0x00004000
110 #define JME_PCI_SSCTRL 0xF4
111 #define SSCTRL_PHYMASK 0x30
112 #define SSCTRL_PHYEA 0x20
114 #define JME_PCI_PHYTEST 0xF8
116 #define JME_PCI_GPR 0xFC
120 * -----------------------------------------------------------------------
121 * Register Size IO space Memory space
122 * -----------------------------------------------------------------------
123 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~
124 * BAR1 + 0x7F BAR0 + 0x7F
125 * -----------------------------------------------------------------------
126 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~
127 * BAR2 + 0x7F BAR0 + 0x47F
128 * -----------------------------------------------------------------------
129 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~
130 * BAR2 + 0x7F BAR0 + 0x87F
131 * -----------------------------------------------------------------------
132 * To simplify register access fuctions and to get better performance
133 * this driver doesn't support IO space access. It could be implemented
134 * as a function which selects appropriate BARs to access requested
138 /* Tx control and status. */
139 #define JME_TXCSR 0x0000
140 #define TXCSR_QWEIGHT_MASK 0x0F000000
141 #define TXCSR_QWEIGHT_SHIFT 24
142 #define TXCSR_TXQ_SEL_MASK 0x00070000
143 #define TXCSR_TXQ_SEL_SHIFT 16
144 #define TXCSR_TXQ_START 0x00000001
145 #define TXCSR_TXQ_START_SHIFT 8
146 #define TXCSR_FIFO_THRESH_4QW 0x00000000
147 #define TXCSR_FIFO_THRESH_8QW 0x00000040
148 #define TXCSR_FIFO_THRESH_12QW 0x00000080
149 #define TXCSR_FIFO_THRESH_16QW 0x000000C0
150 #define TXCSR_DMA_SIZE_64 0x00000000
151 #define TXCSR_DMA_SIZE_128 0x00000010
152 #define TXCSR_DMA_SIZE_256 0x00000020
153 #define TXCSR_DMA_SIZE_512 0x00000030
154 #define TXCSR_DMA_BURST 0x00000004
155 #define TXCSR_TX_SUSPEND 0x00000002
156 #define TXCSR_TX_ENB 0x00000001
165 #define TXCSR_TXQ_WEIGHT(x) \
166 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK)
167 #define TXCSR_TXQ_WEIGHT_MIN 0
168 #define TXCSR_TXQ_WEIGHT_MAX 15
169 #define TXCSR_TXQ_N_SEL(x) \
170 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK)
171 #define TXCSR_TXQ_N_START(x) \
172 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x)))
174 /* Tx queue descriptor base address. 16bytes alignment required. */
175 #define JME_TXDBA_LO 0x0004
176 #define JME_TXDBA_HI 0x0008
178 /* Tx queue descriptor count. multiple of 16(max = 1024). */
179 #define JME_TXQDC 0x000C
180 #define TXQDC_MASK 0x0000007F0
182 /* Tx queue next descriptor address. */
183 #define JME_TXNDA 0x0010
184 #define TXNDA_ADDR_MASK 0xFFFFFFF0
185 #define TXNDA_DESC_EMPTY 0x00000008
186 #define TXNDA_DESC_VALID 0x00000004
187 #define TXNDA_DESC_WAIT 0x00000002
188 #define TXNDA_DESC_FETCH 0x00000001
190 /* Tx MAC control ans status. */
191 #define JME_TXMAC 0x0014
192 #define TXMAC_IFG2_MASK 0xC0000000
193 #define TXMAC_IFG2_DEFAULT 0x40000000
194 #define TXMAC_IFG1_MASK 0x30000000
195 #define TXMAC_IFG1_DEFAULT 0x20000000
196 #define TXMAC_THRESH_1_PKT 0x00000300
197 #define TXMAC_THRESH_1_2_PKT 0x00000200
198 #define TXMAC_THRESH_1_4_PKT 0x00000100
199 #define TXMAC_THRESH_1_8_PKT 0x00000000
200 #define TXMAC_FRAME_BURST 0x00000080
201 #define TXMAC_CARRIER_EXT 0x00000040
202 #define TXMAC_IFG_ENB 0x00000020
203 #define TXMAC_BACKOFF 0x00000010
204 #define TXMAC_CARRIER_SENSE 0x00000008
205 #define TXMAC_COLL_ENB 0x00000004
206 #define TXMAC_CRC_ENB 0x00000002
207 #define TXMAC_PAD_ENB 0x00000001
209 /* Tx pause frame control. */
210 #define JME_TXPFC 0x0018
211 #define TXPFC_VLAN_TAG_MASK 0xFFFF0000
212 #define TXPFC_VLAN_TAG_SHIFT 16
213 #define TXPFC_VLAN_ENB 0x00008000
214 #define TXPFC_PAUSE_ENB 0x00000001
216 /* Tx timer/retry at half duplex. */
217 #define JME_TXTRHD 0x001C
218 #define TXTRHD_RT_PERIOD_ENB 0x80000000
219 #define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00
220 #define TXTRHD_RT_PERIOD_SHIFT 8
221 #define TXTRHD_RT_LIMIT_ENB 0x00000080
222 #define TXTRHD_RT_LIMIT_MASK 0x0000007F
223 #define TXTRHD_RT_LIMIT_SHIFT 0
224 #define TXTRHD_RT_PERIOD_DEFAULT 8192
225 #define TXTRHD_RT_LIMIT_DEFAULT 8
227 /* Rx control & status. */
228 #define JME_RXCSR 0x0020
229 #define RXCSR_FIFO_FTHRESH_16T 0x00000000
230 #define RXCSR_FIFO_FTHRESH_32T 0x10000000
231 #define RXCSR_FIFO_FTHRESH_64T 0x20000000
232 #define RXCSR_FIFO_FTHRESH_128T 0x30000000
233 #define RXCSR_FIFO_FTHRESH_MASK 0x30000000
234 #define RXCSR_FIFO_THRESH_16QW 0x00000000
235 #define RXCSR_FIFO_THRESH_32QW 0x04000000
236 #define RXCSR_FIFO_THRESH_64QW 0x08000000
237 #define RXCSR_FIFO_THRESH_128QW 0x0C000000
238 #define RXCSR_FIFO_THRESH_MASK 0x0C000000
239 #define RXCSR_DMA_SIZE_16 0x00000000
240 #define RXCSR_DMA_SIZE_32 0x01000000
241 #define RXCSR_DMA_SIZE_64 0x02000000
242 #define RXCSR_DMA_SIZE_128 0x03000000
243 #define RXCSR_RXQ_SEL_MASK 0x00030000
244 #define RXCSR_RXQ_SEL_SHIFT 16
245 #define RXCSR_DESC_RT_GAP_MASK 0x0000F000
246 #define RXCSR_DESC_RT_GAP_SHIFT 12
247 #define RXCSR_DESC_RT_GAP_256 0x00000000
248 #define RXCSR_DESC_RT_GAP_512 0x00001000
249 #define RXCSR_DESC_RT_GAP_1024 0x00002000
250 #define RXCSR_DESC_RT_GAP_2048 0x00003000
251 #define RXCSR_DESC_RT_GAP_4096 0x00004000
252 #define RXCSR_DESC_RT_GAP_8192 0x00005000
253 #define RXCSR_DESC_RT_GAP_16384 0x00006000
254 #define RXCSR_DESC_RT_GAP_32768 0x00007000
255 #define RXCSR_DESC_RT_CNT_MASK 0x00000F00
256 #define RXCSR_DESC_RT_CNT_SHIFT 8
257 #define RXCSR_PASS_WAKEUP_PKT 0x00000040
258 #define RXCSR_PASS_MAGIC_PKT 0x00000020
259 #define RXCSR_PASS_RUNT_PKT 0x00000010
260 #define RXCSR_PASS_BAD_PKT 0x00000008
261 #define RXCSR_RXQ_START 0x00000004
262 #define RXCSR_RX_SUSPEND 0x00000002
263 #define RXCSR_RX_ENB 0x00000001
265 #define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT)
270 #define RXCSR_DESC_RT_CNT(x) \
271 ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK)
272 #define RXCSR_DESC_RT_CNT_DEFAULT 32
274 /* Rx queue descriptor base address. 16bytes alignment needed. */
275 #define JME_RXDBA_LO 0x0024
276 #define JME_RXDBA_HI 0x0028
278 /* Rx queue descriptor count. multiple of 16(max = 1024). */
279 #define JME_RXQDC 0x002C
280 #define RXQDC_MASK 0x0000007F0
282 /* Rx queue next descriptor address. */
283 #define JME_RXNDA 0x0030
284 #define RXNDA_ADDR_MASK 0xFFFFFFF0
285 #define RXNDA_DESC_EMPTY 0x00000008
286 #define RXNDA_DESC_VALID 0x00000004
287 #define RXNDA_DESC_WAIT 0x00000002
288 #define RXNDA_DESC_FETCH 0x00000001
290 /* Rx MAC control and status. */
291 #define JME_RXMAC 0x0034
292 #define RXMAC_RSS_UNICAST 0x00000000
293 #define RXMAC_RSS_UNI_MULTICAST 0x00010000
294 #define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000
295 #define RXMAC_RSS_ALLFRAME 0x00030000
296 #define RXMAC_PROMISC 0x00000800
297 #define RXMAC_BROADCAST 0x00000400
298 #define RXMAC_MULTICAST 0x00000200
299 #define RXMAC_UNICAST 0x00000100
300 #define RXMAC_ALLMULTI 0x00000080
301 #define RXMAC_MULTICAST_FILTER 0x00000040
302 #define RXMAC_COLL_DET_ENB 0x00000020
303 #define RXMAC_FC_ENB 0x00000008
304 #define RXMAC_VLAN_ENB 0x00000004
305 #define RXMAC_PAD_10BYTES 0x00000002
306 #define RXMAC_CSUM_ENB 0x00000001
308 /* Rx unicast MAC address. */
309 #define JME_PAR0 0x0038
310 #define JME_PAR1 0x003C
312 /* Rx multicast address hash table. */
313 #define JME_MAR0 0x0040
314 #define JME_MAR1 0x0044
316 /* Wakeup frame output data port. */
317 #define JME_WFODP 0x0048
319 /* Wakeup frame output interface. */
320 #define JME_WFOI 0x004C
321 #define WFOI_MASK_0_31 0x00000000
322 #define WFOI_MASK_31_63 0x00000010
323 #define WFOI_MASK_64_95 0x00000020
324 #define WFOI_MASK_96_127 0x00000030
325 #define WFOI_MASK_SEL 0x00000008
326 #define WFOI_CRC_SEL 0x00000000
327 #define WFOI_WAKEUP_FRAME_MASK 0x00000007
328 #define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK)
330 /* Station management interface. */
331 #define JME_SMI 0x0050
332 #define SMI_DATA_MASK 0xFFFF0000
333 #define SMI_DATA_SHIFT 16
334 #define SMI_REG_ADDR_MASK 0x0000F800
335 #define SMI_REG_ADDR_SHIFT 11
336 #define SMI_PHY_ADDR_MASK 0x000007C0
337 #define SMI_PHY_ADDR_SHIFT 6
338 #define SMI_OP_WRITE 0x00000020
339 #define SMI_OP_READ 0x00000000
340 #define SMI_OP_EXECUTE 0x00000010
341 #define SMI_MDIO 0x00000008
342 #define SMI_MDOE 0x00000004
343 #define SMI_MDC 0x00000002
344 #define SMI_MDEN 0x00000001
345 #define SMI_REG_ADDR(x) \
346 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK)
347 #define SMI_PHY_ADDR(x) \
348 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK)
350 /* Global host control. */
351 #define JME_GHC 0x0054
352 #define GHC_LOOPBACK 0x80000000
353 #define GHC_RESET 0x40000000
354 #define GHC_TXOFL_CLKSRC 0x00800000
355 #define GHC_TXOFL_CLKSRC_1000 0x00400000
356 #define GHC_TXMAC_CLKSRC 0x00200000
357 #define GHC_TXMAC_CLKSRC_1000 0x00100000
358 #define GHC_FULL_DUPLEX 0x00000040
359 #define GHC_SPEED_UNKNOWN 0x00000000
360 #define GHC_SPEED_10 0x00000010
361 #define GHC_SPEED_100 0x00000020
362 #define GHC_SPEED_1000 0x00000030
363 #define GHC_SPEED_MASK 0x00000030
364 #define GHC_LINK_OFF 0x00000004
365 #define GHC_LINK_ON 0x00000002
366 #define GHC_LINK_STAT_POLLING 0x00000001
368 /* Power management control and status. */
369 #define JME_PMCS 0x0060
370 #define PMCS_WAKEUP_FRAME_7 0x80000000
371 #define PMCS_WAKEUP_FRAME_6 0x40000000
372 #define PMCS_WAKEUP_FRAME_5 0x20000000
373 #define PMCS_WAKEUP_FRAME_4 0x10000000
374 #define PMCS_WAKEUP_FRAME_3 0x08000000
375 #define PMCS_WAKEUP_FRAME_2 0x04000000
376 #define PMCS_WAKEUP_FRAME_1 0x02000000
377 #define PMCS_WAKEUP_FRAME_0 0x01000000
378 #define PMCS_LINK_FAIL 0x00040000
379 #define PMCS_LINK_RISING 0x00020000
380 #define PMCS_MAGIC_FRAME 0x00010000
381 #define PMCS_WAKEUP_FRAME_7_ENB 0x00008000
382 #define PMCS_WAKEUP_FRAME_6_ENB 0x00004000
383 #define PMCS_WAKEUP_FRAME_5_ENB 0x00002000
384 #define PMCS_WAKEUP_FRAME_4_ENB 0x00001000
385 #define PMCS_WAKEUP_FRAME_3_ENB 0x00000800
386 #define PMCS_WAKEUP_FRAME_2_ENB 0x00000400
387 #define PMCS_WAKEUP_FRAME_1_ENB 0x00000200
388 #define PMCS_WAKEUP_FRAME_0_ENB 0x00000100
389 #define PMCS_LINK_FAIL_ENB 0x00000004
390 #define PMCS_LINK_RISING_ENB 0x00000002
391 #define PMCS_MAGIC_FRAME_ENB 0x00000001
392 #define PMCS_WOL_ENB_MASK 0x0000FFFF
394 /* Giga PHY & EEPROM registers. */
395 #define JME_PHY_EEPROM_BASE_ADDR 0x0400
397 #define JME_GIGAR0LO 0x0400
398 #define JME_GIGAR0HI 0x0404
399 #define JME_GIGARALO 0x0408
400 #define JME_GIGARAHI 0x040C
401 #define JME_GIGARBLO 0x0410
402 #define JME_GIGARBHI 0x0414
403 #define JME_GIGARCLO 0x0418
404 #define JME_GIGARCHI 0x041C
405 #define JME_GIGARDLO 0x0420
406 #define JME_GIGARDHI 0x0424
408 #define JME_PHYPWR 0x0424 /* XXX same as JME_GIGARDHI */
409 #define PHYPWR_DOWN1SEL 0x01000000
410 #define PHYPWR_DOWN1SW 0x02000000
411 #define PHYPWR_DOWN2 0x04000000
413 * XTL_OUT Clock select
414 * (an internal free-running clock)
415 * 0: xtl_out = A_XTL25_O
416 * 1: xtl_out = PD_OSC
418 #define PHYPWR_CLKSEL 0x08000000
421 /* BIST status and control. */
422 #define JME_GIGACSR 0x0428
423 #define GIGACSR_STATUS 0x40000000
424 #define GIGACSR_CTRL_MASK 0x30000000
425 #define GIGACSR_CTRL_DEFAULT 0x30000000
426 #define GIGACSR_TX_CLK_MASK 0x0F000000
427 #define GIGACSR_RX_CLK_MASK 0x00F00000
428 #define GIGACSR_TX_CLK_INV 0x00080000
429 #define GIGACSR_RX_CLK_INV 0x00040000
430 #define GIGACSR_PHY_RST 0x00010000
431 #define GIGACSR_IRQ_N_O 0x00001000
432 #define GIGACSR_BIST_OK 0x00000200
433 #define GIGACSR_BIST_DONE 0x00000100
434 #define GIGACSR_BIST_LED_ENB 0x00000010
435 #define GIGACSR_BIST_MASK 0x00000003
437 /* PHY Link Status. */
438 #define JME_LNKSTS 0x0430
439 #define LINKSTS_SPEED_10 0x00000000
440 #define LINKSTS_SPEED_100 0x00004000
441 #define LINKSTS_SPEED_1000 0x00008000
442 #define LINKSTS_FULL_DUPLEX 0x00002000
443 #define LINKSTS_PAGE_RCVD 0x00001000
444 #define LINKSTS_SPDDPX_RESOLVED 0x00000800
445 #define LINKSTS_UP 0x00000400
446 #define LINKSTS_ANEG_COMP 0x00000200
447 #define LINKSTS_MDI_CROSSOVR 0x00000040
448 #define LINKSTS_LPAR_PAUSE_ASYM 0x00000002
449 #define LINKSTS_LPAR_PAUSE 0x00000001
451 /* SMB control and status. */
452 #define JME_SMBCSR 0x0440
453 #define SMBCSR_SLAVE_ADDR_MASK 0x7F000000
454 #define SMBCSR_WR_DATA_NACK 0x00040000
455 #define SMBCSR_CMD_NACK 0x00020000
456 #define SMBCSR_RELOAD 0x00010000
457 #define SMBCSR_CMD_ADDR_MASK 0x0000FF00
458 #define SMBCSR_SCL_STAT 0x00000080
459 #define SMBCSR_SDA_STAT 0x00000040
460 #define SMBCSR_EEPROM_PRESENT 0x00000020
461 #define SMBCSR_INIT_LD_DONE 0x00000010
462 #define SMBCSR_HW_BUSY_MASK 0x0000000F
463 #define SMBCSR_HW_IDLE 0x00000000
466 #define JME_SMBINTF 0x0444
467 #define SMBINTF_RD_DATA_MASK 0xFF000000
468 #define SMBINTF_RD_DATA_SHIFT 24
469 #define SMBINTF_WR_DATA_MASK 0x00FF0000
470 #define SMBINTF_WR_DATA_SHIFT 16
471 #define SMBINTF_ADDR_MASK 0x0000FF00
472 #define SMBINTF_ADDR_SHIFT 8
473 #define SMBINTF_RD 0x00000020
474 #define SMBINTF_WR 0x00000000
475 #define SMBINTF_CMD_TRIGGER 0x00000010
476 #define SMBINTF_BUSY 0x00000010
477 #define SMBINTF_FAST_MODE 0x00000008
478 #define SMBINTF_GPIO_SCL 0x00000004
479 #define SMBINTF_GPIO_SDA 0x00000002
480 #define SMBINTF_GPIO_ENB 0x00000001
482 #define JME_EEPROM_SIG0 0x55
483 #define JME_EEPROM_SIG1 0xAA
484 #define JME_EEPROM_DESC_BYTES 3
485 #define JME_EEPROM_DESC_END 0x80
486 #define JME_EEPROM_FUNC_MASK 0x70
487 #define JME_EEPROM_FUNC_SHIFT 4
488 #define JME_EEPROM_PAGE_MASK 0x0F
489 #define JME_EEPROM_PAGE_SHIFT 0
491 #define JME_EEPROM_FUNC0 0
492 /* PCI configuration space. */
493 #define JME_EEPROM_PAGE_BAR0 0
494 /* 128 bytes I/O window. */
495 #define JME_EEPROM_PAGE_BAR1 1
496 /* 256 bytes I/O window. */
497 #define JME_EEPROM_PAGE_BAR2 2
499 #define JME_EEPROM_END 0xFF
501 #define JME_EEPROM_MKDESC(f, p) \
502 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \
503 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT))
505 /* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */
506 #define JME_EEPINTF 0x0448
507 #define EEPINTF_DATA_MASK 0xFFFF0000
508 #define EEPINTF_DATA_SHIFT 16
509 #define EEPINTF_ADDR_MASK 0x0000FC00
510 #define EEPINTF_ADDR_SHIFT 10
511 #define EEPRINTF_OP_MASK 0x00000300
512 #define EEPINTF_OP_EXECUTE 0x00000080
513 #define EEPINTF_DATA_OUT 0x00000008
514 #define EEPINTF_DATA_IN 0x00000004
515 #define EEPINTF_CLK 0x00000002
516 #define EEPINTF_SEL 0x00000001
518 /* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */
519 #define JME_EEPCSR 0x044C
520 #define EEPCSR_EEPROM_RELOAD 0x00000002
521 #define EEPCSR_EEPROM_PRESENT 0x00000001
523 /* Misc registers. */
524 #define JME_MISC_BASE_ADDR 0x800
526 /* Timer control and status. */
527 #define JME_TMCSR 0x0800
528 #define TMCSR_SW_INTR 0x80000000
529 #define TMCSR_TIMER_INTR 0x10000000
530 #define TMCSR_TIMER_ENB 0x01000000
531 #define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF
533 /* GPIO control and status. */
534 #define JME_GPIO 0x0804
535 #define GPIO_4_SPI_IN 0x80000000
536 #define GPIO_3_SPI_IN 0x40000000
537 #define GPIO_4_SPI_OUT 0x20000000
538 #define GPIO_4_SPI_OUT_ENB 0x10000000
539 #define GPIO_3_SPI_OUT 0x08000000
540 #define GPIO_3_SPI_OUT_ENB 0x04000000
541 #define GPIO_3_4_LED 0x00000000
542 #define GPIO_3_4_GPIO 0x02000000
543 #define GPIO_2_CLKREQN_IN 0x00100000
544 #define GPIO_2_CLKREQN_OUT 0x00040000
545 #define GPIO_2_CLKREQN_OUT_ENB 0x00020000
546 #define GPIO_1_LED42_IN 0x00001000
547 #define GPIO_1_LED42_OUT 0x00000400
548 #define GPIO_1_LED42_OUT_ENB 0x00000200
549 #define GPIO_1_LED42_ENB 0x00000100
550 #define GPIO_0_SDA_IN 0x00000010
551 #define GPIO_0_SDA_OUT 0x00000004
552 #define GPIO_0_SDA_OUT_ENB 0x00000002
553 #define GPIO_0_SDA_ENB 0x00000001
555 /* General purpose register 0. */
556 #define JME_GPREG0 0x0808
557 #define GPREG0_SH_POST_DW7_DIS 0x80000000
558 #define GPREG0_SH_POST_DW6_DIS 0x40000000
559 #define GPREG0_SH_POST_DW5_DIS 0x20000000
560 #define GPREG0_SH_POST_DW4_DIS 0x10000000
561 #define GPREG0_SH_POST_DW3_DIS 0x08000000
562 #define GPREG0_SH_POST_DW2_DIS 0x04000000
563 #define GPREG0_SH_POST_DW1_DIS 0x02000000
564 #define GPREG0_SH_POST_DW0_DIS 0x01000000
565 #define GPREG0_DMA_RD_REQ_8 0x00000000
566 #define GPREG0_DMA_RD_REQ_6 0x00100000
567 #define GPREG0_DMA_RD_REQ_5 0x00200000
568 #define GPREG0_DMA_RD_REQ_4 0x00300000
569 #define GPREG0_POST_DW0_ENB 0x00040000
570 #define GPREG0_PCC_CLR_DIS 0x00020000
571 #define GPREG0_FORCE_SCL_OUT 0x00010000
572 #define GPREG0_DL_RSTB_DIS 0x00008000
573 #define GPREG0_STICKY_RESET 0x00004000
574 #define GPREG0_DL_RSTB_CFG_DIS 0x00002000
575 #define GPREG0_LINK_CHG_POLL 0x00001000
576 #define GPREG0_LINK_CHG_DIRECT 0x00000000
577 #define GPREG0_MSI_GEN_SEL 0x00000800
578 #define GPREG0_SMB_PAD_PU_DIS 0x00000400
579 #define GPREG0_PCC_UNIT_16US 0x00000000
580 #define GPREG0_PCC_UNIT_256US 0x00000100
581 #define GPREG0_PCC_UNIT_US 0x00000200
582 #define GPREG0_PCC_UNIT_MS 0x00000300
583 #define GPREG0_PCC_UNIT_MASK 0x00000300
584 #define GPREG0_INTR_EVENT_ENB 0x00000080
585 #define GPREG0_PME_ENB 0x00000020
586 #define GPREG0_PHY_ADDR_MASK 0x0000001F
587 #define GPREG0_PHY_ADDR_SHIFT 0
588 #define GPREG0_PHY_ADDR 1
590 /* General purpose register 1. */
591 #define JME_GPREG1 0x080C
592 #define GPREG1_WA_HDX 0x00000020 /* 250A2 only, for 10/100 mode */
593 #define GPREG1_WA_IP6RSS 0x00000040 /* 250A2 only, for 10/100 mode */
594 #define GPREG1_DIS_RXMAC_CLKSRC 0x04000000
596 /* MSIX entry number of interrupt source. */
597 #define JME_MSINUM_BASE 0x0810
598 #define JME_MSINUM(x) (JME_MSINUM_BASE + (4 * (x)))
599 #define JME_MSINUM_CNT 4
600 #define JME_MSINUM_FACTOR 8
602 /* Interrupt event status. */
603 #define JME_INTR_STATUS 0x0820
604 #define INTR_SW 0x80000000
605 #define INTR_TIMER 0x40000000
606 #define INTR_LINKCHG 0x20000000
607 #define INTR_PAUSE 0x10000000
608 #define INTR_MAGIC_PKT 0x08000000
609 #define INTR_WAKEUP_PKT 0x04000000
610 #define INTR_RXQ0_COAL_TO 0x02000000
611 #define INTR_RXQ1_COAL_TO 0x01000000
612 #define INTR_RXQ2_COAL_TO 0x00800000
613 #define INTR_RXQ3_COAL_TO 0x00400000
614 #define INTR_TXQ_COAL_TO 0x00200000
615 #define INTR_RXQ0_COAL 0x00100000
616 #define INTR_RXQ1_COAL 0x00080000
617 #define INTR_RXQ2_COAL 0x00040000
618 #define INTR_RXQ3_COAL 0x00020000
619 #define INTR_TXQ_COAL 0x00010000
620 #define INTR_RXQ3_DESC_EMPTY 0x00008000
621 #define INTR_RXQ2_DESC_EMPTY 0x00004000
622 #define INTR_RXQ1_DESC_EMPTY 0x00002000
623 #define INTR_RXQ0_DESC_EMPTY 0x00001000
624 #define INTR_RXQ3_COMP 0x00000800
625 #define INTR_RXQ2_COMP 0x00000400
626 #define INTR_RXQ1_COMP 0x00000200
627 #define INTR_RXQ0_COMP 0x00000100
628 #define INTR_TXQ7_COMP 0x00000080
629 #define INTR_TXQ6_COMP 0x00000040
630 #define INTR_TXQ5_COMP 0x00000020
631 #define INTR_TXQ4_COMP 0x00000010
632 #define INTR_TXQ3_COMP 0x00000008
633 #define INTR_TXQ2_COMP 0x00000004
634 #define INTR_TXQ1_COMP 0x00000002
635 #define INTR_TXQ0_COMP 0x00000001
637 #define JME_INTR_CNT 32
639 #define INTR_RXQ_COAL_TO \
640 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \
641 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO)
643 #define INTR_RXQ_COAL \
644 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \
647 #define INTR_RXQ_COMP \
648 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \
651 #define INTR_RXQ_DESC_EMPTY \
652 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \
653 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY)
655 #define INTR_RXQ_COMP \
656 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \
659 #define INTR_TXQ_COMP \
660 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \
661 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \
662 INTR_TXQ6_COMP | INTR_TXQ7_COMP)
665 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \
666 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY)
669 #define N_INTR_TIMER 30
670 #define N_INTR_LINKCHG 29
671 #define N_INTR_PAUSE 28
672 #define N_INTR_MAGIC_PKT 27
673 #define N_INTR_WAKEUP_PKT 26
674 #define N_INTR_RXQ0_COAL_TO 25
675 #define N_INTR_RXQ1_COAL_TO 24
676 #define N_INTR_RXQ2_COAL_TO 23
677 #define N_INTR_RXQ3_COAL_TO 22
678 #define N_INTR_TXQ_COAL_TO 21
679 #define N_INTR_RXQ0_COAL 20
680 #define N_INTR_RXQ1_COAL 19
681 #define N_INTR_RXQ2_COAL 18
682 #define N_INTR_RXQ3_COAL 17
683 #define N_INTR_TXQ_COAL 16
684 #define N_INTR_RXQ3_DESC_EMPTY 15
685 #define N_INTR_RXQ2_DESC_EMPTY 14
686 #define N_INTR_RXQ1_DESC_EMPTY 13
687 #define N_INTR_RXQ0_DESC_EMPTY 12
688 #define N_INTR_RXQ3_COMP 11
689 #define N_INTR_RXQ2_COMP 10
690 #define N_INTR_RXQ1_COMP 9
691 #define N_INTR_RXQ0_COMP 8
692 #define N_INTR_TXQ7_COMP 7
693 #define N_INTR_TXQ6_COMP 6
694 #define N_INTR_TXQ5_COMP 5
695 #define N_INTR_TXQ4_COMP 4
696 #define N_INTR_TXQ3_COMP 3
697 #define N_INTR_TXQ2_COMP 2
698 #define N_INTR_TXQ1_COMP 1
699 #define N_INTR_TXQ0_COMP 0
701 /* Interrupt request status. */
702 #define JME_INTR_REQ_STATUS 0x0824
704 /* Interrupt enable - setting port. */
705 #define JME_INTR_MASK_SET 0x0828
707 /* Interrupt enable - clearing port. */
708 #define JME_INTR_MASK_CLR 0x082C
710 /* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */
711 #define JME_PCCRX(r) (0x0830 + ((r) * 4))
712 #define PCCRX_COAL_TO_MASK 0xFFFF0000
713 #define PCCRX_COAL_TO_SHIFT 16
714 #define PCCRX_COAL_PKT_MASK 0x0000FF00
715 #define PCCRX_COAL_PKT_SHIFT 8
717 #define PCCRX_COAL_TO_MIN 1
718 #define PCCRX_COAL_TO_DEFAULT 150
719 #define PCCRX_COAL_TO_MAX 65535
721 #define PCCRX_COAL_PKT_MIN 0
722 #define PCCRX_COAL_PKT_DEFAULT 64
723 #define PCCRX_COAL_PKT_MAX 255
725 /* Packet completion coalescing control of Tx queue. */
726 #define JME_PCCTX 0x0840
727 #define PCCTX_COAL_TO_MASK 0xFFFF0000
728 #define PCCTX_COAL_TO_SHIFT 16
729 #define PCCTX_COAL_PKT_MASK 0x0000FF00
730 #define PCCTX_COAL_PKT_SHIFT 8
731 #define PCCTX_COAL_TXQ7 0x00000080
732 #define PCCTX_COAL_TXQ6 0x00000040
733 #define PCCTX_COAL_TXQ5 0x00000020
734 #define PCCTX_COAL_TXQ4 0x00000010
735 #define PCCTX_COAL_TXQ3 0x00000008
736 #define PCCTX_COAL_TXQ2 0x00000004
737 #define PCCTX_COAL_TXQ1 0x00000002
738 #define PCCTX_COAL_TXQ0 0x00000001
740 #define PCCTX_COAL_TO_MIN 1
741 #define PCCTX_COAL_TO_DEFAULT 250
742 #define PCCTX_COAL_TO_MAX 65535
744 #define PCCTX_COAL_PKT_MIN 0
745 #define PCCTX_COAL_PKT_DEFAULT 128
746 #define PCCTX_COAL_PKT_MAX 255
748 /* Chip mode and FPGA version. */
749 #define JME_CHIPMODE 0x0844
750 #define CHIPMODE_FPGA_REV_MASK 0xFFFF0000
751 #define CHIPMODE_FPGA_REV_SHIFT 16
752 #define CHIPMODE_NOT_FPGA 0
753 #define CHIPMODE_REVECO_MASK 0x0000F000
754 #define CHIPMODE_REVECO_SHIFT 12
755 #define CHIPMODE_REVFM_MASK 0x00000F00
756 #define CHIPMODE_REVFM_SHIFT 8
757 #define CHIPMODE_MODE_48P 0x0000000C
758 #define CHIPMODE_MODE_64P 0x00000004
759 #define CHIPMODE_MODE_128P_MAC 0x00000003
760 #define CHIPMODE_MODE_128P_DBG 0x00000002
761 #define CHIPMODE_MODE_128P_PHY 0x00000000
763 /* Shadow status base address high/low. */
764 #define JME_SHBASE_ADDR_HI 0x0848
765 #define JME_SHBASE_ADDR_LO 0x084C
766 #define SHBASE_ADDR_LO_MASK 0xFFFFFFE0
767 #define SHBASE_POST_FORCE 0x00000002
768 #define SHBASE_POST_ENB 0x00000001
771 #define JME_TIMER1 0x0870
772 #define JME_TIMER2 0x0874
773 #define TIMER_ENB 0x01000000
774 #define TIMER_CNT_MASK 0x00FFFFFF
775 #define TIMER_CNT_SHIFT 0
776 #define TIMER_UNIT 1024 /* 1024us */
778 /* Aggresive power mode control. */
779 #define JME_APMC 0x087C
780 #define APMC_PCIE_SDOWN_STAT 0x80000000
781 #define APMC_PCIE_SDOWN_ENB 0x40000000
782 #define APMC_PSEUDO_HOT_PLUG 0x20000000
783 #define APMC_EXT_PLUGIN_ENB 0x04000000
784 #define APMC_EXT_PLUGIN_CTL_MSK 0x03000000
785 #define APMC_DIS_SRAM 0x00000004
786 #define APMC_DIS_CLKPM 0x00000002
787 #define APMC_DIS_CLKTX 0x00000001
789 /* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */
790 #define JME_PCCSRX_BASE 0x0880
791 #define JME_PCCSRX_END 0x088F
792 #define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4))
793 #define PCCSRX_TO_MASK 0xFFFF0000
794 #define PCCSRX_TO_SHIFT 16
795 #define PCCSRX_PKT_CNT_MASK 0x0000FF00
796 #define PCCSRX_PKT_CNT_SHIFT 8
798 /* Packet completion coalesing status of Tx queue. */
799 #define JME_PCCSTX 0x0890
800 #define PCCSTX_TO_MASK 0xFFFF0000
801 #define PCCSTX_TO_SHIFT 16
802 #define PCCSTX_PKT_CNT_MASK 0x0000FF00
803 #define PCCSTX_PKT_CNT_SHIFT 8
805 /* Tx queues empty indicator. */
806 #define JME_TXQEMPTY 0x0894
807 #define TXQEMPTY_TXQ7 0x00000080
808 #define TXQEMPTY_TXQ6 0x00000040
809 #define TXQEMPTY_TXQ5 0x00000020
810 #define TXQEMPTY_TXQ4 0x00000010
811 #define TXQEMPTY_TXQ3 0x00000008
812 #define TXQEMPTY_TXQ2 0x00000004
813 #define TXQEMPTY_TXQ1 0x00000002
814 #define TXQEMPTY_TXQ0 0x00000001
815 #define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y)))
817 /* RSS control registers. */
818 #define JME_RSS_BASE 0x0C00
820 #define JME_RSSC 0x0C00
821 #define RSSC_HASH_LEN_MASK 0x0000E000
822 #define RSSC_HASH_64_ENTRY 0x0000A000
823 #define RSSC_HASH_128_ENTRY 0x0000E000
824 #define RSSC_HASH_NONE 0x00001000
825 #define RSSC_HASH_IPV6 0x00000800
826 #define RSSC_HASH_IPV4 0x00000400
827 #define RSSC_HASH_IPV6_TCP 0x00000200
828 #define RSSC_HASH_IPV4_TCP 0x00000100
829 #define RSSC_NCPU_MASK 0x000000F8
830 #define RSSC_NCPU_SHIFT 3
831 #define RSSC_DIS_RSS 0x00000000
832 #define RSSC_2RXQ_ENB 0x00000001
833 #define RSSS_4RXQ_ENB 0x00000002
836 #define JME_RSSCPU 0x0C04
837 #define RSSCPU_N_SEL(x) ((1 << (x))
839 /* RSS Hash value. */
840 #define JME_RSSHASH 0x0C10
842 #define JME_RSSHASH_STAT 0x0C14
844 #define JME_RSS_RDATA0 0x0C18
846 #define JME_RSS_RDATA1 0x0C1C
848 /* RSS secret key. */
849 #define JME_RSSKEY_BASE 0x0C40
850 #define RSSKEY_NREGS 10
851 #define RSSKEY_REGSIZE 4
852 #define RSSKEY_REGVAL(k, x) (k[(x) * RSSKEY_REGSIZE] << 24 | \
853 k[(x) * RSSKEY_REGSIZE + 1] << 16 | \
854 k[(x) * RSSKEY_REGSIZE + 2] << 8 | \
855 k[(x) * RSSKEY_REGSIZE + 3])
856 #define RSSKEY_REG(x) (JME_RSSKEY_BASE + (RSSKEY_REGSIZE * (x)))
858 /* RSS indirection table entries. */
859 #define JME_RSSTBL_BASE 0x0C80
860 #define RSSTBL_NREGS 32
861 #define RSSTBL_REGSIZE 4
862 #define RSSTBL_REG(x) (JME_RSSTBL_BASE + (RSSTBL_REGSIZE * (x)))
865 #define JME_MSIX_BASE_ADDR 0x2000
867 #define JME_MSIX_BASE 0x2000
868 #define JME_MSIX_END 0x207F
869 #define JME_MSIX_NENTRY 8
870 #define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10))
871 #define MSIX_ADDR_HI_OFF 0x00
872 #define MSIX_ADDR_LO_OFF 0x04
873 #define MSIX_ADDR_LO_MASK 0xFFFFFFFC
874 #define MSIX_DATA_OFF 0x08
875 #define MSIX_VECTOR_OFF 0x0C
876 #define MSIX_VECTOR_RSVD 0x80000000
877 #define MSIX_VECTOR_DIS 0x00000001
880 #define JME_MSIX_PBA_BASE_ADDR 0x3000
882 #define JME_MSIX_PBA 0x3000
883 #define MSIX_PBA_RSVD_MASK 0xFFFFFF00
884 #define MSIX_PBA_RSVD_SHIFT 8
885 #define MSIX_PBA_PEND_MASK 0x000000FF
886 #define MSIX_PBA_PEND_SHIFT 0
887 #define MSIX_PBA_PEND_ENTRY7 0x00000080
888 #define MSIX_PBA_PEND_ENTRY6 0x00000040
889 #define MSIX_PBA_PEND_ENTRY5 0x00000020
890 #define MSIX_PBA_PEND_ENTRY4 0x00000010
891 #define MSIX_PBA_PEND_ENTRY3 0x00000008
892 #define MSIX_PBA_PEND_ENTRY2 0x00000004
893 #define MSIX_PBA_PEND_ENTRY1 0x00000002
894 #define MSIX_PBA_PEND_ENTRY0 0x00000001
896 #define JME_PHY_OUI 0x001B8C
897 #define JME_PHY_MODEL 0x21
898 #define JME_PHY_REV 0x01
899 #define JME_PHY_ADDR 1
901 /* JMC250 shadow status block. */
913 /* JMC250 descriptor structures. */
921 #define JME_TD_OWN 0x80000000
922 #define JME_TD_INTR 0x40000000
923 #define JME_TD_64BIT 0x20000000
924 #define JME_TD_TCPCSUM 0x10000000
925 #define JME_TD_UDPCSUM 0x08000000
926 #define JME_TD_IPCSUM 0x04000000
927 #define JME_TD_TSO 0x02000000
928 #define JME_TD_VLAN_TAG 0x01000000
929 #define JME_TD_VLAN_MASK 0x0000FFFF
931 #define JME_TD_MSS_MASK 0xFFFC0000
932 #define JME_TD_MSS_SHIFT 18
933 #define JME_TD_BUF_LEN_MASK 0x0000FFFF
934 #define JME_TD_BUF_LEN_SHIFT 0
936 #define JME_TD_FRAME_LEN_MASK 0x0000FFFF
937 #define JME_TD_FRAME_LEN_SHIFT 0
940 * Only the first Tx descriptor of a packet is updated
941 * after packet transmission.
943 #define JME_TD_TMOUT 0x20000000
944 #define JME_TD_RETRY_EXP 0x10000000
945 #define JME_TD_COLLISION 0x08000000
946 #define JME_TD_UNDERRUN 0x04000000
947 #define JME_TD_EHDR_SIZE_MASK 0x000000FF
948 #define JME_TD_EHDR_SIZE_SHIFT 0
950 #define JME_TD_SEG_CNT_MASK 0xFFFF0000
951 #define JME_TD_SEG_CNT_SHIFT 16
952 #define JME_TD_RETRY_CNT_MASK 0x0000FFFF
953 #define JME_TD_RETRY_CNT_SHIFT 0
955 #define JME_RD_OWN 0x80000000
956 #define JME_RD_INTR 0x40000000
957 #define JME_RD_64BIT 0x20000000
959 #define JME_RD_BUF_LEN_MASK 0x0000FFFF
960 #define JME_RD_BUF_LEN_SHIFT 0
963 * Only the first Rx descriptor of a packet is updated
964 * after packet reception.
966 #define JME_RD_MORE_FRAG 0x20000000
967 #define JME_RD_TCP 0x10000000
968 #define JME_RD_UDP 0x08000000
969 #define JME_RD_IPCSUM 0x04000000
970 #define JME_RD_TCPCSUM 0x02000000
971 #define JME_RD_UDPCSUM 0x01000000
972 #define JME_RD_VLAN_TAG 0x00800000
973 #define JME_RD_IPV4 0x00400000
974 #define JME_RD_IPV6 0x00200000
975 #define JME_RD_PAUSE 0x00100000
976 #define JME_RD_MAGIC 0x00080000
977 #define JME_RD_WAKEUP 0x00040000
978 #define JME_RD_BCAST 0x00030000
979 #define JME_RD_MCAST 0x00020000
980 #define JME_RD_UCAST 0x00010000
981 #define JME_RD_VLAN_MASK 0x0000FFFF
982 #define JME_RD_VLAN_SHIFT 0
984 #define JME_RD_VALID 0x80000000
985 #define JME_RD_CNT_MASK 0x7F000000
986 #define JME_RD_CNT_SHIFT 24
987 #define JME_RD_GIANT 0x00800000
988 #define JME_RD_GMII_ERR 0x00400000
989 #define JME_RD_NBL_RCVD 0x00200000
990 #define JME_RD_COLL 0x00100000
991 #define JME_RD_ABORT 0x00080000
992 #define JME_RD_RUNT 0x00040000
993 #define JME_RD_FIFO_OVRN 0x00020000
994 #define JME_RD_CRC_ERR 0x00010000
995 #define JME_RD_FRAME_LEN_MASK 0x0000FFFF
997 #define JME_RX_ERR_STAT \
998 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \
999 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \
1000 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR)
1002 #define JME_RD_ERR_MASK 0x00FF0000
1003 #define JME_RD_ERR_SHIFT 16
1004 #define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT)
1005 #define JME_RX_ERR_BITS "\20" \
1006 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \
1007 "\5COLL\6NBLRCVD\7GMIIERR\10"
1009 #define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT)
1010 #define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK)
1011 #define JME_RX_PAD_BYTES 10
1013 #define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF
1015 #define JME_RD_RSS_HASH_MASK 0x00003F00
1016 #define JME_RD_RSS_HASH_SHIFT 8
1017 #define JME_RD_RSS_HASH_NONE 0x00000000
1018 #define JME_RD_RSS_HASH_IPV4 0x00000100
1019 #define JME_RD_RSS_HASH_IPV4TCP 0x00000200
1020 #define JME_RD_RSS_HASH_IPV6 0x00000400
1021 #define JME_RD_RSS_HASH_IPV6TCP 0x00001000
1022 #define JME_RD_HASH_FN_MASK 0x0000000f
1023 #define JME_RD_HASH_FN_NONE 0x00000000
1024 #define JME_RD_HASH_FN_TOEPLITZ 0x00000001
1027 #define GTCR_TEST_1 0x2000
1029 /* MII register, extended register address */
1030 #define JME_MII_EXT_ADDR 0x1E
1031 #define JME_MII_EXT_ADDR_RD 0x4000
1032 #define JME_MII_EXT_ADDR_WR 0x8000
1033 #define JME_MII_EXT_COM0 0x0030
1034 #define JME_MII_EXT_COM1 0x0031
1035 #define JME_MII_EXT_COM2 0x0032
1037 /* MII register, extended register data */
1038 #define JME_MII_EXT_DATA 0x1F
1039 #define JME_MII_EXT_COM2_CALIB_EN 0x0001
1040 #define JME_MII_EXT_COM2_CALIB_MODE0 0x0002
1041 #define JME_MII_EXT_COM2_CALIB_LATCH 0x0010