2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.14 2011/05/05 19:15:15 delphij Exp $
30 * Device driver for Intel's On Die thermal sensor via MSR.
31 * First introduced in Intel's Core line of processors.
34 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/types.h>
38 #include <sys/module.h>
40 #include <sys/kernel.h>
41 #include <sys/sensors.h>
42 #include <sys/proc.h> /* for curthread */
43 #include <sys/sched.h>
44 #include <sys/thread2.h>
46 #include <machine/specialreg.h>
47 #include <machine/cpufunc.h>
48 #include <machine/cputypes.h>
49 #include <machine/md_var.h>
51 struct coretemp_softc {
52 struct ksensordev sc_sensordev;
53 struct ksensor sc_sensor;
57 struct globaldata *sc_gd;
59 volatile uint32_t sc_flags; /* CORETEMP_FLAG_ */
60 volatile uint64_t sc_msr;
63 #define CORETEMP_FLAG_INITED 0x1
64 #define CORETEMP_FLAG_PENDING 0x2
69 static void coretemp_identify(driver_t *driver, device_t parent);
70 static int coretemp_probe(device_t dev);
71 static int coretemp_attach(device_t dev);
72 static int coretemp_detach(device_t dev);
74 static int coretemp_get_temp(device_t dev);
75 static void coretemp_refresh(void *arg);
77 static device_method_t coretemp_methods[] = {
78 /* Device interface */
79 DEVMETHOD(device_identify, coretemp_identify),
80 DEVMETHOD(device_probe, coretemp_probe),
81 DEVMETHOD(device_attach, coretemp_attach),
82 DEVMETHOD(device_detach, coretemp_detach),
87 static driver_t coretemp_driver = {
90 sizeof(struct coretemp_softc),
93 static devclass_t coretemp_devclass;
94 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL);
95 MODULE_VERSION(coretemp, 1);
98 coretemp_identify(driver_t *driver, device_t parent)
103 /* Make sure we're not being doubly invoked. */
104 if (device_find_child(parent, "coretemp", -1) != NULL)
107 /* Check that CPUID 0x06 is supported and the vendor is Intel.*/
108 if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL)
111 * CPUID 0x06 returns 1 if the processor has on-die thermal
112 * sensors. EBX[0:3] contains the number of sensors.
114 do_cpuid(0x06, regs);
115 if ((regs[0] & 0x1) != 1)
119 * We add a child for each CPU since settings must be performed
120 * on each CPU in the SMP case.
122 child = device_add_child(parent, "coretemp", -1);
124 device_printf(parent, "add coretemp child failed\n");
128 coretemp_probe(device_t dev)
130 if (resource_disabled("coretemp", 0))
133 device_set_desc(dev, "CPU On-Die Thermal Sensors");
135 return (BUS_PROBE_GENERIC);
139 coretemp_attach(device_t dev)
141 struct coretemp_softc *sc = device_get_softc(dev);
144 int cpu_model, cpu_stepping;
148 pdev = device_get_parent(dev);
149 cpu_model = CPUID_TO_MODEL(cpu_id);
150 cpu_stepping = cpu_id & CPUID_STEPPING;
153 * Some CPUs, namely the PIII, don't have thermal sensors, but
154 * report them when the CPUID check is performed in
155 * coretemp_identify(). This leads to a later GPF when the sensor
156 * is queried via a MSR, so we stop here.
162 * XXXrpaulo: I have this CPU model and when it returns from C3
163 * coretemp continues to function properly.
167 * Check for errata AE18.
168 * "Processor Digital Thermal Sensor (DTS) Readout stops
169 * updating upon returning from C3/C4 state."
171 * Adapted from the Linux coretemp driver.
173 if (cpu_model == 0xe && cpu_stepping < 0xc) {
174 msr = rdmsr(MSR_BIOS_SIGN);
177 device_printf(dev, "not supported (Intel errata "
178 "AE18), try updating your BIOS\n");
185 * Use 100C as the initial value.
189 if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) {
191 * On some Core 2 CPUs, there's an undocumented MSR that
192 * can tell us if Tj(max) is 100 or 85.
194 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted
195 * from the Linux coretemp driver.
197 msr = rdmsr(MSR_IA32_EXT_CONFIG);
200 } else if (cpu_model == 0x17) {
201 switch (cpu_stepping) {
202 case 0x6: /* Mobile Core 2 Duo */
205 default: /* Unknown stepping */
208 } else if (cpu_model == 0x1c) {
209 switch (cpu_stepping) {
210 case 0xa: /* 45nm Atom D400, N400 and D500 series */
219 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
221 * This method is described in Intel white paper "CPU
222 * Monitoring With DTS/PECI". (#322683)
224 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
226 tjtarget = (msr >> 16) & 0xff;
229 * On earlier generation of processors, the value
230 * obtained from IA32_TEMPERATURE_TARGET register is
231 * an offset that needs to be summed with a model
232 * specific base. It is however not clear what
233 * these numbers are, with the publicly available
234 * documents from Intel.
236 * For now, we consider [70, 100]C range, as
237 * described in #322683, as "reasonable" and accept
238 * these values whenever the MSR is available for
239 * read, regardless the CPU model.
241 if (tjtarget >= 70 && tjtarget <= 100)
242 sc->sc_tjmax = tjtarget;
244 device_printf(dev, "Tj(target) value %d "
245 "does not seem right.\n", tjtarget);
247 device_printf(dev, "Can not get Tj(target) "
248 "from your CPU, using 100C.\n");
252 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax);
254 sc->sc_cpu = device_get_unit(device_get_parent(dev));
255 sc->sc_gd = globaldata_find(sc->sc_cpu);
258 * Add hw.sensors.cpuN.temp0 MIB.
260 strlcpy(sc->sc_sensordev.xname, device_get_nameunit(pdev),
261 sizeof(sc->sc_sensordev.xname));
262 sc->sc_sensor.type = SENSOR_TEMP;
263 sc->sc_sensor.flags |= SENSOR_FINVALID;
264 sc->sc_sensor.value = 0;
265 sensor_attach(&sc->sc_sensordev, &sc->sc_sensor);
266 sensor_task_register(sc, coretemp_refresh, 2);
267 sensordev_install(&sc->sc_sensordev);
273 coretemp_detach(device_t dev)
275 struct coretemp_softc *sc = device_get_softc(dev);
277 sensordev_deinstall(&sc->sc_sensordev);
278 sensor_task_unregister(sc);
280 lwkt_synchronize_ipiqs("coretemp");
286 coretemp_ipifunc(void *xsc)
288 struct coretemp_softc *sc = xsc;
290 sc->sc_msr = rdmsr(MSR_THERM_STATUS);
292 sc->sc_flags &= ~CORETEMP_FLAG_PENDING;
296 coretemp_get_temp(device_t dev)
300 struct coretemp_softc *sc = device_get_softc(dev);
306 * Send IPI to the specific CPU to read the correct
307 * temperature. If the IPI does not complete yet,
308 * i.e. CORETEMP_FLAG_PENDING is set, return -1.
310 if (ncpus > 1 && cpu != mycpuid) {
311 if ((sc->sc_flags & CORETEMP_FLAG_INITED) == 0) {
312 /* The first time we are called */
313 KASSERT((sc->sc_flags & CORETEMP_FLAG_PENDING) == 0,
314 ("has pending bit set"));
315 sc->sc_flags |= CORETEMP_FLAG_INITED |
316 CORETEMP_FLAG_PENDING;
318 lwkt_send_ipiq_passive(sc->sc_gd, coretemp_ipifunc, sc);
321 if (sc->sc_flags & CORETEMP_FLAG_PENDING) {
322 /* IPI does not complete yet */
325 sc->sc_flags |= CORETEMP_FLAG_PENDING;
329 msr = rdmsr(MSR_THERM_STATUS);
333 * Check for Thermal Status and Thermal Status Log.
335 if ((msr & 0x3) == 0x3)
336 device_printf(dev, "PROCHOT asserted\n");
339 * Bit 31 contains "Reading valid"
341 if (((msr >> 31) & 0x1) == 1) {
343 * Starting on bit 16 and ending on bit 22.
345 temp = sc->sc_tjmax - ((msr >> 16) & 0x7f);
350 * Check for Critical Temperature Status and Critical
352 * It doesn't really matter if the current temperature is
353 * invalid because the "Critical Temperature Log" bit will
354 * tell us if the Critical Temperature has been reached in
355 * past. It's not directly related to the current temperature.
357 * If we reach a critical level, allow devctl(4) to catch this
358 * and shutdown the system.
360 if (((msr >> 4) & 0x3) == 0x3) {
361 device_printf(dev, "critical temperature detected, "
362 "suggest system shutdown\n");
363 ksnprintf(stemp, sizeof(stemp), "%d", temp);
364 devctl_notify("coretemp", "Thermal", stemp, "notify=0xcc");
367 if (sc->sc_flags & CORETEMP_FLAG_PENDING) {
369 lwkt_send_ipiq_passive(sc->sc_gd, coretemp_ipifunc, sc);
376 coretemp_refresh(void *arg)
378 struct coretemp_softc *sc = arg;
379 device_t dev = sc->sc_dev;
380 struct ksensor *s = &sc->sc_sensor;
383 temp = coretemp_get_temp(dev);
386 /* No updates; keep the previous value */
387 } else if (temp == -1) {
388 s->flags |= SENSOR_FINVALID;
391 s->flags &= ~SENSOR_FINVALID;
392 s->value = temp * 1000000 + 273150000;