2 * Copyright (c) 1991 The Regents of the University of California.
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6 * modification, are permitted provided that the following conditions
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15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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29 * from: @(#)fdreg.h 7.1 (Berkeley) 5/9/91
30 * $FreeBSD: src/sys/isa/fdreg.h,v 1.13 2000/01/06 07:13:54 imp Exp $
31 * $DragonFly: src/sys/dev/disk/fd/fdreg.h,v 1.3 2003/08/07 21:16:52 dillon Exp $
35 * AT floppy controller registers and bitfields
38 /* uses NEC765 controller */
42 #define FDOUT 2 /* Digital Output Register (W) */
43 #define FDO_FDSEL 0x03 /* floppy device select */
44 #define FDO_FRST 0x04 /* floppy controller reset */
45 #define FDO_FDMAEN 0x08 /* enable floppy DMA and Interrupt */
46 #define FDO_MOEN0 0x10 /* motor enable drive 0 */
47 #define FDO_MOEN1 0x20 /* motor enable drive 1 */
48 #define FDO_MOEN2 0x40 /* motor enable drive 2 */
49 #define FDO_MOEN3 0x80 /* motor enable drive 3 */
51 #define FDSTS 4 /* NEC 765 Main Status Register (R) */
52 #define FDDATA 5 /* NEC 765 Data Register (R/W) */
53 #define FDCTL 7 /* Control Register (W) */
56 # define FDC_500KBPS 0x00 /* 500KBPS MFM drive transfer rate */
57 # define FDC_300KBPS 0x01 /* 300KBPS MFM drive transfer rate */
58 # define FDC_250KBPS 0x02 /* 250KBPS MFM drive transfer rate */
59 # define FDC_125KBPS 0x03 /* 125KBPS FM drive transfer rate */
60 /* for some controllers 1MPBS instead */
61 #endif /* FDC_500KBPS */
64 * this is the secret PIO data port (offset from base)
66 #define FDC_YE_DATAPORT 6
68 #define FDIN 7 /* Digital Input Register (R) */
69 #define FDI_DCHG 0x80 /* diskette has been changed */
70 /* requires drive and motor being selected */
71 /* is cleared by any step pulse to drive */