2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * This code is derived from software contributed to The DragonFly Project
7 * by Matthew Dillon <dillon@backplane.com>
9 * This code is derived from software contributed to Berkeley by
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in
20 * the documentation and/or other materials provided with the
22 * 3. Neither the name of The DragonFly Project nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific, prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * $DragonFly: src/sys/platform/pc32/icu/icu_abi.c,v 1.14 2007/07/07 12:13:47 sephe Exp $
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/machintr.h>
46 #include <sys/interrupt.h>
49 #include <machine/segments.h>
50 #include <machine/md_var.h>
51 #include <machine/intr_machdep.h>
52 #include <machine/globaldata.h>
53 #include <machine/smp.h>
55 #include <sys/thread2.h>
57 #include <machine_base/icu/elcr_var.h>
59 #include <machine_base/icu/icu.h>
60 #include <machine_base/icu/icu_ipl.h>
61 #include <machine_base/apic/ioapic.h>
64 IDTVEC(icu_intr0), IDTVEC(icu_intr1),
65 IDTVEC(icu_intr2), IDTVEC(icu_intr3),
66 IDTVEC(icu_intr4), IDTVEC(icu_intr5),
67 IDTVEC(icu_intr6), IDTVEC(icu_intr7),
68 IDTVEC(icu_intr8), IDTVEC(icu_intr9),
69 IDTVEC(icu_intr10), IDTVEC(icu_intr11),
70 IDTVEC(icu_intr12), IDTVEC(icu_intr13),
71 IDTVEC(icu_intr14), IDTVEC(icu_intr15);
73 static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
74 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1),
75 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3),
76 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5),
77 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7),
78 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9),
79 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11),
80 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13),
81 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15)
84 static struct icu_irqmap {
85 int im_type; /* ICU_IMT_ */
86 enum intr_trigger im_trig;
87 } icu_irqmaps[IDT_HWI_VECTORS];
89 #define ICU_IMT_UNUSED 0 /* KEEP THIS */
90 #define ICU_IMT_RESERVED 1
91 #define ICU_IMT_LINE 2
92 #define ICU_IMT_SYSCALL 3
94 extern void ICU_INTREN(int);
95 extern void ICU_INTRDIS(int);
97 extern int imcr_present;
99 static void icu_abi_intr_setup(int, int);
100 static void icu_abi_intr_teardown(int);
101 static void icu_abi_intr_config(int, enum intr_trigger, enum intr_polarity);
102 static int icu_abi_intr_cpuid(int);
104 static void icu_abi_finalize(void);
105 static void icu_abi_cleanup(void);
106 static void icu_abi_setdefault(void);
107 static void icu_abi_stabilize(void);
108 static void icu_abi_initmap(void);
110 struct machintr_abi MachIntrABI_ICU = {
113 .intr_disable = ICU_INTRDIS,
114 .intr_enable = ICU_INTREN,
115 .intr_setup = icu_abi_intr_setup,
116 .intr_teardown = icu_abi_intr_teardown,
117 .intr_config = icu_abi_intr_config,
118 .intr_cpuid = icu_abi_intr_cpuid,
120 .finalize = icu_abi_finalize,
121 .cleanup = icu_abi_cleanup,
122 .setdefault = icu_abi_setdefault,
123 .stabilize = icu_abi_stabilize,
124 .initmap = icu_abi_initmap
128 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
132 * Called before interrupts are physically enabled
135 icu_abi_stabilize(void)
139 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
140 machintr_intr_disable(intr);
141 machintr_intr_enable(ICU_IRQ_SLAVE);
145 * Called after interrupts physically enabled but before the
146 * critical section is released.
149 icu_abi_cleanup(void)
151 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
155 * Called after stablize and cleanup; critical section is not
156 * held and interrupts are not physically disabled.
159 icu_abi_finalize(void)
161 KKASSERT(MachIntrABI.type == MACHINTR_ICU);
162 KKASSERT(!ioapic_enable);
165 * If an IMCR is present, programming bit 0 disconnects the 8259
166 * from the BSP. The 8259 may still be connected to LINT0 on the
169 * If we are running SMP the LAPIC is active, try to use virtual
170 * wire mode so we can use other interrupt sources within the LAPIC
171 * in addition to the 8259.
180 icu_abi_intr_setup(int intr, int flags __unused)
184 KKASSERT(intr >= 0 && intr < ICU_HWI_VECTORS && intr != ICU_IRQ_SLAVE);
189 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
190 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
191 machintr_intr_enable(intr);
197 icu_abi_intr_teardown(int intr)
201 KKASSERT(intr >= 0 && intr < ICU_HWI_VECTORS && intr != ICU_IRQ_SLAVE);
206 machintr_intr_disable(intr);
207 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
208 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
214 icu_abi_setdefault(void)
218 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
219 if (intr == ICU_IRQ_SLAVE)
221 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
222 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
227 icu_abi_initmap(void)
231 for (i = 0; i < ICU_HWI_VECTORS; ++i)
232 icu_irqmaps[i].im_type = ICU_IMT_LINE;
233 icu_irqmaps[ICU_IRQ_SLAVE].im_type = ICU_IMT_RESERVED;
236 for (i = 0; i < ICU_HWI_VECTORS; ++i)
237 icu_irqmaps[i].im_trig = elcr_read_trigger(i);
240 * NOTE: Trigger mode does not matter at all
242 for (i = 0; i < ICU_HWI_VECTORS; ++i)
243 icu_irqmaps[i].im_trig = INTR_TRIGGER_EDGE;
245 icu_irqmaps[IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type = ICU_IMT_SYSCALL;
249 icu_abi_intr_config(int irq, enum intr_trigger trig,
250 enum intr_polarity pola __unused)
252 struct icu_irqmap *map;
254 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
256 KKASSERT(irq >= 0 && irq < IDT_HWI_VECTORS);
257 map = &icu_irqmaps[irq];
259 KKASSERT(map->im_type == ICU_IMT_LINE);
261 /* TODO: Check whether it is configured or not */
263 if (trig == map->im_trig)
267 kprintf("ICU: irq %d, %s -> %s\n", irq,
268 intr_str_trigger(map->im_trig),
269 intr_str_trigger(trig));
275 kprintf("ICU: no ELCR, skip irq %d config\n", irq);
278 elcr_write_trigger(irq, map->im_trig);
282 icu_abi_intr_cpuid(int irq __unused)