1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
36 #include "basic-block.h"
42 #include "protector.h"
44 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
45 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(x, y) 2
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx *reg_last_reload_reg;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static char *reg_has_output_reload;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload;
99 /* Element N is the constant value to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a constant.
101 find_reloads looks at this in order to replace pseudo reg N
102 with the constant it stands for. */
103 rtx *reg_equiv_constant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
112 This is used when the address is not valid as a memory address
113 (because its displacement is too big for the machine.) */
114 rtx *reg_equiv_address;
116 /* Element N is the memory slot to which pseudo reg N is equivalent,
117 or zero if pseudo reg N is not equivalent to a memory slot. */
120 /* Widest width in which each pseudo reg is referred to (via subreg). */
121 static int *reg_max_ref_width;
123 /* Element N is the list of insns that initialized reg N from its equivalent
124 constant or memory slot. */
125 static rtx *reg_equiv_init;
127 /* Vector to remember old contents of reg_renumber before spilling. */
128 static short *reg_old_renumber;
130 /* During reload_as_needed, element N contains the last pseudo regno reloaded
131 into hard register N. If that pseudo reg occupied more than one register,
132 reg_reloaded_contents points to that pseudo for each spill register in
133 use; all of these must remain set for an inheritance to occur. */
134 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
136 /* During reload_as_needed, element N contains the insn for which
137 hard register N was last used. Its contents are significant only
138 when reg_reloaded_valid is set for this register. */
139 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
141 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
142 static HARD_REG_SET reg_reloaded_valid;
143 /* Indicate if the register was dead at the end of the reload.
144 This is only valid if reg_reloaded_contents is set and valid. */
145 static HARD_REG_SET reg_reloaded_dead;
147 /* Number of spill-regs so far; number of valid elements of spill_regs. */
150 /* In parallel with spill_regs, contains REG rtx's for those regs.
151 Holds the last rtx used for any given reg, or 0 if it has never
152 been used for spilling yet. This rtx is reused, provided it has
154 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
156 /* In parallel with spill_regs, contains nonzero for a spill reg
157 that was stored after the last time it was used.
158 The precise value is the insn generated to do the store. */
159 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
161 /* This is the register that was stored with spill_reg_store. This is a
162 copy of reload_out / reload_out_reg when the value was stored; if
163 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
164 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
166 /* This table is the inverse mapping of spill_regs:
167 indexed by hard reg number,
168 it contains the position of that reg in spill_regs,
169 or -1 for something that is not in spill_regs.
171 ?!? This is no longer accurate. */
172 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
174 /* This reg set indicates registers that can't be used as spill registers for
175 the currently processed insn. These are the hard registers which are live
176 during the insn, but not allocated to pseudos, as well as fixed
178 static HARD_REG_SET bad_spill_regs;
180 /* These are the hard registers that can't be used as spill register for any
181 insn. This includes registers used for user variables and registers that
182 we can't eliminate. A register that appears in this set also can't be used
183 to retry register allocation. */
184 static HARD_REG_SET bad_spill_regs_global;
186 /* Describes order of use of registers for reloading
187 of spilled pseudo-registers. `n_spills' is the number of
188 elements that are actually valid; new ones are added at the end.
190 Both spill_regs and spill_reg_order are used on two occasions:
191 once during find_reload_regs, where they keep track of the spill registers
192 for a single insn, but also during reload_as_needed where they show all
193 the registers ever used by reload. For the latter case, the information
194 is calculated during finish_spills. */
195 static short spill_regs[FIRST_PSEUDO_REGISTER];
197 /* This vector of reg sets indicates, for each pseudo, which hard registers
198 may not be used for retrying global allocation because the register was
199 formerly spilled from one of them. If we allowed reallocating a pseudo to
200 a register that it was already allocated to, reload might not
202 static HARD_REG_SET *pseudo_previous_regs;
204 /* This vector of reg sets indicates, for each pseudo, which hard
205 registers may not be used for retrying global allocation because they
206 are used as spill registers during one of the insns in which the
208 static HARD_REG_SET *pseudo_forbidden_regs;
210 /* All hard regs that have been used as spill registers for any insn are
211 marked in this set. */
212 static HARD_REG_SET used_spill_regs;
214 /* Index of last register assigned as a spill register. We allocate in
215 a round-robin fashion. */
216 static int last_spill_reg;
218 /* Describes order of preference for putting regs into spill_regs.
219 Contains the numbers of all the hard regs, in order most preferred first.
220 This order is different for each function.
221 It is set up by order_regs_for_reload.
222 Empty elements at the end contain -1. */
223 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
225 /* Nonzero if indirect addressing is supported on the machine; this means
226 that spilling (REG n) does not require reloading it into a register in
227 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
228 value indicates the level of indirect addressing supported, e.g., two
229 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
231 static char spill_indirect_levels;
233 /* Nonzero if indirect addressing is supported when the innermost MEM is
234 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
235 which these are valid is the same as spill_indirect_levels, above. */
236 char indirect_symref_ok;
238 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
239 char double_reg_address_ok;
241 /* Record the stack slot for each spilled hard register. */
242 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
244 /* Width allocated so far for that stack slot. */
245 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
247 /* Record which pseudos needed to be spilled. */
248 static regset spilled_pseudos;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory used while processing one insn. */
279 char *reload_firstobj;
281 #define obstack_chunk_alloc xmalloc
282 #define obstack_chunk_free free
284 /* List of labels that must never be deleted. */
285 extern rtx forced_labels;
287 /* List of insn_chain instructions, one for every insn that reload needs to
289 struct insn_chain *reload_insn_chain;
292 extern tree current_function_decl;
294 extern union tree_node *current_function_decl;
297 /* List of all insns needing reloads. */
298 static struct insn_chain *insns_need_reload;
300 /* This structure is used to record information about register eliminations.
301 Each array entry describes one possible way of eliminating a register
302 in favor of another. If there is more than one way of eliminating a
303 particular register, the most preferred should be specified first. */
307 int from; /* Register number to be eliminated. */
308 int to; /* Register number used as replacement. */
309 int initial_offset; /* Initial difference between values. */
310 int can_eliminate; /* Non-zero if this elimination can be done. */
311 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
312 insns made by reload. */
313 int offset; /* Current offset between the two regs. */
314 int previous_offset; /* Offset at end of previous insn. */
315 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
316 rtx from_rtx; /* REG rtx for the register to be eliminated.
317 We cannot simply compare the number since
318 we might then spuriously replace a hard
319 register corresponding to a pseudo
320 assigned to the reg to be eliminated. */
321 rtx to_rtx; /* REG rtx for the replacement. */
324 static struct elim_table * reg_eliminate = 0;
326 /* This is an intermediate structure to initialize the table. It has
327 exactly the members provided by ELIMINABLE_REGS. */
328 static struct elim_table_1
332 } reg_eliminate_1[] =
334 /* If a set of eliminable registers was specified, define the table from it.
335 Otherwise, default to the normal case of the frame pointer being
336 replaced by the stack pointer. */
338 #ifdef ELIMINABLE_REGS
341 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
344 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
346 /* Record the number of pending eliminations that have an offset not equal
347 to their initial offset. If non-zero, we use a new copy of each
348 replacement result in any insns encountered. */
349 int num_not_at_initial_offset;
351 /* Count the number of registers that we may be able to eliminate. */
352 static int num_eliminable;
353 /* And the number of registers that are equivalent to a constant that
354 can be eliminated to frame_pointer / arg_pointer + constant. */
355 static int num_eliminable_invariants;
357 /* For each label, we record the offset of each elimination. If we reach
358 a label by more than one path and an offset differs, we cannot do the
359 elimination. This information is indexed by the number of the label.
360 The first table is an array of flags that records whether we have yet
361 encountered a label and the second table is an array of arrays, one
362 entry in the latter array for each elimination. */
364 static char *offsets_known_at;
365 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
367 /* Number of labels in the current function. */
369 static int num_labels;
371 struct hard_reg_n_uses
377 static void maybe_fix_stack_asms PROTO((void));
378 static void calculate_needs_all_insns PROTO((int));
379 static void calculate_needs PROTO((struct insn_chain *));
380 static void find_reload_regs PROTO((struct insn_chain *chain,
382 static void find_tworeg_group PROTO((struct insn_chain *, int,
384 static void find_group PROTO((struct insn_chain *, int,
386 static int possible_group_p PROTO((struct insn_chain *, int));
387 static void count_possible_groups PROTO((struct insn_chain *, int));
388 static int modes_equiv_for_class_p PROTO((enum machine_mode,
391 static void delete_caller_save_insns PROTO((void));
393 static void spill_failure PROTO((rtx));
394 static void new_spill_reg PROTO((struct insn_chain *, int, int,
396 static void maybe_mark_pseudo_spilled PROTO((int));
397 static void delete_dead_insn PROTO((rtx));
398 static void alter_reg PROTO((int, int));
399 static void set_label_offsets PROTO((rtx, rtx, int));
400 static int eliminate_regs_in_insn PROTO((rtx, int));
401 static void update_eliminable_offsets PROTO((void));
402 static void mark_not_eliminable PROTO((rtx, rtx));
403 static void set_initial_elim_offsets PROTO((void));
404 static void verify_initial_elim_offsets PROTO((void));
405 static void set_initial_label_offsets PROTO((void));
406 static void set_offsets_for_label PROTO((rtx));
407 static void init_elim_table PROTO((void));
408 static void update_eliminables PROTO((HARD_REG_SET *));
409 static void spill_hard_reg PROTO((int, FILE *, int));
410 static int finish_spills PROTO((int, FILE *));
411 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
412 static void scan_paradoxical_subregs PROTO((rtx));
413 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
414 static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
415 static void order_regs_for_reload PROTO((struct insn_chain *));
416 static void reload_as_needed PROTO((int));
417 static void forget_old_reloads_1 PROTO((rtx, rtx));
418 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
419 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
421 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
423 static int reload_reg_free_p PROTO((int, int, enum reload_type));
424 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int, int));
425 static int free_for_value_p PROTO((int, enum machine_mode, int,
426 enum reload_type, rtx, rtx,
428 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
429 static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
431 static int conflicts_with_override PROTO((rtx));
432 static void choose_reload_regs PROTO((struct insn_chain *));
433 static void merge_assigned_reloads PROTO((rtx));
434 static void emit_reload_insns PROTO((struct insn_chain *));
435 static void delete_output_reload PROTO((rtx, int, int));
436 static void delete_address_reloads PROTO((rtx, rtx));
437 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
438 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
439 static int constraint_accepts_reg_p PROTO((const char *, rtx));
440 static void reload_cse_regs_1 PROTO((rtx));
441 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
442 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
443 static void reload_cse_invalidate_mem PROTO((rtx));
444 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
445 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
446 static int reload_cse_noop_set_p PROTO((rtx, rtx));
447 static int reload_cse_simplify_set PROTO((rtx, rtx));
448 static int reload_cse_simplify_operands PROTO((rtx));
449 static void reload_cse_check_clobber PROTO((rtx, rtx));
450 static void reload_cse_record_set PROTO((rtx, rtx));
451 static void reload_combine PROTO((void));
452 static void reload_combine_note_use PROTO((rtx *, rtx));
453 static void reload_combine_note_store PROTO((rtx, rtx));
454 static void reload_cse_move2add PROTO((rtx));
455 static void move2add_note_store PROTO((rtx, rtx));
457 static void add_auto_inc_notes PROTO((rtx, rtx));
460 /* Initialize the reload pass once per compilation. */
467 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
468 Set spill_indirect_levels to the number of levels such addressing is
469 permitted, zero if it is not permitted at all. */
472 = gen_rtx_MEM (Pmode,
474 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
476 spill_indirect_levels = 0;
478 while (memory_address_p (QImode, tem))
480 spill_indirect_levels++;
481 tem = gen_rtx_MEM (Pmode, tem);
484 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
486 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
487 indirect_symref_ok = memory_address_p (QImode, tem);
489 /* See if reg+reg is a valid (and offsettable) address. */
491 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
493 tem = gen_rtx_PLUS (Pmode,
494 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
495 gen_rtx_REG (Pmode, i));
496 /* This way, we make sure that reg+reg is an offsettable address. */
497 tem = plus_constant (tem, 4);
499 if (memory_address_p (QImode, tem))
501 double_reg_address_ok = 1;
506 /* Initialize obstack for our rtl allocation. */
507 gcc_obstack_init (&reload_obstack);
508 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
511 /* List of insn chains that are currently unused. */
512 static struct insn_chain *unused_insn_chains = 0;
514 /* Allocate an empty insn_chain structure. */
518 struct insn_chain *c;
520 if (unused_insn_chains == 0)
522 c = (struct insn_chain *)
523 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
524 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
525 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
529 c = unused_insn_chains;
530 unused_insn_chains = c->next;
532 c->is_caller_save_insn = 0;
533 c->need_operand_change = 0;
539 /* Small utility function to set all regs in hard reg set TO which are
540 allocated to pseudos in regset FROM. */
542 compute_use_by_pseudos (to, from)
547 EXECUTE_IF_SET_IN_REG_SET
548 (from, FIRST_PSEUDO_REGISTER, regno,
550 int r = reg_renumber[regno];
554 /* reload_combine uses the information from
555 BASIC_BLOCK->global_live_at_start, which might still
556 contain registers that have not actually been allocated
557 since they have an equivalence. */
558 if (! reload_completed)
563 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
565 SET_HARD_REG_BIT (*to, r + nregs);
570 /* Global variables used by reload and its subroutines. */
572 /* Set during calculate_needs if an insn needs register elimination. */
573 static int something_needs_elimination;
574 /* Set during calculate_needs if an insn needs an operand changed. */
575 int something_needs_operands_changed;
577 /* Nonzero means we couldn't get enough spill regs. */
580 /* Main entry point for the reload pass.
582 FIRST is the first insn of the function being compiled.
584 GLOBAL nonzero means we were called from global_alloc
585 and should attempt to reallocate any pseudoregs that we
586 displace from hard regs we will use for reloads.
587 If GLOBAL is zero, we do not have enough information to do that,
588 so any pseudo reg that is spilled must go to the stack.
590 DUMPFILE is the global-reg debugging dump file stream, or 0.
591 If it is nonzero, messages are written to it to describe
592 which registers are seized as reload regs, which pseudo regs
593 are spilled from them, and where the pseudo regs are reallocated to.
595 Return value is nonzero if reload failed
596 and we must not do any more for this function. */
599 reload (first, global, dumpfile)
606 register struct elim_table *ep;
608 /* The two pointers used to track the true location of the memory used
609 for label offsets. */
610 char *real_known_ptr = NULL_PTR;
611 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
613 /* Make sure even insns with volatile mem refs are recognizable. */
618 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
620 /* Make sure that the last insn in the chain
621 is not something that needs reloading. */
622 emit_note (NULL_PTR, NOTE_INSN_DELETED);
624 /* Enable find_equiv_reg to distinguish insns made by reload. */
625 reload_first_uid = get_max_uid ();
627 #ifdef SECONDARY_MEMORY_NEEDED
628 /* Initialize the secondary memory table. */
629 clear_secondary_mem ();
632 /* We don't have a stack slot for any spill reg yet. */
633 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
634 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
636 /* Initialize the save area information for caller-save, in case some
640 /* Compute which hard registers are now in use
641 as homes for pseudo registers.
642 This is done here rather than (eg) in global_alloc
643 because this point is reached even if not optimizing. */
644 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
647 /* A function that receives a nonlocal goto must save all call-saved
649 if (current_function_has_nonlocal_label)
650 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
652 if (! call_used_regs[i] && ! fixed_regs[i])
653 regs_ever_live[i] = 1;
656 /* Find all the pseudo registers that didn't get hard regs
657 but do have known equivalent constants or memory slots.
658 These include parameters (known equivalent to parameter slots)
659 and cse'd or loop-moved constant memory addresses.
661 Record constant equivalents in reg_equiv_constant
662 so they will be substituted by find_reloads.
663 Record memory equivalents in reg_mem_equiv so they can
664 be substituted eventually by altering the REG-rtx's. */
666 reg_equiv_constant = (rtx *) xmalloc (max_regno * sizeof (rtx));
667 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
668 reg_equiv_memory_loc = (rtx *) xmalloc (max_regno * sizeof (rtx));
669 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
670 reg_equiv_mem = (rtx *) xmalloc (max_regno * sizeof (rtx));
671 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
672 reg_equiv_init = (rtx *) xmalloc (max_regno * sizeof (rtx));
673 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
674 reg_equiv_address = (rtx *) xmalloc (max_regno * sizeof (rtx));
675 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
676 reg_max_ref_width = (int *) xmalloc (max_regno * sizeof (int));
677 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
678 reg_old_renumber = (short *) xmalloc (max_regno * sizeof (short));
679 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
680 pseudo_forbidden_regs
681 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
683 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
685 CLEAR_HARD_REG_SET (bad_spill_regs_global);
686 bzero ((char *) pseudo_previous_regs, max_regno * sizeof (HARD_REG_SET));
688 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
689 Also find all paradoxical subregs and find largest such for each pseudo.
690 On machines with small register classes, record hard registers that
691 are used for user variables. These can never be used for spills.
692 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
693 caller-saved registers must be marked live. */
695 num_eliminable_invariants = 0;
696 for (insn = first; insn; insn = NEXT_INSN (insn))
698 rtx set = single_set (insn);
700 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
701 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
702 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
703 if (! call_used_regs[i])
704 regs_ever_live[i] = 1;
706 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
708 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
710 #ifdef LEGITIMATE_PIC_OPERAND_P
711 && (! function_invariant_p (XEXP (note, 0))
713 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
717 rtx x = XEXP (note, 0);
718 i = REGNO (SET_DEST (set));
719 if (i > LAST_VIRTUAL_REGISTER)
721 if (GET_CODE (x) == MEM)
723 /* If the operand is a PLUS, the MEM may be shared,
724 so make sure we have an unshared copy here. */
725 if (GET_CODE (XEXP (x, 0)) == PLUS)
728 reg_equiv_memory_loc[i] = x;
730 else if (function_invariant_p (x))
732 if (GET_CODE (x) == PLUS)
734 /* This is PLUS of frame pointer and a constant,
735 and might be shared. Unshare it. */
736 reg_equiv_constant[i] = copy_rtx (x);
737 num_eliminable_invariants++;
739 else if (x == frame_pointer_rtx
740 || x == arg_pointer_rtx)
742 reg_equiv_constant[i] = x;
743 num_eliminable_invariants++;
745 else if (LEGITIMATE_CONSTANT_P (x))
746 reg_equiv_constant[i] = x;
748 reg_equiv_memory_loc[i]
749 = force_const_mem (GET_MODE (SET_DEST (set)), x);
754 /* If this register is being made equivalent to a MEM
755 and the MEM is not SET_SRC, the equivalencing insn
756 is one with the MEM as a SET_DEST and it occurs later.
757 So don't mark this insn now. */
758 if (GET_CODE (x) != MEM
759 || rtx_equal_p (SET_SRC (set), x))
761 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
766 /* If this insn is setting a MEM from a register equivalent to it,
767 this is the equivalencing insn. */
768 else if (set && GET_CODE (SET_DEST (set)) == MEM
769 && GET_CODE (SET_SRC (set)) == REG
770 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
771 && rtx_equal_p (SET_DEST (set),
772 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
773 reg_equiv_init[REGNO (SET_SRC (set))]
774 = gen_rtx_INSN_LIST (VOIDmode, insn,
775 reg_equiv_init[REGNO (SET_SRC (set))]);
777 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
778 scan_paradoxical_subregs (PATTERN (insn));
783 num_labels = max_label_num () - get_first_label_num ();
785 /* Allocate the tables used to store offset information at labels. */
786 /* We used to use alloca here, but the size of what it would try to
787 allocate would occasionally cause it to exceed the stack limit and
788 cause a core dump. */
789 real_known_ptr = xmalloc (num_labels);
791 = (int (*)[NUM_ELIMINABLE_REGS])
792 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
794 offsets_known_at = real_known_ptr - get_first_label_num ();
796 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
798 /* Alter each pseudo-reg rtx to contain its hard reg number.
799 Assign stack slots to the pseudos that lack hard regs or equivalents.
800 Do not touch virtual registers. */
802 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
805 /* If we have some registers we think can be eliminated, scan all insns to
806 see if there is an insn that sets one of these registers to something
807 other than itself plus a constant. If so, the register cannot be
808 eliminated. Doing this scan here eliminates an extra pass through the
809 main reload loop in the most common case where register elimination
811 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
812 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
813 || GET_CODE (insn) == CALL_INSN)
814 note_stores (PATTERN (insn), mark_not_eliminable);
816 #ifndef REGISTER_CONSTRAINTS
817 /* If all the pseudo regs have hard regs,
818 except for those that are never referenced,
819 we know that no reloads are needed. */
820 /* But that is not true if there are register constraints, since
821 in that case some pseudos might be in the wrong kind of hard reg. */
823 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
824 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
827 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
829 free (real_known_ptr);
831 free (reg_equiv_constant);
832 free (reg_equiv_memory_loc);
833 free (reg_equiv_mem);
834 free (reg_equiv_init);
835 free (reg_equiv_address);
836 free (reg_max_ref_width);
837 free (reg_old_renumber);
838 free (pseudo_previous_regs);
839 free (pseudo_forbidden_regs);
844 maybe_fix_stack_asms ();
846 insns_need_reload = 0;
847 something_needs_elimination = 0;
849 /* Initialize to -1, which means take the first spill register. */
852 spilled_pseudos = ALLOCA_REG_SET ();
854 /* Spill any hard regs that we know we can't eliminate. */
855 CLEAR_HARD_REG_SET (used_spill_regs);
856 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
857 if (! ep->can_eliminate)
858 spill_hard_reg (ep->from, dumpfile, 1);
860 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
861 if (frame_pointer_needed)
862 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
864 finish_spills (global, dumpfile);
866 /* From now on, we may need to generate moves differently. We may also
867 allow modifications of insns which cause them to not be recognized.
868 Any such modifications will be cleaned up during reload itself. */
869 reload_in_progress = 1;
871 /* This loop scans the entire function each go-round
872 and repeats until one repetition spills no additional hard regs. */
875 int something_changed;
877 struct insn_chain *chain;
879 HOST_WIDE_INT starting_frame_size;
881 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
882 here because the stack size may be a part of the offset computation
883 for register elimination, and there might have been new stack slots
884 created in the last iteration of this loop. */
885 assign_stack_local (BLKmode, 0, 0);
887 starting_frame_size = get_frame_size ();
889 set_initial_elim_offsets ();
890 set_initial_label_offsets ();
892 /* For each pseudo register that has an equivalent location defined,
893 try to eliminate any eliminable registers (such as the frame pointer)
894 assuming initial offsets for the replacement register, which
897 If the resulting location is directly addressable, substitute
898 the MEM we just got directly for the old REG.
900 If it is not addressable but is a constant or the sum of a hard reg
901 and constant, it is probably not addressable because the constant is
902 out of range, in that case record the address; we will generate
903 hairy code to compute the address in a register each time it is
904 needed. Similarly if it is a hard register, but one that is not
905 valid as an address register.
907 If the location is not addressable, but does not have one of the
908 above forms, assign a stack slot. We have to do this to avoid the
909 potential of producing lots of reloads if, e.g., a location involves
910 a pseudo that didn't get a hard register and has an equivalent memory
911 location that also involves a pseudo that didn't get a hard register.
913 Perhaps at some point we will improve reload_when_needed handling
914 so this problem goes away. But that's very hairy. */
916 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
917 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
919 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
921 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
923 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
924 else if (CONSTANT_P (XEXP (x, 0))
925 || (GET_CODE (XEXP (x, 0)) == REG
926 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
927 || (GET_CODE (XEXP (x, 0)) == PLUS
928 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
929 && (REGNO (XEXP (XEXP (x, 0), 0))
930 < FIRST_PSEUDO_REGISTER)
931 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
932 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
935 /* Make a new stack slot. Then indicate that something
936 changed so we go back and recompute offsets for
937 eliminable registers because the allocation of memory
938 below might change some offset. reg_equiv_{mem,address}
939 will be set up for this pseudo on the next pass around
941 reg_equiv_memory_loc[i] = 0;
942 reg_equiv_init[i] = 0;
947 if (caller_save_needed)
950 /* If we allocated another stack slot, redo elimination bookkeeping. */
951 if (starting_frame_size != get_frame_size ())
954 if (caller_save_needed)
956 save_call_clobbered_regs ();
957 /* That might have allocated new insn_chain structures. */
958 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
961 calculate_needs_all_insns (global);
963 CLEAR_REG_SET (spilled_pseudos);
966 something_changed = 0;
968 /* If we allocated any new memory locations, make another pass
969 since it might have changed elimination offsets. */
970 if (starting_frame_size != get_frame_size ())
971 something_changed = 1;
974 HARD_REG_SET to_spill;
975 CLEAR_HARD_REG_SET (to_spill);
976 update_eliminables (&to_spill);
977 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
978 if (TEST_HARD_REG_BIT (to_spill, i))
980 spill_hard_reg (i, dumpfile, 1);
983 /* Regardless of the state of spills, if we previously had
984 a register that we thought we could eliminate, but no can
985 not eliminate, we must run another pass.
987 Consider pseudos which have an entry in reg_equiv_* which
988 reference an eliminable register. We must make another pass
989 to update reg_equiv_* so that we do not substitute in the
990 old value from when we thought the elimination could be
992 something_changed = 1;
996 CLEAR_HARD_REG_SET (used_spill_regs);
997 /* Try to satisfy the needs for each insn. */
998 for (chain = insns_need_reload; chain != 0;
999 chain = chain->next_need_reload)
1000 find_reload_regs (chain, dumpfile);
1005 if (insns_need_reload != 0 || did_spill)
1006 something_changed |= finish_spills (global, dumpfile);
1008 if (! something_changed)
1011 if (caller_save_needed)
1012 delete_caller_save_insns ();
1015 /* If global-alloc was run, notify it of any register eliminations we have
1018 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1019 if (ep->can_eliminate)
1020 mark_elimination (ep->from, ep->to);
1022 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1023 If that insn didn't set the register (i.e., it copied the register to
1024 memory), just delete that insn instead of the equivalencing insn plus
1025 anything now dead. If we call delete_dead_insn on that insn, we may
1026 delete the insn that actually sets the register if the register dies
1027 there and that is incorrect. */
1029 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1031 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1034 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1036 rtx equiv_insn = XEXP (list, 0);
1037 if (GET_CODE (equiv_insn) == NOTE)
1039 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1040 delete_dead_insn (equiv_insn);
1043 PUT_CODE (equiv_insn, NOTE);
1044 NOTE_SOURCE_FILE (equiv_insn) = 0;
1045 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1051 /* Use the reload registers where necessary
1052 by generating move instructions to move the must-be-register
1053 values into or out of the reload registers. */
1055 if (insns_need_reload != 0 || something_needs_elimination
1056 || something_needs_operands_changed)
1058 int old_frame_size = get_frame_size ();
1060 reload_as_needed (global);
1062 if (old_frame_size != get_frame_size ())
1066 verify_initial_elim_offsets ();
1069 /* If we were able to eliminate the frame pointer, show that it is no
1070 longer live at the start of any basic block. If it ls live by
1071 virtue of being in a pseudo, that pseudo will be marked live
1072 and hence the frame pointer will be known to be live via that
1075 if (! frame_pointer_needed)
1076 for (i = 0; i < n_basic_blocks; i++)
1077 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1078 HARD_FRAME_POINTER_REGNUM);
1080 /* Come here (with failure set nonzero) if we can't get enough spill regs
1081 and we decide not to abort about it. */
1084 reload_in_progress = 0;
1086 /* Now eliminate all pseudo regs by modifying them into
1087 their equivalent memory references.
1088 The REG-rtx's for the pseudos are modified in place,
1089 so all insns that used to refer to them now refer to memory.
1091 For a reg that has a reg_equiv_address, all those insns
1092 were changed by reloading so that no insns refer to it any longer;
1093 but the DECL_RTL of a variable decl may refer to it,
1094 and if so this causes the debugging info to mention the variable. */
1096 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1101 int is_readonly = 0;
1103 if (reg_equiv_memory_loc[i])
1105 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1106 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1107 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1110 if (reg_equiv_mem[i])
1111 addr = XEXP (reg_equiv_mem[i], 0);
1113 if (reg_equiv_address[i])
1114 addr = reg_equiv_address[i];
1118 if (reg_renumber[i] < 0)
1120 rtx reg = regno_reg_rtx[i];
1121 XEXP (reg, 0) = addr;
1122 REG_USERVAR_P (reg) = 0;
1123 RTX_UNCHANGING_P (reg) = is_readonly;
1124 MEM_IN_STRUCT_P (reg) = in_struct;
1125 MEM_SCALAR_P (reg) = is_scalar;
1126 /* We have no alias information about this newly created
1128 MEM_ALIAS_SET (reg) = 0;
1129 PUT_CODE (reg, MEM);
1131 else if (reg_equiv_mem[i])
1132 XEXP (reg_equiv_mem[i], 0) = addr;
1136 /* We must set reload_completed now since the cleanup_subreg_operands call
1137 below will re-recognize each insn and reload may have generated insns
1138 which are only valid during and after reload. */
1139 reload_completed = 1;
1141 /* Make a pass over all the insns and delete all USEs which we
1142 inserted only to tag a REG_EQUAL note on them. Remove all
1143 REG_DEAD and REG_UNUSED notes. Delete all CLOBBER insns and
1144 simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1145 REG_LIBCALL notes since they are no longer useful or accurate.
1146 Strip and regenerate REG_INC notes that may have been moved
1149 for (insn = first; insn; insn = NEXT_INSN (insn))
1150 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1154 if ((GET_CODE (PATTERN (insn)) == USE
1155 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1156 || GET_CODE (PATTERN (insn)) == CLOBBER)
1158 PUT_CODE (insn, NOTE);
1159 NOTE_SOURCE_FILE (insn) = 0;
1160 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1164 pnote = ®_NOTES (insn);
1167 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1168 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1169 || REG_NOTE_KIND (*pnote) == REG_INC
1170 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1171 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1172 *pnote = XEXP (*pnote, 1);
1174 pnote = &XEXP (*pnote, 1);
1178 add_auto_inc_notes (insn, PATTERN (insn));
1181 /* And simplify (subreg (reg)) if it appears as an operand. */
1182 cleanup_subreg_operands (insn);
1185 /* If we are doing stack checking, give a warning if this function's
1186 frame size is larger than we expect. */
1187 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1189 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1190 static int verbose_warned = 0;
1192 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1193 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1194 size += UNITS_PER_WORD;
1196 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1198 warning ("frame size too large for reliable stack checking");
1199 if (! verbose_warned)
1201 warning ("try reducing the number of local variables");
1207 /* Indicate that we no longer have known memory locations or constants. */
1208 if (reg_equiv_constant)
1209 free (reg_equiv_constant);
1210 reg_equiv_constant = 0;
1211 if (reg_equiv_memory_loc)
1212 free (reg_equiv_memory_loc);
1213 reg_equiv_memory_loc = 0;
1216 free (real_known_ptr);
1220 free (reg_equiv_mem);
1221 free (reg_equiv_init);
1222 free (reg_equiv_address);
1223 free (reg_max_ref_width);
1224 free (reg_old_renumber);
1225 free (pseudo_previous_regs);
1226 free (pseudo_forbidden_regs);
1228 FREE_REG_SET (spilled_pseudos);
1230 CLEAR_HARD_REG_SET (used_spill_regs);
1231 for (i = 0; i < n_spills; i++)
1232 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1234 /* Free all the insn_chain structures at once. */
1235 obstack_free (&reload_obstack, reload_startobj);
1236 unused_insn_chains = 0;
1241 /* Yet another special case. Unfortunately, reg-stack forces people to
1242 write incorrect clobbers in asm statements. These clobbers must not
1243 cause the register to appear in bad_spill_regs, otherwise we'll call
1244 fatal_insn later. We clear the corresponding regnos in the live
1245 register sets to avoid this.
1246 The whole thing is rather sick, I'm afraid. */
1248 maybe_fix_stack_asms ()
1251 char *constraints[MAX_RECOG_OPERANDS];
1252 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1253 struct insn_chain *chain;
1255 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1258 HARD_REG_SET clobbered, allowed;
1261 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1262 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1264 pat = PATTERN (chain->insn);
1265 if (GET_CODE (pat) != PARALLEL)
1268 CLEAR_HARD_REG_SET (clobbered);
1269 CLEAR_HARD_REG_SET (allowed);
1271 /* First, make a mask of all stack regs that are clobbered. */
1272 for (i = 0; i < XVECLEN (pat, 0); i++)
1274 rtx t = XVECEXP (pat, 0, i);
1275 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1276 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1279 /* Get the operand values and constraints out of the insn. */
1280 decode_asm_operands (pat, recog_operand, recog_operand_loc,
1281 constraints, operand_mode);
1283 /* For every operand, see what registers are allowed. */
1284 for (i = 0; i < noperands; i++)
1286 char *p = constraints[i];
1287 /* For every alternative, we compute the class of registers allowed
1288 for reloading in CLS, and merge its contents into the reg set
1290 int cls = (int) NO_REGS;
1296 if (c == '\0' || c == ',' || c == '#')
1298 /* End of one alternative - mark the regs in the current
1299 class, and reset the class. */
1300 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1305 } while (c != '\0' && c != ',');
1313 case '=': case '+': case '*': case '%': case '?': case '!':
1314 case '0': case '1': case '2': case '3': case '4': case 'm':
1315 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1316 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1317 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1319 #ifdef EXTRA_CONSTRAINT
1320 case 'Q': case 'R': case 'S': case 'T': case 'U':
1325 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1330 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1334 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1339 /* Those of the registers which are clobbered, but allowed by the
1340 constraints, must be usable as reload registers. So clear them
1341 out of the life information. */
1342 AND_HARD_REG_SET (allowed, clobbered);
1343 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1344 if (TEST_HARD_REG_BIT (allowed, i))
1346 CLEAR_REGNO_REG_SET (chain->live_before, i);
1347 CLEAR_REGNO_REG_SET (chain->live_after, i);
1355 /* Walk the chain of insns, and determine for each whether it needs reloads
1356 and/or eliminations. Build the corresponding insns_need_reload list, and
1357 set something_needs_elimination as appropriate. */
1359 calculate_needs_all_insns (global)
1362 struct insn_chain **pprev_reload = &insns_need_reload;
1363 struct insn_chain **pchain;
1365 something_needs_elimination = 0;
1367 for (pchain = &reload_insn_chain; *pchain != 0; pchain = &(*pchain)->next)
1370 struct insn_chain *chain;
1375 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1376 include REG_LABEL), we need to see what effects this has on the
1377 known offsets at labels. */
1379 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1380 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1381 && REG_NOTES (insn) != 0))
1382 set_label_offsets (insn, insn, 0);
1384 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1386 rtx old_body = PATTERN (insn);
1387 int old_code = INSN_CODE (insn);
1388 rtx old_notes = REG_NOTES (insn);
1389 int did_elimination = 0;
1390 int operands_changed = 0;
1391 rtx set = single_set (insn);
1393 /* Skip insns that only set an equivalence. */
1394 if (set && GET_CODE (SET_DEST (set)) == REG
1395 && reg_renumber[REGNO (SET_DEST (set))] < 0
1396 && reg_equiv_constant[REGNO (SET_DEST (set))])
1398 /* Must clear out the shortcuts, in case they were set last
1400 chain->need_elim = 0;
1401 chain->need_reload = 0;
1402 chain->need_operand_change = 0;
1406 /* If needed, eliminate any eliminable registers. */
1407 if (num_eliminable || num_eliminable_invariants)
1408 did_elimination = eliminate_regs_in_insn (insn, 0);
1410 /* Analyze the instruction. */
1411 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1412 global, spill_reg_order);
1414 /* If a no-op set needs more than one reload, this is likely
1415 to be something that needs input address reloads. We
1416 can't get rid of this cleanly later, and it is of no use
1417 anyway, so discard it now.
1418 We only do this when expensive_optimizations is enabled,
1419 since this complements reload inheritance / output
1420 reload deletion, and it can make debugging harder. */
1421 if (flag_expensive_optimizations && n_reloads > 1)
1423 rtx set = single_set (insn);
1425 && SET_SRC (set) == SET_DEST (set)
1426 && GET_CODE (SET_SRC (set)) == REG
1427 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1429 PUT_CODE (insn, NOTE);
1430 NOTE_SOURCE_FILE (insn) = 0;
1431 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1436 update_eliminable_offsets ();
1438 /* Remember for later shortcuts which insns had any reloads or
1439 register eliminations. */
1440 chain->need_elim = did_elimination;
1441 chain->need_reload = n_reloads > 0;
1442 chain->need_operand_change = operands_changed;
1444 /* Discard any register replacements done. */
1445 if (did_elimination)
1447 obstack_free (&reload_obstack, reload_firstobj);
1448 PATTERN (insn) = old_body;
1449 INSN_CODE (insn) = old_code;
1450 REG_NOTES (insn) = old_notes;
1451 something_needs_elimination = 1;
1454 something_needs_operands_changed |= operands_changed;
1458 *pprev_reload = chain;
1459 pprev_reload = &chain->next_need_reload;
1461 calculate_needs (chain);
1468 /* Compute the most additional registers needed by one instruction,
1469 given by CHAIN. Collect information separately for each class of regs.
1471 To compute the number of reload registers of each class needed for an
1472 insn, we must simulate what choose_reload_regs can do. We do this by
1473 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1474 reloads are used in both. The input part uses those reloads,
1475 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1476 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1477 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1479 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1480 which are live for the entire output portion, and the maximum of all the
1481 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1483 The total number of registers needed is the maximum of the
1484 inputs and outputs. */
1487 calculate_needs (chain)
1488 struct insn_chain *chain;
1492 /* Each `struct needs' corresponds to one RELOAD_... type. */
1496 struct needs output;
1498 struct needs other_addr;
1499 struct needs op_addr;
1500 struct needs op_addr_reload;
1501 struct needs in_addr[MAX_RECOG_OPERANDS];
1502 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1503 struct needs out_addr[MAX_RECOG_OPERANDS];
1504 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1507 bzero ((char *) chain->group_size, sizeof chain->group_size);
1508 for (i = 0; i < N_REG_CLASSES; i++)
1509 chain->group_mode[i] = VOIDmode;
1510 bzero ((char *) &insn_needs, sizeof insn_needs);
1512 /* Count each reload once in every class
1513 containing the reload's own class. */
1515 for (i = 0; i < n_reloads; i++)
1517 register enum reg_class *p;
1518 enum reg_class class = reload_reg_class[i];
1520 enum machine_mode mode;
1521 struct needs *this_needs;
1523 /* Don't count the dummy reloads, for which one of the
1524 regs mentioned in the insn can be used for reloading.
1525 Don't count optional reloads.
1526 Don't count reloads that got combined with others. */
1527 if (reload_reg_rtx[i] != 0
1528 || reload_optional[i] != 0
1529 || (reload_out[i] == 0 && reload_in[i] == 0
1530 && ! reload_secondary_p[i]))
1533 mode = reload_inmode[i];
1534 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1535 mode = reload_outmode[i];
1536 size = CLASS_MAX_NREGS (class, mode);
1538 /* Decide which time-of-use to count this reload for. */
1539 switch (reload_when_needed[i])
1542 this_needs = &insn_needs.other;
1544 case RELOAD_FOR_INPUT:
1545 this_needs = &insn_needs.input;
1547 case RELOAD_FOR_OUTPUT:
1548 this_needs = &insn_needs.output;
1550 case RELOAD_FOR_INSN:
1551 this_needs = &insn_needs.insn;
1553 case RELOAD_FOR_OTHER_ADDRESS:
1554 this_needs = &insn_needs.other_addr;
1556 case RELOAD_FOR_INPUT_ADDRESS:
1557 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1559 case RELOAD_FOR_INPADDR_ADDRESS:
1560 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1562 case RELOAD_FOR_OUTPUT_ADDRESS:
1563 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1565 case RELOAD_FOR_OUTADDR_ADDRESS:
1566 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1568 case RELOAD_FOR_OPERAND_ADDRESS:
1569 this_needs = &insn_needs.op_addr;
1571 case RELOAD_FOR_OPADDR_ADDR:
1572 this_needs = &insn_needs.op_addr_reload;
1580 enum machine_mode other_mode, allocate_mode;
1582 /* Count number of groups needed separately from
1583 number of individual regs needed. */
1584 this_needs->groups[(int) class]++;
1585 p = reg_class_superclasses[(int) class];
1586 while (*p != LIM_REG_CLASSES)
1587 this_needs->groups[(int) *p++]++;
1589 /* Record size and mode of a group of this class. */
1590 /* If more than one size group is needed,
1591 make all groups the largest needed size. */
1592 if (chain->group_size[(int) class] < size)
1594 other_mode = chain->group_mode[(int) class];
1595 allocate_mode = mode;
1597 chain->group_size[(int) class] = size;
1598 chain->group_mode[(int) class] = mode;
1603 allocate_mode = chain->group_mode[(int) class];
1606 /* Crash if two dissimilar machine modes both need
1607 groups of consecutive regs of the same class. */
1609 if (other_mode != VOIDmode && other_mode != allocate_mode
1610 && ! modes_equiv_for_class_p (allocate_mode,
1612 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1617 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) class] += 1;
1618 p = reg_class_superclasses[(int) class];
1619 while (*p != LIM_REG_CLASSES)
1620 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) *p++] += 1;
1626 /* All reloads have been counted for this insn;
1627 now merge the various times of use.
1628 This sets insn_needs, etc., to the maximum total number
1629 of registers needed at any point in this insn. */
1631 for (i = 0; i < N_REG_CLASSES; i++)
1633 int j, in_max, out_max;
1635 /* Compute normal and nongroup needs. */
1636 for (j = 0; j <= 1; j++)
1639 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1641 in_max = MAX (in_max,
1642 (insn_needs.in_addr[k].regs[j][i]
1643 + insn_needs.in_addr_addr[k].regs[j][i]));
1644 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1645 out_max = MAX (out_max,
1646 insn_needs.out_addr_addr[k].regs[j][i]);
1649 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1650 and operand addresses but not things used to reload
1651 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1652 don't conflict with things needed to reload inputs or
1655 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1656 insn_needs.op_addr_reload.regs[j][i]),
1659 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1661 insn_needs.input.regs[j][i]
1662 = MAX (insn_needs.input.regs[j][i]
1663 + insn_needs.op_addr.regs[j][i]
1664 + insn_needs.insn.regs[j][i],
1665 in_max + insn_needs.input.regs[j][i]);
1667 insn_needs.output.regs[j][i] += out_max;
1668 insn_needs.other.regs[j][i]
1669 += MAX (MAX (insn_needs.input.regs[j][i],
1670 insn_needs.output.regs[j][i]),
1671 insn_needs.other_addr.regs[j][i]);
1675 /* Now compute group needs. */
1676 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1678 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1679 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1680 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1681 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1684 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1685 insn_needs.op_addr_reload.groups[i]),
1687 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1689 insn_needs.input.groups[i]
1690 = MAX (insn_needs.input.groups[i]
1691 + insn_needs.op_addr.groups[i]
1692 + insn_needs.insn.groups[i],
1693 in_max + insn_needs.input.groups[i]);
1695 insn_needs.output.groups[i] += out_max;
1696 insn_needs.other.groups[i]
1697 += MAX (MAX (insn_needs.input.groups[i],
1698 insn_needs.output.groups[i]),
1699 insn_needs.other_addr.groups[i]);
1702 /* Record the needs for later. */
1703 chain->need = insn_needs.other;
1706 /* Find a group of exactly 2 registers.
1708 First try to fill out the group by spilling a single register which
1709 would allow completion of the group.
1711 Then try to create a new group from a pair of registers, neither of
1712 which are explicitly used.
1714 Then try to create a group from any pair of registers. */
1717 find_tworeg_group (chain, class, dumpfile)
1718 struct insn_chain *chain;
1723 /* First, look for a register that will complete a group. */
1724 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1728 j = potential_reload_regs[i];
1729 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1730 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1731 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1732 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1733 && HARD_REGNO_MODE_OK (other, chain->group_mode[class])
1734 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1735 /* We don't want one part of another group.
1736 We could get "two groups" that overlap! */
1737 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))
1738 || (j < FIRST_PSEUDO_REGISTER - 1
1739 && (other = j + 1, spill_reg_order[other] >= 0)
1740 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1741 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1742 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1743 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1744 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))))
1746 register enum reg_class *p;
1748 /* We have found one that will complete a group,
1749 so count off one group as provided. */
1750 chain->need.groups[class]--;
1751 p = reg_class_superclasses[class];
1752 while (*p != LIM_REG_CLASSES)
1754 if (chain->group_size [(int) *p] <= chain->group_size [class])
1755 chain->need.groups[(int) *p]--;
1759 /* Indicate both these regs are part of a group. */
1760 SET_HARD_REG_BIT (chain->counted_for_groups, j);
1761 SET_HARD_REG_BIT (chain->counted_for_groups, other);
1765 /* We can't complete a group, so start one. */
1766 if (i == FIRST_PSEUDO_REGISTER)
1767 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1770 j = potential_reload_regs[i];
1771 /* Verify that J+1 is a potential reload reg. */
1772 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1773 if (potential_reload_regs[k] == j + 1)
1775 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1776 && k < FIRST_PSEUDO_REGISTER
1777 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1778 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1779 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1780 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1781 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1)
1782 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1786 /* I should be the index in potential_reload_regs
1787 of the new reload reg we have found. */
1789 new_spill_reg (chain, i, class, 0, dumpfile);
1792 /* Find a group of more than 2 registers.
1793 Look for a sufficient sequence of unspilled registers, and spill them all
1797 find_group (chain, class, dumpfile)
1798 struct insn_chain *chain;
1804 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1806 int j = potential_reload_regs[i];
1809 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
1810 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]))
1813 /* Check each reg in the sequence. */
1814 for (k = 0; k < chain->group_size[class]; k++)
1815 if (! (spill_reg_order[j + k] < 0
1816 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1817 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1819 /* We got a full sequence, so spill them all. */
1820 if (k == chain->group_size[class])
1822 register enum reg_class *p;
1823 for (k = 0; k < chain->group_size[class]; k++)
1826 SET_HARD_REG_BIT (chain->counted_for_groups, j + k);
1827 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1828 if (potential_reload_regs[idx] == j + k)
1830 new_spill_reg (chain, idx, class, 0, dumpfile);
1833 /* We have found one that will complete a group,
1834 so count off one group as provided. */
1835 chain->need.groups[class]--;
1836 p = reg_class_superclasses[class];
1837 while (*p != LIM_REG_CLASSES)
1839 if (chain->group_size [(int) *p]
1840 <= chain->group_size [class])
1841 chain->need.groups[(int) *p]--;
1848 /* There are no groups left. */
1849 spill_failure (chain->insn);
1853 /* If pseudo REG conflicts with one of our reload registers, mark it as
1856 maybe_mark_pseudo_spilled (reg)
1860 int r = reg_renumber[reg];
1865 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1866 for (i = 0; i < n_spills; i++)
1867 if (r <= spill_regs[i] && r + nregs > spill_regs[i])
1869 SET_REGNO_REG_SET (spilled_pseudos, reg);
1874 /* Find more reload regs to satisfy the remaining need of an insn, which
1876 Do it by ascending class number, since otherwise a reg
1877 might be spilled for a big class and might fail to count
1878 for a smaller class even though it belongs to that class.
1880 Count spilled regs in `spills', and add entries to
1881 `spill_regs' and `spill_reg_order'.
1883 ??? Note there is a problem here.
1884 When there is a need for a group in a high-numbered class,
1885 and also need for non-group regs that come from a lower class,
1886 the non-group regs are chosen first. If there aren't many regs,
1887 they might leave no room for a group.
1889 This was happening on the 386. To fix it, we added the code
1890 that calls possible_group_p, so that the lower class won't
1891 break up the last possible group.
1893 Really fixing the problem would require changes above
1894 in counting the regs already spilled, and in choose_reload_regs.
1895 It might be hard to avoid introducing bugs there. */
1898 find_reload_regs (chain, dumpfile)
1899 struct insn_chain *chain;
1903 short *group_needs = chain->need.groups;
1904 short *simple_needs = chain->need.regs[0];
1905 short *nongroup_needs = chain->need.regs[1];
1908 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1910 /* Compute the order of preference for hard registers to spill.
1911 Store them by decreasing preference in potential_reload_regs. */
1913 order_regs_for_reload (chain);
1915 /* So far, no hard regs have been spilled. */
1917 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1918 spill_reg_order[i] = -1;
1920 CLEAR_HARD_REG_SET (chain->used_spill_regs);
1921 CLEAR_HARD_REG_SET (chain->counted_for_groups);
1922 CLEAR_HARD_REG_SET (chain->counted_for_nongroups);
1924 for (class = 0; class < N_REG_CLASSES; class++)
1926 /* First get the groups of registers.
1927 If we got single registers first, we might fragment
1929 while (group_needs[class] > 0)
1931 /* If any single spilled regs happen to form groups,
1932 count them now. Maybe we don't really need
1933 to spill another group. */
1934 count_possible_groups (chain, class);
1936 if (group_needs[class] <= 0)
1939 /* Groups of size 2, the only groups used on most machines,
1940 are treated specially. */
1941 if (chain->group_size[class] == 2)
1942 find_tworeg_group (chain, class, dumpfile);
1944 find_group (chain, class, dumpfile);
1949 /* Now similarly satisfy all need for single registers. */
1951 while (simple_needs[class] > 0 || nongroup_needs[class] > 0)
1953 /* If we spilled enough regs, but they weren't counted
1954 against the non-group need, see if we can count them now.
1955 If so, we can avoid some actual spilling. */
1956 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0)
1957 for (i = 0; i < n_spills; i++)
1959 int regno = spill_regs[i];
1960 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1961 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
1962 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)
1963 && nongroup_needs[class] > 0)
1965 register enum reg_class *p;
1967 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
1968 nongroup_needs[class]--;
1969 p = reg_class_superclasses[class];
1970 while (*p != LIM_REG_CLASSES)
1971 nongroup_needs[(int) *p++]--;
1975 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0)
1978 /* Consider the potential reload regs that aren't
1979 yet in use as reload regs, in order of preference.
1980 Find the most preferred one that's in this class. */
1982 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1984 int regno = potential_reload_regs[i];
1986 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1987 /* If this reg will not be available for groups,
1988 pick one that does not foreclose possible groups.
1989 This is a kludge, and not very general,
1990 but it should be sufficient to make the 386 work,
1991 and the problem should not occur on machines with
1993 && (nongroup_needs[class] == 0
1994 || possible_group_p (chain, regno)))
1998 /* If we couldn't get a register, try to get one even if we
1999 might foreclose possible groups. This may cause problems
2000 later, but that's better than aborting now, since it is
2001 possible that we will, in fact, be able to form the needed
2002 group even with this allocation. */
2004 if (i >= FIRST_PSEUDO_REGISTER
2005 && asm_noperands (chain->insn) < 0)
2006 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2007 if (potential_reload_regs[i] >= 0
2008 && TEST_HARD_REG_BIT (reg_class_contents[class],
2009 potential_reload_regs[i]))
2012 /* I should be the index in potential_reload_regs
2013 of the new reload reg we have found. */
2015 new_spill_reg (chain, i, class, 1, dumpfile);
2021 /* We know which hard regs to use, now mark the pseudos that live in them
2022 as needing to be kicked out. */
2023 EXECUTE_IF_SET_IN_REG_SET
2024 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
2026 maybe_mark_pseudo_spilled (i);
2028 EXECUTE_IF_SET_IN_REG_SET
2029 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
2031 maybe_mark_pseudo_spilled (i);
2034 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs);
2038 dump_needs (chain, dumpfile)
2039 struct insn_chain *chain;
2042 static char *reg_class_names[] = REG_CLASS_NAMES;
2044 struct needs *n = &chain->need;
2046 for (i = 0; i < N_REG_CLASSES; i++)
2048 if (n->regs[i][0] > 0)
2050 ";; Need %d reg%s of class %s.\n",
2051 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s",
2052 reg_class_names[i]);
2053 if (n->regs[i][1] > 0)
2055 ";; Need %d nongroup reg%s of class %s.\n",
2056 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s",
2057 reg_class_names[i]);
2058 if (n->groups[i] > 0)
2060 ";; Need %d group%s (%smode) of class %s.\n",
2061 n->groups[i], n->groups[i] == 1 ? "" : "s",
2062 mode_name[(int) chain->group_mode[i]],
2063 reg_class_names[i]);
2067 /* Delete all insns that were inserted by emit_caller_save_insns during
2070 delete_caller_save_insns ()
2072 struct insn_chain *c = reload_insn_chain;
2076 while (c != 0 && c->is_caller_save_insn)
2078 struct insn_chain *next = c->next;
2081 if (insn == BLOCK_HEAD (c->block))
2082 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
2083 if (insn == BLOCK_END (c->block))
2084 BLOCK_END (c->block) = PREV_INSN (insn);
2085 if (c == reload_insn_chain)
2086 reload_insn_chain = next;
2088 if (NEXT_INSN (insn) != 0)
2089 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2090 if (PREV_INSN (insn) != 0)
2091 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2094 next->prev = c->prev;
2096 c->prev->next = next;
2097 c->next = unused_insn_chains;
2098 unused_insn_chains = c;
2106 /* Nonzero if, after spilling reg REGNO for non-groups,
2107 it will still be possible to find a group if we still need one. */
2110 possible_group_p (chain, regno)
2111 struct insn_chain *chain;
2115 int class = (int) NO_REGS;
2117 for (i = 0; i < (int) N_REG_CLASSES; i++)
2118 if (chain->need.groups[i] > 0)
2124 if (class == (int) NO_REGS)
2127 /* Consider each pair of consecutive registers. */
2128 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2130 /* Ignore pairs that include reg REGNO. */
2131 if (i == regno || i + 1 == regno)
2134 /* Ignore pairs that are outside the class that needs the group.
2135 ??? Here we fail to handle the case where two different classes
2136 independently need groups. But this never happens with our
2137 current machine descriptions. */
2138 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2139 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2142 /* A pair of consecutive regs we can still spill does the trick. */
2143 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2144 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2145 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2148 /* A pair of one already spilled and one we can spill does it
2149 provided the one already spilled is not otherwise reserved. */
2150 if (spill_reg_order[i] < 0
2151 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2152 && spill_reg_order[i + 1] >= 0
2153 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1)
2154 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1))
2156 if (spill_reg_order[i + 1] < 0
2157 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2158 && spill_reg_order[i] >= 0
2159 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i)
2160 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i))
2167 /* Count any groups of CLASS that can be formed from the registers recently
2171 count_possible_groups (chain, class)
2172 struct insn_chain *chain;
2178 /* Now find all consecutive groups of spilled registers
2179 and mark each group off against the need for such groups.
2180 But don't count them against ordinary need, yet. */
2182 if (chain->group_size[class] == 0)
2185 CLEAR_HARD_REG_SET (new);
2187 /* Make a mask of all the regs that are spill regs in class I. */
2188 for (i = 0; i < n_spills; i++)
2190 int regno = spill_regs[i];
2192 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
2193 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
2194 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno))
2195 SET_HARD_REG_BIT (new, regno);
2198 /* Find each consecutive group of them. */
2199 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++)
2200 if (TEST_HARD_REG_BIT (new, i)
2201 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
2202 && HARD_REGNO_MODE_OK (i, chain->group_mode[class]))
2204 for (j = 1; j < chain->group_size[class]; j++)
2205 if (! TEST_HARD_REG_BIT (new, i + j))
2208 if (j == chain->group_size[class])
2210 /* We found a group. Mark it off against this class's need for
2211 groups, and against each superclass too. */
2212 register enum reg_class *p;
2214 chain->need.groups[class]--;
2215 p = reg_class_superclasses[class];
2216 while (*p != LIM_REG_CLASSES)
2218 if (chain->group_size [(int) *p] <= chain->group_size [class])
2219 chain->need.groups[(int) *p]--;
2223 /* Don't count these registers again. */
2224 for (j = 0; j < chain->group_size[class]; j++)
2225 SET_HARD_REG_BIT (chain->counted_for_groups, i + j);
2228 /* Skip to the last reg in this group. When i is incremented above,
2229 it will then point to the first reg of the next possible group. */
2234 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2235 another mode that needs to be reloaded for the same register class CLASS.
2236 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2237 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2239 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2240 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2241 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2242 causes unnecessary failures on machines requiring alignment of register
2243 groups when the two modes are different sizes, because the larger mode has
2244 more strict alignment rules than the smaller mode. */
2247 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2248 enum machine_mode allocate_mode, other_mode;
2249 enum reg_class class;
2252 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2254 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2255 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2256 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2262 /* Handle the failure to find a register to spill.
2263 INSN should be one of the insns which needed this particular spill reg. */
2266 spill_failure (insn)
2269 if (asm_noperands (PATTERN (insn)) >= 0)
2270 error_for_asm (insn, "`asm' needs too many reloads");
2272 fatal_insn ("Unable to find a register to spill.", insn);
2275 /* Add a new register to the tables of available spill-registers.
2276 CHAIN is the insn for which the register will be used; we decrease the
2278 I is the index of this register in potential_reload_regs.
2279 CLASS is the regclass whose need is being satisfied.
2280 NONGROUP is 0 if this register is part of a group.
2281 DUMPFILE is the same as the one that `reload' got. */
2284 new_spill_reg (chain, i, class, nongroup, dumpfile)
2285 struct insn_chain *chain;
2291 register enum reg_class *p;
2292 int regno = potential_reload_regs[i];
2294 if (i >= FIRST_PSEUDO_REGISTER)
2296 spill_failure (chain->insn);
2301 if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
2303 static char *reg_class_names[] = REG_CLASS_NAMES;
2305 if (asm_noperands (PATTERN (chain->insn)) < 0)
2307 /* The error message is still correct - we know only that it wasn't
2308 an asm statement that caused the problem, but one of the global
2309 registers declared by the users might have screwed us. */
2310 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2311 regno, reg_names[regno], reg_class_names[class]);
2312 error ("This may be due to a compiler bug or to impossible asm");
2313 error ("statements or clauses.");
2314 fatal_insn ("This is the instruction:", chain->insn);
2316 error_for_asm (chain->insn, "Invalid `asm' statement:");
2317 error_for_asm (chain->insn,
2318 "fixed or forbidden register %d (%s) was spilled for class %s.",
2319 regno, reg_names[regno], reg_class_names[class]);
2324 /* Make reg REGNO an additional reload reg. */
2326 potential_reload_regs[i] = -1;
2327 spill_regs[n_spills] = regno;
2328 spill_reg_order[regno] = n_spills;
2330 fprintf (dumpfile, "Spilling reg %d.\n", regno);
2331 SET_HARD_REG_BIT (chain->used_spill_regs, regno);
2333 /* Clear off the needs we just satisfied. */
2335 chain->need.regs[0][class]--;
2336 p = reg_class_superclasses[class];
2337 while (*p != LIM_REG_CLASSES)
2338 chain->need.regs[0][(int) *p++]--;
2340 if (nongroup && chain->need.regs[1][class] > 0)
2342 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
2343 chain->need.regs[1][class]--;
2344 p = reg_class_superclasses[class];
2345 while (*p != LIM_REG_CLASSES)
2346 chain->need.regs[1][(int) *p++]--;
2352 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2353 data that is dead in INSN. */
2356 delete_dead_insn (insn)
2359 rtx prev = prev_real_insn (insn);
2362 /* If the previous insn sets a register that dies in our insn, delete it
2364 if (prev && GET_CODE (PATTERN (prev)) == SET
2365 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2366 && reg_mentioned_p (prev_dest, PATTERN (insn))
2367 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2368 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2369 delete_dead_insn (prev);
2371 PUT_CODE (insn, NOTE);
2372 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2373 NOTE_SOURCE_FILE (insn) = 0;
2376 /* Modify the home of pseudo-reg I.
2377 The new home is present in reg_renumber[I].
2379 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2380 or it may be -1, meaning there is none or it is not relevant.
2381 This is used so that all pseudos spilled from a given hard reg
2382 can share one stack slot. */
2385 alter_reg (i, from_reg)
2389 /* When outputting an inline function, this can happen
2390 for a reg that isn't actually used. */
2391 if (regno_reg_rtx[i] == 0)
2394 /* If the reg got changed to a MEM at rtl-generation time,
2396 if (GET_CODE (regno_reg_rtx[i]) != REG)
2399 /* Modify the reg-rtx to contain the new hard reg
2400 number or else to contain its pseudo reg number. */
2401 REGNO (regno_reg_rtx[i])
2402 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2404 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2405 allocate a stack slot for it. */
2407 if (reg_renumber[i] < 0
2408 && REG_N_REFS (i) > 0
2409 && reg_equiv_constant[i] == 0
2410 && reg_equiv_memory_loc[i] == 0)
2413 int inherent_size = PSEUDO_REGNO_BYTES (i);
2414 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2417 /* Each pseudo reg has an inherent size which comes from its own mode,
2418 and a total size which provides room for paradoxical subregs
2419 which refer to the pseudo reg in wider modes.
2421 We can use a slot already allocated if it provides both
2422 enough inherent space and enough total space.
2423 Otherwise, we allocate a new slot, making sure that it has no less
2424 inherent space, and no less total space, then the previous slot. */
2427 /* No known place to spill from => no slot to reuse. */
2428 x = assign_stack_local_for_pseudo_reg (GET_MODE (regno_reg_rtx[i]), total_size,
2429 inherent_size == total_size ? 0 : -1);
2430 if (BYTES_BIG_ENDIAN)
2431 /* Cancel the big-endian correction done in assign_stack_local.
2432 Get the address of the beginning of the slot.
2433 This is so we can do a big-endian correction unconditionally
2435 adjust = inherent_size - total_size;
2437 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2439 /* Reuse a stack slot if possible. */
2440 else if (spill_stack_slot[from_reg] != 0
2441 && spill_stack_slot_width[from_reg] >= total_size
2442 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2444 x = spill_stack_slot[from_reg];
2445 /* Allocate a bigger slot. */
2448 /* Compute maximum size needed, both for inherent size
2449 and for total size. */
2450 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2452 if (spill_stack_slot[from_reg])
2454 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2456 mode = GET_MODE (spill_stack_slot[from_reg]);
2457 if (spill_stack_slot_width[from_reg] > total_size)
2458 total_size = spill_stack_slot_width[from_reg];
2460 /* Make a slot with that size. */
2461 x = assign_stack_local (mode, total_size,
2462 inherent_size == total_size ? 0 : -1);
2464 if (BYTES_BIG_ENDIAN)
2466 /* Cancel the big-endian correction done in assign_stack_local.
2467 Get the address of the beginning of the slot.
2468 This is so we can do a big-endian correction unconditionally
2470 adjust = GET_MODE_SIZE (mode) - total_size;
2472 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2475 plus_constant (XEXP (x, 0), adjust));
2477 spill_stack_slot[from_reg] = stack_slot;
2478 spill_stack_slot_width[from_reg] = total_size;
2481 /* On a big endian machine, the "address" of the slot
2482 is the address of the low part that fits its inherent mode. */
2483 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2484 adjust += (total_size - inherent_size);
2486 /* If we have any adjustment to make, or if the stack slot is the
2487 wrong mode, make a new stack slot. */
2488 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2490 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2491 plus_constant (XEXP (x, 0), adjust));
2493 /* If this was shared among registers, must ensure we never
2494 set it readonly since that can cause scheduling
2495 problems. Note we would only have in this adjustment
2496 case in any event, since the code above doesn't set it. */
2499 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2502 /* Save the stack slot for later. */
2503 reg_equiv_memory_loc[i] = x;
2507 /* Mark the slots in regs_ever_live for the hard regs
2508 used by pseudo-reg number REGNO. */
2511 mark_home_live (regno)
2514 register int i, lim;
2515 i = reg_renumber[regno];
2518 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2520 regs_ever_live[i++] = 1;
2523 /* This function handles the tracking of elimination offsets around branches.
2525 X is a piece of RTL being scanned.
2527 INSN is the insn that it came from, if any.
2529 INITIAL_P is non-zero if we are to set the offset to be the initial
2530 offset and zero if we are setting the offset of the label to be the
2534 set_label_offsets (x, insn, initial_p)
2539 enum rtx_code code = GET_CODE (x);
2542 struct elim_table *p;
2547 if (LABEL_REF_NONLOCAL_P (x))
2552 /* ... fall through ... */
2555 /* If we know nothing about this label, set the desired offsets. Note
2556 that this sets the offset at a label to be the offset before a label
2557 if we don't know anything about the label. This is not correct for
2558 the label after a BARRIER, but is the best guess we can make. If
2559 we guessed wrong, we will suppress an elimination that might have
2560 been possible had we been able to guess correctly. */
2562 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2564 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2565 offsets_at[CODE_LABEL_NUMBER (x)][i]
2566 = (initial_p ? reg_eliminate[i].initial_offset
2567 : reg_eliminate[i].offset);
2568 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2571 /* Otherwise, if this is the definition of a label and it is
2572 preceded by a BARRIER, set our offsets to the known offset of
2576 && (tem = prev_nonnote_insn (insn)) != 0
2577 && GET_CODE (tem) == BARRIER)
2578 set_offsets_for_label (insn);
2580 /* If neither of the above cases is true, compare each offset
2581 with those previously recorded and suppress any eliminations
2582 where the offsets disagree. */
2584 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2585 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2586 != (initial_p ? reg_eliminate[i].initial_offset
2587 : reg_eliminate[i].offset))
2588 reg_eliminate[i].can_eliminate = 0;
2593 set_label_offsets (PATTERN (insn), insn, initial_p);
2595 /* ... fall through ... */
2599 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2600 and hence must have all eliminations at their initial offsets. */
2601 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2602 if (REG_NOTE_KIND (tem) == REG_LABEL)
2603 set_label_offsets (XEXP (tem, 0), insn, 1);
2608 /* Each of the labels in the address vector must be at their initial
2609 offsets. We want the first field for ADDR_VEC and the second
2610 field for ADDR_DIFF_VEC. */
2612 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2613 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2618 /* We only care about setting PC. If the source is not RETURN,
2619 IF_THEN_ELSE, or a label, disable any eliminations not at
2620 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2621 isn't one of those possibilities. For branches to a label,
2622 call ourselves recursively.
2624 Note that this can disable elimination unnecessarily when we have
2625 a non-local goto since it will look like a non-constant jump to
2626 someplace in the current function. This isn't a significant
2627 problem since such jumps will normally be when all elimination
2628 pairs are back to their initial offsets. */
2630 if (SET_DEST (x) != pc_rtx)
2633 switch (GET_CODE (SET_SRC (x)))
2640 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2644 tem = XEXP (SET_SRC (x), 1);
2645 if (GET_CODE (tem) == LABEL_REF)
2646 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2647 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2650 tem = XEXP (SET_SRC (x), 2);
2651 if (GET_CODE (tem) == LABEL_REF)
2652 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2653 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2661 /* If we reach here, all eliminations must be at their initial
2662 offset because we are doing a jump to a variable address. */
2663 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2664 if (p->offset != p->initial_offset)
2665 p->can_eliminate = 0;
2673 /* Used for communication between the next two function to properly share
2674 the vector for an ASM_OPERANDS. */
2676 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2678 /* Scan X and replace any eliminable registers (such as fp) with a
2679 replacement (such as sp), plus an offset.
2681 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2682 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2683 MEM, we are allowed to replace a sum of a register and the constant zero
2684 with the register, which we cannot do outside a MEM. In addition, we need
2685 to record the fact that a register is referenced outside a MEM.
2687 If INSN is an insn, it is the insn containing X. If we replace a REG
2688 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2689 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2690 the REG is being modified.
2692 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2693 That's used when we eliminate in expressions stored in notes.
2694 This means, do not set ref_outside_mem even if the reference
2697 If we see a modification to a register we know about, take the
2698 appropriate action (see case SET, below).
2700 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2701 replacements done assuming all offsets are at their initial values. If
2702 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2703 encounter, return the actual location so that find_reloads will do
2704 the proper thing. */
2707 eliminate_regs (x, mem_mode, insn)
2709 enum machine_mode mem_mode;
2712 enum rtx_code code = GET_CODE (x);
2713 struct elim_table *ep;
2720 if (! current_function_decl)
2739 /* This is only for the benefit of the debugging backends, which call
2740 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2741 removed after CSE. */
2742 new = eliminate_regs (XEXP (x, 0), 0, insn);
2743 if (GET_CODE (new) == MEM)
2744 return XEXP (new, 0);
2750 /* First handle the case where we encounter a bare register that
2751 is eliminable. Replace it with a PLUS. */
2752 if (regno < FIRST_PSEUDO_REGISTER)
2754 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2756 if (ep->from_rtx == x && ep->can_eliminate)
2759 /* Refs inside notes don't count for this purpose. */
2760 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2761 || GET_CODE (insn) == INSN_LIST)))
2762 ep->ref_outside_mem = 1;
2763 return plus_constant (ep->to_rtx, ep->previous_offset);
2767 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2768 && reg_equiv_constant[regno]
2769 && ! CONSTANT_P (reg_equiv_constant[regno]))
2770 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2775 /* If this is the sum of an eliminable register and a constant, rework
2777 if (GET_CODE (XEXP (x, 0)) == REG
2778 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2779 && CONSTANT_P (XEXP (x, 1)))
2781 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2783 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2786 /* Refs inside notes don't count for this purpose. */
2787 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2788 || GET_CODE (insn) == INSN_LIST)))
2789 ep->ref_outside_mem = 1;
2791 /* The only time we want to replace a PLUS with a REG (this
2792 occurs when the constant operand of the PLUS is the negative
2793 of the offset) is when we are inside a MEM. We won't want
2794 to do so at other times because that would change the
2795 structure of the insn in a way that reload can't handle.
2796 We special-case the commonest situation in
2797 eliminate_regs_in_insn, so just replace a PLUS with a
2798 PLUS here, unless inside a MEM. */
2799 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2800 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2803 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2804 plus_constant (XEXP (x, 1),
2805 ep->previous_offset));
2808 /* If the register is not eliminable, we are done since the other
2809 operand is a constant. */
2813 /* If this is part of an address, we want to bring any constant to the
2814 outermost PLUS. We will do this by doing register replacement in
2815 our operands and seeing if a constant shows up in one of them.
2817 We assume here this is part of an address (or a "load address" insn)
2818 since an eliminable register is not likely to appear in any other
2821 If we have (plus (eliminable) (reg)), we want to produce
2822 (plus (plus (replacement) (reg) (const))). If this was part of a
2823 normal add insn, (plus (replacement) (reg)) will be pushed as a
2824 reload. This is the desired action. */
2827 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2828 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2830 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2832 /* If one side is a PLUS and the other side is a pseudo that
2833 didn't get a hard register but has a reg_equiv_constant,
2834 we must replace the constant here since it may no longer
2835 be in the position of any operand. */
2836 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2837 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2838 && reg_renumber[REGNO (new1)] < 0
2839 && reg_equiv_constant != 0
2840 && reg_equiv_constant[REGNO (new1)] != 0)
2841 new1 = reg_equiv_constant[REGNO (new1)];
2842 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2843 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2844 && reg_renumber[REGNO (new0)] < 0
2845 && reg_equiv_constant[REGNO (new0)] != 0)
2846 new0 = reg_equiv_constant[REGNO (new0)];
2848 new = form_sum (new0, new1);
2850 /* As above, if we are not inside a MEM we do not want to
2851 turn a PLUS into something else. We might try to do so here
2852 for an addition of 0 if we aren't optimizing. */
2853 if (! mem_mode && GET_CODE (new) != PLUS)
2854 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2862 /* If this is the product of an eliminable register and a
2863 constant, apply the distribute law and move the constant out
2864 so that we have (plus (mult ..) ..). This is needed in order
2865 to keep load-address insns valid. This case is pathological.
2866 We ignore the possibility of overflow here. */
2867 if (GET_CODE (XEXP (x, 0)) == REG
2868 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2869 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2870 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2872 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2875 /* Refs inside notes don't count for this purpose. */
2876 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2877 || GET_CODE (insn) == INSN_LIST)))
2878 ep->ref_outside_mem = 1;
2881 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2882 ep->previous_offset * INTVAL (XEXP (x, 1)));
2885 /* ... fall through ... */
2890 case DIV: case UDIV:
2891 case MOD: case UMOD:
2892 case AND: case IOR: case XOR:
2893 case ROTATERT: case ROTATE:
2894 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2896 case GE: case GT: case GEU: case GTU:
2897 case LE: case LT: case LEU: case LTU:
2899 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2901 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2903 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2904 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2909 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2912 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2913 if (new != XEXP (x, 0))
2915 /* If this is a REG_DEAD note, it is not valid anymore.
2916 Using the eliminated version could result in creating a
2917 REG_DEAD note for the stack or frame pointer. */
2918 if (GET_MODE (x) == REG_DEAD)
2920 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2923 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2927 /* ... fall through ... */
2930 /* Now do eliminations in the rest of the chain. If this was
2931 an EXPR_LIST, this might result in allocating more memory than is
2932 strictly needed, but it simplifies the code. */
2935 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2936 if (new != XEXP (x, 1))
2937 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2945 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2946 if (ep->to_rtx == XEXP (x, 0))
2948 int size = GET_MODE_SIZE (mem_mode);
2950 /* If more bytes than MEM_MODE are pushed, account for them. */
2951 #ifdef PUSH_ROUNDING
2952 if (ep->to_rtx == stack_pointer_rtx)
2953 size = PUSH_ROUNDING (size);
2955 if (code == PRE_DEC || code == POST_DEC)
2961 /* Fall through to generic unary operation case. */
2962 case STRICT_LOW_PART:
2964 case SIGN_EXTEND: case ZERO_EXTEND:
2965 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2966 case FLOAT: case FIX:
2967 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2971 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2972 if (new != XEXP (x, 0))
2973 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2977 /* Similar to above processing, but preserve SUBREG_WORD.
2978 Convert (subreg (mem)) to (mem) if not paradoxical.
2979 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2980 pseudo didn't get a hard reg, we must replace this with the
2981 eliminated version of the memory location because push_reloads
2982 may do the replacement in certain circumstances. */
2983 if (GET_CODE (SUBREG_REG (x)) == REG
2984 && (GET_MODE_SIZE (GET_MODE (x))
2985 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2986 && reg_equiv_memory_loc != 0
2987 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2990 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2993 /* If we didn't change anything, we must retain the pseudo. */
2994 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2995 new = SUBREG_REG (x);
2998 /* In this case, we must show that the pseudo is used in this
2999 insn so that delete_output_reload will do the right thing. */
3000 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
3001 && GET_CODE (insn) != INSN_LIST)
3002 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
3005 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
3007 /* Ensure NEW isn't shared in case we have to reload it. */
3008 new = copy_rtx (new);
3011 new = SUBREG_REG (x);
3015 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
3017 if (new != XEXP (x, 0))
3019 int x_size = GET_MODE_SIZE (GET_MODE (x));
3020 int new_size = GET_MODE_SIZE (GET_MODE (new));
3022 if (GET_CODE (new) == MEM
3023 && ((x_size < new_size
3024 #ifdef WORD_REGISTER_OPERATIONS
3025 /* On these machines, combine can create rtl of the form
3026 (set (subreg:m1 (reg:m2 R) 0) ...)
3027 where m1 < m2, and expects something interesting to
3028 happen to the entire word. Moreover, it will use the
3029 (reg:m2 R) later, expecting all bits to be preserved.
3030 So if the number of words is the same, preserve the
3031 subreg so that push_reloads can see it. */
3032 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
3035 || (x_size == new_size))
3038 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3039 enum machine_mode mode = GET_MODE (x);
3041 if (BYTES_BIG_ENDIAN)
3042 offset += (MIN (UNITS_PER_WORD,
3043 GET_MODE_SIZE (GET_MODE (new)))
3044 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3046 PUT_MODE (new, mode);
3047 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3051 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
3057 /* If using a register that is the source of an eliminate we still
3058 think can be performed, note it cannot be performed since we don't
3059 know how this register is used. */
3060 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3061 if (ep->from_rtx == XEXP (x, 0))
3062 ep->can_eliminate = 0;
3064 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3065 if (new != XEXP (x, 0))
3066 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3070 /* If clobbering a register that is the replacement register for an
3071 elimination we still think can be performed, note that it cannot
3072 be performed. Otherwise, we need not be concerned about it. */
3073 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3074 if (ep->to_rtx == XEXP (x, 0))
3075 ep->can_eliminate = 0;
3077 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3078 if (new != XEXP (x, 0))
3079 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3085 /* Properly handle sharing input and constraint vectors. */
3086 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3088 /* When we come to a new vector not seen before,
3089 scan all its elements; keep the old vector if none
3090 of them changes; otherwise, make a copy. */
3091 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3092 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3093 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3094 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3097 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3098 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3101 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3102 new_asm_operands_vec = old_asm_operands_vec;
3104 new_asm_operands_vec
3105 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3108 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3109 if (new_asm_operands_vec == old_asm_operands_vec)
3112 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3113 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3114 ASM_OPERANDS_OUTPUT_IDX (x),
3115 new_asm_operands_vec,
3116 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3117 ASM_OPERANDS_SOURCE_FILE (x),
3118 ASM_OPERANDS_SOURCE_LINE (x));
3119 new->volatil = x->volatil;
3124 /* Check for setting a register that we know about. */
3125 if (GET_CODE (SET_DEST (x)) == REG)
3127 /* See if this is setting the replacement register for an
3130 If DEST is the hard frame pointer, we do nothing because we
3131 assume that all assignments to the frame pointer are for
3132 non-local gotos and are being done at a time when they are valid
3133 and do not disturb anything else. Some machines want to
3134 eliminate a fake argument pointer (or even a fake frame pointer)
3135 with either the real frame or the stack pointer. Assignments to
3136 the hard frame pointer must not prevent this elimination. */
3138 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3140 if (ep->to_rtx == SET_DEST (x)
3141 && SET_DEST (x) != hard_frame_pointer_rtx)
3143 /* If it is being incremented, adjust the offset. Otherwise,
3144 this elimination can't be done. */
3145 rtx src = SET_SRC (x);
3147 if (GET_CODE (src) == PLUS
3148 && XEXP (src, 0) == SET_DEST (x)
3149 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3150 ep->offset -= INTVAL (XEXP (src, 1));
3152 ep->can_eliminate = 0;
3155 /* Now check to see we are assigning to a register that can be
3156 eliminated. If so, it must be as part of a PARALLEL, since we
3157 will not have been called if this is a single SET. So indicate
3158 that we can no longer eliminate this reg. */
3159 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3161 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3162 ep->can_eliminate = 0;
3165 /* Now avoid the loop below in this common case. */
3167 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3168 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3170 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3171 write a CLOBBER insn. */
3172 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3173 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3174 && GET_CODE (insn) != INSN_LIST)
3175 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3177 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3178 return gen_rtx_SET (VOIDmode, new0, new1);
3184 /* This is only for the benefit of the debugging backends, which call
3185 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3186 removed after CSE. */
3187 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3188 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3190 /* Our only special processing is to pass the mode of the MEM to our
3191 recursive call and copy the flags. While we are here, handle this
3192 case more efficiently. */
3193 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3194 if (new != XEXP (x, 0))
3196 new = gen_rtx_MEM (GET_MODE (x), new);
3197 new->volatil = x->volatil;
3198 new->unchanging = x->unchanging;
3199 new->in_struct = x->in_struct;
3209 /* Process each of our operands recursively. If any have changed, make a
3211 fmt = GET_RTX_FORMAT (code);
3212 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3216 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3217 if (new != XEXP (x, i) && ! copied)
3219 rtx new_x = rtx_alloc (code);
3220 bcopy ((char *) x, (char *) new_x,
3221 (sizeof (*new_x) - sizeof (new_x->fld)
3222 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3228 else if (*fmt == 'E')
3231 for (j = 0; j < XVECLEN (x, i); j++)
3233 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3234 if (new != XVECEXP (x, i, j) && ! copied_vec)
3236 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3240 rtx new_x = rtx_alloc (code);
3241 bcopy ((char *) x, (char *) new_x,
3242 (sizeof (*new_x) - sizeof (new_x->fld)
3243 + (sizeof (new_x->fld[0])
3244 * GET_RTX_LENGTH (code))));
3248 XVEC (x, i) = new_v;
3251 XVECEXP (x, i, j) = new;
3259 /* Scan INSN and eliminate all eliminable registers in it.
3261 If REPLACE is nonzero, do the replacement destructively. Also
3262 delete the insn as dead it if it is setting an eliminable register.
3264 If REPLACE is zero, do all our allocations in reload_obstack.
3266 If no eliminations were done and this insn doesn't require any elimination
3267 processing (these are not identical conditions: it might be updating sp,
3268 but not referencing fp; this needs to be seen during reload_as_needed so
3269 that the offset between fp and sp can be taken into consideration), zero
3270 is returned. Otherwise, 1 is returned. */
3273 eliminate_regs_in_insn (insn, replace)
3277 rtx old_body = PATTERN (insn);
3278 rtx old_set = single_set (insn);
3281 struct elim_table *ep;
3284 push_obstacks (&reload_obstack, &reload_obstack);
3286 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3287 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3289 /* Check for setting an eliminable register. */
3290 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3291 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3293 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3294 /* If this is setting the frame pointer register to the
3295 hardware frame pointer register and this is an elimination
3296 that will be done (tested above), this insn is really
3297 adjusting the frame pointer downward to compensate for
3298 the adjustment done before a nonlocal goto. */
3299 if (ep->from == FRAME_POINTER_REGNUM
3300 && ep->to == HARD_FRAME_POINTER_REGNUM)
3302 rtx src = SET_SRC (old_set);
3303 int offset = 0, ok = 0;
3304 rtx prev_insn, prev_set;
3306 if (src == ep->to_rtx)
3308 else if (GET_CODE (src) == PLUS
3309 && GET_CODE (XEXP (src, 0)) == CONST_INT
3310 && XEXP (src, 1) == ep->to_rtx)
3311 offset = INTVAL (XEXP (src, 0)), ok = 1;
3312 else if (GET_CODE (src) == PLUS
3313 && GET_CODE (XEXP (src, 1)) == CONST_INT
3314 && XEXP (src, 0) == ep->to_rtx)
3315 offset = INTVAL (XEXP (src, 1)), ok = 1;
3316 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3317 && (prev_set = single_set (prev_insn)) != 0
3318 && rtx_equal_p (SET_DEST (prev_set), src))
3320 src = SET_SRC (prev_set);
3321 if (src == ep->to_rtx)
3323 else if (GET_CODE (src) == PLUS
3324 && GET_CODE (XEXP (src, 0)) == CONST_INT
3325 && XEXP (src, 1) == ep->to_rtx)
3326 offset = INTVAL (XEXP (src, 0)), ok = 1;
3327 else if (GET_CODE (src) == PLUS
3328 && GET_CODE (XEXP (src, 1)) == CONST_INT
3329 && XEXP (src, 0) == ep->to_rtx)
3330 offset = INTVAL (XEXP (src, 1)), ok = 1;
3338 = plus_constant (ep->to_rtx, offset - ep->offset);
3340 /* First see if this insn remains valid when we
3341 make the change. If not, keep the INSN_CODE
3342 the same and let reload fit it up. */
3343 validate_change (insn, &SET_SRC (old_set), src, 1);
3344 validate_change (insn, &SET_DEST (old_set),
3346 if (! apply_change_group ())
3348 SET_SRC (old_set) = src;
3349 SET_DEST (old_set) = ep->to_rtx;
3359 /* In this case this insn isn't serving a useful purpose. We
3360 will delete it in reload_as_needed once we know that this
3361 elimination is, in fact, being done.
3363 If REPLACE isn't set, we can't delete this insn, but needn't
3364 process it since it won't be used unless something changes. */
3366 delete_dead_insn (insn);
3371 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3372 in the insn is the negative of the offset in FROM. Substitute
3373 (set (reg) (reg to)) for the insn and change its code.
3375 We have to do this here, rather than in eliminate_regs, so that we can
3376 change the insn code. */
3378 if (GET_CODE (SET_SRC (old_set)) == PLUS
3379 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3380 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3381 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3383 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3384 && ep->can_eliminate)
3386 /* We must stop at the first elimination that will be used.
3387 If this one would replace the PLUS with a REG, do it
3388 now. Otherwise, quit the loop and let eliminate_regs
3389 do its normal replacement. */
3390 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3392 /* We assume here that we don't need a PARALLEL of
3393 any CLOBBERs for this assignment. There's not
3394 much we can do if we do need it. */
3395 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3398 INSN_CODE (insn) = -1;
3407 old_asm_operands_vec = 0;
3409 /* Replace the body of this insn with a substituted form. If we changed
3410 something, return non-zero.
3412 If we are replacing a body that was a (set X (plus Y Z)), try to
3413 re-recognize the insn. We do this in case we had a simple addition
3414 but now can do this as a load-address. This saves an insn in this
3417 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3418 if (new_body != old_body)
3420 /* If we aren't replacing things permanently and we changed something,
3421 make another copy to ensure that all the RTL is new. Otherwise
3422 things can go wrong if find_reload swaps commutative operands
3423 and one is inside RTL that has been copied while the other is not. */
3425 /* Don't copy an asm_operands because (1) there's no need and (2)
3426 copy_rtx can't do it properly when there are multiple outputs. */
3427 if (! replace && asm_noperands (old_body) < 0)
3428 new_body = copy_rtx (new_body);
3430 /* If we had a move insn but now we don't, rerecognize it. This will
3431 cause spurious re-recognition if the old move had a PARALLEL since
3432 the new one still will, but we can't call single_set without
3433 having put NEW_BODY into the insn and the re-recognition won't
3434 hurt in this rare case. */
3436 && ((GET_CODE (SET_SRC (old_set)) == REG
3437 && (GET_CODE (new_body) != SET
3438 || GET_CODE (SET_SRC (new_body)) != REG))
3439 /* If this was a load from or store to memory, compare
3440 the MEM in recog_operand to the one in the insn. If they
3441 are not equal, then rerecognize the insn. */
3443 && ((GET_CODE (SET_SRC (old_set)) == MEM
3444 && SET_SRC (old_set) != recog_operand[1])
3445 || (GET_CODE (SET_DEST (old_set)) == MEM
3446 && SET_DEST (old_set) != recog_operand[0])))
3447 /* If this was an add insn before, rerecognize. */
3448 || GET_CODE (SET_SRC (old_set)) == PLUS))
3450 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3451 /* If recognition fails, store the new body anyway.
3452 It's normal to have recognition failures here
3453 due to bizarre memory addresses; reloading will fix them. */
3454 PATTERN (insn) = new_body;
3457 PATTERN (insn) = new_body;
3462 /* Loop through all elimination pairs. See if any have changed.
3464 We also detect a cases where register elimination cannot be done,
3465 namely, if a register would be both changed and referenced outside a MEM
3466 in the resulting insn since such an insn is often undefined and, even if
3467 not, we cannot know what meaning will be given to it. Note that it is
3468 valid to have a register used in an address in an insn that changes it
3469 (presumably with a pre- or post-increment or decrement).
3471 If anything changes, return nonzero. */
3473 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3475 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3476 ep->can_eliminate = 0;
3478 ep->ref_outside_mem = 0;
3480 if (ep->previous_offset != ep->offset)
3485 /* If we changed something, perform elimination in REG_NOTES. This is
3486 needed even when REPLACE is zero because a REG_DEAD note might refer
3487 to a register that we eliminate and could cause a different number
3488 of spill registers to be needed in the final reload pass than in
3490 if (val && REG_NOTES (insn) != 0)
3491 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3499 /* Loop through all elimination pairs.
3500 Recalculate the number not at initial offset.
3502 Compute the maximum offset (minimum offset if the stack does not
3503 grow downward) for each elimination pair. */
3506 update_eliminable_offsets ()
3508 struct elim_table *ep;
3510 num_not_at_initial_offset = 0;
3511 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3513 ep->previous_offset = ep->offset;
3514 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3515 num_not_at_initial_offset++;
3519 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3520 replacement we currently believe is valid, mark it as not eliminable if X
3521 modifies DEST in any way other than by adding a constant integer to it.
3523 If DEST is the frame pointer, we do nothing because we assume that
3524 all assignments to the hard frame pointer are nonlocal gotos and are being
3525 done at a time when they are valid and do not disturb anything else.
3526 Some machines want to eliminate a fake argument pointer with either the
3527 frame or stack pointer. Assignments to the hard frame pointer must not
3528 prevent this elimination.
3530 Called via note_stores from reload before starting its passes to scan
3531 the insns of the function. */
3534 mark_not_eliminable (dest, x)
3538 register unsigned int i;
3540 /* A SUBREG of a hard register here is just changing its mode. We should
3541 not see a SUBREG of an eliminable hard register, but check just in
3543 if (GET_CODE (dest) == SUBREG)
3544 dest = SUBREG_REG (dest);
3546 if (dest == hard_frame_pointer_rtx)
3549 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3550 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3551 && (GET_CODE (x) != SET
3552 || GET_CODE (SET_SRC (x)) != PLUS
3553 || XEXP (SET_SRC (x), 0) != dest
3554 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3556 reg_eliminate[i].can_eliminate_previous
3557 = reg_eliminate[i].can_eliminate = 0;
3562 /* Verify that the initial elimination offsets did not change since the
3563 last call to set_initial_elim_offsets. This is used to catch cases
3564 where something illegal happened during reload_as_needed that could
3565 cause incorrect code to be generated if we did not check for it. */
3567 verify_initial_elim_offsets ()
3571 #ifdef ELIMINABLE_REGS
3572 struct elim_table *ep;
3574 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3576 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3577 if (t != ep->initial_offset)
3581 INITIAL_FRAME_POINTER_OFFSET (t);
3582 if (t != reg_eliminate[0].initial_offset)
3587 /* Reset all offsets on eliminable registers to their initial values. */
3589 set_initial_elim_offsets ()
3591 struct elim_table *ep = reg_eliminate;
3593 #ifdef ELIMINABLE_REGS
3594 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3596 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3597 ep->previous_offset = ep->offset = ep->initial_offset;
3600 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3601 ep->previous_offset = ep->offset = ep->initial_offset;
3604 num_not_at_initial_offset = 0;
3607 /* Initialize the known label offsets.
3608 Set a known offset for each forced label to be at the initial offset
3609 of each elimination. We do this because we assume that all
3610 computed jumps occur from a location where each elimination is
3611 at its initial offset.
3612 For all other labels, show that we don't know the offsets. */
3615 set_initial_label_offsets ()
3618 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3620 for (x = forced_labels; x; x = XEXP (x, 1))
3622 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3625 /* Set all elimination offsets to the known values for the code label given
3628 set_offsets_for_label (insn)
3632 int label_nr = CODE_LABEL_NUMBER (insn);
3633 struct elim_table *ep;
3635 num_not_at_initial_offset = 0;
3636 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3638 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3639 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3640 num_not_at_initial_offset++;
3644 /* See if anything that happened changes which eliminations are valid.
3645 For example, on the Sparc, whether or not the frame pointer can
3646 be eliminated can depend on what registers have been used. We need
3647 not check some conditions again (such as flag_omit_frame_pointer)
3648 since they can't have changed. */
3651 update_eliminables (pset)
3654 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3655 int previous_frame_pointer_needed = frame_pointer_needed;
3657 struct elim_table *ep;
3659 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3660 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3661 #ifdef ELIMINABLE_REGS
3662 || ! CAN_ELIMINATE (ep->from, ep->to)
3665 ep->can_eliminate = 0;
3667 /* Look for the case where we have discovered that we can't replace
3668 register A with register B and that means that we will now be
3669 trying to replace register A with register C. This means we can
3670 no longer replace register C with register B and we need to disable
3671 such an elimination, if it exists. This occurs often with A == ap,
3672 B == sp, and C == fp. */
3674 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3676 struct elim_table *op;
3677 register int new_to = -1;
3679 if (! ep->can_eliminate && ep->can_eliminate_previous)
3681 /* Find the current elimination for ep->from, if there is a
3683 for (op = reg_eliminate;
3684 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3685 if (op->from == ep->from && op->can_eliminate)
3691 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3693 for (op = reg_eliminate;
3694 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3695 if (op->from == new_to && op->to == ep->to)
3696 op->can_eliminate = 0;
3700 /* See if any registers that we thought we could eliminate the previous
3701 time are no longer eliminable. If so, something has changed and we
3702 must spill the register. Also, recompute the number of eliminable
3703 registers and see if the frame pointer is needed; it is if there is
3704 no elimination of the frame pointer that we can perform. */
3706 frame_pointer_needed = 1;
3707 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3709 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3710 && ep->to != HARD_FRAME_POINTER_REGNUM)
3711 frame_pointer_needed = 0;
3713 if (! ep->can_eliminate && ep->can_eliminate_previous)
3715 ep->can_eliminate_previous = 0;
3716 SET_HARD_REG_BIT (*pset, ep->from);
3721 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3722 /* If we didn't need a frame pointer last time, but we do now, spill
3723 the hard frame pointer. */
3724 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3725 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3729 /* Initialize the table of registers to eliminate. */
3733 struct elim_table *ep;
3734 #ifdef ELIMINABLE_REGS
3735 struct elim_table_1 *ep1;
3740 reg_eliminate = (struct elim_table *)
3741 xmalloc(sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3742 bzero ((PTR) reg_eliminate,
3743 sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3746 /* Does this function require a frame pointer? */
3748 frame_pointer_needed = (! flag_omit_frame_pointer
3749 #ifdef EXIT_IGNORE_STACK
3750 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3751 and restore sp for alloca. So we can't eliminate
3752 the frame pointer in that case. At some point,
3753 we should improve this by emitting the
3754 sp-adjusting insns for this case. */
3755 || (current_function_calls_alloca
3756 && EXIT_IGNORE_STACK)
3758 || FRAME_POINTER_REQUIRED);
3762 #ifdef ELIMINABLE_REGS
3763 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3764 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3766 ep->from = ep1->from;
3768 ep->can_eliminate = ep->can_eliminate_previous
3769 = (CAN_ELIMINATE (ep->from, ep->to)
3770 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3773 reg_eliminate[0].from = reg_eliminate_1[0].from;
3774 reg_eliminate[0].to = reg_eliminate_1[0].to;
3775 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3776 = ! frame_pointer_needed;
3779 /* Count the number of eliminable registers and build the FROM and TO
3780 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3781 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3782 We depend on this. */
3783 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3785 num_eliminable += ep->can_eliminate;
3786 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3787 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3791 /* Kick all pseudos out of hard register REGNO.
3792 If DUMPFILE is nonzero, log actions taken on that file.
3794 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3795 because we found we can't eliminate some register. In the case, no pseudos
3796 are allowed to be in the register, even if they are only in a block that
3797 doesn't require spill registers, unlike the case when we are spilling this
3798 hard reg to produce another spill register.
3800 Return nonzero if any pseudos needed to be kicked out. */
3803 spill_hard_reg (regno, dumpfile, cant_eliminate)
3812 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3813 regs_ever_live[regno] = 1;
3816 /* Spill every pseudo reg that was allocated to this reg
3817 or to something that overlaps this reg. */
3819 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3820 if (reg_renumber[i] >= 0
3821 && reg_renumber[i] <= regno
3823 + HARD_REGNO_NREGS (reg_renumber[i],
3824 PSEUDO_REGNO_MODE (i))
3826 SET_REGNO_REG_SET (spilled_pseudos, i);
3829 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3830 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3832 ior_hard_reg_set (set1, set2)
3833 HARD_REG_SET *set1, *set2;
3835 IOR_HARD_REG_SET (*set1, *set2);
3838 /* After find_reload_regs has been run for all insn that need reloads,
3839 and/or spill_hard_regs was called, this function is used to actually
3840 spill pseudo registers and try to reallocate them. It also sets up the
3841 spill_regs array for use by choose_reload_regs. */
3844 finish_spills (global, dumpfile)
3848 struct insn_chain *chain;
3849 int something_changed = 0;
3852 /* Build the spill_regs array for the function. */
3853 /* If there are some registers still to eliminate and one of the spill regs
3854 wasn't ever used before, additional stack space may have to be
3855 allocated to store this register. Thus, we may have changed the offset
3856 between the stack and frame pointers, so mark that something has changed.
3858 One might think that we need only set VAL to 1 if this is a call-used
3859 register. However, the set of registers that must be saved by the
3860 prologue is not identical to the call-used set. For example, the
3861 register used by the call insn for the return PC is a call-used register,
3862 but must be saved by the prologue. */
3865 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3866 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3868 spill_reg_order[i] = n_spills;
3869 spill_regs[n_spills++] = i;
3870 if (num_eliminable && ! regs_ever_live[i])
3871 something_changed = 1;
3872 regs_ever_live[i] = 1;
3875 spill_reg_order[i] = -1;
3877 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3878 if (REGNO_REG_SET_P (spilled_pseudos, i))
3880 /* Record the current hard register the pseudo is allocated to in
3881 pseudo_previous_regs so we avoid reallocating it to the same
3882 hard reg in a later pass. */
3883 if (reg_renumber[i] < 0)
3885 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3886 /* Mark it as no longer having a hard register home. */
3887 reg_renumber[i] = -1;
3888 /* We will need to scan everything again. */
3889 something_changed = 1;
3892 /* Retry global register allocation if possible. */
3895 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3896 /* For every insn that needs reloads, set the registers used as spill
3897 regs in pseudo_forbidden_regs for every pseudo live across the
3899 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3901 EXECUTE_IF_SET_IN_REG_SET
3902 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
3904 ior_hard_reg_set (pseudo_forbidden_regs + i,
3905 &chain->used_spill_regs);
3907 EXECUTE_IF_SET_IN_REG_SET
3908 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
3910 ior_hard_reg_set (pseudo_forbidden_regs + i,
3911 &chain->used_spill_regs);
3915 /* Retry allocating the spilled pseudos. For each reg, merge the
3916 various reg sets that indicate which hard regs can't be used,
3917 and call retry_global_alloc.
3918 We change spill_pseudos here to only contain pseudos that did not
3919 get a new hard register. */
3920 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3921 if (reg_old_renumber[i] != reg_renumber[i])
3923 HARD_REG_SET forbidden;
3924 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3925 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3926 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3927 retry_global_alloc (i, forbidden);
3928 if (reg_renumber[i] >= 0)
3929 CLEAR_REGNO_REG_SET (spilled_pseudos, i);
3933 /* Fix up the register information in the insn chain.
3934 This involves deleting those of the spilled pseudos which did not get
3935 a new hard register home from the live_{before,after} sets. */
3936 for (chain = reload_insn_chain; chain; chain = chain->next)
3938 HARD_REG_SET used_by_pseudos;
3939 HARD_REG_SET used_by_pseudos2;
3941 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos);
3942 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos);
3944 /* Mark any unallocated hard regs as available for spills. That
3945 makes inheritance work somewhat better. */
3946 if (chain->need_reload)
3948 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
3949 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
3950 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3952 /* Save the old value for the sanity test below. */
3953 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3955 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
3956 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
3957 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3958 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3960 /* Make sure we only enlarge the set. */
3961 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3967 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3968 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3970 int regno = reg_renumber[i];
3971 if (reg_old_renumber[i] == regno)
3974 alter_reg (i, reg_old_renumber[i]);
3975 reg_old_renumber[i] = regno;
3979 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3981 fprintf (dumpfile, " Register %d now in %d.\n\n",
3982 i, reg_renumber[i]);
3986 return something_changed;
3989 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3990 Also mark any hard registers used to store user variables as
3991 forbidden from being used for spill registers. */
3994 scan_paradoxical_subregs (x)
3999 register enum rtx_code code = GET_CODE (x);
4005 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
4006 && REG_USERVAR_P (x))
4007 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
4023 if (GET_CODE (SUBREG_REG (x)) == REG
4024 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
4025 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4026 = GET_MODE_SIZE (GET_MODE (x));
4033 fmt = GET_RTX_FORMAT (code);
4034 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4037 scan_paradoxical_subregs (XEXP (x, i));
4038 else if (fmt[i] == 'E')
4041 for (j = XVECLEN (x, i) - 1; j >=0; j--)
4042 scan_paradoxical_subregs (XVECEXP (x, i, j));
4048 hard_reg_use_compare (p1p, p2p)
4049 const GENERIC_PTR p1p;
4050 const GENERIC_PTR p2p;
4052 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p;
4053 struct hard_reg_n_uses *p2 = (struct hard_reg_n_uses *)p2p;
4054 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
4055 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
4057 return p1->regno - p2->regno;
4062 if (p1->uses > p2->uses)
4064 if (p1->uses < p2->uses)
4066 /* If regs are equally good, sort by regno,
4067 so that the results of qsort leave nothing to chance. */
4068 return p1->regno - p2->regno;
4071 /* Used for communication between order_regs_for_reload and count_pseudo.
4072 Used to avoid counting one pseudo twice. */
4073 static regset pseudos_counted;
4075 /* Update the costs in N_USES, considering that pseudo REG is live. */
4077 count_pseudo (n_uses, reg)
4078 struct hard_reg_n_uses *n_uses;
4081 int r = reg_renumber[reg];
4084 if (REGNO_REG_SET_P (pseudos_counted, reg))
4086 SET_REGNO_REG_SET (pseudos_counted, reg);
4091 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
4093 n_uses[r++].uses += REG_N_REFS (reg);
4095 /* Choose the order to consider regs for use as reload registers
4096 based on how much trouble would be caused by spilling one.
4097 Store them in order of decreasing preference in potential_reload_regs. */
4100 order_regs_for_reload (chain)
4101 struct insn_chain *chain;
4105 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
4107 pseudos_counted = ALLOCA_REG_SET ();
4109 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
4111 /* Count number of uses of each hard reg by pseudo regs allocated to it
4112 and then order them by decreasing use. */
4114 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4118 hard_reg_n_uses[i].regno = i;
4119 hard_reg_n_uses[i].uses = 0;
4121 /* Test the various reasons why we can't use a register for
4122 spilling in this insn. */
4124 || REGNO_REG_SET_P (chain->live_before, i)
4125 || REGNO_REG_SET_P (chain->live_after, i))
4127 SET_HARD_REG_BIT (bad_spill_regs, i);
4131 /* Now find out which pseudos are allocated to it, and update
4133 CLEAR_REG_SET (pseudos_counted);
4135 EXECUTE_IF_SET_IN_REG_SET
4136 (chain->live_before, FIRST_PSEUDO_REGISTER, j,
4138 count_pseudo (hard_reg_n_uses, j);
4140 EXECUTE_IF_SET_IN_REG_SET
4141 (chain->live_after, FIRST_PSEUDO_REGISTER, j,
4143 count_pseudo (hard_reg_n_uses, j);
4147 FREE_REG_SET (pseudos_counted);
4149 /* Prefer registers not so far used, for use in temporary loading.
4150 Among them, if REG_ALLOC_ORDER is defined, use that order.
4151 Otherwise, prefer registers not preserved by calls. */
4153 #ifdef REG_ALLOC_ORDER
4154 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4156 int regno = reg_alloc_order[i];
4158 if (hard_reg_n_uses[regno].uses == 0
4159 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno))
4160 potential_reload_regs[o++] = regno;
4163 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4165 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]
4166 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4167 potential_reload_regs[o++] = i;
4169 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4171 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]
4172 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4173 potential_reload_regs[o++] = i;
4177 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
4178 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
4180 /* Now add the regs that are already used,
4181 preferring those used less often. The fixed and otherwise forbidden
4182 registers will be at the end of this list. */
4184 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4185 if (hard_reg_n_uses[i].uses != 0
4186 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4187 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4188 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4189 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4190 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4193 /* Reload pseudo-registers into hard regs around each insn as needed.
4194 Additional register load insns are output before the insn that needs it
4195 and perhaps store insns after insns that modify the reloaded pseudo reg.
4197 reg_last_reload_reg and reg_reloaded_contents keep track of
4198 which registers are already available in reload registers.
4199 We update these for the reloads that we perform,
4200 as the insns are scanned. */
4203 reload_as_needed (live_known)
4206 struct insn_chain *chain;
4207 #if defined (AUTO_INC_DEC) || defined (INSN_CLOBBERS_REGNO_P)
4212 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4213 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4214 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
4215 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4216 reg_has_output_reload = (char *) alloca (max_regno);
4217 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4219 set_initial_elim_offsets ();
4221 for (chain = reload_insn_chain; chain; chain = chain->next)
4224 rtx insn = chain->insn;
4225 rtx old_next = NEXT_INSN (insn);
4227 /* If we pass a label, copy the offsets from the label information
4228 into the current offsets of each elimination. */
4229 if (GET_CODE (insn) == CODE_LABEL)
4230 set_offsets_for_label (insn);
4232 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4234 rtx oldpat = PATTERN (insn);
4236 /* If this is a USE and CLOBBER of a MEM, ensure that any
4237 references to eliminable registers have been removed. */
4239 if ((GET_CODE (PATTERN (insn)) == USE
4240 || GET_CODE (PATTERN (insn)) == CLOBBER)
4241 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4242 XEXP (XEXP (PATTERN (insn), 0), 0)
4243 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4244 GET_MODE (XEXP (PATTERN (insn), 0)),
4247 /* If we need to do register elimination processing, do so.
4248 This might delete the insn, in which case we are done. */
4249 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4251 eliminate_regs_in_insn (insn, 1);
4252 if (GET_CODE (insn) == NOTE)
4254 update_eliminable_offsets ();
4259 /* If need_elim is nonzero but need_reload is zero, one might think
4260 that we could simply set n_reloads to 0. However, find_reloads
4261 could have done some manipulation of the insn (such as swapping
4262 commutative operands), and these manipulations are lost during
4263 the first pass for every insn that needs register elimination.
4264 So the actions of find_reloads must be redone here. */
4266 if (! chain->need_elim && ! chain->need_reload
4267 && ! chain->need_operand_change)
4269 /* First find the pseudo regs that must be reloaded for this insn.
4270 This info is returned in the tables reload_... (see reload.h).
4271 Also modify the body of INSN by substituting RELOAD
4272 rtx's for those pseudo regs. */
4275 bzero (reg_has_output_reload, max_regno);
4276 CLEAR_HARD_REG_SET (reg_is_output_reload);
4278 find_reloads (insn, 1, spill_indirect_levels, live_known,
4284 rtx next = NEXT_INSN (insn);
4287 prev = PREV_INSN (insn);
4289 /* Now compute which reload regs to reload them into. Perhaps
4290 reusing reload regs from previous insns, or else output
4291 load insns to reload them. Maybe output store insns too.
4292 Record the choices of reload reg in reload_reg_rtx. */
4293 choose_reload_regs (chain);
4295 /* Merge any reloads that we didn't combine for fear of
4296 increasing the number of spill registers needed but now
4297 discover can be safely merged. */
4298 if (SMALL_REGISTER_CLASSES)
4299 merge_assigned_reloads (insn);
4301 /* Generate the insns to reload operands into or out of
4302 their reload regs. */
4303 emit_reload_insns (chain);
4305 /* Substitute the chosen reload regs from reload_reg_rtx
4306 into the insn's body (or perhaps into the bodies of other
4307 load and store insn that we just made for reloading
4308 and that we moved the structure into). */
4311 /* If this was an ASM, make sure that all the reload insns
4312 we have generated are valid. If not, give an error
4315 if (asm_noperands (PATTERN (insn)) >= 0)
4316 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4317 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4318 && (recog_memoized (p) < 0
4319 || (extract_insn (p), ! constrain_operands (1))))
4321 error_for_asm (insn,
4322 "`asm' operand requires impossible reload");
4324 NOTE_SOURCE_FILE (p) = 0;
4325 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4329 if (num_eliminable && chain->need_elim)
4330 update_eliminable_offsets ();
4332 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4333 is no longer validly lying around to save a future reload.
4334 Note that this does not detect pseudos that were reloaded
4335 for this insn in order to be stored in
4336 (obeying register constraints). That is correct; such reload
4337 registers ARE still valid. */
4338 note_stores (oldpat, forget_old_reloads_1);
4340 /* There may have been CLOBBER insns placed after INSN. So scan
4341 between INSN and NEXT and use them to forget old reloads. */
4342 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4343 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4344 note_stores (PATTERN (x), forget_old_reloads_1);
4347 /* Likewise for regs altered by auto-increment in this insn.
4348 REG_INC notes have been changed by reloading:
4349 find_reloads_address_1 records substitutions for them,
4350 which have been performed by subst_reloads above. */
4351 for (i = n_reloads - 1; i >= 0; i--)
4353 rtx in_reg = reload_in_reg[i];
4356 enum rtx_code code = GET_CODE (in_reg);
4357 /* PRE_INC / PRE_DEC will have the reload register ending up
4358 with the same value as the stack slot, but that doesn't
4359 hold true for POST_INC / POST_DEC. Either we have to
4360 convert the memory access to a true POST_INC / POST_DEC,
4361 or we can't use the reload register for inheritance. */
4362 if ((code == POST_INC || code == POST_DEC)
4363 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4364 REGNO (reload_reg_rtx[i]))
4365 /* Make sure it is the inc/dec pseudo, and not
4366 some other (e.g. output operand) pseudo. */
4367 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
4368 == REGNO (XEXP (in_reg, 0))))
4371 rtx reload_reg = reload_reg_rtx[i];
4372 enum machine_mode mode = GET_MODE (reload_reg);
4376 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4378 /* We really want to ignore REG_INC notes here, so
4379 use PATTERN (p) as argument to reg_set_p . */
4380 if (reg_set_p (reload_reg, PATTERN (p)))
4382 n = count_occurrences (PATTERN (p), reload_reg);
4387 n = validate_replace_rtx (reload_reg,
4388 gen_rtx (code, mode,
4392 /* We must also verify that the constraints
4393 are met after the replacement. */
4396 n = constrain_operands (1);
4400 /* If the constraints were not met, then
4401 undo the replacement. */
4404 validate_replace_rtx (gen_rtx (code, mode,
4416 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4418 /* Mark this as having an output reload so that the
4419 REG_INC processing code below won't invalidate
4420 the reload for inheritance. */
4421 SET_HARD_REG_BIT (reg_is_output_reload,
4422 REGNO (reload_reg));
4423 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4426 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX);
4428 else if ((code == PRE_INC || code == PRE_DEC)
4429 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4430 REGNO (reload_reg_rtx[i]))
4431 /* Make sure it is the inc/dec pseudo, and not
4432 some other (e.g. output operand) pseudo. */
4433 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
4434 == REGNO (XEXP (in_reg, 0))))
4436 SET_HARD_REG_BIT (reg_is_output_reload,
4437 REGNO (reload_reg_rtx[i]));
4438 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4442 /* If a pseudo that got a hard register is auto-incremented,
4443 we must purge records of copying it into pseudos without
4445 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4446 if (REG_NOTE_KIND (x) == REG_INC)
4448 /* See if this pseudo reg was reloaded in this insn.
4449 If so, its last-reload info is still valid
4450 because it is based on this insn's reload. */
4451 for (i = 0; i < n_reloads; i++)
4452 if (reload_out[i] == XEXP (x, 0))
4456 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4460 /* A reload reg's contents are unknown after a label. */
4461 if (GET_CODE (insn) == CODE_LABEL)
4462 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4464 /* Don't assume a reload reg is still good after a call insn
4465 if it is a call-used reg. */
4466 else if (GET_CODE (insn) == CALL_INSN)
4467 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4469 /* In case registers overlap, allow certain insns to invalidate
4470 particular hard registers. */
4472 #ifdef INSN_CLOBBERS_REGNO_P
4473 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4474 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4475 && INSN_CLOBBERS_REGNO_P (insn, i))
4476 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4485 /* Discard all record of any value reloaded from X,
4486 or reloaded in X from someplace else;
4487 unless X is an output reload reg of the current insn.
4489 X may be a hard reg (the reload reg)
4490 or it may be a pseudo reg that was reloaded from. */
4493 forget_old_reloads_1 (x, ignored)
4495 rtx ignored ATTRIBUTE_UNUSED;
4501 /* note_stores does give us subregs of hard regs. */
4502 while (GET_CODE (x) == SUBREG)
4504 offset += SUBREG_WORD (x);
4508 if (GET_CODE (x) != REG)
4511 regno = REGNO (x) + offset;
4513 if (regno >= FIRST_PSEUDO_REGISTER)
4518 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4519 /* Storing into a spilled-reg invalidates its contents.
4520 This can happen if a block-local pseudo is allocated to that reg
4521 and it wasn't spilled because this block's total need is 0.
4522 Then some insn might have an optional reload and use this reg. */
4523 for (i = 0; i < nr; i++)
4524 /* But don't do this if the reg actually serves as an output
4525 reload reg in the current instruction. */
4527 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4529 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4530 spill_reg_store[regno + i] = 0;
4534 /* Since value of X has changed,
4535 forget any value previously copied from it. */
4538 /* But don't forget a copy if this is the output reload
4539 that establishes the copy's validity. */
4540 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4541 reg_last_reload_reg[regno + nr] = 0;
4544 /* For each reload, the mode of the reload register. */
4545 static enum machine_mode reload_mode[MAX_RELOADS];
4547 /* For each reload, the largest number of registers it will require. */
4548 static int reload_nregs[MAX_RELOADS];
4550 /* Comparison function for qsort to decide which of two reloads
4551 should be handled first. *P1 and *P2 are the reload numbers. */
4554 reload_reg_class_lower (r1p, r2p)
4555 const GENERIC_PTR r1p;
4556 const GENERIC_PTR r2p;
4558 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4561 /* Consider required reloads before optional ones. */
4562 t = reload_optional[r1] - reload_optional[r2];
4566 /* Count all solitary classes before non-solitary ones. */
4567 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4568 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4572 /* Aside from solitaires, consider all multi-reg groups first. */
4573 t = reload_nregs[r2] - reload_nregs[r1];
4577 /* Consider reloads in order of increasing reg-class number. */
4578 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4582 /* If reloads are equally urgent, sort by reload number,
4583 so that the results of qsort leave nothing to chance. */
4587 /* The following HARD_REG_SETs indicate when each hard register is
4588 used for a reload of various parts of the current insn. */
4590 /* If reg is unavailable for all reloads. */
4591 static HARD_REG_SET reload_reg_unavailable;
4592 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4593 static HARD_REG_SET reload_reg_used;
4594 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4595 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4596 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4597 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4598 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4599 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4600 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4601 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4602 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4603 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4604 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4605 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4606 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4607 static HARD_REG_SET reload_reg_used_in_op_addr;
4608 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4609 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4610 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4611 static HARD_REG_SET reload_reg_used_in_insn;
4612 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4613 static HARD_REG_SET reload_reg_used_in_other_addr;
4615 /* If reg is in use as a reload reg for any sort of reload. */
4616 static HARD_REG_SET reload_reg_used_at_all;
4618 /* If reg is use as an inherited reload. We just mark the first register
4620 static HARD_REG_SET reload_reg_used_for_inherit;
4622 /* Records which hard regs are used in any way, either as explicit use or
4623 by being allocated to a pseudo during any point of the current insn. */
4624 static HARD_REG_SET reg_used_in_insn;
4626 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4627 TYPE. MODE is used to indicate how many consecutive regs are
4631 mark_reload_reg_in_use (regno, opnum, type, mode)
4634 enum reload_type type;
4635 enum machine_mode mode;
4637 int nregs = HARD_REGNO_NREGS (regno, mode);
4640 for (i = regno; i < nregs + regno; i++)
4645 SET_HARD_REG_BIT (reload_reg_used, i);
4648 case RELOAD_FOR_INPUT_ADDRESS:
4649 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4652 case RELOAD_FOR_INPADDR_ADDRESS:
4653 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4656 case RELOAD_FOR_OUTPUT_ADDRESS:
4657 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4660 case RELOAD_FOR_OUTADDR_ADDRESS:
4661 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4664 case RELOAD_FOR_OPERAND_ADDRESS:
4665 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4668 case RELOAD_FOR_OPADDR_ADDR:
4669 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4672 case RELOAD_FOR_OTHER_ADDRESS:
4673 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4676 case RELOAD_FOR_INPUT:
4677 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4680 case RELOAD_FOR_OUTPUT:
4681 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4684 case RELOAD_FOR_INSN:
4685 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4689 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4693 /* Similarly, but show REGNO is no longer in use for a reload. */
4696 clear_reload_reg_in_use (regno, opnum, type, mode)
4699 enum reload_type type;
4700 enum machine_mode mode;
4702 int nregs = HARD_REGNO_NREGS (regno, mode);
4703 int start_regno, end_regno;
4705 /* A complication is that for some reload types, inheritance might
4706 allow multiple reloads of the same types to share a reload register.
4707 We set check_opnum if we have to check only reloads with the same
4708 operand number, and check_any if we have to check all reloads. */
4709 int check_opnum = 0;
4711 HARD_REG_SET *used_in_set;
4716 used_in_set = &reload_reg_used;
4719 case RELOAD_FOR_INPUT_ADDRESS:
4720 used_in_set = &reload_reg_used_in_input_addr[opnum];
4723 case RELOAD_FOR_INPADDR_ADDRESS:
4725 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4728 case RELOAD_FOR_OUTPUT_ADDRESS:
4729 used_in_set = &reload_reg_used_in_output_addr[opnum];
4732 case RELOAD_FOR_OUTADDR_ADDRESS:
4734 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4737 case RELOAD_FOR_OPERAND_ADDRESS:
4738 used_in_set = &reload_reg_used_in_op_addr;
4741 case RELOAD_FOR_OPADDR_ADDR:
4743 used_in_set = &reload_reg_used_in_op_addr_reload;
4746 case RELOAD_FOR_OTHER_ADDRESS:
4747 used_in_set = &reload_reg_used_in_other_addr;
4751 case RELOAD_FOR_INPUT:
4752 used_in_set = &reload_reg_used_in_input[opnum];
4755 case RELOAD_FOR_OUTPUT:
4756 used_in_set = &reload_reg_used_in_output[opnum];
4759 case RELOAD_FOR_INSN:
4760 used_in_set = &reload_reg_used_in_insn;
4765 /* We resolve conflicts with remaining reloads of the same type by
4766 excluding the intervals of of reload registers by them from the
4767 interval of freed reload registers. Since we only keep track of
4768 one set of interval bounds, we might have to exclude somewhat
4769 more then what would be necessary if we used a HARD_REG_SET here.
4770 But this should only happen very infrequently, so there should
4771 be no reason to worry about it. */
4773 start_regno = regno;
4774 end_regno = regno + nregs;
4775 if (check_opnum || check_any)
4777 for (i = n_reloads - 1; i >= 0; i--)
4779 if (reload_when_needed[i] == type
4780 && (check_any || reload_opnum[i] == opnum)
4781 && reload_reg_rtx[i])
4783 int conflict_start = true_regnum (reload_reg_rtx[i]);
4786 + HARD_REGNO_NREGS (conflict_start, reload_mode[i]));
4788 /* If there is an overlap with the first to-be-freed register,
4789 adjust the interval start. */
4790 if (conflict_start <= start_regno && conflict_end > start_regno)
4791 start_regno = conflict_end;
4792 /* Otherwise, if there is a conflict with one of the other
4793 to-be-freed registers, adjust the interval end. */
4794 if (conflict_start > start_regno && conflict_start < end_regno)
4795 end_regno = conflict_start;
4799 for (i = start_regno; i < end_regno; i++)
4800 CLEAR_HARD_REG_BIT (*used_in_set, i);
4803 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4804 specified by OPNUM and TYPE. */
4807 reload_reg_free_p (regno, opnum, type)
4810 enum reload_type type;
4814 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4815 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4821 /* In use for anything means we can't use it for RELOAD_OTHER. */
4822 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4823 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4824 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4827 for (i = 0; i < reload_n_operands; i++)
4828 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4829 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4830 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4831 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4832 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4833 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4838 case RELOAD_FOR_INPUT:
4839 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4840 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4843 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4846 /* If it is used for some other input, can't use it. */
4847 for (i = 0; i < reload_n_operands; i++)
4848 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4851 /* If it is used in a later operand's address, can't use it. */
4852 for (i = opnum + 1; i < reload_n_operands; i++)
4853 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4854 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4859 case RELOAD_FOR_INPUT_ADDRESS:
4860 /* Can't use a register if it is used for an input address for this
4861 operand or used as an input in an earlier one. */
4862 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4863 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4866 for (i = 0; i < opnum; i++)
4867 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4872 case RELOAD_FOR_INPADDR_ADDRESS:
4873 /* Can't use a register if it is used for an input address
4874 for this operand or used as an input in an earlier
4876 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4879 for (i = 0; i < opnum; i++)
4880 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4885 case RELOAD_FOR_OUTPUT_ADDRESS:
4886 /* Can't use a register if it is used for an output address for this
4887 operand or used as an output in this or a later operand. */
4888 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4891 for (i = opnum; i < reload_n_operands; i++)
4892 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4897 case RELOAD_FOR_OUTADDR_ADDRESS:
4898 /* Can't use a register if it is used for an output address
4899 for this operand or used as an output in this or a
4901 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4904 for (i = opnum; i < reload_n_operands; i++)
4905 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4910 case RELOAD_FOR_OPERAND_ADDRESS:
4911 for (i = 0; i < reload_n_operands; i++)
4912 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4915 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4916 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4918 case RELOAD_FOR_OPADDR_ADDR:
4919 for (i = 0; i < reload_n_operands; i++)
4920 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4923 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4925 case RELOAD_FOR_OUTPUT:
4926 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4927 outputs, or an operand address for this or an earlier output. */
4928 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4931 for (i = 0; i < reload_n_operands; i++)
4932 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4935 for (i = 0; i <= opnum; i++)
4936 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4937 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4942 case RELOAD_FOR_INSN:
4943 for (i = 0; i < reload_n_operands; i++)
4944 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4945 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4948 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4949 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4951 case RELOAD_FOR_OTHER_ADDRESS:
4952 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4957 /* Return 1 if the value in reload reg REGNO, as used by a reload
4958 needed for the part of the insn specified by OPNUM and TYPE,
4959 is still available in REGNO at the end of the insn.
4961 We can assume that the reload reg was already tested for availability
4962 at the time it is needed, and we should not check this again,
4963 in case the reg has already been marked in use. */
4966 reload_reg_reaches_end_p (regno, opnum, type)
4969 enum reload_type type;
4976 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4977 its value must reach the end. */
4980 /* If this use is for part of the insn,
4981 its value reaches if no subsequent part uses the same register.
4982 Just like the above function, don't try to do this with lots
4985 case RELOAD_FOR_OTHER_ADDRESS:
4986 /* Here we check for everything else, since these don't conflict
4987 with anything else and everything comes later. */
4989 for (i = 0; i < reload_n_operands; i++)
4990 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4991 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4992 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4993 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4994 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4995 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4998 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4999 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5000 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5002 case RELOAD_FOR_INPUT_ADDRESS:
5003 case RELOAD_FOR_INPADDR_ADDRESS:
5004 /* Similar, except that we check only for this and subsequent inputs
5005 and the address of only subsequent inputs and we do not need
5006 to check for RELOAD_OTHER objects since they are known not to
5009 for (i = opnum; i < reload_n_operands; i++)
5010 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5013 for (i = opnum + 1; i < reload_n_operands; i++)
5014 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5015 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5018 for (i = 0; i < reload_n_operands; i++)
5019 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5020 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5021 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5024 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5027 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5028 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5030 case RELOAD_FOR_INPUT:
5031 /* Similar to input address, except we start at the next operand for
5032 both input and input address and we do not check for
5033 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5036 for (i = opnum + 1; i < reload_n_operands; i++)
5037 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5038 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5039 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5042 /* ... fall through ... */
5044 case RELOAD_FOR_OPERAND_ADDRESS:
5045 /* Check outputs and their addresses. */
5047 for (i = 0; i < reload_n_operands; i++)
5048 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5049 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5050 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5055 case RELOAD_FOR_OPADDR_ADDR:
5056 for (i = 0; i < reload_n_operands; i++)
5057 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5058 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5059 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5062 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5063 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5065 case RELOAD_FOR_INSN:
5066 /* These conflict with other outputs with RELOAD_OTHER. So
5067 we need only check for output addresses. */
5071 /* ... fall through ... */
5073 case RELOAD_FOR_OUTPUT:
5074 case RELOAD_FOR_OUTPUT_ADDRESS:
5075 case RELOAD_FOR_OUTADDR_ADDRESS:
5076 /* We already know these can't conflict with a later output. So the
5077 only thing to check are later output addresses. */
5078 for (i = opnum + 1; i < reload_n_operands; i++)
5079 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5080 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5089 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5092 This function uses the same algorithm as reload_reg_free_p above. */
5095 reloads_conflict (r1, r2)
5098 enum reload_type r1_type = reload_when_needed[r1];
5099 enum reload_type r2_type = reload_when_needed[r2];
5100 int r1_opnum = reload_opnum[r1];
5101 int r2_opnum = reload_opnum[r2];
5103 /* RELOAD_OTHER conflicts with everything. */
5104 if (r2_type == RELOAD_OTHER)
5107 /* Otherwise, check conflicts differently for each type. */
5111 case RELOAD_FOR_INPUT:
5112 return (r2_type == RELOAD_FOR_INSN
5113 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5114 || r2_type == RELOAD_FOR_OPADDR_ADDR
5115 || r2_type == RELOAD_FOR_INPUT
5116 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5117 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5118 && r2_opnum > r1_opnum));
5120 case RELOAD_FOR_INPUT_ADDRESS:
5121 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5122 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5124 case RELOAD_FOR_INPADDR_ADDRESS:
5125 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5126 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5128 case RELOAD_FOR_OUTPUT_ADDRESS:
5129 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5130 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5132 case RELOAD_FOR_OUTADDR_ADDRESS:
5133 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5134 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5136 case RELOAD_FOR_OPERAND_ADDRESS:
5137 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5138 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5140 case RELOAD_FOR_OPADDR_ADDR:
5141 return (r2_type == RELOAD_FOR_INPUT
5142 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5144 case RELOAD_FOR_OUTPUT:
5145 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5146 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5147 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5148 && r2_opnum <= r1_opnum));
5150 case RELOAD_FOR_INSN:
5151 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5152 || r2_type == RELOAD_FOR_INSN
5153 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5155 case RELOAD_FOR_OTHER_ADDRESS:
5156 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5166 /* Vector of reload-numbers showing the order in which the reloads should
5168 short reload_order[MAX_RELOADS];
5170 /* Indexed by reload number, 1 if incoming value
5171 inherited from previous insns. */
5172 char reload_inherited[MAX_RELOADS];
5174 /* For an inherited reload, this is the insn the reload was inherited from,
5175 if we know it. Otherwise, this is 0. */
5176 rtx reload_inheritance_insn[MAX_RELOADS];
5178 /* If non-zero, this is a place to get the value of the reload,
5179 rather than using reload_in. */
5180 rtx reload_override_in[MAX_RELOADS];
5182 /* For each reload, the hard register number of the register used,
5183 or -1 if we did not need a register for this reload. */
5184 int reload_spill_index[MAX_RELOADS];
5186 /* Subroutine of free_for_value_p, used to check a single register. */
5189 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
5190 ignore_address_reloads)
5193 enum reload_type type;
5196 int ignore_address_reloads;
5199 /* Set if we see an input reload that must not share its reload register
5200 with any new earlyclobber, but might otherwise share the reload
5201 register with an output or input-output reload. */
5202 int check_earlyclobber = 0;
5206 /* ??? reload_reg_used is abused to hold the registers that are not
5207 available as spill registers, including hard registers that are
5208 earlyclobbered in asms. As a temporary measure, reject anything
5209 in reload_reg_used. */
5210 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5213 if (out == const0_rtx)
5219 /* We use some pseudo 'time' value to check if the lifetimes of the
5220 new register use would overlap with the one of a previous reload
5221 that is not read-only or uses a different value.
5222 The 'time' used doesn't have to be linear in any shape or form, just
5224 Some reload types use different 'buckets' for each operand.
5225 So there are MAX_RECOG_OPERANDS different time values for each
5227 We compute TIME1 as the time when the register for the prospective
5228 new reload ceases to be live, and TIME2 for each existing
5229 reload as the time when that the reload register of that reload
5231 Where there is little to be gained by exact lifetime calculations,
5232 we just make conservative assumptions, i.e. a longer lifetime;
5233 this is done in the 'default:' cases. */
5236 case RELOAD_FOR_OTHER_ADDRESS:
5237 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5238 time1 = copy ? 0 : 1;
5241 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5243 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5244 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5245 respectively, to the time values for these, we get distinct time
5246 values. To get distinct time values for each operand, we have to
5247 multiply opnum by at least three. We round that up to four because
5248 multiply by four is often cheaper. */
5249 case RELOAD_FOR_INPADDR_ADDRESS:
5250 time1 = opnum * 4 + 2;
5252 case RELOAD_FOR_INPUT_ADDRESS:
5253 time1 = opnum * 4 + 3;
5255 case RELOAD_FOR_INPUT:
5256 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5257 executes (inclusive). */
5258 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5260 case RELOAD_FOR_OPADDR_ADDR:
5262 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5263 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5265 case RELOAD_FOR_OPERAND_ADDRESS:
5266 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5268 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5270 case RELOAD_FOR_OUTADDR_ADDRESS:
5271 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5273 case RELOAD_FOR_OUTPUT_ADDRESS:
5274 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5277 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5280 for (i = 0; i < n_reloads; i++)
5282 rtx reg = reload_reg_rtx[i];
5283 if (reg && GET_CODE (reg) == REG
5284 && ((unsigned) regno - true_regnum (reg)
5285 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5288 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
5289 || reload_out[i] || out)
5292 switch (reload_when_needed[i])
5294 case RELOAD_FOR_OTHER_ADDRESS:
5297 case RELOAD_FOR_INPADDR_ADDRESS:
5298 /* find_reloads makes sure that a
5299 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5300 by at most one - the first -
5301 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5302 address reload is inherited, the address address reload
5303 goes away, so we can ignore this conflict. */
5304 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5305 && ignore_address_reloads
5306 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5307 Then the address address is still needed to store
5308 back the new address. */
5309 && ! reload_out[reloadnum])
5311 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5312 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5314 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5315 && ignore_address_reloads
5316 /* Unless we are reloading an auto_inc expression. */
5317 && ! reload_out[reloadnum])
5319 time2 = reload_opnum[i] * 4 + 2;
5321 case RELOAD_FOR_INPUT_ADDRESS:
5322 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5323 && ignore_address_reloads
5324 && ! reload_out[reloadnum])
5326 time2 = reload_opnum[i] * 4 + 3;
5328 case RELOAD_FOR_INPUT:
5329 time2 = reload_opnum[i] * 4 + 4;
5330 check_earlyclobber = 1;
5332 /* reload_opnum[i] * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5333 == MAX_RECOG_OPERAND * 4 */
5334 case RELOAD_FOR_OPADDR_ADDR:
5335 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5336 && ignore_address_reloads
5337 && ! reload_out[reloadnum])
5339 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5341 case RELOAD_FOR_OPERAND_ADDRESS:
5342 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5343 check_earlyclobber = 1;
5345 case RELOAD_FOR_INSN:
5346 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5348 case RELOAD_FOR_OUTPUT:
5349 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5350 instruction is executed. */
5351 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5353 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5354 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5356 case RELOAD_FOR_OUTADDR_ADDRESS:
5357 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5358 && ignore_address_reloads
5359 && ! reload_out[reloadnum])
5361 time2 = MAX_RECOG_OPERANDS * 4 + 4 + reload_opnum[i];
5363 case RELOAD_FOR_OUTPUT_ADDRESS:
5364 time2 = MAX_RECOG_OPERANDS * 4 + 5 + reload_opnum[i];
5367 /* If there is no conflict in the input part, handle this
5368 like an output reload. */
5369 if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
5371 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5372 /* Earlyclobbered outputs must conflict with inputs. */
5373 if (earlyclobber_operand_p (reload_out[i]))
5374 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5378 /* RELOAD_OTHER might be live beyond instruction execution,
5379 but this is not obvious when we set time2 = 1. So check
5380 here if there might be a problem with the new reload
5381 clobbering the register used by the RELOAD_OTHER. */
5389 && (! reload_in[i] || reload_out[i]
5390 || ! rtx_equal_p (reload_in[i], value)))
5391 || (out && reload_out_reg[reloadnum]
5392 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5398 /* Earlyclobbered outputs must conflict with inputs. */
5399 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5405 /* Return 1 if the value in reload reg REGNO, as used by a reload
5406 needed for the part of the insn specified by OPNUM and TYPE,
5407 may be used to load VALUE into it.
5409 MODE is the mode in which the register is used, this is needed to
5410 determine how many hard regs to test.
5412 Other read-only reloads with the same value do not conflict
5413 unless OUT is non-zero and these other reloads have to live while
5414 output reloads live.
5415 If OUT is CONST0_RTX, this is a special case: it means that the
5416 test should not be for using register REGNO as reload register, but
5417 for copying from register REGNO into the reload register.
5419 RELOADNUM is the number of the reload we want to load this value for;
5420 a reload does not conflict with itself.
5422 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5423 reloads that load an address for the very reload we are considering.
5425 The caller has to make sure that there is no conflict with the return
5429 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
5430 ignore_address_reloads)
5432 enum machine_mode mode;
5434 enum reload_type type;
5437 int ignore_address_reloads;
5439 int nregs = HARD_REGNO_NREGS (regno, mode);
5441 if (! reload_reg_free_for_value_p (regno + nregs, opnum, type, value, out,
5442 reloadnum, ignore_address_reloads))
5447 /* Determine whether the reload reg X overlaps any rtx'es used for
5448 overriding inheritance. Return nonzero if so. */
5451 conflicts_with_override (x)
5455 for (i = 0; i < n_reloads; i++)
5456 if (reload_override_in[i]
5457 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5462 /* Find a spill register to use as a reload register for reload R.
5463 LAST_RELOAD is non-zero if this is the last reload for the insn being
5466 Set reload_reg_rtx[R] to the register allocated.
5468 If NOERROR is nonzero, we return 1 if successful,
5469 or 0 if we couldn't find a spill reg and we didn't change anything. */
5472 allocate_reload_reg (chain, r, last_reload, noerror)
5473 struct insn_chain *chain;
5478 rtx insn = chain->insn;
5479 int i, pass, count, regno;
5482 /* If we put this reload ahead, thinking it is a group,
5483 then insist on finding a group. Otherwise we can grab a
5484 reg that some other reload needs.
5485 (That can happen when we have a 68000 DATA_OR_FP_REG
5486 which is a group of data regs or one fp reg.)
5487 We need not be so restrictive if there are no more reloads
5490 ??? Really it would be nicer to have smarter handling
5491 for that kind of reg class, where a problem like this is normal.
5492 Perhaps those classes should be avoided for reloading
5493 by use of more alternatives. */
5495 int force_group = reload_nregs[r] > 1 && ! last_reload;
5497 /* If we want a single register and haven't yet found one,
5498 take any reg in the right class and not in use.
5499 If we want a consecutive group, here is where we look for it.
5501 We use two passes so we can first look for reload regs to
5502 reuse, which are already in use for other reloads in this insn,
5503 and only then use additional registers.
5504 I think that maximizing reuse is needed to make sure we don't
5505 run out of reload regs. Suppose we have three reloads, and
5506 reloads A and B can share regs. These need two regs.
5507 Suppose A and B are given different regs.
5508 That leaves none for C. */
5509 for (pass = 0; pass < 2; pass++)
5511 /* I is the index in spill_regs.
5512 We advance it round-robin between insns to use all spill regs
5513 equally, so that inherited reloads have a chance
5514 of leapfrogging each other. Don't do this, however, when we have
5515 group needs and failure would be fatal; if we only have a relatively
5516 small number of spill registers, and more than one of them has
5517 group needs, then by starting in the middle, we may end up
5518 allocating the first one in such a way that we are not left with
5519 sufficient groups to handle the rest. */
5521 if (noerror || ! force_group)
5526 for (count = 0; count < n_spills; count++)
5528 int class = (int) reload_reg_class[r];
5534 regnum = spill_regs[i];
5536 if ((reload_reg_free_p (regnum, reload_opnum[r],
5537 reload_when_needed[r])
5539 /* We check reload_reg_used to make sure we
5540 don't clobber the return register. */
5541 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5542 && free_for_value_p (regnum, reload_mode[r],
5544 reload_when_needed[r],
5545 reload_in[r], reload_out[r], r, 1)))
5546 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5547 && HARD_REGNO_MODE_OK (regnum, reload_mode[r])
5548 /* Look first for regs to share, then for unshared. But
5549 don't share regs used for inherited reloads; they are
5550 the ones we want to preserve. */
5552 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5554 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5557 int nr = HARD_REGNO_NREGS (regnum, reload_mode[r]);
5558 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5559 (on 68000) got us two FP regs. If NR is 1,
5560 we would reject both of them. */
5562 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5563 /* If we need only one reg, we have already won. */
5566 /* But reject a single reg if we demand a group. */
5571 /* Otherwise check that as many consecutive regs as we need
5573 Also, don't use for a group registers that are
5574 needed for nongroups. */
5575 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
5578 regno = regnum + nr - 1;
5579 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5580 && spill_reg_order[regno] >= 0
5581 && reload_reg_free_p (regno, reload_opnum[r],
5582 reload_when_needed[r])
5583 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
5593 /* If we found something on pass 1, omit pass 2. */
5594 if (count < n_spills)
5598 /* We should have found a spill register by now. */
5599 if (count == n_spills)
5606 /* I is the index in SPILL_REG_RTX of the reload register we are to
5607 allocate. Get an rtx for it and find its register number. */
5609 new = spill_reg_rtx[i];
5611 if (new == 0 || GET_MODE (new) != reload_mode[r])
5612 spill_reg_rtx[i] = new
5613 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5615 regno = true_regnum (new);
5617 /* Detect when the reload reg can't hold the reload mode.
5618 This used to be one `if', but Sequent compiler can't handle that. */
5619 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5621 enum machine_mode test_mode = VOIDmode;
5623 test_mode = GET_MODE (reload_in[r]);
5624 /* If reload_in[r] has VOIDmode, it means we will load it
5625 in whatever mode the reload reg has: to wit, reload_mode[r].
5626 We have already tested that for validity. */
5627 /* Aside from that, we need to test that the expressions
5628 to reload from or into have modes which are valid for this
5629 reload register. Otherwise the reload insns would be invalid. */
5630 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5631 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5632 if (! (reload_out[r] != 0
5633 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5635 /* The reg is OK. */
5638 /* Mark as in use for this insn the reload regs we use
5640 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5641 reload_when_needed[r], reload_mode[r]);
5643 reload_reg_rtx[r] = new;
5644 reload_spill_index[r] = spill_regs[i];
5649 /* The reg is not OK. */
5654 if (asm_noperands (PATTERN (insn)) < 0)
5655 /* It's the compiler's fault. */
5656 fatal_insn ("Could not find a spill register", insn);
5658 /* It's the user's fault; the operand's mode and constraint
5659 don't match. Disable this reload so we don't crash in final. */
5660 error_for_asm (insn,
5661 "`asm' operand constraint incompatible with operand size");
5664 reload_reg_rtx[r] = 0;
5665 reload_optional[r] = 1;
5666 reload_secondary_p[r] = 1;
5671 /* Assign hard reg targets for the pseudo-registers we must reload
5672 into hard regs for this insn.
5673 Also output the instructions to copy them in and out of the hard regs.
5675 For machines with register classes, we are responsible for
5676 finding a reload reg in the proper class. */
5679 choose_reload_regs (chain)
5680 struct insn_chain *chain;
5682 rtx insn = chain->insn;
5684 int max_group_size = 1;
5685 enum reg_class group_class = NO_REGS;
5689 rtx save_reload_reg_rtx[MAX_RELOADS];
5690 char save_reload_inherited[MAX_RELOADS];
5691 rtx save_reload_inheritance_insn[MAX_RELOADS];
5692 rtx save_reload_override_in[MAX_RELOADS];
5693 int save_reload_spill_index[MAX_RELOADS];
5694 HARD_REG_SET save_reload_reg_used;
5695 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5696 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5697 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5698 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5699 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5700 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5701 HARD_REG_SET save_reload_reg_used_in_op_addr;
5702 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5703 HARD_REG_SET save_reload_reg_used_in_insn;
5704 HARD_REG_SET save_reload_reg_used_in_other_addr;
5705 HARD_REG_SET save_reload_reg_used_at_all;
5707 bzero (reload_inherited, MAX_RELOADS);
5708 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5709 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5711 CLEAR_HARD_REG_SET (reload_reg_used);
5712 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5713 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5714 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5715 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5716 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5718 CLEAR_HARD_REG_SET (reg_used_in_insn);
5721 REG_SET_TO_HARD_REG_SET (tmp, chain->live_before);
5722 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5723 REG_SET_TO_HARD_REG_SET (tmp, chain->live_after);
5724 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5725 compute_use_by_pseudos (®_used_in_insn, chain->live_before);
5726 compute_use_by_pseudos (®_used_in_insn, chain->live_after);
5728 for (i = 0; i < reload_n_operands; i++)
5730 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5731 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5732 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5733 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5734 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5735 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5738 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5740 #if 0 /* Not needed, now that we can always retry without inheritance. */
5741 /* See if we have more mandatory reloads than spill regs.
5742 If so, then we cannot risk optimizations that could prevent
5743 reloads from sharing one spill register.
5745 Since we will try finding a better register than reload_reg_rtx
5746 unless it is equal to reload_in or reload_out, count such reloads. */
5750 for (j = 0; j < n_reloads; j++)
5751 if (! reload_optional[j]
5752 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5753 && (reload_reg_rtx[j] == 0
5754 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5755 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5762 /* In order to be certain of getting the registers we need,
5763 we must sort the reloads into order of increasing register class.
5764 Then our grabbing of reload registers will parallel the process
5765 that provided the reload registers.
5767 Also note whether any of the reloads wants a consecutive group of regs.
5768 If so, record the maximum size of the group desired and what
5769 register class contains all the groups needed by this insn. */
5771 for (j = 0; j < n_reloads; j++)
5773 reload_order[j] = j;
5774 reload_spill_index[j] = -1;
5777 = (reload_inmode[j] == VOIDmode
5778 || (GET_MODE_SIZE (reload_outmode[j])
5779 > GET_MODE_SIZE (reload_inmode[j])))
5780 ? reload_outmode[j] : reload_inmode[j];
5782 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5784 if (reload_nregs[j] > 1)
5786 max_group_size = MAX (reload_nregs[j], max_group_size);
5787 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5790 /* If we have already decided to use a certain register,
5791 don't use it in another way. */
5792 if (reload_reg_rtx[j])
5793 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5794 reload_when_needed[j], reload_mode[j]);
5798 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5800 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5801 sizeof reload_reg_rtx);
5802 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5803 bcopy ((char *) reload_inheritance_insn,
5804 (char *) save_reload_inheritance_insn,
5805 sizeof reload_inheritance_insn);
5806 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5807 sizeof reload_override_in);
5808 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5809 sizeof reload_spill_index);
5810 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5811 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5812 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5813 reload_reg_used_in_op_addr);
5815 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5816 reload_reg_used_in_op_addr_reload);
5818 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5819 reload_reg_used_in_insn);
5820 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5821 reload_reg_used_in_other_addr);
5823 for (i = 0; i < reload_n_operands; i++)
5825 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5826 reload_reg_used_in_output[i]);
5827 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5828 reload_reg_used_in_input[i]);
5829 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5830 reload_reg_used_in_input_addr[i]);
5831 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5832 reload_reg_used_in_inpaddr_addr[i]);
5833 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5834 reload_reg_used_in_output_addr[i]);
5835 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5836 reload_reg_used_in_outaddr_addr[i]);
5839 /* If -O, try first with inheritance, then turning it off.
5840 If not -O, don't do inheritance.
5841 Using inheritance when not optimizing leads to paradoxes
5842 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5843 because one side of the comparison might be inherited. */
5845 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5847 /* Process the reloads in order of preference just found.
5848 Beyond this point, subregs can be found in reload_reg_rtx.
5850 This used to look for an existing reloaded home for all
5851 of the reloads, and only then perform any new reloads.
5852 But that could lose if the reloads were done out of reg-class order
5853 because a later reload with a looser constraint might have an old
5854 home in a register needed by an earlier reload with a tighter constraint.
5856 To solve this, we make two passes over the reloads, in the order
5857 described above. In the first pass we try to inherit a reload
5858 from a previous insn. If there is a later reload that needs a
5859 class that is a proper subset of the class being processed, we must
5860 also allocate a spill register during the first pass.
5862 Then make a second pass over the reloads to allocate any reloads
5863 that haven't been given registers yet. */
5865 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5867 for (j = 0; j < n_reloads; j++)
5869 register int r = reload_order[j];
5870 rtx search_equiv = NULL_RTX;
5872 /* Ignore reloads that got marked inoperative. */
5873 if (reload_out[r] == 0 && reload_in[r] == 0
5874 && ! reload_secondary_p[r])
5877 /* If find_reloads chose to use reload_in or reload_out as a reload
5878 register, we don't need to chose one. Otherwise, try even if it
5879 found one since we might save an insn if we find the value lying
5881 Try also when reload_in is a pseudo without a hard reg. */
5882 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5883 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5884 || (rtx_equal_p (reload_out[r], reload_reg_rtx[r])
5885 && GET_CODE (reload_in[r]) != MEM
5886 && true_regnum (reload_in[r]) < FIRST_PSEUDO_REGISTER)))
5889 #if 0 /* No longer needed for correct operation.
5890 It might give better code, or might not; worth an experiment? */
5891 /* If this is an optional reload, we can't inherit from earlier insns
5892 until we are sure that any non-optional reloads have been allocated.
5893 The following code takes advantage of the fact that optional reloads
5894 are at the end of reload_order. */
5895 if (reload_optional[r] != 0)
5896 for (i = 0; i < j; i++)
5897 if ((reload_out[reload_order[i]] != 0
5898 || reload_in[reload_order[i]] != 0
5899 || reload_secondary_p[reload_order[i]])
5900 && ! reload_optional[reload_order[i]]
5901 && reload_reg_rtx[reload_order[i]] == 0)
5902 allocate_reload_reg (chain, reload_order[i], 0, inheritance);
5905 /* First see if this pseudo is already available as reloaded
5906 for a previous insn. We cannot try to inherit for reloads
5907 that are smaller than the maximum number of registers needed
5908 for groups unless the register we would allocate cannot be used
5911 We could check here to see if this is a secondary reload for
5912 an object that is already in a register of the desired class.
5913 This would avoid the need for the secondary reload register.
5914 But this is complex because we can't easily determine what
5915 objects might want to be loaded via this reload. So let a
5916 register be allocated here. In `emit_reload_insns' we suppress
5917 one of the loads in the case described above. */
5922 register int regno = -1;
5923 enum machine_mode mode;
5925 if (reload_in[r] == 0)
5927 else if (GET_CODE (reload_in[r]) == REG)
5929 regno = REGNO (reload_in[r]);
5930 mode = GET_MODE (reload_in[r]);
5932 else if (GET_CODE (reload_in_reg[r]) == REG)
5934 regno = REGNO (reload_in_reg[r]);
5935 mode = GET_MODE (reload_in_reg[r]);
5937 else if (GET_CODE (reload_in_reg[r]) == SUBREG
5938 && GET_CODE (SUBREG_REG (reload_in_reg[r])) == REG)
5940 word = SUBREG_WORD (reload_in_reg[r]);
5941 regno = REGNO (SUBREG_REG (reload_in_reg[r]));
5942 if (regno < FIRST_PSEUDO_REGISTER)
5944 mode = GET_MODE (reload_in_reg[r]);
5947 else if ((GET_CODE (reload_in_reg[r]) == PRE_INC
5948 || GET_CODE (reload_in_reg[r]) == PRE_DEC
5949 || GET_CODE (reload_in_reg[r]) == POST_INC
5950 || GET_CODE (reload_in_reg[r]) == POST_DEC)
5951 && GET_CODE (XEXP (reload_in_reg[r], 0)) == REG)
5953 regno = REGNO (XEXP (reload_in_reg[r], 0));
5954 mode = GET_MODE (XEXP (reload_in_reg[r], 0));
5955 reload_out[r] = reload_in[r];
5959 /* This won't work, since REGNO can be a pseudo reg number.
5960 Also, it takes much more hair to keep track of all the things
5961 that can invalidate an inherited reload of part of a pseudoreg. */
5962 else if (GET_CODE (reload_in[r]) == SUBREG
5963 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5964 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5967 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5969 enum reg_class class = reload_reg_class[r], last_class;
5970 rtx last_reg = reg_last_reload_reg[regno];
5972 i = REGNO (last_reg) + word;
5973 last_class = REGNO_REG_CLASS (i);
5974 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5975 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5976 && reg_reloaded_contents[i] == regno
5977 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5978 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5979 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5980 /* Even if we can't use this register as a reload
5981 register, we might use it for reload_override_in,
5982 if copying it to the desired class is cheap
5984 || ((REGISTER_MOVE_COST (last_class, class)
5985 < MEMORY_MOVE_COST (mode, class, 1))
5986 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5987 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5991 #ifdef SECONDARY_MEMORY_NEEDED
5992 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5997 && (reload_nregs[r] == max_group_size
5998 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6000 && free_for_value_p (i, reload_mode[r], reload_opnum[r],
6001 reload_when_needed[r], reload_in[r],
6004 /* If a group is needed, verify that all the subsequent
6005 registers still have their values intact. */
6007 = HARD_REGNO_NREGS (i, reload_mode[r]);
6010 for (k = 1; k < nr; k++)
6011 if (reg_reloaded_contents[i + k] != regno
6012 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6019 last_reg = (GET_MODE (last_reg) == mode
6020 ? last_reg : gen_rtx_REG (mode, i));
6022 /* We found a register that contains the
6023 value we need. If this register is the
6024 same as an `earlyclobber' operand of the
6025 current insn, just mark it as a place to
6026 reload from since we can't use it as the
6027 reload register itself. */
6029 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6030 if (reg_overlap_mentioned_for_reload_p
6031 (reg_last_reload_reg[regno],
6032 reload_earlyclobbers[i1]))
6035 if (i1 != n_earlyclobbers
6036 || ! (free_for_value_p (i, reload_mode[r],
6038 reload_when_needed[r],
6040 reload_out[r], r, 1))
6041 /* Don't use it if we'd clobber a pseudo reg. */
6042 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6044 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6045 /* Don't clobber the frame pointer. */
6046 || (i == HARD_FRAME_POINTER_REGNUM
6048 /* Don't really use the inherited spill reg
6049 if we need it wider than we've got it. */
6050 || (GET_MODE_SIZE (reload_mode[r])
6051 > GET_MODE_SIZE (mode))
6052 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
6055 /* If find_reloads chose reload_out as reload
6056 register, stay with it - that leaves the
6057 inherited register for subsequent reloads. */
6058 || (reload_out[r] && reload_reg_rtx[r]
6059 && rtx_equal_p (reload_out[r],
6060 reload_reg_rtx[r])))
6062 if (! reload_optional[r])
6064 reload_override_in[r] = last_reg;
6065 reload_inheritance_insn[r]
6066 = reg_reloaded_insn[i];
6072 /* We can use this as a reload reg. */
6073 /* Mark the register as in use for this part of
6075 mark_reload_reg_in_use (i,
6077 reload_when_needed[r],
6079 reload_reg_rtx[r] = last_reg;
6080 reload_inherited[r] = 1;
6081 reload_inheritance_insn[r]
6082 = reg_reloaded_insn[i];
6083 reload_spill_index[r] = i;
6084 for (k = 0; k < nr; k++)
6085 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6093 /* Here's another way to see if the value is already lying around. */
6095 && reload_in[r] != 0
6096 && ! reload_inherited[r]
6097 && reload_out[r] == 0
6098 && (CONSTANT_P (reload_in[r])
6099 || GET_CODE (reload_in[r]) == PLUS
6100 || GET_CODE (reload_in[r]) == REG
6101 || GET_CODE (reload_in[r]) == MEM)
6102 && (reload_nregs[r] == max_group_size
6103 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
6104 search_equiv = reload_in[r];
6105 /* If this is an output reload from a simple move insn, look
6106 if an equivalence for the input is available. */
6107 else if (inheritance && reload_in[r] == 0 && reload_out[r] != 0)
6109 rtx set = single_set (insn);
6112 && rtx_equal_p (reload_out[r], SET_DEST (set))
6113 && CONSTANT_P (SET_SRC (set)))
6114 search_equiv = SET_SRC (set);
6120 = find_equiv_reg (search_equiv, insn, reload_reg_class[r],
6121 -1, NULL_PTR, 0, reload_mode[r]);
6126 if (GET_CODE (equiv) == REG)
6127 regno = REGNO (equiv);
6128 else if (GET_CODE (equiv) == SUBREG)
6130 /* This must be a SUBREG of a hard register.
6131 Make a new REG since this might be used in an
6132 address and not all machines support SUBREGs
6134 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
6135 equiv = gen_rtx_REG (reload_mode[r], regno);
6141 /* If we found a spill reg, reject it unless it is free
6142 and of the desired class. */
6144 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
6145 && ! free_for_value_p (regno, reload_mode[r],
6147 reload_when_needed[r],
6148 reload_in[r], reload_out[r], r,
6150 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
6154 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
6157 /* We found a register that contains the value we need.
6158 If this register is the same as an `earlyclobber' operand
6159 of the current insn, just mark it as a place to reload from
6160 since we can't use it as the reload register itself. */
6163 for (i = 0; i < n_earlyclobbers; i++)
6164 if (reg_overlap_mentioned_for_reload_p (equiv,
6165 reload_earlyclobbers[i]))
6167 if (! reload_optional[r])
6168 reload_override_in[r] = equiv;
6173 /* If the equiv register we have found is explicitly clobbered
6174 in the current insn, it depends on the reload type if we
6175 can use it, use it for reload_override_in, or not at all.
6176 In particular, we then can't use EQUIV for a
6177 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6179 if (equiv != 0 && regno_clobbered_p (regno, insn,
6182 switch (reload_when_needed[r])
6184 case RELOAD_FOR_OTHER_ADDRESS:
6185 case RELOAD_FOR_INPADDR_ADDRESS:
6186 case RELOAD_FOR_INPUT_ADDRESS:
6187 case RELOAD_FOR_OPADDR_ADDR:
6190 case RELOAD_FOR_INPUT:
6191 case RELOAD_FOR_OPERAND_ADDRESS:
6192 if (! reload_optional[r])
6193 reload_override_in[r] = equiv;
6200 else if (regno_clobbered_p (regno, insn, reload_mode[r], 1))
6201 switch (reload_when_needed[r])
6203 case RELOAD_FOR_OTHER_ADDRESS:
6204 case RELOAD_FOR_INPADDR_ADDRESS:
6205 case RELOAD_FOR_INPUT_ADDRESS:
6206 case RELOAD_FOR_OPADDR_ADDR:
6207 case RELOAD_FOR_OPERAND_ADDRESS:
6208 case RELOAD_FOR_INPUT:
6211 if (! reload_optional[r])
6212 reload_override_in[r] = equiv;
6219 /* If we found an equivalent reg, say no code need be generated
6220 to load it, and use it as our reload reg. */
6221 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
6223 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
6225 reload_reg_rtx[r] = equiv;
6226 reload_inherited[r] = 1;
6228 /* If reg_reloaded_valid is not set for this register,
6229 there might be a stale spill_reg_store lying around.
6230 We must clear it, since otherwise emit_reload_insns
6231 might delete the store. */
6232 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6233 spill_reg_store[regno] = NULL_RTX;
6234 /* If any of the hard registers in EQUIV are spill
6235 registers, mark them as in use for this insn. */
6236 for (k = 0; k < nr; k++)
6238 i = spill_reg_order[regno + k];
6241 mark_reload_reg_in_use (regno, reload_opnum[r],
6242 reload_when_needed[r],
6244 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6251 /* If we found a register to use already, or if this is an optional
6252 reload, we are done. */
6253 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
6256 #if 0 /* No longer needed for correct operation. Might or might not
6257 give better code on the average. Want to experiment? */
6259 /* See if there is a later reload that has a class different from our
6260 class that intersects our class or that requires less register
6261 than our reload. If so, we must allocate a register to this
6262 reload now, since that reload might inherit a previous reload
6263 and take the only available register in our class. Don't do this
6264 for optional reloads since they will force all previous reloads
6265 to be allocated. Also don't do this for reloads that have been
6268 for (i = j + 1; i < n_reloads; i++)
6270 int s = reload_order[i];
6272 if ((reload_in[s] == 0 && reload_out[s] == 0
6273 && ! reload_secondary_p[s])
6274 || reload_optional[s])
6277 if ((reload_reg_class[s] != reload_reg_class[r]
6278 && reg_classes_intersect_p (reload_reg_class[r],
6279 reload_reg_class[s]))
6280 || reload_nregs[s] < reload_nregs[r])
6287 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance);
6291 /* Now allocate reload registers for anything non-optional that
6292 didn't get one yet. */
6293 for (j = 0; j < n_reloads; j++)
6295 register int r = reload_order[j];
6297 /* Ignore reloads that got marked inoperative. */
6298 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
6301 /* Skip reloads that already have a register allocated or are
6303 if (reload_reg_rtx[r] != 0 || reload_optional[r])
6306 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
6310 /* If that loop got all the way, we have won. */
6314 /* Loop around and try without any inheritance. */
6315 /* First undo everything done by the failed attempt
6316 to allocate with inheritance. */
6317 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
6318 sizeof reload_reg_rtx);
6319 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
6320 sizeof reload_inherited);
6321 bcopy ((char *) save_reload_inheritance_insn,
6322 (char *) reload_inheritance_insn,
6323 sizeof reload_inheritance_insn);
6324 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
6325 sizeof reload_override_in);
6326 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
6327 sizeof reload_spill_index);
6328 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
6329 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
6330 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
6331 save_reload_reg_used_in_op_addr);
6332 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
6333 save_reload_reg_used_in_op_addr_reload);
6334 COPY_HARD_REG_SET (reload_reg_used_in_insn,
6335 save_reload_reg_used_in_insn);
6336 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
6337 save_reload_reg_used_in_other_addr);
6339 for (i = 0; i < reload_n_operands; i++)
6341 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
6342 save_reload_reg_used_in_input[i]);
6343 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
6344 save_reload_reg_used_in_output[i]);
6345 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
6346 save_reload_reg_used_in_input_addr[i]);
6347 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
6348 save_reload_reg_used_in_inpaddr_addr[i]);
6349 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
6350 save_reload_reg_used_in_output_addr[i]);
6351 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
6352 save_reload_reg_used_in_outaddr_addr[i]);
6356 /* If we thought we could inherit a reload, because it seemed that
6357 nothing else wanted the same reload register earlier in the insn,
6358 verify that assumption, now that all reloads have been assigned.
6359 Likewise for reloads where reload_override_in has been set. */
6361 /* If doing expensive optimizations, do one preliminary pass that doesn't
6362 cancel any inheritance, but removes reloads that have been needed only
6363 for reloads that we know can be inherited. */
6364 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6366 for (j = 0; j < n_reloads; j++)
6368 register int r = reload_order[j];
6370 if (reload_inherited[r] && reload_reg_rtx[r])
6371 check_reg = reload_reg_rtx[r];
6372 else if (reload_override_in[r]
6373 && (GET_CODE (reload_override_in[r]) == REG
6374 || GET_CODE (reload_override_in[r]) == SUBREG))
6375 check_reg = reload_override_in[r];
6378 if (! free_for_value_p (true_regnum (check_reg), reload_mode[r],
6379 reload_opnum[r], reload_when_needed[r],
6381 (reload_inherited[r]
6382 ? reload_out[r] : const0_rtx),
6387 reload_inherited[r] = 0;
6388 reload_override_in[r] = 0;
6390 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6391 reload_override_in, then we do not need its related
6392 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6393 likewise for other reload types.
6394 We handle this by removing a reload when its only replacement
6395 is mentioned in reload_in of the reload we are going to inherit.
6396 A special case are auto_inc expressions; even if the input is
6397 inherited, we still need the address for the output. We can
6398 recognize them because they have RELOAD_OUT set but not
6400 If we suceeded removing some reload and we are doing a preliminary
6401 pass just to remove such reloads, make another pass, since the
6402 removal of one reload might allow us to inherit another one. */
6403 else if ((! reload_out[r] || reload_out_reg[r])
6405 && remove_address_replacements (reload_in[r]) && pass)
6410 /* Now that reload_override_in is known valid,
6411 actually override reload_in. */
6412 for (j = 0; j < n_reloads; j++)
6413 if (reload_override_in[j])
6414 reload_in[j] = reload_override_in[j];
6416 /* If this reload won't be done because it has been cancelled or is
6417 optional and not inherited, clear reload_reg_rtx so other
6418 routines (such as subst_reloads) don't get confused. */
6419 for (j = 0; j < n_reloads; j++)
6420 if (reload_reg_rtx[j] != 0
6421 && ((reload_optional[j] && ! reload_inherited[j])
6422 || (reload_in[j] == 0 && reload_out[j] == 0
6423 && ! reload_secondary_p[j])))
6425 int regno = true_regnum (reload_reg_rtx[j]);
6427 if (spill_reg_order[regno] >= 0)
6428 clear_reload_reg_in_use (regno, reload_opnum[j],
6429 reload_when_needed[j], reload_mode[j]);
6430 reload_reg_rtx[j] = 0;
6431 reload_spill_index[j] = -1;
6434 /* Record which pseudos and which spill regs have output reloads. */
6435 for (j = 0; j < n_reloads; j++)
6437 register int r = reload_order[j];
6439 i = reload_spill_index[r];
6441 /* I is nonneg if this reload uses a register.
6442 If reload_reg_rtx[r] is 0, this is an optional reload
6443 that we opted to ignore. */
6444 if (reload_out_reg[r] != 0 && GET_CODE (reload_out_reg[r]) == REG
6445 && reload_reg_rtx[r] != 0)
6447 register int nregno = REGNO (reload_out_reg[r]);
6450 if (nregno < FIRST_PSEUDO_REGISTER)
6451 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
6454 reg_has_output_reload[nregno + nr] = 1;
6458 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
6460 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6463 if (reload_when_needed[r] != RELOAD_OTHER
6464 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
6465 && reload_when_needed[r] != RELOAD_FOR_INSN)
6471 /* Deallocate the reload register for reload R. This is called from
6472 remove_address_replacements. */
6474 deallocate_reload_reg (r)
6479 if (! reload_reg_rtx[r])
6481 regno = true_regnum (reload_reg_rtx[r]);
6482 reload_reg_rtx[r] = 0;
6483 if (spill_reg_order[regno] >= 0)
6484 clear_reload_reg_in_use (regno, reload_opnum[r], reload_when_needed[r],
6486 reload_spill_index[r] = -1;
6489 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6490 reloads of the same item for fear that we might not have enough reload
6491 registers. However, normally they will get the same reload register
6492 and hence actually need not be loaded twice.
6494 Here we check for the most common case of this phenomenon: when we have
6495 a number of reloads for the same object, each of which were allocated
6496 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6497 reload, and is not modified in the insn itself. If we find such,
6498 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6499 This will not increase the number of spill registers needed and will
6500 prevent redundant code. */
6503 merge_assigned_reloads (insn)
6508 /* Scan all the reloads looking for ones that only load values and
6509 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6510 assigned and not modified by INSN. */
6512 for (i = 0; i < n_reloads; i++)
6514 int conflicting_input = 0;
6515 int max_input_address_opnum = -1;
6516 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6518 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
6519 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
6520 || reg_set_p (reload_reg_rtx[i], insn))
6523 /* Look at all other reloads. Ensure that the only use of this
6524 reload_reg_rtx is in a reload that just loads the same value
6525 as we do. Note that any secondary reloads must be of the identical
6526 class since the values, modes, and result registers are the
6527 same, so we need not do anything with any secondary reloads. */
6529 for (j = 0; j < n_reloads; j++)
6531 if (i == j || reload_reg_rtx[j] == 0
6532 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
6536 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6537 && reload_opnum[j] > max_input_address_opnum)
6538 max_input_address_opnum = reload_opnum[j];
6540 /* If the reload regs aren't exactly the same (e.g, different modes)
6541 or if the values are different, we can't merge this reload.
6542 But if it is an input reload, we might still merge
6543 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6545 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6546 || reload_out[j] != 0 || reload_in[j] == 0
6547 || ! rtx_equal_p (reload_in[i], reload_in[j]))
6549 if (reload_when_needed[j] != RELOAD_FOR_INPUT
6550 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
6551 || reload_opnum[i] > reload_opnum[j])
6552 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
6554 conflicting_input = 1;
6555 if (min_conflicting_input_opnum > reload_opnum[j])
6556 min_conflicting_input_opnum = reload_opnum[j];
6560 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6561 we, in fact, found any matching reloads. */
6564 && max_input_address_opnum <= min_conflicting_input_opnum)
6566 for (j = 0; j < n_reloads; j++)
6567 if (i != j && reload_reg_rtx[j] != 0
6568 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6569 && (! conflicting_input
6570 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6571 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
6573 reload_when_needed[i] = RELOAD_OTHER;
6575 reload_spill_index[j] = -1;
6576 transfer_replacements (i, j);
6579 /* If this is now RELOAD_OTHER, look for any reloads that load
6580 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6581 if they were for inputs, RELOAD_OTHER for outputs. Note that
6582 this test is equivalent to looking for reloads for this operand
6585 if (reload_when_needed[i] == RELOAD_OTHER)
6586 for (j = 0; j < n_reloads; j++)
6587 if (reload_in[j] != 0
6588 && reload_when_needed[i] != RELOAD_OTHER
6589 && reg_overlap_mentioned_for_reload_p (reload_in[j],
6591 reload_when_needed[j]
6592 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6593 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6594 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6600 /* Output insns to reload values in and out of the chosen reload regs. */
6603 emit_reload_insns (chain)
6604 struct insn_chain *chain;
6606 rtx insn = chain->insn;
6609 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6610 rtx other_input_address_reload_insns = 0;
6611 rtx other_input_reload_insns = 0;
6612 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6613 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6614 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6615 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6616 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6617 rtx operand_reload_insns = 0;
6618 rtx other_operand_reload_insns = 0;
6619 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6620 rtx following_insn = NEXT_INSN (insn);
6621 rtx before_insn = PREV_INSN (insn);
6623 /* Values to be put in spill_reg_store are put here first. */
6624 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6625 HARD_REG_SET reg_reloaded_died;
6627 CLEAR_HARD_REG_SET (reg_reloaded_died);
6629 for (j = 0; j < reload_n_operands; j++)
6630 input_reload_insns[j] = input_address_reload_insns[j]
6631 = inpaddr_address_reload_insns[j]
6632 = output_reload_insns[j] = output_address_reload_insns[j]
6633 = outaddr_address_reload_insns[j]
6634 = other_output_reload_insns[j] = 0;
6636 /* Now output the instructions to copy the data into and out of the
6637 reload registers. Do these in the order that the reloads were reported,
6638 since reloads of base and index registers precede reloads of operands
6639 and the operands may need the base and index registers reloaded. */
6641 for (j = 0; j < n_reloads; j++)
6644 rtx oldequiv_reg = 0;
6645 rtx this_reload_insn = 0;
6646 int expect_occurrences = 1;
6648 if (reload_reg_rtx[j]
6649 && REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
6650 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = 0;
6652 old = (reload_in[j] && GET_CODE (reload_in[j]) == MEM
6653 ? reload_in_reg[j] : reload_in[j]);
6656 /* AUTO_INC reloads need to be handled even if inherited. We got an
6657 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6658 && (! reload_inherited[j] || (reload_out[j] && ! reload_out_reg[j]))
6659 && ! rtx_equal_p (reload_reg_rtx[j], old)
6660 && reload_reg_rtx[j] != 0)
6662 register rtx reloadreg = reload_reg_rtx[j];
6664 enum machine_mode mode;
6667 /* Determine the mode to reload in.
6668 This is very tricky because we have three to choose from.
6669 There is the mode the insn operand wants (reload_inmode[J]).
6670 There is the mode of the reload register RELOADREG.
6671 There is the intrinsic mode of the operand, which we could find
6672 by stripping some SUBREGs.
6673 It turns out that RELOADREG's mode is irrelevant:
6674 we can change that arbitrarily.
6676 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6677 then the reload reg may not support QImode moves, so use SImode.
6678 If foo is in memory due to spilling a pseudo reg, this is safe,
6679 because the QImode value is in the least significant part of a
6680 slot big enough for a SImode. If foo is some other sort of
6681 memory reference, then it is impossible to reload this case,
6682 so previous passes had better make sure this never happens.
6684 Then consider a one-word union which has SImode and one of its
6685 members is a float, being fetched as (SUBREG:SF union:SI).
6686 We must fetch that as SFmode because we could be loading into
6687 a float-only register. In this case OLD's mode is correct.
6689 Consider an immediate integer: it has VOIDmode. Here we need
6690 to get a mode from something else.
6692 In some cases, there is a fourth mode, the operand's
6693 containing mode. If the insn specifies a containing mode for
6694 this operand, it overrides all others.
6696 I am not sure whether the algorithm here is always right,
6697 but it does the right things in those cases. */
6699 mode = GET_MODE (old);
6700 if (mode == VOIDmode)
6701 mode = reload_inmode[j];
6703 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6704 /* If we need a secondary register for this operation, see if
6705 the value is already in a register in that class. Don't
6706 do this if the secondary register will be used as a scratch
6709 if (reload_secondary_in_reload[j] >= 0
6710 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6713 = find_equiv_reg (old, insn,
6714 reload_reg_class[reload_secondary_in_reload[j]],
6715 -1, NULL_PTR, 0, mode);
6718 /* If reloading from memory, see if there is a register
6719 that already holds the same value. If so, reload from there.
6720 We can pass 0 as the reload_reg_p argument because
6721 any other reload has either already been emitted,
6722 in which case find_equiv_reg will see the reload-insn,
6723 or has yet to be emitted, in which case it doesn't matter
6724 because we will use this equiv reg right away. */
6726 if (oldequiv == 0 && optimize
6727 && (GET_CODE (old) == MEM
6728 || (GET_CODE (old) == REG
6729 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6730 && reg_renumber[REGNO (old)] < 0)))
6731 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6732 -1, NULL_PTR, 0, mode);
6736 int regno = true_regnum (oldequiv);
6738 /* Don't use OLDEQUIV if any other reload changes it at an
6739 earlier stage of this insn or at this stage. */
6740 if (! free_for_value_p (regno, reload_mode[j],
6742 reload_when_needed[j],
6743 reload_in[j], const0_rtx, j, 0))
6746 /* If it is no cheaper to copy from OLDEQUIV into the
6747 reload register than it would be to move from memory,
6748 don't use it. Likewise, if we need a secondary register
6752 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6753 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6754 reload_reg_class[j])
6755 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
6756 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6757 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6761 #ifdef SECONDARY_MEMORY_NEEDED
6762 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6763 reload_reg_class[j],
6770 /* delete_output_reload is only invoked properly if old contains
6771 the original pseudo register. Since this is replaced with a
6772 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6773 find the pseudo in RELOAD_IN_REG. */
6775 && reload_override_in[j]
6776 && GET_CODE (reload_in_reg[j]) == REG)
6779 old = reload_in_reg[j];
6783 else if (GET_CODE (oldequiv) == REG)
6784 oldequiv_reg = oldequiv;
6785 else if (GET_CODE (oldequiv) == SUBREG)
6786 oldequiv_reg = SUBREG_REG (oldequiv);
6788 /* If we are reloading from a register that was recently stored in
6789 with an output-reload, see if we can prove there was
6790 actually no need to store the old value in it. */
6792 if (optimize && GET_CODE (oldequiv) == REG
6793 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6794 && spill_reg_store[REGNO (oldequiv)]
6795 && GET_CODE (old) == REG
6796 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6797 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6798 reload_out_reg[j])))
6799 delete_output_reload (insn, j, REGNO (oldequiv));
6801 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6802 then load RELOADREG from OLDEQUIV. Note that we cannot use
6803 gen_lowpart_common since it can do the wrong thing when
6804 RELOADREG has a multi-word mode. Note that RELOADREG
6805 must always be a REG here. */
6807 if (GET_MODE (reloadreg) != mode)
6808 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6809 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6810 oldequiv = SUBREG_REG (oldequiv);
6811 if (GET_MODE (oldequiv) != VOIDmode
6812 && mode != GET_MODE (oldequiv))
6813 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6815 /* Switch to the right place to emit the reload insns. */
6816 switch (reload_when_needed[j])
6819 where = &other_input_reload_insns;
6821 case RELOAD_FOR_INPUT:
6822 where = &input_reload_insns[reload_opnum[j]];
6824 case RELOAD_FOR_INPUT_ADDRESS:
6825 where = &input_address_reload_insns[reload_opnum[j]];
6827 case RELOAD_FOR_INPADDR_ADDRESS:
6828 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6830 case RELOAD_FOR_OUTPUT_ADDRESS:
6831 where = &output_address_reload_insns[reload_opnum[j]];
6833 case RELOAD_FOR_OUTADDR_ADDRESS:
6834 where = &outaddr_address_reload_insns[reload_opnum[j]];
6836 case RELOAD_FOR_OPERAND_ADDRESS:
6837 where = &operand_reload_insns;
6839 case RELOAD_FOR_OPADDR_ADDR:
6840 where = &other_operand_reload_insns;
6842 case RELOAD_FOR_OTHER_ADDRESS:
6843 where = &other_input_address_reload_insns;
6849 push_to_sequence (*where);
6852 /* Auto-increment addresses must be reloaded in a special way. */
6853 if (reload_out[j] && ! reload_out_reg[j])
6855 /* We are not going to bother supporting the case where a
6856 incremented register can't be copied directly from
6857 OLDEQUIV since this seems highly unlikely. */
6858 if (reload_secondary_in_reload[j] >= 0)
6861 if (reload_inherited[j])
6862 oldequiv = reloadreg;
6864 old = XEXP (reload_in_reg[j], 0);
6866 if (optimize && GET_CODE (oldequiv) == REG
6867 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6868 && spill_reg_store[REGNO (oldequiv)]
6869 && GET_CODE (old) == REG
6870 && (dead_or_set_p (insn,
6871 spill_reg_stored_to[REGNO (oldequiv)])
6872 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6874 delete_output_reload (insn, j, REGNO (oldequiv));
6876 /* Prevent normal processing of this reload. */
6878 /* Output a special code sequence for this case. */
6879 new_spill_reg_store[REGNO (reloadreg)]
6880 = inc_for_reload (reloadreg, oldequiv, reload_out[j],
6884 /* If we are reloading a pseudo-register that was set by the previous
6885 insn, see if we can get rid of that pseudo-register entirely
6886 by redirecting the previous insn into our reload register. */
6888 else if (optimize && GET_CODE (old) == REG
6889 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6890 && dead_or_set_p (insn, old)
6891 /* This is unsafe if some other reload
6892 uses the same reg first. */
6893 && ! conflicts_with_override (reloadreg)
6894 && free_for_value_p (REGNO (reloadreg), reload_mode[j],
6895 reload_opnum[j], reload_when_needed[j],
6896 old, reload_out[j], j, 0))
6898 rtx temp = PREV_INSN (insn);
6899 while (temp && GET_CODE (temp) == NOTE)
6900 temp = PREV_INSN (temp);
6902 && GET_CODE (temp) == INSN
6903 && GET_CODE (PATTERN (temp)) == SET
6904 && SET_DEST (PATTERN (temp)) == old
6905 /* Make sure we can access insn_operand_constraint. */
6906 && asm_noperands (PATTERN (temp)) < 0
6907 /* This is unsafe if prev insn rejects our reload reg. */
6908 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6910 /* This is unsafe if operand occurs more than once in current
6911 insn. Perhaps some occurrences aren't reloaded. */
6912 && count_occurrences (PATTERN (insn), old) == 1
6913 /* Don't risk splitting a matching pair of operands. */
6914 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6916 /* Store into the reload register instead of the pseudo. */
6917 SET_DEST (PATTERN (temp)) = reloadreg;
6919 /* If the previous insn is an output reload, the source is
6920 a reload register, and its spill_reg_store entry will
6921 contain the previous destination. This is now
6923 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6924 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6926 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6927 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6930 /* If these are the only uses of the pseudo reg,
6931 pretend for GDB it lives in the reload reg we used. */
6932 if (REG_N_DEATHS (REGNO (old)) == 1
6933 && REG_N_SETS (REGNO (old)) == 1)
6935 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6936 alter_reg (REGNO (old), -1);
6942 /* We can't do that, so output an insn to load RELOADREG. */
6946 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6947 rtx second_reload_reg = 0;
6948 enum insn_code icode;
6950 /* If we have a secondary reload, pick up the secondary register
6951 and icode, if any. If OLDEQUIV and OLD are different or
6952 if this is an in-out reload, recompute whether or not we
6953 still need a secondary register and what the icode should
6954 be. If we still need a secondary register and the class or
6955 icode is different, go back to reloading from OLD if using
6956 OLDEQUIV means that we got the wrong type of register. We
6957 cannot have different class or icode due to an in-out reload
6958 because we don't make such reloads when both the input and
6959 output need secondary reload registers. */
6961 if (reload_secondary_in_reload[j] >= 0)
6963 int secondary_reload = reload_secondary_in_reload[j];
6964 rtx real_oldequiv = oldequiv;
6968 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6969 and similarly for OLD.
6970 See comments in get_secondary_reload in reload.c. */
6971 /* If it is a pseudo that cannot be replaced with its
6972 equivalent MEM, we must fall back to reload_in, which
6973 will have all the necessary substitutions registered.
6974 Likewise for a pseudo that can't be replaced with its
6975 equivalent constant.
6977 Take extra care for subregs of such pseudos. Note that
6978 we cannot use reg_equiv_mem in this case because it is
6979 not in the right mode. */
6982 if (GET_CODE (tmp) == SUBREG)
6983 tmp = SUBREG_REG (tmp);
6984 if (GET_CODE (tmp) == REG
6985 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6986 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6987 || reg_equiv_constant[REGNO (tmp)] != 0))
6989 if (! reg_equiv_mem[REGNO (tmp)]
6990 || num_not_at_initial_offset
6991 || GET_CODE (oldequiv) == SUBREG)
6992 real_oldequiv = reload_in[j];
6994 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6998 if (GET_CODE (tmp) == SUBREG)
6999 tmp = SUBREG_REG (tmp);
7000 if (GET_CODE (tmp) == REG
7001 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7002 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7003 || reg_equiv_constant[REGNO (tmp)] != 0))
7005 if (! reg_equiv_mem[REGNO (tmp)]
7006 || num_not_at_initial_offset
7007 || GET_CODE (old) == SUBREG)
7008 real_old = reload_in[j];
7010 real_old = reg_equiv_mem[REGNO (tmp)];
7013 second_reload_reg = reload_reg_rtx[secondary_reload];
7014 icode = reload_secondary_in_icode[j];
7016 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7017 || (reload_in[j] != 0 && reload_out[j] != 0))
7019 enum reg_class new_class
7020 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
7021 mode, real_oldequiv);
7023 if (new_class == NO_REGS)
7024 second_reload_reg = 0;
7027 enum insn_code new_icode;
7028 enum machine_mode new_mode;
7030 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
7031 REGNO (second_reload_reg)))
7032 oldequiv = old, real_oldequiv = real_old;
7035 new_icode = reload_in_optab[(int) mode];
7036 if (new_icode != CODE_FOR_nothing
7037 && ((insn_operand_predicate[(int) new_icode][0]
7038 && ! ((*insn_operand_predicate[(int) new_icode][0])
7040 || (insn_operand_predicate[(int) new_icode][1]
7041 && ! ((*insn_operand_predicate[(int) new_icode][1])
7042 (real_oldequiv, mode)))))
7043 new_icode = CODE_FOR_nothing;
7045 if (new_icode == CODE_FOR_nothing)
7048 new_mode = insn_operand_mode[(int) new_icode][2];
7050 if (GET_MODE (second_reload_reg) != new_mode)
7052 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
7054 oldequiv = old, real_oldequiv = real_old;
7057 = gen_rtx_REG (new_mode,
7058 REGNO (second_reload_reg));
7064 /* If we still need a secondary reload register, check
7065 to see if it is being used as a scratch or intermediate
7066 register and generate code appropriately. If we need
7067 a scratch register, use REAL_OLDEQUIV since the form of
7068 the insn may depend on the actual address if it is
7071 if (second_reload_reg)
7073 if (icode != CODE_FOR_nothing)
7075 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7076 second_reload_reg));
7081 /* See if we need a scratch register to load the
7082 intermediate register (a tertiary reload). */
7083 enum insn_code tertiary_icode
7084 = reload_secondary_in_icode[secondary_reload];
7086 if (tertiary_icode != CODE_FOR_nothing)
7088 rtx third_reload_reg
7089 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
7091 emit_insn ((GEN_FCN (tertiary_icode)
7092 (second_reload_reg, real_oldequiv,
7093 third_reload_reg)));
7096 gen_reload (second_reload_reg, real_oldequiv,
7098 reload_when_needed[j]);
7100 oldequiv = second_reload_reg;
7106 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7108 rtx real_oldequiv = oldequiv;
7110 if ((GET_CODE (oldequiv) == REG
7111 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7112 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7113 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7114 || (GET_CODE (oldequiv) == SUBREG
7115 && GET_CODE (SUBREG_REG (oldequiv)) == REG
7116 && (REGNO (SUBREG_REG (oldequiv))
7117 >= FIRST_PSEUDO_REGISTER)
7118 && ((reg_equiv_memory_loc
7119 [REGNO (SUBREG_REG (oldequiv))] != 0)
7120 || (reg_equiv_constant
7121 [REGNO (SUBREG_REG (oldequiv))] != 0))))
7122 real_oldequiv = reload_in[j];
7123 gen_reload (reloadreg, real_oldequiv, reload_opnum[j],
7124 reload_when_needed[j]);
7129 this_reload_insn = get_last_insn ();
7130 /* End this sequence. */
7131 *where = get_insns ();
7134 /* Update reload_override_in so that delete_address_reloads_1
7135 can see the actual register usage. */
7137 reload_override_in[j] = oldequiv;
7140 /* When inheriting a wider reload, we have a MEM in reload_in[j],
7141 e.g. inheriting a SImode output reload for
7142 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7143 if (optimize && reload_inherited[j] && reload_in[j]
7144 && GET_CODE (reload_in[j]) == MEM
7145 && GET_CODE (reload_in_reg[j]) == MEM
7146 && reload_spill_index[j] >= 0
7147 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7150 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
7152 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7155 /* If we are reloading a register that was recently stored in with an
7156 output-reload, see if we can prove there was
7157 actually no need to store the old value in it. */
7160 && (reload_inherited[j] || reload_override_in[j])
7161 && reload_reg_rtx[j]
7162 && GET_CODE (reload_reg_rtx[j]) == REG
7163 && spill_reg_store[REGNO (reload_reg_rtx[j])] != 0
7165 /* There doesn't seem to be any reason to restrict this to pseudos
7166 and doing so loses in the case where we are copying from a
7167 register of the wrong class. */
7168 && REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
7169 >= FIRST_PSEUDO_REGISTER
7171 /* The insn might have already some references to stackslots
7172 replaced by MEMs, while reload_out_reg still names the
7174 && (dead_or_set_p (insn,
7175 spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
7176 || rtx_equal_p (spill_reg_stored_to[REGNO (reload_reg_rtx[j])],
7177 reload_out_reg[j])))
7178 delete_output_reload (insn, j, REGNO (reload_reg_rtx[j]));
7180 /* Input-reloading is done. Now do output-reloading,
7181 storing the value from the reload-register after the main insn
7182 if reload_out[j] is nonzero.
7184 ??? At some point we need to support handling output reloads of
7185 JUMP_INSNs or insns that set cc0. */
7187 /* If this is an output reload that stores something that is
7188 not loaded in this same reload, see if we can eliminate a previous
7191 rtx pseudo = reload_out_reg[j];
7194 && GET_CODE (pseudo) == REG
7195 && ! rtx_equal_p (reload_in_reg[j], pseudo)
7196 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7197 && reg_last_reload_reg[REGNO (pseudo)])
7199 int pseudo_no = REGNO (pseudo);
7200 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7202 /* We don't need to test full validity of last_regno for
7203 inherit here; we only want to know if the store actually
7204 matches the pseudo. */
7205 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7206 && reg_reloaded_contents[last_regno] == pseudo_no
7207 && spill_reg_store[last_regno]
7208 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7209 delete_output_reload (insn, j, last_regno);
7213 old = reload_out_reg[j];
7215 && reload_reg_rtx[j] != old
7216 && reload_reg_rtx[j] != 0)
7218 register rtx reloadreg = reload_reg_rtx[j];
7219 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7220 register rtx second_reloadreg = 0;
7223 enum machine_mode mode;
7226 /* An output operand that dies right away does need a reload,
7227 but need not be copied from it. Show the new location in the
7229 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
7230 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7232 XEXP (note, 0) = reload_reg_rtx[j];
7235 /* Likewise for a SUBREG of an operand that dies. */
7236 else if (GET_CODE (old) == SUBREG
7237 && GET_CODE (SUBREG_REG (old)) == REG
7238 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7241 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7245 else if (GET_CODE (old) == SCRATCH)
7246 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7247 but we don't want to make an output reload. */
7251 /* Strip off of OLD any size-increasing SUBREGs such as
7252 (SUBREG:SI foo:QI 0). */
7254 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
7255 && (GET_MODE_SIZE (GET_MODE (old))
7256 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
7257 old = SUBREG_REG (old);
7260 /* If is a JUMP_INSN, we can't support output reloads yet. */
7261 if (GET_CODE (insn) == JUMP_INSN)
7264 if (reload_when_needed[j] == RELOAD_OTHER)
7267 push_to_sequence (output_reload_insns[reload_opnum[j]]);
7269 old = reload_out[j];
7271 /* Determine the mode to reload in.
7272 See comments above (for input reloading). */
7274 mode = GET_MODE (old);
7275 if (mode == VOIDmode)
7277 /* VOIDmode should never happen for an output. */
7278 if (asm_noperands (PATTERN (insn)) < 0)
7279 /* It's the compiler's fault. */
7280 fatal_insn ("VOIDmode on an output", insn);
7281 error_for_asm (insn, "output operand is constant in `asm'");
7282 /* Prevent crash--use something we know is valid. */
7284 old = gen_rtx_REG (mode, REGNO (reloadreg));
7287 if (GET_MODE (reloadreg) != mode)
7288 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7290 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7292 /* If we need two reload regs, set RELOADREG to the intermediate
7293 one, since it will be stored into OLD. We might need a secondary
7294 register only for an input reload, so check again here. */
7296 if (reload_secondary_out_reload[j] >= 0)
7300 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7301 && reg_equiv_mem[REGNO (old)] != 0)
7302 real_old = reg_equiv_mem[REGNO (old)];
7304 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
7308 second_reloadreg = reloadreg;
7309 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
7311 /* See if RELOADREG is to be used as a scratch register
7312 or as an intermediate register. */
7313 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
7315 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
7316 (real_old, second_reloadreg, reloadreg)));
7321 /* See if we need both a scratch and intermediate reload
7324 int secondary_reload = reload_secondary_out_reload[j];
7325 enum insn_code tertiary_icode
7326 = reload_secondary_out_icode[secondary_reload];
7328 if (GET_MODE (reloadreg) != mode)
7329 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7331 if (tertiary_icode != CODE_FOR_nothing)
7334 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
7337 /* Copy primary reload reg to secondary reload reg.
7338 (Note that these have been swapped above, then
7339 secondary reload reg to OLD using our insn. */
7341 /* If REAL_OLD is a paradoxical SUBREG, remove it
7342 and try to put the opposite SUBREG on
7344 if (GET_CODE (real_old) == SUBREG
7345 && (GET_MODE_SIZE (GET_MODE (real_old))
7346 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7347 && 0 != (tem = gen_lowpart_common
7348 (GET_MODE (SUBREG_REG (real_old)),
7350 real_old = SUBREG_REG (real_old), reloadreg = tem;
7352 gen_reload (reloadreg, second_reloadreg,
7353 reload_opnum[j], reload_when_needed[j]);
7354 emit_insn ((GEN_FCN (tertiary_icode)
7355 (real_old, reloadreg, third_reloadreg)));
7360 /* Copy between the reload regs here and then to
7363 gen_reload (reloadreg, second_reloadreg,
7364 reload_opnum[j], reload_when_needed[j]);
7370 /* Output the last reload insn. */
7375 /* Don't output the last reload if OLD is not the dest of
7376 INSN and is in the src and is clobbered by INSN. */
7377 if (! flag_expensive_optimizations
7378 || GET_CODE (old) != REG
7379 || !(set = single_set (insn))
7380 || rtx_equal_p (old, SET_DEST (set))
7381 || !reg_mentioned_p (old, SET_SRC (set))
7382 || !regno_clobbered_p (REGNO (old), insn, reload_mode[j], 0))
7383 gen_reload (old, reloadreg, reload_opnum[j],
7384 reload_when_needed[j]);
7387 /* Look at all insns we emitted, just to be safe. */
7388 for (p = get_insns (); p; p = NEXT_INSN (p))
7389 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7391 rtx pat = PATTERN (p);
7393 /* If this output reload doesn't come from a spill reg,
7394 clear any memory of reloaded copies of the pseudo reg.
7395 If this output reload comes from a spill reg,
7396 reg_has_output_reload will make this do nothing. */
7397 note_stores (pat, forget_old_reloads_1);
7399 if (reg_mentioned_p (reload_reg_rtx[j], pat))
7401 rtx set = single_set (insn);
7402 if (reload_spill_index[j] < 0
7404 && SET_SRC (set) == reload_reg_rtx[j])
7406 int src = REGNO (SET_SRC (set));
7408 reload_spill_index[j] = src;
7409 SET_HARD_REG_BIT (reg_is_output_reload, src);
7410 if (find_regno_note (insn, REG_DEAD, src))
7411 SET_HARD_REG_BIT (reg_reloaded_died, src);
7413 if (REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
7415 int s = reload_secondary_out_reload[j];
7416 set = single_set (p);
7417 /* If this reload copies only to the secondary reload
7418 register, the secondary reload does the actual
7420 if (s >= 0 && set == NULL_RTX)
7421 ; /* We can't tell what function the secondary reload
7422 has and where the actual store to the pseudo is
7423 made; leave new_spill_reg_store alone. */
7425 && SET_SRC (set) == reload_reg_rtx[j]
7426 && SET_DEST (set) == reload_reg_rtx[s])
7428 /* Usually the next instruction will be the
7429 secondary reload insn; if we can confirm
7430 that it is, setting new_spill_reg_store to
7431 that insn will allow an extra optimization. */
7432 rtx s_reg = reload_reg_rtx[s];
7433 rtx next = NEXT_INSN (p);
7434 reload_out[s] = reload_out[j];
7435 reload_out_reg[s] = reload_out_reg[j];
7436 set = single_set (next);
7437 if (set && SET_SRC (set) == s_reg
7438 && ! new_spill_reg_store[REGNO (s_reg)])
7440 SET_HARD_REG_BIT (reg_is_output_reload,
7442 new_spill_reg_store[REGNO (s_reg)] = next;
7446 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = p;
7451 if (reload_when_needed[j] == RELOAD_OTHER)
7453 emit_insns (other_output_reload_insns[reload_opnum[j]]);
7454 other_output_reload_insns[reload_opnum[j]] = get_insns ();
7457 output_reload_insns[reload_opnum[j]] = get_insns ();
7463 /* Now write all the insns we made for reloads in the order expected by
7464 the allocation functions. Prior to the insn being reloaded, we write
7465 the following reloads:
7467 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7469 RELOAD_OTHER reloads.
7471 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7472 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7473 RELOAD_FOR_INPUT reload for the operand.
7475 RELOAD_FOR_OPADDR_ADDRS reloads.
7477 RELOAD_FOR_OPERAND_ADDRESS reloads.
7479 After the insn being reloaded, we write the following:
7481 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7482 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7483 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7484 reloads for the operand. The RELOAD_OTHER output reloads are
7485 output in descending order by reload number. */
7487 emit_insns_before (other_input_address_reload_insns, insn);
7488 emit_insns_before (other_input_reload_insns, insn);
7490 for (j = 0; j < reload_n_operands; j++)
7492 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7493 emit_insns_before (input_address_reload_insns[j], insn);
7494 emit_insns_before (input_reload_insns[j], insn);
7497 emit_insns_before (other_operand_reload_insns, insn);
7498 emit_insns_before (operand_reload_insns, insn);
7500 for (j = 0; j < reload_n_operands; j++)
7502 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7503 emit_insns_before (output_address_reload_insns[j], following_insn);
7504 emit_insns_before (output_reload_insns[j], following_insn);
7505 emit_insns_before (other_output_reload_insns[j], following_insn);
7508 /* Keep basic block info up to date. */
7511 if (BLOCK_HEAD (chain->block) == insn)
7512 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7513 if (BLOCK_END (chain->block) == insn)
7514 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7517 /* For all the spill regs newly reloaded in this instruction,
7518 record what they were reloaded from, so subsequent instructions
7519 can inherit the reloads.
7521 Update spill_reg_store for the reloads of this insn.
7522 Copy the elements that were updated in the loop above. */
7524 for (j = 0; j < n_reloads; j++)
7526 register int r = reload_order[j];
7527 register int i = reload_spill_index[r];
7529 /* If this is a non-inherited input reload from a pseudo, we must
7530 clear any memory of a previous store to the same pseudo. Only do
7531 something if there will not be an output reload for the pseudo
7533 if (reload_in_reg[r] != 0
7534 && ! (reload_inherited[r] || reload_override_in[r]))
7536 rtx reg = reload_in_reg[r];
7538 if (GET_CODE (reg) == SUBREG)
7539 reg = SUBREG_REG (reg);
7541 if (GET_CODE (reg) == REG
7542 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7543 && ! reg_has_output_reload[REGNO (reg)])
7545 int nregno = REGNO (reg);
7547 if (reg_last_reload_reg[nregno])
7549 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7551 if (reg_reloaded_contents[last_regno] == nregno)
7552 spill_reg_store[last_regno] = 0;
7557 /* I is nonneg if this reload used a register.
7558 If reload_reg_rtx[r] is 0, this is an optional reload
7559 that we opted to ignore. */
7561 if (i >= 0 && reload_reg_rtx[r] != 0)
7564 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
7566 int part_reaches_end = 0;
7567 int all_reaches_end = 1;
7569 /* For a multi register reload, we need to check if all or part
7570 of the value lives to the end. */
7571 for (k = 0; k < nr; k++)
7573 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
7574 reload_when_needed[r]))
7575 part_reaches_end = 1;
7577 all_reaches_end = 0;
7580 /* Ignore reloads that don't reach the end of the insn in
7582 if (all_reaches_end)
7584 /* First, clear out memory of what used to be in this spill reg.
7585 If consecutive registers are used, clear them all. */
7587 for (k = 0; k < nr; k++)
7588 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7590 /* Maybe the spill reg contains a copy of reload_out. */
7591 if (reload_out[r] != 0
7592 && (GET_CODE (reload_out[r]) == REG
7594 || ! reload_out_reg[r]
7596 || GET_CODE (reload_out_reg[r]) == REG))
7598 rtx out = (GET_CODE (reload_out[r]) == REG
7602 /* AUTO_INC */ : XEXP (reload_in_reg[r], 0));
7603 register int nregno = REGNO (out);
7604 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7605 : HARD_REGNO_NREGS (nregno,
7606 GET_MODE (reload_reg_rtx[r])));
7608 spill_reg_store[i] = new_spill_reg_store[i];
7609 spill_reg_stored_to[i] = out;
7610 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7612 /* If NREGNO is a hard register, it may occupy more than
7613 one register. If it does, say what is in the
7614 rest of the registers assuming that both registers
7615 agree on how many words the object takes. If not,
7616 invalidate the subsequent registers. */
7618 if (nregno < FIRST_PSEUDO_REGISTER)
7619 for (k = 1; k < nnr; k++)
7620 reg_last_reload_reg[nregno + k]
7622 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7623 REGNO (reload_reg_rtx[r]) + k)
7626 /* Now do the inverse operation. */
7627 for (k = 0; k < nr; k++)
7629 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7630 reg_reloaded_contents[i + k]
7631 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7634 reg_reloaded_insn[i + k] = insn;
7635 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7639 /* Maybe the spill reg contains a copy of reload_in. Only do
7640 something if there will not be an output reload for
7641 the register being reloaded. */
7642 else if (reload_out_reg[r] == 0
7643 && reload_in[r] != 0
7644 && ((GET_CODE (reload_in[r]) == REG
7645 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER
7646 && ! reg_has_output_reload[REGNO (reload_in[r])])
7647 || (GET_CODE (reload_in_reg[r]) == REG
7648 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))
7649 && ! reg_set_p (reload_reg_rtx[r], PATTERN (insn)))
7651 register int nregno;
7654 if (GET_CODE (reload_in[r]) == REG
7655 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER)
7656 nregno = REGNO (reload_in[r]);
7657 else if (GET_CODE (reload_in_reg[r]) == REG)
7658 nregno = REGNO (reload_in_reg[r]);
7660 nregno = REGNO (XEXP (reload_in_reg[r], 0));
7662 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7663 : HARD_REGNO_NREGS (nregno,
7664 GET_MODE (reload_reg_rtx[r])));
7666 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7668 if (nregno < FIRST_PSEUDO_REGISTER)
7669 for (k = 1; k < nnr; k++)
7670 reg_last_reload_reg[nregno + k]
7672 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7673 REGNO (reload_reg_rtx[r]) + k)
7676 /* Unless we inherited this reload, show we haven't
7677 recently done a store.
7678 Previous stores of inherited auto_inc expressions
7679 also have to be discarded. */
7680 if (! reload_inherited[r]
7681 || (reload_out[r] && ! reload_out_reg[r]))
7682 spill_reg_store[i] = 0;
7684 for (k = 0; k < nr; k++)
7686 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7687 reg_reloaded_contents[i + k]
7688 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7691 reg_reloaded_insn[i + k] = insn;
7692 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7697 /* However, if part of the reload reaches the end, then we must
7698 invalidate the old info for the part that survives to the end. */
7699 else if (part_reaches_end)
7701 for (k = 0; k < nr; k++)
7702 if (reload_reg_reaches_end_p (i + k,
7704 reload_when_needed[r]))
7705 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7709 /* The following if-statement was #if 0'd in 1.34 (or before...).
7710 It's reenabled in 1.35 because supposedly nothing else
7711 deals with this problem. */
7713 /* If a register gets output-reloaded from a non-spill register,
7714 that invalidates any previous reloaded copy of it.
7715 But forget_old_reloads_1 won't get to see it, because
7716 it thinks only about the original insn. So invalidate it here. */
7717 if (i < 0 && reload_out[r] != 0
7718 && (GET_CODE (reload_out[r]) == REG
7719 || (GET_CODE (reload_out[r]) == MEM
7720 && GET_CODE (reload_out_reg[r]) == REG)))
7722 rtx out = (GET_CODE (reload_out[r]) == REG
7723 ? reload_out[r] : reload_out_reg[r]);
7724 register int nregno = REGNO (out);
7725 if (nregno >= FIRST_PSEUDO_REGISTER)
7727 rtx src_reg, store_insn;
7729 reg_last_reload_reg[nregno] = 0;
7731 /* If we can find a hard register that is stored, record
7732 the storing insn so that we may delete this insn with
7733 delete_output_reload. */
7734 src_reg = reload_reg_rtx[r];
7736 /* If this is an optional reload, try to find the source reg
7737 from an input reload. */
7740 rtx set = single_set (insn);
7741 if (set && SET_DEST (set) == reload_out[r])
7745 src_reg = SET_SRC (set);
7747 for (k = 0; k < n_reloads; k++)
7749 if (reload_in[k] == src_reg)
7751 src_reg = reload_reg_rtx[k];
7758 store_insn = new_spill_reg_store[REGNO (src_reg)];
7759 if (src_reg && GET_CODE (src_reg) == REG
7760 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7762 int src_regno = REGNO (src_reg);
7763 int nr = HARD_REGNO_NREGS (src_regno, reload_mode[r]);
7764 /* The place where to find a death note varies with
7765 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7766 necessarily checked exactly in the code that moves
7767 notes, so just check both locations. */
7768 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7770 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7773 spill_reg_store[src_regno + nr] = store_insn;
7774 spill_reg_stored_to[src_regno + nr] = out;
7775 reg_reloaded_contents[src_regno + nr] = nregno;
7776 reg_reloaded_insn[src_regno + nr] = store_insn;
7777 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7778 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7779 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7781 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7783 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7785 reg_last_reload_reg[nregno] = src_reg;
7790 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7792 while (num_regs-- > 0)
7793 reg_last_reload_reg[nregno + num_regs] = 0;
7797 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7800 /* Emit code to perform a reload from IN (which may be a reload register) to
7801 OUT (which may also be a reload register). IN or OUT is from operand
7802 OPNUM with reload type TYPE.
7804 Returns first insn emitted. */
7807 gen_reload (out, in, opnum, type)
7811 enum reload_type type;
7813 rtx last = get_last_insn ();
7816 /* If IN is a paradoxical SUBREG, remove it and try to put the
7817 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7818 if (GET_CODE (in) == SUBREG
7819 && (GET_MODE_SIZE (GET_MODE (in))
7820 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7821 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7822 in = SUBREG_REG (in), out = tem;
7823 else if (GET_CODE (out) == SUBREG
7824 && (GET_MODE_SIZE (GET_MODE (out))
7825 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7826 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7827 out = SUBREG_REG (out), in = tem;
7829 /* How to do this reload can get quite tricky. Normally, we are being
7830 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7831 register that didn't get a hard register. In that case we can just
7832 call emit_move_insn.
7834 We can also be asked to reload a PLUS that adds a register or a MEM to
7835 another register, constant or MEM. This can occur during frame pointer
7836 elimination and while reloading addresses. This case is handled by
7837 trying to emit a single insn to perform the add. If it is not valid,
7838 we use a two insn sequence.
7840 Finally, we could be called to handle an 'o' constraint by putting
7841 an address into a register. In that case, we first try to do this
7842 with a named pattern of "reload_load_address". If no such pattern
7843 exists, we just emit a SET insn and hope for the best (it will normally
7844 be valid on machines that use 'o').
7846 This entire process is made complex because reload will never
7847 process the insns we generate here and so we must ensure that
7848 they will fit their constraints and also by the fact that parts of
7849 IN might be being reloaded separately and replaced with spill registers.
7850 Because of this, we are, in some sense, just guessing the right approach
7851 here. The one listed above seems to work.
7853 ??? At some point, this whole thing needs to be rethought. */
7855 if (GET_CODE (in) == PLUS
7856 && (GET_CODE (XEXP (in, 0)) == REG
7857 || GET_CODE (XEXP (in, 0)) == SUBREG
7858 || GET_CODE (XEXP (in, 0)) == MEM)
7859 && (GET_CODE (XEXP (in, 1)) == REG
7860 || GET_CODE (XEXP (in, 1)) == SUBREG
7861 || CONSTANT_P (XEXP (in, 1))
7862 || GET_CODE (XEXP (in, 1)) == MEM))
7864 /* We need to compute the sum of a register or a MEM and another
7865 register, constant, or MEM, and put it into the reload
7866 register. The best possible way of doing this is if the machine
7867 has a three-operand ADD insn that accepts the required operands.
7869 The simplest approach is to try to generate such an insn and see if it
7870 is recognized and matches its constraints. If so, it can be used.
7872 It might be better not to actually emit the insn unless it is valid,
7873 but we need to pass the insn as an operand to `recog' and
7874 `extract_insn' and it is simpler to emit and then delete the insn if
7875 not valid than to dummy things up. */
7877 rtx op0, op1, tem, insn;
7880 op0 = find_replacement (&XEXP (in, 0));
7881 op1 = find_replacement (&XEXP (in, 1));
7883 /* Since constraint checking is strict, commutativity won't be
7884 checked, so we need to do that here to avoid spurious failure
7885 if the add instruction is two-address and the second operand
7886 of the add is the same as the reload reg, which is frequently
7887 the case. If the insn would be A = B + A, rearrange it so
7888 it will be A = A + B as constrain_operands expects. */
7890 if (GET_CODE (XEXP (in, 1)) == REG
7891 && REGNO (out) == REGNO (XEXP (in, 1)))
7892 tem = op0, op0 = op1, op1 = tem;
7894 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7895 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7897 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7898 code = recog_memoized (insn);
7902 extract_insn (insn);
7903 /* We want constrain operands to treat this insn strictly in
7904 its validity determination, i.e., the way it would after reload
7906 if (constrain_operands (1))
7910 delete_insns_since (last);
7912 /* If that failed, we must use a conservative two-insn sequence.
7913 use move to copy constant, MEM, or pseudo register to the reload
7914 register since "move" will be able to handle an arbitrary operand,
7915 unlike add which can't, in general. Then add the registers.
7917 If there is another way to do this for a specific machine, a
7918 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7921 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7923 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7924 || (GET_CODE (op1) == REG
7925 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7926 || (code != CODE_FOR_nothing
7927 && ! (*insn_operand_predicate[code][2]) (op1, insn_operand_mode[code][2])))
7928 tem = op0, op0 = op1, op1 = tem;
7930 gen_reload (out, op0, opnum, type);
7932 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7933 This fixes a problem on the 32K where the stack pointer cannot
7934 be used as an operand of an add insn. */
7936 if (rtx_equal_p (op0, op1))
7939 insn = emit_insn (gen_add2_insn (out, op1));
7941 /* If that failed, copy the address register to the reload register.
7942 Then add the constant to the reload register. */
7944 code = recog_memoized (insn);
7948 extract_insn (insn);
7949 /* We want constrain operands to treat this insn strictly in
7950 its validity determination, i.e., the way it would after reload
7952 if (constrain_operands (1))
7954 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7956 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7961 delete_insns_since (last);
7963 gen_reload (out, op1, opnum, type);
7964 insn = emit_insn (gen_add2_insn (out, op0));
7965 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7968 #ifdef SECONDARY_MEMORY_NEEDED
7969 /* If we need a memory location to do the move, do it that way. */
7970 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7971 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7972 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7973 REGNO_REG_CLASS (REGNO (out)),
7976 /* Get the memory to use and rewrite both registers to its mode. */
7977 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7979 if (GET_MODE (loc) != GET_MODE (out))
7980 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7982 if (GET_MODE (loc) != GET_MODE (in))
7983 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7985 gen_reload (loc, in, opnum, type);
7986 gen_reload (out, loc, opnum, type);
7990 /* If IN is a simple operand, use gen_move_insn. */
7991 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7992 emit_insn (gen_move_insn (out, in));
7994 #ifdef HAVE_reload_load_address
7995 else if (HAVE_reload_load_address)
7996 emit_insn (gen_reload_load_address (out, in));
7999 /* Otherwise, just write (set OUT IN) and hope for the best. */
8001 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8003 /* Return the first insn emitted.
8004 We can not just return get_last_insn, because there may have
8005 been multiple instructions emitted. Also note that gen_move_insn may
8006 emit more than one insn itself, so we can not assume that there is one
8007 insn emitted per emit_insn_before call. */
8009 return last ? NEXT_INSN (last) : get_insns ();
8012 /* Delete a previously made output-reload
8013 whose result we now believe is not needed.
8014 First we double-check.
8016 INSN is the insn now being processed.
8017 LAST_RELOAD_REG is the hard register number for which we want to delete
8018 the last output reload.
8019 J is the reload-number that originally used REG. The caller has made
8020 certain that reload J doesn't use REG any longer for input. */
8023 delete_output_reload (insn, j, last_reload_reg)
8026 int last_reload_reg;
8028 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8029 rtx reg = spill_reg_stored_to[last_reload_reg];
8032 int n_inherited = 0;
8036 /* Get the raw pseudo-register referred to. */
8038 while (GET_CODE (reg) == SUBREG)
8039 reg = SUBREG_REG (reg);
8040 substed = reg_equiv_memory_loc[REGNO (reg)];
8042 /* This is unsafe if the operand occurs more often in the current
8043 insn than it is inherited. */
8044 for (k = n_reloads - 1; k >= 0; k--)
8046 rtx reg2 = reload_in[k];
8049 if (GET_CODE (reg2) == MEM || reload_override_in[k])
8050 reg2 = reload_in_reg[k];
8052 if (reload_out[k] && ! reload_out_reg[k])
8053 reg2 = XEXP (reload_in_reg[k], 0);
8055 while (GET_CODE (reg2) == SUBREG)
8056 reg2 = SUBREG_REG (reg2);
8057 if (rtx_equal_p (reg2, reg))
8059 if (reload_inherited[k] || reload_override_in[k] || k == j)
8062 reg2 = reload_out_reg[k];
8065 while (GET_CODE (reg2) == SUBREG)
8066 reg2 = XEXP (reg2, 0);
8067 if (rtx_equal_p (reg2, reg))
8074 n_occurrences = count_occurrences (PATTERN (insn), reg);
8076 n_occurrences += count_occurrences (PATTERN (insn),
8077 eliminate_regs (substed, 0,
8079 if (n_occurrences > n_inherited)
8082 /* If the pseudo-reg we are reloading is no longer referenced
8083 anywhere between the store into it and here,
8084 and no jumps or labels intervene, then the value can get
8085 here through the reload reg alone.
8086 Otherwise, give up--return. */
8087 for (i1 = NEXT_INSN (output_reload_insn);
8088 i1 != insn; i1 = NEXT_INSN (i1))
8090 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
8092 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
8093 && reg_mentioned_p (reg, PATTERN (i1)))
8095 /* If this is USE in front of INSN, we only have to check that
8096 there are no more references than accounted for by inheritance. */
8097 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
8099 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8100 i1 = NEXT_INSN (i1);
8102 if (n_occurrences <= n_inherited && i1 == insn)
8108 /* The caller has already checked that REG dies or is set in INSN.
8109 It has also checked that we are optimizing, and thus some inaccurancies
8110 in the debugging information are acceptable.
8111 So we could just delete output_reload_insn.
8112 But in some cases we can improve the debugging information without
8113 sacrificing optimization - maybe even improving the code:
8114 See if the pseudo reg has been completely replaced
8115 with reload regs. If so, delete the store insn
8116 and forget we had a stack slot for the pseudo. */
8117 if (reload_out[j] != reload_in[j]
8118 && REG_N_DEATHS (REGNO (reg)) == 1
8119 && REG_N_SETS (REGNO (reg)) == 1
8120 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
8121 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8125 /* We know that it was used only between here
8126 and the beginning of the current basic block.
8127 (We also know that the last use before INSN was
8128 the output reload we are thinking of deleting, but never mind that.)
8129 Search that range; see if any ref remains. */
8130 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8132 rtx set = single_set (i2);
8134 /* Uses which just store in the pseudo don't count,
8135 since if they are the only uses, they are dead. */
8136 if (set != 0 && SET_DEST (set) == reg)
8138 if (GET_CODE (i2) == CODE_LABEL
8139 || GET_CODE (i2) == JUMP_INSN)
8141 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
8142 && reg_mentioned_p (reg, PATTERN (i2)))
8144 /* Some other ref remains; just delete the output reload we
8146 delete_address_reloads (output_reload_insn, insn);
8147 PUT_CODE (output_reload_insn, NOTE);
8148 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8149 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8154 /* Delete the now-dead stores into this pseudo. */
8155 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8157 rtx set = single_set (i2);
8159 if (set != 0 && SET_DEST (set) == reg)
8161 delete_address_reloads (i2, insn);
8162 /* This might be a basic block head,
8163 thus don't use delete_insn. */
8164 PUT_CODE (i2, NOTE);
8165 NOTE_SOURCE_FILE (i2) = 0;
8166 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
8168 if (GET_CODE (i2) == CODE_LABEL
8169 || GET_CODE (i2) == JUMP_INSN)
8173 /* For the debugging info,
8174 say the pseudo lives in this reload reg. */
8175 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
8176 alter_reg (REGNO (reg), -1);
8178 delete_address_reloads (output_reload_insn, insn);
8179 PUT_CODE (output_reload_insn, NOTE);
8180 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8181 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8185 /* We are going to delete DEAD_INSN. Recursively delete loads of
8186 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8187 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8189 delete_address_reloads (dead_insn, current_insn)
8190 rtx dead_insn, current_insn;
8192 rtx set = single_set (dead_insn);
8193 rtx set2, dst, prev, next;
8196 rtx dst = SET_DEST (set);
8197 if (GET_CODE (dst) == MEM)
8198 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8200 /* If we deleted the store from a reloaded post_{in,de}c expression,
8201 we can delete the matching adds. */
8202 prev = PREV_INSN (dead_insn);
8203 next = NEXT_INSN (dead_insn);
8204 if (! prev || ! next)
8206 set = single_set (next);
8207 set2 = single_set (prev);
8209 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8210 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8211 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8213 dst = SET_DEST (set);
8214 if (! rtx_equal_p (dst, SET_DEST (set2))
8215 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8216 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8217 || (INTVAL (XEXP (SET_SRC (set), 1))
8218 != - INTVAL (XEXP (SET_SRC (set2), 1))))
8224 /* Subfunction of delete_address_reloads: process registers found in X. */
8226 delete_address_reloads_1 (dead_insn, x, current_insn)
8227 rtx dead_insn, x, current_insn;
8229 rtx prev, set, dst, i2;
8231 enum rtx_code code = GET_CODE (x);
8235 char *fmt= GET_RTX_FORMAT (code);
8236 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8239 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8240 else if (fmt[i] == 'E')
8242 for (j = XVECLEN (x, i) - 1; j >=0; j--)
8243 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8250 if (spill_reg_order[REGNO (x)] < 0)
8253 /* Scan backwards for the insn that sets x. This might be a way back due
8255 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8257 code = GET_CODE (prev);
8258 if (code == CODE_LABEL || code == JUMP_INSN)
8260 if (GET_RTX_CLASS (code) != 'i')
8262 if (reg_set_p (x, PATTERN (prev)))
8264 if (reg_referenced_p (x, PATTERN (prev)))
8267 if (! prev || INSN_UID (prev) < reload_first_uid)
8269 /* Check that PREV only sets the reload register. */
8270 set = single_set (prev);
8273 dst = SET_DEST (set);
8274 if (GET_CODE (dst) != REG
8275 || ! rtx_equal_p (dst, x))
8277 if (! reg_set_p (dst, PATTERN (dead_insn)))
8279 /* Check if DST was used in a later insn -
8280 it might have been inherited. */
8281 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8283 if (GET_CODE (i2) == CODE_LABEL)
8285 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
8287 if (reg_referenced_p (dst, PATTERN (i2)))
8289 /* If there is a reference to the register in the current insn,
8290 it might be loaded in a non-inherited reload. If no other
8291 reload uses it, that means the register is set before
8293 if (i2 == current_insn)
8295 for (j = n_reloads - 1; j >= 0; j--)
8296 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8297 || reload_override_in[j] == dst)
8299 for (j = n_reloads - 1; j >= 0; j--)
8300 if (reload_in[j] && reload_reg_rtx[j] == dst)
8307 if (GET_CODE (i2) == JUMP_INSN)
8309 /* If DST is still live at CURRENT_INSN, check if it is used for
8310 any reload. Note that even if CURRENT_INSN sets DST, we still
8311 have to check the reloads. */
8312 if (i2 == current_insn)
8314 for (j = n_reloads - 1; j >= 0; j--)
8315 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8316 || reload_override_in[j] == dst)
8318 /* ??? We can't finish the loop here, because dst might be
8319 allocated to a pseudo in this block if no reload in this
8320 block needs any of the clsses containing DST - see
8321 spill_hard_reg. There is no easy way to tell this, so we
8322 have to scan till the end of the basic block. */
8324 if (reg_set_p (dst, PATTERN (i2)))
8328 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8329 reg_reloaded_contents[REGNO (dst)] = -1;
8330 /* Can't use delete_insn here because PREV might be a basic block head. */
8331 PUT_CODE (prev, NOTE);
8332 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
8333 NOTE_SOURCE_FILE (prev) = 0;
8336 /* Output reload-insns to reload VALUE into RELOADREG.
8337 VALUE is an autoincrement or autodecrement RTX whose operand
8338 is a register or memory location;
8339 so reloading involves incrementing that location.
8340 IN is either identical to VALUE, or some cheaper place to reload from.
8342 INC_AMOUNT is the number to increment or decrement by (always positive).
8343 This cannot be deduced from VALUE.
8345 Return the instruction that stores into RELOADREG. */
8348 inc_for_reload (reloadreg, in, value, inc_amount)
8353 /* REG or MEM to be copied and incremented. */
8354 rtx incloc = XEXP (value, 0);
8355 /* Nonzero if increment after copying. */
8356 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8362 rtx real_in = in == value ? XEXP (in, 0) : in;
8364 /* No hard register is equivalent to this register after
8365 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8366 we could inc/dec that register as well (maybe even using it for
8367 the source), but I'm not sure it's worth worrying about. */
8368 if (GET_CODE (incloc) == REG)
8369 reg_last_reload_reg[REGNO (incloc)] = 0;
8371 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8372 inc_amount = - inc_amount;
8374 inc = GEN_INT (inc_amount);
8376 /* If this is post-increment, first copy the location to the reload reg. */
8377 if (post && real_in != reloadreg)
8378 emit_insn (gen_move_insn (reloadreg, real_in));
8382 /* See if we can directly increment INCLOC. Use a method similar to
8383 that in gen_reload. */
8385 last = get_last_insn ();
8386 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8387 gen_rtx_PLUS (GET_MODE (incloc),
8390 code = recog_memoized (add_insn);
8393 extract_insn (add_insn);
8394 if (constrain_operands (1))
8396 /* If this is a pre-increment and we have incremented the value
8397 where it lives, copy the incremented value to RELOADREG to
8398 be used as an address. */
8401 emit_insn (gen_move_insn (reloadreg, incloc));
8406 delete_insns_since (last);
8409 /* If couldn't do the increment directly, must increment in RELOADREG.
8410 The way we do this depends on whether this is pre- or post-increment.
8411 For pre-increment, copy INCLOC to the reload register, increment it
8412 there, then save back. */
8416 if (in != reloadreg)
8417 emit_insn (gen_move_insn (reloadreg, real_in));
8418 emit_insn (gen_add2_insn (reloadreg, inc));
8419 store = emit_insn (gen_move_insn (incloc, reloadreg));
8424 Because this might be a jump insn or a compare, and because RELOADREG
8425 may not be available after the insn in an input reload, we must do
8426 the incrementation before the insn being reloaded for.
8428 We have already copied IN to RELOADREG. Increment the copy in
8429 RELOADREG, save that back, then decrement RELOADREG so it has
8430 the original value. */
8432 emit_insn (gen_add2_insn (reloadreg, inc));
8433 store = emit_insn (gen_move_insn (incloc, reloadreg));
8434 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8440 /* Return 1 if we are certain that the constraint-string STRING allows
8441 the hard register REG. Return 0 if we can't be sure of this. */
8444 constraint_accepts_reg_p (string, reg)
8449 int regno = true_regnum (reg);
8452 /* Initialize for first alternative. */
8454 /* Check that each alternative contains `g' or `r'. */
8456 switch (c = *string++)
8459 /* If an alternative lacks `g' or `r', we lose. */
8462 /* If an alternative lacks `g' or `r', we lose. */
8465 /* Initialize for next alternative. */
8470 /* Any general reg wins for this alternative. */
8471 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8475 /* Any reg in specified class wins for this alternative. */
8477 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8479 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8485 /* Return the number of places FIND appears within X, but don't count
8486 an occurrence if some SET_DEST is FIND. */
8489 count_occurrences (x, find)
8490 register rtx x, find;
8493 register enum rtx_code code;
8494 register char *format_ptr;
8502 code = GET_CODE (x);
8517 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
8521 if (SET_DEST (x) == find)
8522 return count_occurrences (SET_SRC (x), find);
8529 format_ptr = GET_RTX_FORMAT (code);
8532 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8534 switch (*format_ptr++)
8537 count += count_occurrences (XEXP (x, i), find);
8541 if (XVEC (x, i) != NULL)
8543 for (j = 0; j < XVECLEN (x, i); j++)
8544 count += count_occurrences (XVECEXP (x, i, j), find);
8552 /* This array holds values which are equivalent to a hard register
8553 during reload_cse_regs. Each array element is an EXPR_LIST of
8554 values. Each time a hard register is set, we set the corresponding
8555 array element to the value. Each time a hard register is copied
8556 into memory, we add the memory location to the corresponding array
8557 element. We don't store values or memory addresses with side
8558 effects in this array.
8560 If the value is a CONST_INT, then the mode of the containing
8561 EXPR_LIST is the mode in which that CONST_INT was referenced.
8563 We sometimes clobber a specific entry in a list. In that case, we
8564 just set XEXP (list-entry, 0) to 0. */
8566 static rtx *reg_values;
8568 /* This is a preallocated REG rtx which we use as a temporary in
8569 reload_cse_invalidate_regno, so that we don't need to allocate a
8570 new one each time through a loop in that function. */
8572 static rtx invalidate_regno_rtx;
8574 /* Invalidate any entries in reg_values which depend on REGNO,
8575 including those for REGNO itself. This is called if REGNO is
8576 changing. If CLOBBER is true, then always forget anything we
8577 currently know about REGNO. MODE is the mode of the assignment to
8578 REGNO, which is used to determine how many hard registers are being
8579 changed. If MODE is VOIDmode, then only REGNO is being changed;
8580 this is used when invalidating call clobbered registers across a
8584 reload_cse_invalidate_regno (regno, mode, clobber)
8586 enum machine_mode mode;
8592 /* Our callers don't always go through true_regnum; we may see a
8593 pseudo-register here from a CLOBBER or the like. We probably
8594 won't ever see a pseudo-register that has a real register number,
8595 for we check anyhow for safety. */
8596 if (regno >= FIRST_PSEUDO_REGISTER)
8597 regno = reg_renumber[regno];
8601 if (mode == VOIDmode)
8602 endregno = regno + 1;
8604 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8607 for (i = regno; i < endregno; i++)
8610 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8614 for (x = reg_values[i]; x; x = XEXP (x, 1))
8616 if (XEXP (x, 0) != 0
8617 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8619 /* If this is the only entry on the list, clear
8620 reg_values[i]. Otherwise, just clear this entry on
8622 if (XEXP (x, 1) == 0 && x == reg_values[i])
8632 /* We must look at earlier registers, in case REGNO is part of a
8633 multi word value but is not the first register. If an earlier
8634 register has a value in a mode which overlaps REGNO, then we must
8635 invalidate that earlier register. Note that we do not need to
8636 check REGNO or later registers (we must not check REGNO itself,
8637 because we would incorrectly conclude that there was a conflict). */
8639 for (i = 0; i < regno; i++)
8643 for (x = reg_values[i]; x; x = XEXP (x, 1))
8645 if (XEXP (x, 0) != 0)
8647 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8648 REGNO (invalidate_regno_rtx) = i;
8649 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8652 reload_cse_invalidate_regno (i, VOIDmode, 1);
8660 /* The memory at address MEM_BASE is being changed.
8661 Return whether this change will invalidate VAL. */
8664 reload_cse_mem_conflict_p (mem_base, val)
8672 code = GET_CODE (val);
8675 /* Get rid of a few simple cases quickly. */
8688 if (GET_MODE (mem_base) == BLKmode
8689 || GET_MODE (val) == BLKmode)
8691 if (anti_dependence (val, mem_base))
8693 /* The address may contain nested MEMs. */
8700 fmt = GET_RTX_FORMAT (code);
8702 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8706 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8709 else if (fmt[i] == 'E')
8713 for (j = 0; j < XVECLEN (val, i); j++)
8714 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8722 /* Invalidate any entries in reg_values which are changed because of a
8723 store to MEM_RTX. If this is called because of a non-const call
8724 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8727 reload_cse_invalidate_mem (mem_rtx)
8732 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8736 for (x = reg_values[i]; x; x = XEXP (x, 1))
8738 if (XEXP (x, 0) != 0
8739 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8741 /* If this is the only entry on the list, clear
8742 reg_values[i]. Otherwise, just clear this entry on
8744 if (XEXP (x, 1) == 0 && x == reg_values[i])
8755 /* Invalidate DEST, which is being assigned to or clobbered. The
8756 second parameter exists so that this function can be passed to
8757 note_stores; it is ignored. */
8760 reload_cse_invalidate_rtx (dest, ignore)
8762 rtx ignore ATTRIBUTE_UNUSED;
8764 while (GET_CODE (dest) == STRICT_LOW_PART
8765 || GET_CODE (dest) == SIGN_EXTRACT
8766 || GET_CODE (dest) == ZERO_EXTRACT
8767 || GET_CODE (dest) == SUBREG)
8768 dest = XEXP (dest, 0);
8770 if (GET_CODE (dest) == REG)
8771 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8772 else if (GET_CODE (dest) == MEM)
8773 reload_cse_invalidate_mem (dest);
8776 /* Do a very simple CSE pass over the hard registers.
8778 This function detects no-op moves where we happened to assign two
8779 different pseudo-registers to the same hard register, and then
8780 copied one to the other. Reload will generate a useless
8781 instruction copying a register to itself.
8783 This function also detects cases where we load a value from memory
8784 into two different registers, and (if memory is more expensive than
8785 registers) changes it to simply copy the first register into the
8788 Another optimization is performed that scans the operands of each
8789 instruction to see whether the value is already available in a
8790 hard register. It then replaces the operand with the hard register
8791 if possible, much like an optional reload would. */
8794 reload_cse_regs_1 (first)
8802 init_alias_analysis ();
8804 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8805 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8807 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8808 free them when we are done. */
8809 push_obstacks (&reload_obstack, &reload_obstack);
8810 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8812 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8813 memory for a non-const call instruction. */
8814 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8816 /* This is used in reload_cse_invalidate_regno to avoid consing a
8817 new REG in a loop in that function. */
8818 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8820 for (insn = first; insn; insn = NEXT_INSN (insn))
8824 if (GET_CODE (insn) == CODE_LABEL)
8826 /* Forget all the register values at a code label. We don't
8827 try to do anything clever around jumps. */
8828 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8834 #ifdef NON_SAVING_SETJMP
8835 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8836 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8838 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8845 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8848 /* If this is a call instruction, forget anything stored in a
8849 call clobbered register, or, if this is not a const call, in
8851 if (GET_CODE (insn) == CALL_INSN)
8853 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8854 if (call_used_regs[i])
8855 reload_cse_invalidate_regno (i, VOIDmode, 1);
8857 if (! CONST_CALL_P (insn))
8858 reload_cse_invalidate_mem (callmem);
8862 /* Forget all the register values at a volatile asm. */
8863 if (GET_CODE (insn) == INSN
8864 && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
8865 && MEM_VOLATILE_P (PATTERN (insn)))
8866 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8869 body = PATTERN (insn);
8870 if (GET_CODE (body) == SET)
8873 if (reload_cse_noop_set_p (body, insn))
8875 /* If this sets the return value of the function, we must keep
8876 a USE around, in case this is in a different basic block
8877 than the final USE. Otherwise, we could loose important
8878 register lifeness information on SMALL_REGISTER_CLASSES
8879 machines, where return registers might be used as spills:
8880 subsequent passes assume that spill registers are dead at
8881 the end of a basic block. */
8882 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8885 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8886 INSN_CODE (insn) = -1;
8887 REG_NOTES (insn) = NULL_RTX;
8888 push_obstacks (&reload_obstack, &reload_obstack);
8892 PUT_CODE (insn, NOTE);
8893 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8894 NOTE_SOURCE_FILE (insn) = 0;
8897 /* We're done with this insn. */
8901 /* It's not a no-op, but we can try to simplify it. */
8902 count += reload_cse_simplify_set (body, insn);
8905 apply_change_group ();
8907 reload_cse_simplify_operands (insn);
8909 reload_cse_record_set (body, body);
8911 else if (GET_CODE (body) == PARALLEL)
8914 rtx value = NULL_RTX;
8916 /* If every action in a PARALLEL is a noop, we can delete
8917 the entire PARALLEL. */
8918 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8920 rtx part = XVECEXP (body, 0, i);
8921 if (GET_CODE (part) == SET)
8923 if (! reload_cse_noop_set_p (part, insn))
8925 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8929 value = SET_DEST (part);
8932 else if (GET_CODE (part) != CLOBBER)
8940 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8941 INSN_CODE (insn) = -1;
8942 REG_NOTES (insn) = NULL_RTX;
8943 push_obstacks (&reload_obstack, &reload_obstack);
8947 PUT_CODE (insn, NOTE);
8948 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8949 NOTE_SOURCE_FILE (insn) = 0;
8952 /* We're done with this insn. */
8956 /* It's not a no-op, but we can try to simplify it. */
8957 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8958 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8959 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8962 apply_change_group ();
8964 reload_cse_simplify_operands (insn);
8966 /* Look through the PARALLEL and record the values being
8967 set, if possible. Also handle any CLOBBERs. */
8968 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8970 rtx x = XVECEXP (body, 0, i);
8972 if (GET_CODE (x) == SET)
8973 reload_cse_record_set (x, body);
8975 note_stores (x, reload_cse_invalidate_rtx);
8979 note_stores (body, reload_cse_invalidate_rtx);
8982 /* Clobber any registers which appear in REG_INC notes. We
8983 could keep track of the changes to their values, but it is
8984 unlikely to help. */
8988 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8989 if (REG_NOTE_KIND (x) == REG_INC)
8990 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8994 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8995 after we have processed the insn. */
8996 if (GET_CODE (insn) == CALL_INSN)
9000 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
9001 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
9002 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
9006 /* Free all the temporary structures we created, and go back to the
9007 regular obstacks. */
9008 obstack_free (&reload_obstack, firstobj);
9012 /* Call cse / combine like post-reload optimization phases.
9013 FIRST is the first instruction. */
9015 reload_cse_regs (first)
9018 reload_cse_regs_1 (first);
9020 reload_cse_move2add (first);
9021 if (flag_expensive_optimizations)
9022 reload_cse_regs_1 (first);
9025 /* Return whether the values known for REGNO are equal to VAL. MODE
9026 is the mode of the object that VAL is being copied to; this matters
9027 if VAL is a CONST_INT. */
9030 reload_cse_regno_equal_p (regno, val, mode)
9033 enum machine_mode mode;
9040 for (x = reg_values[regno]; x; x = XEXP (x, 1))
9041 if (XEXP (x, 0) != 0
9042 && rtx_equal_p (XEXP (x, 0), val)
9043 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
9044 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
9045 && (GET_CODE (val) != CONST_INT
9046 || mode == GET_MODE (x)
9047 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
9048 /* On a big endian machine if the value spans more than
9049 one register then this register holds the high part of
9050 it and we can't use it.
9052 ??? We should also compare with the high part of the
9054 && !(WORDS_BIG_ENDIAN
9055 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
9056 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
9057 GET_MODE_BITSIZE (GET_MODE (x))))))
9063 /* See whether a single set is a noop. SET is the set instruction we
9064 are should check, and INSN is the instruction from which it came. */
9067 reload_cse_noop_set_p (set, insn)
9072 enum machine_mode dest_mode;
9076 src = SET_SRC (set);
9077 dest = SET_DEST (set);
9078 dest_mode = GET_MODE (dest);
9080 if (side_effects_p (src))
9083 dreg = true_regnum (dest);
9084 sreg = true_regnum (src);
9086 /* Check for setting a register to itself. In this case, we don't
9087 have to worry about REG_DEAD notes. */
9088 if (dreg >= 0 && dreg == sreg)
9094 /* Check for setting a register to itself. */
9098 /* Check for setting a register to a value which we already know
9099 is in the register. */
9100 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
9103 /* Check for setting a register DREG to another register SREG
9104 where SREG is equal to a value which is already in DREG. */
9109 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9113 if (XEXP (x, 0) == 0)
9116 if (dest_mode == GET_MODE (x))
9118 else if (GET_MODE_BITSIZE (dest_mode)
9119 < GET_MODE_BITSIZE (GET_MODE (x)))
9120 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9125 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
9133 else if (GET_CODE (dest) == MEM)
9135 /* Check for storing a register to memory when we know that the
9136 register is equivalent to the memory location. */
9138 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
9139 && ! side_effects_p (dest))
9146 /* Try to simplify a single SET instruction. SET is the set pattern.
9147 INSN is the instruction it came from.
9148 This function only handles one case: if we set a register to a value
9149 which is not a register, we try to find that value in some other register
9150 and change the set into a register copy. */
9153 reload_cse_simplify_set (set, insn)
9159 enum machine_mode dest_mode;
9160 enum reg_class dclass;
9163 dreg = true_regnum (SET_DEST (set));
9167 src = SET_SRC (set);
9168 if (side_effects_p (src) || true_regnum (src) >= 0)
9171 dclass = REGNO_REG_CLASS (dreg);
9173 /* If memory loads are cheaper than register copies, don't change them. */
9174 if (GET_CODE (src) == MEM
9175 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
9178 /* If the constant is cheaper than a register, don't change it. */
9179 if (CONSTANT_P (src)
9180 && rtx_cost (src, SET) < 2)
9183 dest_mode = GET_MODE (SET_DEST (set));
9184 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
9187 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
9188 && reload_cse_regno_equal_p (i, src, dest_mode))
9192 /* Pop back to the real obstacks while changing the insn. */
9195 validated = validate_change (insn, &SET_SRC (set),
9196 gen_rtx_REG (dest_mode, i), 1);
9198 /* Go back to the obstack we are using for temporary
9200 push_obstacks (&reload_obstack, &reload_obstack);
9209 /* Try to replace operands in INSN with equivalent values that are already
9210 in registers. This can be viewed as optional reloading.
9212 For each non-register operand in the insn, see if any hard regs are
9213 known to be equivalent to that operand. Record the alternatives which
9214 can accept these hard registers. Among all alternatives, select the
9215 ones which are better or equal to the one currently matching, where
9216 "better" is in terms of '?' and '!' constraints. Among the remaining
9217 alternatives, select the one which replaces most operands with
9221 reload_cse_simplify_operands (insn)
9224 #ifdef REGISTER_CONSTRAINTS
9227 const char *constraints[MAX_RECOG_OPERANDS];
9229 /* Vector recording how bad an alternative is. */
9230 int *alternative_reject;
9231 /* Vector recording how many registers can be introduced by choosing
9232 this alternative. */
9233 int *alternative_nregs;
9234 /* Array of vectors recording, for each operand and each alternative,
9235 which hard register to substitute, or -1 if the operand should be
9237 int *op_alt_regno[MAX_RECOG_OPERANDS];
9238 /* Array of alternatives, sorted in order of decreasing desirability. */
9239 int *alternative_order;
9240 rtx reg = gen_rtx_REG (VOIDmode, -1);
9242 extract_insn (insn);
9244 if (recog_n_alternatives == 0 || recog_n_operands == 0)
9247 /* Figure out which alternative currently matches. */
9248 if (! constrain_operands (1))
9249 fatal_insn_not_found (insn);
9251 alternative_reject = (int *) alloca (recog_n_alternatives * sizeof (int));
9252 alternative_nregs = (int *) alloca (recog_n_alternatives * sizeof (int));
9253 alternative_order = (int *) alloca (recog_n_alternatives * sizeof (int));
9254 bzero ((char *)alternative_reject, recog_n_alternatives * sizeof (int));
9255 bzero ((char *)alternative_nregs, recog_n_alternatives * sizeof (int));
9257 for (i = 0; i < recog_n_operands; i++)
9259 enum machine_mode mode;
9263 op_alt_regno[i] = (int *) alloca (recog_n_alternatives * sizeof (int));
9264 for (j = 0; j < recog_n_alternatives; j++)
9265 op_alt_regno[i][j] = -1;
9267 p = constraints[i] = recog_constraints[i];
9268 mode = recog_operand_mode[i];
9270 /* Add the reject values for each alternative given by the constraints
9271 for this operand. */
9279 alternative_reject[j] += 3;
9281 alternative_reject[j] += 300;
9284 /* We won't change operands which are already registers. We
9285 also don't want to modify output operands. */
9286 regno = true_regnum (recog_operand[i]);
9288 || constraints[i][0] == '='
9289 || constraints[i][0] == '+')
9292 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
9294 int class = (int) NO_REGS;
9296 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
9299 REGNO (reg) = regno;
9300 PUT_MODE (reg, mode);
9302 /* We found a register equal to this operand. Now look for all
9303 alternatives that can accept this register and have not been
9304 assigned a register they can use yet. */
9313 case '=': case '+': case '?':
9314 case '#': case '&': case '!':
9316 case '0': case '1': case '2': case '3': case '4':
9317 case 'm': case '<': case '>': case 'V': case 'o':
9318 case 'E': case 'F': case 'G': case 'H':
9319 case 's': case 'i': case 'n':
9320 case 'I': case 'J': case 'K': case 'L':
9321 case 'M': case 'N': case 'O': case 'P':
9322 #ifdef EXTRA_CONSTRAINT
9323 case 'Q': case 'R': case 'S': case 'T': case 'U':
9326 /* These don't say anything we care about. */
9330 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
9335 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
9338 case ',': case '\0':
9339 /* See if REGNO fits this alternative, and set it up as the
9340 replacement register if we don't have one for this
9341 alternative yet and the operand being replaced is not
9342 a cheap CONST_INT. */
9343 if (op_alt_regno[i][j] == -1
9344 && reg_fits_class_p (reg, class, 0, mode)
9345 && (GET_CODE (recog_operand[i]) != CONST_INT
9346 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
9348 alternative_nregs[j]++;
9349 op_alt_regno[i][j] = regno;
9361 /* Record all alternatives which are better or equal to the currently
9362 matching one in the alternative_order array. */
9363 for (i = j = 0; i < recog_n_alternatives; i++)
9364 if (alternative_reject[i] <= alternative_reject[which_alternative])
9365 alternative_order[j++] = i;
9366 recog_n_alternatives = j;
9368 /* Sort it. Given a small number of alternatives, a dumb algorithm
9369 won't hurt too much. */
9370 for (i = 0; i < recog_n_alternatives - 1; i++)
9373 int best_reject = alternative_reject[alternative_order[i]];
9374 int best_nregs = alternative_nregs[alternative_order[i]];
9377 for (j = i + 1; j < recog_n_alternatives; j++)
9379 int this_reject = alternative_reject[alternative_order[j]];
9380 int this_nregs = alternative_nregs[alternative_order[j]];
9382 if (this_reject < best_reject
9383 || (this_reject == best_reject && this_nregs < best_nregs))
9386 best_reject = this_reject;
9387 best_nregs = this_nregs;
9391 tmp = alternative_order[best];
9392 alternative_order[best] = alternative_order[i];
9393 alternative_order[i] = tmp;
9396 /* Substitute the operands as determined by op_alt_regno for the best
9398 j = alternative_order[0];
9400 /* Pop back to the real obstacks while changing the insn. */
9403 for (i = 0; i < recog_n_operands; i++)
9405 enum machine_mode mode = recog_operand_mode[i];
9406 if (op_alt_regno[i][j] == -1)
9409 validate_change (insn, recog_operand_loc[i],
9410 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
9413 for (i = recog_n_dups - 1; i >= 0; i--)
9415 int op = recog_dup_num[i];
9416 enum machine_mode mode = recog_operand_mode[op];
9418 if (op_alt_regno[op][j] == -1)
9421 validate_change (insn, recog_dup_loc[i],
9422 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
9425 /* Go back to the obstack we are using for temporary
9427 push_obstacks (&reload_obstack, &reload_obstack);
9429 return apply_change_group ();
9435 /* These two variables are used to pass information from
9436 reload_cse_record_set to reload_cse_check_clobber. */
9438 static int reload_cse_check_clobbered;
9439 static rtx reload_cse_check_src;
9441 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9442 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9443 second argument, which is passed by note_stores, is ignored. */
9446 reload_cse_check_clobber (dest, ignore)
9448 rtx ignore ATTRIBUTE_UNUSED;
9450 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
9451 reload_cse_check_clobbered = 1;
9454 /* Record the result of a SET instruction. SET is the set pattern.
9455 BODY is the pattern of the insn that it came from. */
9458 reload_cse_record_set (set, body)
9464 enum machine_mode dest_mode;
9466 dest = SET_DEST (set);
9467 src = SET_SRC (set);
9468 dreg = true_regnum (dest);
9469 sreg = true_regnum (src);
9470 dest_mode = GET_MODE (dest);
9472 /* Some machines don't define AUTO_INC_DEC, but they still use push
9473 instructions. We need to catch that case here in order to
9474 invalidate the stack pointer correctly. Note that invalidating
9475 the stack pointer is different from invalidating DEST. */
9477 while (GET_CODE (x) == SUBREG
9478 || GET_CODE (x) == ZERO_EXTRACT
9479 || GET_CODE (x) == SIGN_EXTRACT
9480 || GET_CODE (x) == STRICT_LOW_PART)
9482 if (push_operand (x, GET_MODE (x)))
9484 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
9485 reload_cse_invalidate_rtx (dest, NULL_RTX);
9489 /* We can only handle an assignment to a register, or a store of a
9490 register to a memory location. For other cases, we just clobber
9491 the destination. We also have to just clobber if there are side
9492 effects in SRC or DEST. */
9493 if ((dreg < 0 && GET_CODE (dest) != MEM)
9494 || side_effects_p (src)
9495 || side_effects_p (dest))
9497 reload_cse_invalidate_rtx (dest, NULL_RTX);
9502 /* We don't try to handle values involving CC, because it's a pain
9503 to keep track of when they have to be invalidated. */
9504 if (reg_mentioned_p (cc0_rtx, src)
9505 || reg_mentioned_p (cc0_rtx, dest))
9507 reload_cse_invalidate_rtx (dest, NULL_RTX);
9512 /* If BODY is a PARALLEL, then we need to see whether the source of
9513 SET is clobbered by some other instruction in the PARALLEL. */
9514 if (GET_CODE (body) == PARALLEL)
9518 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9522 x = XVECEXP (body, 0, i);
9526 reload_cse_check_clobbered = 0;
9527 reload_cse_check_src = src;
9528 note_stores (x, reload_cse_check_clobber);
9529 if (reload_cse_check_clobbered)
9531 reload_cse_invalidate_rtx (dest, NULL_RTX);
9541 /* This is an assignment to a register. Update the value we
9542 have stored for the register. */
9547 /* This is a copy from one register to another. Any values
9548 which were valid for SREG are now valid for DREG. If the
9549 mode changes, we use gen_lowpart_common to extract only
9550 the part of the value that is copied. */
9551 reg_values[dreg] = 0;
9552 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9556 if (XEXP (x, 0) == 0)
9558 if (dest_mode == GET_MODE (XEXP (x, 0)))
9560 else if (GET_MODE_BITSIZE (dest_mode)
9561 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9564 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9566 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9571 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9573 /* We've changed DREG, so invalidate any values held by other
9574 registers that depend upon it. */
9575 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9577 /* If this assignment changes more than one hard register,
9578 forget anything we know about the others. */
9579 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9580 reg_values[dreg + i] = 0;
9582 else if (GET_CODE (dest) == MEM)
9584 /* Invalidate conflicting memory locations. */
9585 reload_cse_invalidate_mem (dest);
9587 /* If we're storing a register to memory, add DEST to the list
9589 if (sreg >= 0 && ! side_effects_p (dest))
9590 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9595 /* We should have bailed out earlier. */
9600 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9602 This code might also be useful when reload gave up on reg+reg addresssing
9603 because of clashes between the return register and INDEX_REG_CLASS. */
9605 /* The maximum number of uses of a register we can keep track of to
9606 replace them with reg+reg addressing. */
9607 #define RELOAD_COMBINE_MAX_USES 6
9609 /* INSN is the insn where a register has ben used, and USEP points to the
9610 location of the register within the rtl. */
9611 struct reg_use { rtx insn, *usep; };
9613 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9614 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9615 indicates where it becomes live again.
9616 Otherwise, USE_INDEX is the index of the last encountered use of the
9617 register (which is first among these we have seen since we scan backwards),
9618 OFFSET contains the constant offset that is added to the register in
9619 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9620 last, of these uses.
9621 STORE_RUID is always meaningful if we only want to use a value in a
9622 register in a different place: it denotes the next insn in the insn
9623 stream (i.e. the last ecountered) that sets or clobbers the register. */
9626 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9631 } reg_state[FIRST_PSEUDO_REGISTER];
9633 /* Reverse linear uid. This is increased in reload_combine while scanning
9634 the instructions from last to first. It is used to set last_label_ruid
9635 and the store_ruid / use_ruid fields in reg_state. */
9636 static int reload_combine_ruid;
9638 #define LABEL_LIVE(LABEL) \
9639 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
9645 int first_index_reg = 1, last_index_reg = 0;
9647 int last_label_ruid;
9648 int min_labelno, n_labels;
9649 HARD_REG_SET ever_live_at_start, *label_live;
9651 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9652 reload has already used it where appropriate, so there is no use in
9653 trying to generate it now. */
9654 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
9657 /* To avoid wasting too much time later searching for an index register,
9658 determine the minimum and maximum index register numbers. */
9659 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9661 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9663 if (! last_index_reg)
9665 first_index_reg = i;
9668 /* If no index register is available, we can quit now. */
9669 if (first_index_reg > last_index_reg)
9672 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
9673 information is a bit fuzzy immediately after reload, but it's
9674 still good enough to determine which registers are live at a jump
9676 min_labelno = get_first_label_num ();
9677 n_labels = max_label_num () - min_labelno;
9678 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
9679 CLEAR_HARD_REG_SET (ever_live_at_start);
9680 for (i = n_basic_blocks - 1; i >= 0; i--)
9682 insn = BLOCK_HEAD (i);
9683 if (GET_CODE (insn) == CODE_LABEL)
9687 REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start);
9688 compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start);
9689 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
9690 IOR_HARD_REG_SET (ever_live_at_start, live);
9694 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9695 last_label_ruid = reload_combine_ruid = 0;
9696 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9698 reg_state[i].store_ruid = reload_combine_ruid;
9700 reg_state[i].use_index = -1;
9702 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9705 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9709 /* We cannot do our optimization across labels. Invalidating all the use
9710 information we have would be costly, so we just note where the label
9711 is and then later disable any optimization that would cross it. */
9712 if (GET_CODE (insn) == CODE_LABEL)
9713 last_label_ruid = reload_combine_ruid;
9714 if (GET_CODE (insn) == BARRIER)
9716 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9717 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9719 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9721 reload_combine_ruid++;
9723 /* Look for (set (REGX) (CONST_INT))
9724 (set (REGX) (PLUS (REGX) (REGY)))
9726 ... (MEM (REGX)) ...
9728 (set (REGZ) (CONST_INT))
9730 ... (MEM (PLUS (REGZ) (REGY)))... .
9732 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9733 and that we know all uses of REGX before it dies. */
9734 set = single_set (insn);
9736 && GET_CODE (SET_DEST (set)) == REG
9737 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9738 GET_MODE (SET_DEST (set)))
9740 && GET_CODE (SET_SRC (set)) == PLUS
9741 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9742 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9743 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9745 rtx reg = SET_DEST (set);
9746 rtx plus = SET_SRC (set);
9747 rtx base = XEXP (plus, 1);
9748 rtx prev = prev_nonnote_insn (insn);
9749 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9750 int regno = REGNO (reg);
9752 rtx reg_sum = NULL_RTX;
9754 /* Now, we need an index register.
9755 We'll set index_reg to this index register, const_reg to the
9756 register that is to be loaded with the constant
9757 (denoted as REGZ in the substitution illustration above),
9758 and reg_sum to the register-register that we want to use to
9759 substitute uses of REG (typically in MEMs) with.
9760 First check REG and BASE for being index registers;
9761 we can use them even if they are not dead. */
9762 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9763 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9771 /* Otherwise, look for a free index register. Since we have
9772 checked above that neiter REG nor BASE are index registers,
9773 if we find anything at all, it will be different from these
9775 for (i = first_index_reg; i <= last_index_reg; i++)
9777 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9778 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9779 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9780 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9782 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9783 const_reg = index_reg;
9784 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9789 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9790 (REGY), i.e. BASE, is not clobbered before the last use we'll
9793 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9794 && rtx_equal_p (SET_DEST (prev_set), reg)
9795 && reg_state[regno].use_index >= 0
9796 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid
9801 /* Change destination register and - if necessary - the
9802 constant value in PREV, the constant loading instruction. */
9803 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9804 if (reg_state[regno].offset != const0_rtx)
9805 validate_change (prev,
9806 &SET_SRC (prev_set),
9807 GEN_INT (INTVAL (SET_SRC (prev_set))
9808 + INTVAL (reg_state[regno].offset)),
9810 /* Now for every use of REG that we have recorded, replace REG
9812 for (i = reg_state[regno].use_index;
9813 i < RELOAD_COMBINE_MAX_USES; i++)
9814 validate_change (reg_state[regno].reg_use[i].insn,
9815 reg_state[regno].reg_use[i].usep,
9818 if (apply_change_group ())
9822 /* Delete the reg-reg addition. */
9823 PUT_CODE (insn, NOTE);
9824 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9825 NOTE_SOURCE_FILE (insn) = 0;
9827 if (reg_state[regno].offset != const0_rtx)
9829 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9831 for (np = ®_NOTES (prev); *np; )
9833 if (REG_NOTE_KIND (*np) == REG_EQUAL
9834 || REG_NOTE_KIND (*np) == REG_EQUIV)
9835 *np = XEXP (*np, 1);
9837 np = &XEXP (*np, 1);
9840 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9841 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9846 note_stores (PATTERN (insn), reload_combine_note_store);
9847 if (GET_CODE (insn) == CALL_INSN)
9851 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9853 if (call_used_regs[i])
9855 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9856 reg_state[i].store_ruid = reload_combine_ruid;
9859 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9860 link = XEXP (link, 1))
9862 rtx use = XEXP (link, 0);
9863 int regno = REGNO (XEXP (use, 0));
9864 if (GET_CODE (use) == CLOBBER)
9866 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9867 reg_state[regno].store_ruid = reload_combine_ruid;
9870 reg_state[regno].use_index = -1;
9873 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN)
9875 /* Non-spill registers might be used at the call destination in
9876 some unknown fashion, so we have to mark the unknown use. */
9878 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
9879 && JUMP_LABEL (insn))
9880 live = &LABEL_LIVE (JUMP_LABEL (insn));
9882 live = &ever_live_at_start;
9883 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9885 if (TEST_HARD_REG_BIT (*live, i))
9886 reg_state[i].use_index = -1;
9889 reload_combine_note_use (&PATTERN (insn), insn);
9890 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9892 if (REG_NOTE_KIND (note) == REG_INC
9893 && GET_CODE (XEXP (note, 0)) == REG)
9895 int regno = REGNO (XEXP (note, 0));
9897 reg_state[regno].store_ruid = reload_combine_ruid;
9898 reg_state[regno].use_index = -1;
9905 /* Check if DST is a register or a subreg of a register; if it is,
9906 update reg_state[regno].store_ruid and reg_state[regno].use_index
9907 accordingly. Called via note_stores from reload_combine. */
9909 reload_combine_note_store (dst, set)
9914 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9916 if (GET_CODE (dst) == SUBREG)
9918 regno = SUBREG_WORD (dst);
9919 dst = SUBREG_REG (dst);
9921 if (GET_CODE (dst) != REG)
9923 regno += REGNO (dst);
9925 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9926 careful with registers / register parts that are not full words.
9928 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
9929 if (GET_CODE (set) != SET
9930 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
9931 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
9932 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
9934 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9936 reg_state[i].use_index = -1;
9937 reg_state[i].store_ruid = reload_combine_ruid;
9942 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9944 reg_state[i].store_ruid = reload_combine_ruid;
9945 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9950 /* XP points to a piece of rtl that has to be checked for any uses of
9952 *XP is the pattern of INSN, or a part of it.
9953 Called from reload_combine, and recursively by itself. */
9955 reload_combine_note_use (xp, insn)
9959 enum rtx_code code = x->code;
9962 rtx offset = const0_rtx; /* For the REG case below. */
9967 if (GET_CODE (SET_DEST (x)) == REG)
9969 reload_combine_note_use (&SET_SRC (x), insn);
9975 /* If this is the USE of a return value, we can't change it. */
9976 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
9978 /* Mark the return register as used in an unknown fashion. */
9979 rtx reg = XEXP (x, 0);
9980 int regno = REGNO (reg);
9981 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
9983 while (--nregs >= 0)
9984 reg_state[regno + nregs].use_index = -1;
9990 if (GET_CODE (SET_DEST (x)) == REG)
9995 /* We are interested in (plus (reg) (const_int)) . */
9996 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9998 offset = XEXP (x, 1);
10000 /* Fall through. */
10003 int regno = REGNO (x);
10007 /* Some spurious USEs of pseudo registers might remain.
10008 Just ignore them. */
10009 if (regno >= FIRST_PSEUDO_REGISTER)
10012 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
10014 /* We can't substitute into multi-hard-reg uses. */
10017 while (--nregs >= 0)
10018 reg_state[regno + nregs].use_index = -1;
10022 /* If this register is already used in some unknown fashion, we
10024 If we decrement the index from zero to -1, we can't store more
10025 uses, so this register becomes used in an unknown fashion. */
10026 use_index = --reg_state[regno].use_index;
10030 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
10032 /* We have found another use for a register that is already
10033 used later. Check if the offsets match; if not, mark the
10034 register as used in an unknown fashion. */
10035 if (! rtx_equal_p (offset, reg_state[regno].offset))
10037 reg_state[regno].use_index = -1;
10043 /* This is the first use of this register we have seen since we
10044 marked it as dead. */
10045 reg_state[regno].offset = offset;
10046 reg_state[regno].use_ruid = reload_combine_ruid;
10048 reg_state[regno].reg_use[use_index].insn = insn;
10049 reg_state[regno].reg_use[use_index].usep = xp;
10057 /* Recursively process the components of X. */
10058 fmt = GET_RTX_FORMAT (code);
10059 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10062 reload_combine_note_use (&XEXP (x, i), insn);
10063 else if (fmt[i] == 'E')
10065 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10066 reload_combine_note_use (&XVECEXP (x, i, j), insn);
10071 /* See if we can reduce the cost of a constant by replacing a move with
10073 /* We cannot do our optimization across labels. Invalidating all the
10074 information about register contents we have would be costly, so we
10075 use last_label_luid (local variable of reload_cse_move2add) to note
10076 where the label is and then later disable any optimization that would
10078 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
10079 reg_set_luid[n] is larger than last_label_luid[n] . */
10080 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
10081 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
10082 reg_mode[n] to be valid.
10083 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
10084 has been set to reg_offset[n] in mode reg_mode[n] .
10085 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
10086 register n has been set to the sum of reg_offset[n] and register
10087 reg_base_reg[n], calculated in mode reg_mode[n] . */
10088 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
10089 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
10090 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
10091 /* move2add_luid is linearily increased while scanning the instructions
10092 from first to last. It is used to set reg_set_luid in
10093 reload_cse_move2add and move2add_note_store. */
10094 static int move2add_luid;
10096 /* Generate a CONST_INT and force it in the range of MODE. */
10098 gen_mode_int (mode, value)
10099 enum machine_mode mode;
10100 HOST_WIDE_INT value;
10102 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
10103 int width = GET_MODE_BITSIZE (mode);
10105 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
10107 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
10108 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
10109 cval |= (HOST_WIDE_INT) -1 << width;
10111 return GEN_INT (cval);
10115 reload_cse_move2add (first)
10120 int last_label_luid;
10122 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
10123 reg_set_luid[i] = 0;
10125 last_label_luid = 0;
10127 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
10131 if (GET_CODE (insn) == CODE_LABEL)
10132 last_label_luid = move2add_luid;
10133 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
10135 pat = PATTERN (insn);
10136 /* For simplicity, we only perform this optimization on
10137 straightforward SETs. */
10138 if (GET_CODE (pat) == SET
10139 && GET_CODE (SET_DEST (pat)) == REG)
10141 rtx reg = SET_DEST (pat);
10142 int regno = REGNO (reg);
10143 rtx src = SET_SRC (pat);
10145 /* Check if we have valid information on the contents of this
10146 register in the mode of REG. */
10147 /* ??? We don't know how zero / sign extension is handled, hence
10148 we can't go from a narrower to a wider mode. */
10149 if (reg_set_luid[regno] > last_label_luid
10150 && (GET_MODE_SIZE (GET_MODE (reg))
10151 <= GET_MODE_SIZE (reg_mode[regno]))
10152 && GET_CODE (reg_offset[regno]) == CONST_INT)
10154 /* Try to transform (set (REGX) (CONST_INT A))
10156 (set (REGX) (CONST_INT B))
10158 (set (REGX) (CONST_INT A))
10160 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10162 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
10166 = gen_mode_int (GET_MODE (reg),
10167 INTVAL (src) - INTVAL (reg_offset[regno]));
10168 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
10169 use (set (reg) (reg)) instead.
10170 We don't delete this insn, nor do we convert it into a
10171 note, to avoid losing register notes or the return
10172 value flag. jump2 already knowns how to get rid of
10174 if (new_src == const0_rtx)
10175 success = validate_change (insn, &SET_SRC (pat), reg, 0);
10176 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
10177 && have_add2_insn (GET_MODE (reg)))
10178 success = validate_change (insn, &PATTERN (insn),
10179 gen_add2_insn (reg, new_src), 0);
10180 reg_set_luid[regno] = move2add_luid;
10181 reg_mode[regno] = GET_MODE (reg);
10182 reg_offset[regno] = src;
10186 /* Try to transform (set (REGX) (REGY))
10187 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10189 (set (REGX) (REGY))
10190 (set (REGX) (PLUS (REGX) (CONST_INT B)))
10193 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10195 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10196 else if (GET_CODE (src) == REG
10197 && reg_base_reg[regno] == REGNO (src)
10198 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
10200 rtx next = next_nonnote_insn (insn);
10203 set = single_set (next);
10206 && SET_DEST (set) == reg
10207 && GET_CODE (SET_SRC (set)) == PLUS
10208 && XEXP (SET_SRC (set), 0) == reg
10209 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
10211 rtx src3 = XEXP (SET_SRC (set), 1);
10213 = gen_mode_int (GET_MODE (reg),
10215 - INTVAL (reg_offset[regno]));
10218 if (new_src == const0_rtx)
10219 /* See above why we create (set (reg) (reg)) here. */
10221 = validate_change (next, &SET_SRC (set), reg, 0);
10222 else if ((rtx_cost (new_src, PLUS)
10223 < 2 + rtx_cost (src3, SET))
10224 && have_add2_insn (GET_MODE (reg)))
10226 = validate_change (next, &PATTERN (next),
10227 gen_add2_insn (reg, new_src), 0);
10230 /* INSN might be the first insn in a basic block
10231 if the preceding insn is a conditional jump
10232 or a possible-throwing call. */
10233 PUT_CODE (insn, NOTE);
10234 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
10235 NOTE_SOURCE_FILE (insn) = 0;
10238 reg_set_luid[regno] = move2add_luid;
10239 reg_mode[regno] = GET_MODE (reg);
10240 reg_offset[regno] = src3;
10247 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
10249 if (REG_NOTE_KIND (note) == REG_INC
10250 && GET_CODE (XEXP (note, 0)) == REG)
10252 /* Indicate that this register has been recently written to,
10253 but the exact contents are not available. */
10254 int regno = REGNO (XEXP (note, 0));
10255 if (regno < FIRST_PSEUDO_REGISTER)
10257 reg_set_luid[regno] = move2add_luid;
10258 reg_offset[regno] = note;
10262 note_stores (PATTERN (insn), move2add_note_store);
10263 /* If this is a CALL_INSN, all call used registers are stored with
10265 if (GET_CODE (insn) == CALL_INSN)
10267 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
10269 if (call_used_regs[i])
10271 reg_set_luid[i] = move2add_luid;
10272 reg_offset[i] = insn; /* Invalidate contents. */
10279 /* SET is a SET or CLOBBER that sets DST.
10280 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
10281 Called from reload_cse_move2add via note_stores. */
10283 move2add_note_store (dst, set)
10289 enum machine_mode mode = GET_MODE (dst);
10290 if (GET_CODE (dst) == SUBREG)
10292 regno = SUBREG_WORD (dst);
10293 dst = SUBREG_REG (dst);
10295 if (GET_CODE (dst) != REG)
10298 regno += REGNO (dst);
10300 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
10301 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
10302 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
10303 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
10305 rtx src = SET_SRC (set);
10307 reg_mode[regno] = mode;
10308 switch (GET_CODE (src))
10312 rtx src0 = XEXP (src, 0);
10313 if (GET_CODE (src0) == REG)
10315 if (REGNO (src0) != regno
10316 || reg_offset[regno] != const0_rtx)
10318 reg_base_reg[regno] = REGNO (src0);
10319 reg_set_luid[regno] = move2add_luid;
10321 reg_offset[regno] = XEXP (src, 1);
10324 reg_set_luid[regno] = move2add_luid;
10325 reg_offset[regno] = set; /* Invalidate contents. */
10330 reg_base_reg[regno] = REGNO (SET_SRC (set));
10331 reg_offset[regno] = const0_rtx;
10332 reg_set_luid[regno] = move2add_luid;
10336 reg_base_reg[regno] = -1;
10337 reg_offset[regno] = SET_SRC (set);
10338 reg_set_luid[regno] = move2add_luid;
10344 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
10346 /* Indicate that this register has been recently written to,
10347 but the exact contents are not available. */
10348 reg_set_luid[i] = move2add_luid;
10349 reg_offset[i] = dst;
10354 #ifdef AUTO_INC_DEC
10356 add_auto_inc_notes (insn, x)
10360 enum rtx_code code = GET_CODE (x);
10364 if (code == MEM && auto_inc_p (XEXP (x, 0)))
10367 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
10371 /* Scan all the operand sub-expressions. */
10372 fmt = GET_RTX_FORMAT (code);
10373 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10376 add_auto_inc_notes (insn, XEXP (x, i));
10377 else if (fmt[i] == 'E')
10378 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10379 add_auto_inc_notes (insn, XVECEXP (x, i, j));