sys/dev/serial/rc/rc.c

   1 /*
   2  * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
   3  * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD: src/sys/i386/isa/rc.c,v 1.53.2.1 2001/02/26 04:23:10 jlemon Exp $
  28  * $DragonFly: src/sys/dev/serial/rc/rc.c,v 1.5 2003/07/21 05:50:40 dillon Exp $
  29  *
  30  */
  31
  32 /*
  33  * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
  34  *
  35  */
  36
  37 #include "rc.h"
  38
  39 /*#define RCDEBUG*/
  40
  41 #include <sys/param.h>
  42 #include <sys/systm.h>
  43 #include <sys/tty.h>
  44 #include <sys/proc.h>
  45 #include <sys/conf.h>
  46 #include <sys/dkstat.h>
  47 #include <sys/fcntl.h>
  48 #include <sys/interrupt.h>
  49 #include <sys/kernel.h>
  50 #include <machine/clock.h>
  51 #include <machine/ipl.h>
  52
  53 #include <i386/isa/isa_device.h>
  54
  55 #include <i386/isa/ic/cd180.h>
  56 #include <i386/isa/rcreg.h>
  57
  58 /* Prototypes */
  59 static int     rcprobe         __P((struct isa_device *));
  60 static int     rcattach        __P((struct isa_device *));
  61
  62 #define rcin(port)      RC_IN  (nec, port)
  63 #define rcout(port,v)   RC_OUT (nec, port, v)
  64
  65 #define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
  66 #define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
  67
  68 #define RC_IBUFSIZE     256
  69 #define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
  70 #define RC_OBUFSIZE     512
  71 #define RC_IHIGHWATER   (3 * RC_IBUFSIZE / 4)
  72 #define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
  73 #define LOTS_OF_EVENTS  64
  74
  75 #define RC_FAKEID       0x10
  76
  77 #define RC_PROBED 1
  78 #define RC_ATTACHED 2
  79
  80 #define GET_UNIT(dev)   (minor(dev) & 0x3F)
  81 #define CALLOUT(dev)    (minor(dev) & 0x80)
  82
  83 /* For isa routines */
  84 struct isa_driver rcdriver = {
  85         rcprobe, rcattach, "rc"
  86 };
  87
  88 static  d_open_t        rcopen;
  89 static  d_close_t       rcclose;
  90 static  d_ioctl_t       rcioctl;
  91
  92 #define CDEV_MAJOR      63
  93 static struct cdevsw rc_cdevsw = {
  94         /* name */      "rc",
  95         /* maj */       CDEV_MAJOR,
  96         /* flags */     D_TTY | D_KQFILTER,
  97         /* port */      NULL,
  98         /* autoq */     0,
  99
 100         /* open */      rcopen,
 101         /* close */     rcclose,
 102         /* read */      ttyread,
 103         /* write */     ttywrite,
 104         /* ioctl */     rcioctl,
 105         /* poll */      ttypoll,
 106         /* mmap */      nommap,
 107         /* strategy */  nostrategy,
 108         /* dump */      nodump,
 109         /* psize */     nopsize,
 110         /* kqfilter */  ttykqfilter
 111 };
 112
 113 /* Per-board structure */
 114 static struct rc_softc {
 115         u_int           rcb_probed;     /* 1 - probed, 2 - attached */
 116         u_int           rcb_addr;       /* Base I/O addr        */
 117         u_int           rcb_unit;       /* unit #               */
 118         u_char          rcb_dtr;        /* DTR status           */
 119         struct rc_chans *rcb_baserc;    /* base rc ptr          */
 120 } rc_softc[NRC];
 121
 122 /* Per-channel structure */
 123 static struct rc_chans  {
 124         struct rc_softc *rc_rcb;                /* back ptr             */
 125         u_short          rc_flags;              /* Misc. flags          */
 126         int              rc_chan;               /* Channel #            */
 127         u_char           rc_ier;                /* intr. enable reg     */
 128         u_char           rc_msvr;               /* modem sig. status    */
 129         u_char           rc_cor2;               /* options reg          */
 130         u_char           rc_pendcmd;            /* special cmd pending  */
 131         u_int            rc_dtrwait;            /* dtr timeout          */
 132         u_int            rc_dcdwaits;           /* how many waits DCD in open */
 133         u_char           rc_hotchar;            /* end packed optimize */
 134         struct tty      *rc_tp;                 /* tty struct           */
 135         u_char          *rc_iptr;               /* Chars input buffer         */
 136         u_char          *rc_hiwat;              /* hi-water mark        */
 137         u_char          *rc_bufend;             /* end of buffer        */
 138         u_char          *rc_optr;               /* ptr in output buf    */
 139         u_char          *rc_obufend;            /* end of output buf    */
 140         u_char           rc_ibuf[4 * RC_IBUFSIZE];  /* input buffer         */
 141         u_char           rc_obuf[RC_OBUFSIZE];  /* output buffer        */
 142 } rc_chans[NRC * CD180_NCHAN];
 143
 144 static int rc_scheduled_event = 0;
 145
 146 /* for pstat -t */
 147 static struct tty rc_tty[NRC * CD180_NCHAN];
 148 static const int  nrc_tty = NRC * CD180_NCHAN;
 149
 150 /* Flags */
 151 #define RC_DTR_OFF      0x0001          /* DTR wait, for close/open     */
 152 #define RC_ACTOUT       0x0002          /* Dial-out port active         */
 153 #define RC_RTSFLOW      0x0004          /* RTS flow ctl enabled         */
 154 #define RC_CTSFLOW      0x0008          /* CTS flow ctl enabled         */
 155 #define RC_DORXFER      0x0010          /* RXFER event planned          */
 156 #define RC_DOXXFER      0x0020          /* XXFER event planned          */
 157 #define RC_MODCHG       0x0040          /* Modem status changed         */
 158 #define RC_OSUSP        0x0080          /* Output suspended             */
 159 #define RC_OSBUSY       0x0100          /* start() routine in progress  */
 160 #define RC_WAS_BUFOVFL  0x0200          /* low-level buffer ovferflow   */
 161 #define RC_WAS_SILOVFL  0x0400          /* silo buffer overflow         */
 162 #define RC_SEND_RDY     0x0800          /* ready to send */
 163
 164 /* Table for translation of RCSR status bits to internal form */
 165 static int rc_rcsrt[16] = {
 166         0,             TTY_OE,               TTY_FE,
 167         TTY_FE|TTY_OE, TTY_PE,               TTY_PE|TTY_OE,
 168         TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
 169         TTY_BI|TTY_OE, TTY_BI|TTY_FE,        TTY_BI|TTY_FE|TTY_OE,
 170         TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
 171         TTY_BI|TTY_PE|TTY_FE|TTY_OE
 172 };
 173
 174 /* Static prototypes */
 175 static ointhand2_t rcintr;
 176 static void rc_hwreset          __P((int, int, unsigned int));
 177 static int  rc_test             __P((int, int));
 178 static void rc_discard_output   __P((struct rc_chans *));
 179 static void rc_hardclose        __P((struct rc_chans *));
 180 static int  rc_modctl           __P((struct rc_chans *, int, int));
 181 static void rc_start            __P((struct tty *));
 182 static void rc_stop              __P((struct tty *, int rw));
 183 static int  rc_param            __P((struct tty *, struct termios *));
 184 static swihand_t rcpoll;
 185 static void rc_reinit           __P((struct rc_softc *));
 186 #ifdef RCDEBUG
 187 static void printrcflags();
 188 #endif
 189 static timeout_t rc_dtrwakeup;
 190 static timeout_t rc_wakeup;
 191 static void disc_optim          __P((struct tty *tp, struct termios *t, struct rc_chans *));
 192 static void rc_wait0            __P((int nec, int unit, int chan, int line));
 193
 194 /**********************************************/
 195
 196 /* Quick device probing */
 197 static int
 198 rcprobe(dvp)
 199         struct  isa_device      *dvp;
 200 {
 201         int             irq = ffs(dvp->id_irq) - 1;
 202         register int    nec = dvp->id_iobase;
 203
 204         if (dvp->id_unit > NRC)
 205                 return 0;
 206         if (!RC_VALIDADDR(nec)) {
 207                 printf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
 208                 return 0;
 209         }
 210         if (!RC_VALIDIRQ(irq)) {
 211                 printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
 212                 return 0;
 213         }
 214         rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
 215         rcout(CD180_PPRH, 0x11);
 216         if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
 217                 return 0;
 218         /* Now, test the board more thoroughly, with diagnostic */
 219         if (rc_test(nec, dvp->id_unit))
 220                 return 0;
 221         rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
 222
 223         return 0xF;
 224 }
 225
 226 static int
 227 rcattach(dvp)
 228         struct  isa_device      *dvp;
 229 {
 230         register int            chan, nec = dvp->id_iobase;
 231         struct rc_softc         *rcb = &rc_softc[dvp->id_unit];
 232         struct rc_chans         *rc  = &rc_chans[dvp->id_unit * CD180_NCHAN];
 233         static int              rc_started = 0;
 234         struct tty              *tp;
 235
 236         dvp->id_ointr = rcintr;
 237
 238         /* Thorooughly test the device */
 239         if (rcb->rcb_probed != RC_PROBED)
 240                 return 0;
 241         rcb->rcb_addr   = nec;
 242         rcb->rcb_dtr    = 0;
 243         rcb->rcb_baserc = rc;
 244         rcb->rcb_unit   = dvp->id_unit;
 245         /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
 246         printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
 247                 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
 248
 249         for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
 250                 rc->rc_rcb     = rcb;
 251                 rc->rc_chan    = chan;
 252                 rc->rc_iptr    = rc->rc_ibuf;
 253                 rc->rc_bufend  = &rc->rc_ibuf[RC_IBUFSIZE];
 254                 rc->rc_hiwat   = &rc->rc_ibuf[RC_IHIGHWATER];
 255                 rc->rc_flags   = rc->rc_ier = rc->rc_msvr = 0;
 256                 rc->rc_cor2    = rc->rc_pendcmd = 0;
 257                 rc->rc_optr    = rc->rc_obufend  = rc->rc_obuf;
 258                 rc->rc_dtrwait = 3 * hz;
 259                 rc->rc_dcdwaits= 0;
 260                 rc->rc_hotchar = 0;
 261                 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
 262                 ttychars(tp);
 263                 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
 264                 tp->t_cflag = TTYDEF_CFLAG;
 265                 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
 266         }
 267         rcb->rcb_probed = RC_ATTACHED;
 268         if (!rc_started) {
 269                 cdevsw_add(&rc_cdevsw);
 270                 register_swi(SWI_TTY, rcpoll);
 271                 rc_wakeup((void *)NULL);
 272                 rc_started = 1;
 273         }
 274         return 1;
 275 }
 276
 277 /* RC interrupt handling */
 278 static void
 279 rcintr(unit)
 280         int             unit;
 281 {
 282         register struct rc_softc        *rcb = &rc_softc[unit];
 283         register struct rc_chans        *rc;
 284         register int                    nec, resid;
 285         register u_char                 val, iack, bsr, ucnt, *optr;
 286         int                             good_data, t_state;
 287
 288         if (rcb->rcb_probed != RC_ATTACHED) {
 289                 printf("rc%d: bogus interrupt\n", unit);
 290                 return;
 291         }
 292         nec = rcb->rcb_addr;
 293
 294         bsr = ~(rcin(RC_BSR));
 295
 296         if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
 297                 printf("rc%d: extra interrupt\n", unit);
 298                 rcout(CD180_EOIR, 0);
 299                 return;
 300         }
 301
 302         while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
 303 #ifdef RCDEBUG_DETAILED
 304                 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
 305                         (bsr & RC_BSR_TOUT)?"TOUT ":"",
 306                         (bsr & RC_BSR_RXINT)?"RXINT ":"",
 307                         (bsr & RC_BSR_TXINT)?"TXINT ":"",
 308                         (bsr & RC_BSR_MOINT)?"MOINT":"");
 309 #endif
 310                 if (bsr & RC_BSR_TOUT) {
 311                         printf("rc%d: hardware failure, reset board\n", unit);
 312                         rcout(RC_CTOUT, 0);
 313                         rc_reinit(rcb);
 314                         return;
 315                 }
 316                 if (bsr & RC_BSR_RXINT) {
 317                         iack = rcin(RC_PILR_RX);
 318                         good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
 319                         if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
 320                                 printf("rc%d: fake rxint: %02x\n", unit, iack);
 321                                 goto more_intrs;
 322                         }
 323                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 324                         t_state = rc->rc_tp->t_state;
 325                         /* Do RTS flow control stuff */
 326                         if (  (rc->rc_flags & RC_RTSFLOW)
 327                             || !(t_state & TS_ISOPEN)
 328                            ) {
 329                                 if (  (   !(t_state & TS_ISOPEN)
 330                                        || (t_state & TS_TBLOCK)
 331                                       )
 332                                     && (rc->rc_msvr & MSVR_RTS)
 333                                    )
 334                                         rcout(CD180_MSVR,
 335                                                 rc->rc_msvr &= ~MSVR_RTS);
 336                                 else if (!(rc->rc_msvr & MSVR_RTS))
 337                                         rcout(CD180_MSVR,
 338                                                 rc->rc_msvr |= MSVR_RTS);
 339                         }
 340                         ucnt  = rcin(CD180_RDCR) & 0xF;
 341                         resid = 0;
 342
 343                         if (t_state & TS_ISOPEN) {
 344                                 /* check for input buffer overflow */
 345                                 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
 346                                         resid  = ucnt;
 347                                         ucnt   = rc->rc_bufend - rc->rc_iptr;
 348                                         resid -= ucnt;
 349                                         if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
 350                                                 rc->rc_flags |= RC_WAS_BUFOVFL;
 351                                                 rc_scheduled_event++;
 352                                         }
 353                                 }
 354                                 optr = rc->rc_iptr;
 355                                 /* check foor good data */
 356                                 if (good_data) {
 357                                         while (ucnt-- > 0) {
 358                                                 val = rcin(CD180_RDR);
 359                                                 optr[0] = val;
 360                                                 optr[INPUT_FLAGS_SHIFT] = 0;
 361                                                 optr++;
 362                                                 rc_scheduled_event++;
 363                                                 if (val != 0 && val == rc->rc_hotchar)
 364                                                         setsofttty();
 365                                         }
 366                                 } else {
 367                                         /* Store also status data */
 368                                         while (ucnt-- > 0) {
 369                                                 iack = rcin(CD180_RCSR);
 370                                                 if (iack & RCSR_Timeout)
 371                                                         break;
 372                                                 if (   (iack & RCSR_OE)
 373                                                     && !(rc->rc_flags & RC_WAS_SILOVFL)) {
 374                                                         rc->rc_flags |= RC_WAS_SILOVFL;
 375                                                         rc_scheduled_event++;
 376                                                 }
 377                                                 val = rcin(CD180_RDR);
 378                                                 /*
 379                                                   Don't store PE if IGNPAR and BREAK if IGNBRK,
 380                                                   this hack allows "raw" tty optimization
 381                                                   works even if IGN* is set.
 382                                                 */
 383                                                 if (   !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
 384                                                     || ((!(iack & (RCSR_PE|RCSR_FE))
 385                                                     ||  !(rc->rc_tp->t_iflag & IGNPAR))
 386                                                     && (!(iack & RCSR_Break)
 387                                                     ||  !(rc->rc_tp->t_iflag & IGNBRK)))) {
 388                                                         if (   (iack & (RCSR_PE|RCSR_FE))
 389                                                             && (t_state & TS_CAN_BYPASS_L_RINT)
 390                                                             && ((iack & RCSR_FE)
 391                                                             ||  ((iack & RCSR_PE)
 392                                                             &&  (rc->rc_tp->t_iflag & INPCK))))
 393                                                                 val = 0;
 394                                                         else if (val != 0 && val == rc->rc_hotchar)
 395                                                                 setsofttty();
 396                                                         optr[0] = val;
 397                                                         optr[INPUT_FLAGS_SHIFT] = iack;
 398                                                         optr++;
 399                                                         rc_scheduled_event++;
 400                                                 }
 401                                         }
 402                                 }
 403                                 rc->rc_iptr = optr;
 404                                 rc->rc_flags |= RC_DORXFER;
 405                         } else
 406                                 resid = ucnt;
 407                         /* Clear FIFO if necessary */
 408                         while (resid-- > 0) {
 409                                 if (!good_data)
 410                                         iack = rcin(CD180_RCSR);
 411                                 else
 412                                         iack = 0;
 413                                 if (iack & RCSR_Timeout)
 414                                         break;
 415                                 (void) rcin(CD180_RDR);
 416                         }
 417                         goto more_intrs;
 418                 }
 419                 if (bsr & RC_BSR_MOINT) {
 420                         iack = rcin(RC_PILR_MODEM);
 421                         if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
 422                                 printf("rc%d: fake moint: %02x\n", unit, iack);
 423                                 goto more_intrs;
 424                         }
 425                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 426                         iack = rcin(CD180_MCR);
 427                         rc->rc_msvr = rcin(CD180_MSVR);
 428                         rcout(CD180_MCR, 0);
 429 #ifdef RCDEBUG
 430                         printrcflags(rc, "moint");
 431 #endif
 432                         if (rc->rc_flags & RC_CTSFLOW) {
 433                                 if (rc->rc_msvr & MSVR_CTS)
 434                                         rc->rc_flags |= RC_SEND_RDY;
 435                                 else
 436                                         rc->rc_flags &= ~RC_SEND_RDY;
 437                         } else
 438                                 rc->rc_flags |= RC_SEND_RDY;
 439                         if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
 440                                 rc_scheduled_event += LOTS_OF_EVENTS;
 441                                 rc->rc_flags |= RC_MODCHG;
 442                                 setsofttty();
 443                         }
 444                         goto more_intrs;
 445                 }
 446                 if (bsr & RC_BSR_TXINT) {
 447                         iack = rcin(RC_PILR_TX);
 448                         if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
 449                                 printf("rc%d: fake txint: %02x\n", unit, iack);
 450                                 goto more_intrs;
 451                         }
 452                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 453                         if (    (rc->rc_flags & RC_OSUSP)
 454                             || !(rc->rc_flags & RC_SEND_RDY)
 455                            )
 456                                 goto more_intrs;
 457                         /* Handle breaks and other stuff */
 458                         if (rc->rc_pendcmd) {
 459                                 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
 460                                 rcout(CD180_TDR,  CD180_C_ESC);
 461                                 rcout(CD180_TDR,  rc->rc_pendcmd);
 462                                 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
 463                                 rc->rc_pendcmd = 0;
 464                                 goto more_intrs;
 465                         }
 466                         optr = rc->rc_optr;
 467                         resid = rc->rc_obufend - optr;
 468                         if (resid > CD180_NFIFO)
 469                                 resid = CD180_NFIFO;
 470                         while (resid-- > 0)
 471                                 rcout(CD180_TDR, *optr++);
 472                         rc->rc_optr = optr;
 473
 474                         /* output completed? */
 475                         if (optr >= rc->rc_obufend) {
 476                                 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
 477 #ifdef RCDEBUG
 478                                 printf("rc%d/%d: output completed\n", unit, rc->rc_chan);
 479 #endif
 480                                 if (!(rc->rc_flags & RC_DOXXFER)) {
 481                                         rc_scheduled_event += LOTS_OF_EVENTS;
 482                                         rc->rc_flags |= RC_DOXXFER;
 483                                         setsofttty();
 484                                 }
 485                         }
 486                 }
 487         more_intrs:
 488                 rcout(CD180_EOIR, 0);   /* end of interrupt */
 489                 rcout(RC_CTOUT, 0);
 490                 bsr = ~(rcin(RC_BSR));
 491         }
 492 }
 493
 494 /* Feed characters to output buffer */
 495 static void rc_start(tp)
 496 register struct tty *tp;
 497 {
 498         register struct rc_chans       *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 499         register int                    nec = rc->rc_rcb->rcb_addr, s;
 500
 501         if (rc->rc_flags & RC_OSBUSY)
 502                 return;
 503         s = spltty();
 504         rc->rc_flags |= RC_OSBUSY;
 505         disable_intr();
 506         if (tp->t_state & TS_TTSTOP)
 507                 rc->rc_flags |= RC_OSUSP;
 508         else
 509                 rc->rc_flags &= ~RC_OSUSP;
 510         /* Do RTS flow control stuff */
 511         if (   (rc->rc_flags & RC_RTSFLOW)
 512             && (tp->t_state & TS_TBLOCK)
 513             && (rc->rc_msvr & MSVR_RTS)
 514            ) {
 515                 rcout(CD180_CAR, rc->rc_chan);
 516                 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
 517         } else if (!(rc->rc_msvr & MSVR_RTS)) {
 518                 rcout(CD180_CAR, rc->rc_chan);
 519                 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
 520         }
 521         enable_intr();
 522         if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
 523                 goto out;
 524 #ifdef RCDEBUG
 525         printrcflags(rc, "rcstart");
 526 #endif
 527         ttwwakeup(tp);
 528 #ifdef RCDEBUG
 529         printf("rcstart: outq = %d obuf = %d\n",
 530                 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
 531 #endif
 532         if (tp->t_state & TS_BUSY)
 533                 goto    out;    /* output still in progress ... */
 534
 535         if (tp->t_outq.c_cc > 0) {
 536                 u_int   ocnt;
 537
 538                 tp->t_state |= TS_BUSY;
 539                 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
 540                 disable_intr();
 541                 rc->rc_optr = rc->rc_obuf;
 542                 rc->rc_obufend = rc->rc_optr + ocnt;
 543                 enable_intr();
 544                 if (!(rc->rc_ier & IER_TxRdy)) {
 545 #ifdef RCDEBUG
 546                         printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
 547 #endif
 548                         rcout(CD180_CAR, rc->rc_chan);
 549                         rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
 550                 }
 551         }
 552 out:
 553         rc->rc_flags &= ~RC_OSBUSY;
 554         (void) splx(s);
 555 }
 556
 557 /* Handle delayed events. */
 558 void rcpoll()
 559 {
 560         register struct rc_chans *rc;
 561         register struct rc_softc *rcb;
 562         register u_char        *tptr, *eptr;
 563         register struct tty    *tp;
 564         register int            chan, icnt, nec, unit;
 565
 566         if (rc_scheduled_event == 0)
 567                 return;
 568 repeat:
 569         for (unit = 0; unit < NRC; unit++) {
 570                 rcb = &rc_softc[unit];
 571                 rc = rcb->rcb_baserc;
 572                 nec = rc->rc_rcb->rcb_addr;
 573                 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
 574                         tp = rc->rc_tp;
 575 #ifdef RCDEBUG
 576                         if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
 577                             RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
 578                                 printrcflags(rc, "rcevent");
 579 #endif
 580                         if (rc->rc_flags & RC_WAS_BUFOVFL) {
 581                                 disable_intr();
 582                                 rc->rc_flags &= ~RC_WAS_BUFOVFL;
 583                                 rc_scheduled_event--;
 584                                 enable_intr();
 585                                 printf("rc%d/%d: interrupt-level buffer overflow\n",
 586                                         unit, chan);
 587                         }
 588                         if (rc->rc_flags & RC_WAS_SILOVFL) {
 589                                 disable_intr();
 590                                 rc->rc_flags &= ~RC_WAS_SILOVFL;
 591                                 rc_scheduled_event--;
 592                                 enable_intr();
 593                                 printf("rc%d/%d: silo overflow\n",
 594                                         unit, chan);
 595                         }
 596                         if (rc->rc_flags & RC_MODCHG) {
 597                                 disable_intr();
 598                                 rc->rc_flags &= ~RC_MODCHG;
 599                                 rc_scheduled_event -= LOTS_OF_EVENTS;
 600                                 enable_intr();
 601                                 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
 602                         }
 603                         if (rc->rc_flags & RC_DORXFER) {
 604                                 disable_intr();
 605                                 rc->rc_flags &= ~RC_DORXFER;
 606                                 eptr = rc->rc_iptr;
 607                                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
 608                                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
 609                                 else
 610                                         tptr = rc->rc_ibuf;
 611                                 icnt = eptr - tptr;
 612                                 if (icnt > 0) {
 613                                         if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
 614                                                 rc->rc_iptr   = rc->rc_ibuf;
 615                                                 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
 616                                                 rc->rc_hiwat  = &rc->rc_ibuf[RC_IHIGHWATER];
 617                                         } else {
 618                                                 rc->rc_iptr   = &rc->rc_ibuf[RC_IBUFSIZE];
 619                                                 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
 620                                                 rc->rc_hiwat  =
 621                                                         &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
 622                                         }
 623                                         if (   (rc->rc_flags & RC_RTSFLOW)
 624                                             && (tp->t_state & TS_ISOPEN)
 625                                             && !(tp->t_state & TS_TBLOCK)
 626                                             && !(rc->rc_msvr & MSVR_RTS)
 627                                             ) {
 628                                                 rcout(CD180_CAR, chan);
 629                                                 rcout(CD180_MSVR,
 630                                                         rc->rc_msvr |= MSVR_RTS);
 631                                         }
 632                                         rc_scheduled_event -= icnt;
 633                                 }
 634                                 enable_intr();
 635
 636                                 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
 637                                         goto done1;
 638
 639                                 if (   (tp->t_state & TS_CAN_BYPASS_L_RINT)
 640                                     && !(tp->t_state & TS_LOCAL)) {
 641                                         if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
 642                                             && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
 643                                             && !(tp->t_state & TS_TBLOCK))
 644                                                 ttyblock(tp);
 645                                         tk_nin += icnt;
 646                                         tk_rawcc += icnt;
 647                                         tp->t_rawcc += icnt;
 648                                         if (b_to_q(tptr, icnt, &tp->t_rawq))
 649                                                 printf("rc%d/%d: tty-level buffer overflow\n",
 650                                                         unit, chan);
 651                                         ttwakeup(tp);
 652                                         if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
 653                                             || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
 654                                                 tp->t_state &= ~TS_TTSTOP;
 655                                                 tp->t_lflag &= ~FLUSHO;
 656                                                 rc_start(tp);
 657                                         }
 658                                 } else {
 659                                         for (; tptr < eptr; tptr++)
 660                                                 (*linesw[tp->t_line].l_rint)
 661                                                     (tptr[0] |
 662                                                     rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
 663                                 }
 664 done1: ;
 665                         }
 666                         if (rc->rc_flags & RC_DOXXFER) {
 667                                 disable_intr();
 668                                 rc_scheduled_event -= LOTS_OF_EVENTS;
 669                                 rc->rc_flags &= ~RC_DOXXFER;
 670                                 rc->rc_tp->t_state &= ~TS_BUSY;
 671                                 enable_intr();
 672                                 (*linesw[tp->t_line].l_start)(tp);
 673                         }
 674                 }
 675                 if (rc_scheduled_event == 0)
 676                         break;
 677         }
 678         if (rc_scheduled_event >= LOTS_OF_EVENTS)
 679                 goto repeat;
 680 }
 681
 682 static  void
 683 rc_stop(tp, rw)
 684         register struct tty     *tp;
 685         int                     rw;
 686 {
 687         register struct rc_chans        *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 688         u_char *tptr, *eptr;
 689
 690 #ifdef RCDEBUG
 691         printf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
 692                 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
 693 #endif
 694         if (rw & FWRITE)
 695                 rc_discard_output(rc);
 696         disable_intr();
 697         if (rw & FREAD) {
 698                 rc->rc_flags &= ~RC_DORXFER;
 699                 eptr = rc->rc_iptr;
 700                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
 701                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
 702                         rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
 703                 } else {
 704                         tptr = rc->rc_ibuf;
 705                         rc->rc_iptr = rc->rc_ibuf;
 706                 }
 707                 rc_scheduled_event -= eptr - tptr;
 708         }
 709         if (tp->t_state & TS_TTSTOP)
 710                 rc->rc_flags |= RC_OSUSP;
 711         else
 712                 rc->rc_flags &= ~RC_OSUSP;
 713         enable_intr();
 714 }
 715
 716 static  int
 717 rcopen(dev, flag, mode, p)
 718         dev_t           dev;
 719         int             flag, mode;
 720         struct proc    *p;
 721 {
 722         register struct rc_chans *rc;
 723         register struct tty      *tp;
 724         int             unit, nec, s, error = 0;
 725
 726         unit = GET_UNIT(dev);
 727         if (unit >= NRC * CD180_NCHAN)
 728                 return ENXIO;
 729         if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
 730                 return ENXIO;
 731         rc  = &rc_chans[unit];
 732         tp  = rc->rc_tp;
 733         dev->si_tty = tp;
 734         nec = rc->rc_rcb->rcb_addr;
 735 #ifdef RCDEBUG
 736         printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
 737 #endif
 738         s = spltty();
 739
 740 again:
 741         while (rc->rc_flags & RC_DTR_OFF) {
 742                 error = tsleep(&(rc->rc_dtrwait), PCATCH, "rcdtr", 0);
 743                 if (error != 0)
 744                         goto out;
 745         }
 746         if (tp->t_state & TS_ISOPEN) {
 747                 if (CALLOUT(dev)) {
 748                         if (!(rc->rc_flags & RC_ACTOUT)) {
 749                                 error = EBUSY;
 750                                 goto out;
 751                         }
 752                 } else {
 753                         if (rc->rc_flags & RC_ACTOUT) {
 754                                 if (flag & O_NONBLOCK) {
 755                                         error = EBUSY;
 756                                         goto out;
 757                                 }
 758                                 error = tsleep(&rc->rc_rcb, PCATCH, "rcbi", 0);
 759                                 if (error)
 760                                         goto out;
 761                                 goto again;
 762                         }
 763                 }
 764                 if (tp->t_state & TS_XCLUDE &&
 765                     suser(td)) {
 766                         error = EBUSY;
 767                         goto out;
 768                 }
 769         } else {
 770                 tp->t_oproc   = rc_start;
 771                 tp->t_param   = rc_param;
 772                 tp->t_stop    = rc_stop;
 773                 tp->t_dev     = dev;
 774
 775                 if (CALLOUT(dev))
 776                         tp->t_cflag |= CLOCAL;
 777                 else
 778                         tp->t_cflag &= ~CLOCAL;
 779
 780                 error = rc_param(tp, &tp->t_termios);
 781                 if (error)
 782                         goto out;
 783                 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
 784
 785                 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
 786                         (*linesw[tp->t_line].l_modem)(tp, 1);
 787         }
 788         if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
 789             && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
 790                 rc->rc_dcdwaits++;
 791                 error = tsleep(TSA_CARR_ON(tp), PCATCH, "rcdcd", 0);
 792                 rc->rc_dcdwaits--;
 793                 if (error != 0)
 794                         goto out;
 795                 goto again;
 796         }
 797         error = (*linesw[tp->t_line].l_open)(dev, tp);
 798         disc_optim(tp, &tp->t_termios, rc);
 799         if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
 800                 rc->rc_flags |= RC_ACTOUT;
 801 out:
 802         (void) splx(s);
 803
 804         if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
 805                 rc_hardclose(rc);
 806
 807         return error;
 808 }
 809
 810 static  int
 811 rcclose(dev, flag, mode, p)
 812         dev_t           dev;
 813         int             flag, mode;
 814         struct proc    *p;
 815 {
 816         register struct rc_chans *rc;
 817         register struct tty      *tp;
 818         int  s, unit = GET_UNIT(dev);
 819
 820         if (unit >= NRC * CD180_NCHAN)
 821                 return ENXIO;
 822         rc  = &rc_chans[unit];
 823         tp  = rc->rc_tp;
 824 #ifdef RCDEBUG
 825         printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
 826 #endif
 827         s = spltty();
 828         (*linesw[tp->t_line].l_close)(tp, flag);
 829         disc_optim(tp, &tp->t_termios, rc);
 830         rc_stop(tp, FREAD | FWRITE);
 831         rc_hardclose(rc);
 832         ttyclose(tp);
 833         splx(s);
 834         return 0;
 835 }
 836
 837 static void rc_hardclose(rc)
 838 register struct rc_chans *rc;
 839 {
 840         register int s, nec = rc->rc_rcb->rcb_addr;
 841         register struct tty *tp = rc->rc_tp;
 842
 843         s = spltty();
 844         rcout(CD180_CAR, rc->rc_chan);
 845
 846         /* Disable rx/tx intrs */
 847         rcout(CD180_IER, rc->rc_ier = 0);
 848         if (   (tp->t_cflag & HUPCL)
 849             || (!(rc->rc_flags & RC_ACTOUT)
 850                && !(rc->rc_msvr & MSVR_CD)
 851                && !(tp->t_cflag & CLOCAL))
 852             || !(tp->t_state & TS_ISOPEN)
 853            ) {
 854                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
 855                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
 856                 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
 857                 if (rc->rc_dtrwait) {
 858                         timeout(rc_dtrwakeup, rc, rc->rc_dtrwait);
 859                         rc->rc_flags |= RC_DTR_OFF;
 860                 }
 861         }
 862         rc->rc_flags &= ~RC_ACTOUT;
 863         wakeup((caddr_t) &rc->rc_rcb);  /* wake bi */
 864         wakeup(TSA_CARR_ON(tp));
 865         (void) splx(s);
 866 }
 867
 868 /* Reset the bastard */
 869 static void rc_hwreset(unit, nec, chipid)
 870         register int    unit, nec;
 871         unsigned int    chipid;
 872 {
 873         CCRCMD(unit, -1, CCR_HWRESET);            /* Hardware reset */
 874         DELAY(20000);
 875         WAITFORCCR(unit, -1);
 876
 877         rcout(RC_CTOUT, 0);             /* Clear timeout  */
 878         rcout(CD180_GIVR,  chipid);
 879         rcout(CD180_GICR,  0);
 880
 881         /* Set Prescaler Registers (1 msec) */
 882         rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
 883         rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
 884
 885         /* Initialize Priority Interrupt Level Registers */
 886         rcout(CD180_PILR1, RC_PILR_MODEM);
 887         rcout(CD180_PILR2, RC_PILR_TX);
 888         rcout(CD180_PILR3, RC_PILR_RX);
 889
 890         /* Reset DTR */
 891         rcout(RC_DTREG, ~0);
 892 }
 893
 894 /* Set channel parameters */
 895 static int rc_param(tp, ts)
 896         register struct  tty    *tp;
 897         struct termios          *ts;
 898 {
 899         register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 900         register int    nec = rc->rc_rcb->rcb_addr;
 901         int      idivs, odivs, s, val, cflag, iflag, lflag, inpflow;
 902
 903         if (   ts->c_ospeed < 0 || ts->c_ospeed > 76800
 904             || ts->c_ispeed < 0 || ts->c_ispeed > 76800
 905            )
 906                 return (EINVAL);
 907         if (ts->c_ispeed == 0)
 908                 ts->c_ispeed = ts->c_ospeed;
 909         odivs = RC_BRD(ts->c_ospeed);
 910         idivs = RC_BRD(ts->c_ispeed);
 911
 912         s = spltty();
 913
 914         /* Select channel */
 915         rcout(CD180_CAR, rc->rc_chan);
 916
 917         /* If speed == 0, hangup line */
 918         if (ts->c_ospeed == 0) {
 919                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
 920                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
 921                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
 922         }
 923
 924         tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
 925         cflag = ts->c_cflag;
 926         iflag = ts->c_iflag;
 927         lflag = ts->c_lflag;
 928
 929         if (idivs > 0) {
 930                 rcout(CD180_RBPRL, idivs & 0xFF);
 931                 rcout(CD180_RBPRH, idivs >> 8);
 932         }
 933         if (odivs > 0) {
 934                 rcout(CD180_TBPRL, odivs & 0xFF);
 935                 rcout(CD180_TBPRH, odivs >> 8);
 936         }
 937
 938         /* set timeout value */
 939         if (ts->c_ispeed > 0) {
 940                 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
 941
 942                 if (   !(lflag & ICANON)
 943                     && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
 944                     && ts->c_cc[VTIME] * 10 > itm)
 945                         itm = ts->c_cc[VTIME] * 10;
 946
 947                 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
 948         }
 949
 950         switch (cflag & CSIZE) {
 951                 case CS5:       val = COR1_5BITS;      break;
 952                 case CS6:       val = COR1_6BITS;      break;
 953                 case CS7:       val = COR1_7BITS;      break;
 954                 default:
 955                 case CS8:       val = COR1_8BITS;      break;
 956         }
 957         if (cflag & PARENB) {
 958                 val |= COR1_NORMPAR;
 959                 if (cflag & PARODD)
 960                         val |= COR1_ODDP;
 961                 if (!(cflag & INPCK))
 962                         val |= COR1_Ignore;
 963         } else
 964                 val |= COR1_Ignore;
 965         if (cflag & CSTOPB)
 966                 val |= COR1_2SB;
 967         rcout(CD180_COR1, val);
 968
 969         /* Set FIFO threshold */
 970         val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
 971         inpflow = 0;
 972         if (   (iflag & IXOFF)
 973             && (   ts->c_cc[VSTOP] != _POSIX_VDISABLE
 974                 && (   ts->c_cc[VSTART] != _POSIX_VDISABLE
 975                     || (iflag & IXANY)
 976                    )
 977                )
 978            ) {
 979                 inpflow = 1;
 980                 val |= COR3_SCDE|COR3_FCT;
 981         }
 982         rcout(CD180_COR3, val);
 983
 984         /* Initialize on-chip automatic flow control */
 985         val = 0;
 986         rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
 987         if (cflag & CCTS_OFLOW) {
 988                 rc->rc_flags |= RC_CTSFLOW;
 989                 val |= COR2_CtsAE;
 990         } else
 991                 rc->rc_flags |= RC_SEND_RDY;
 992         if (tp->t_state & TS_TTSTOP)
 993                 rc->rc_flags |= RC_OSUSP;
 994         else
 995                 rc->rc_flags &= ~RC_OSUSP;
 996         if (cflag & CRTS_IFLOW)
 997                 rc->rc_flags |= RC_RTSFLOW;
 998         else
 999                 rc->rc_flags &= ~RC_RTSFLOW;
1000
1001         if (inpflow) {
1002                 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
1003                         rcout(CD180_SCHR1, ts->c_cc[VSTART]);
1004                 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
1005                 val |= COR2_TxIBE;
1006                 if (iflag & IXANY)
1007                         val |= COR2_IXM;
1008         }
1009
1010         rcout(CD180_COR2, rc->rc_cor2 = val);
1011
1012         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1013                 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1014
1015         disc_optim(tp, ts, rc);
1016
1017         /* modem ctl */
1018         val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1019         if (cflag & CCTS_OFLOW)
1020                 val |= MCOR1_CTSzd;
1021         rcout(CD180_MCOR1, val);
1022
1023         val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1024         if (cflag & CCTS_OFLOW)
1025                 val |= MCOR2_CTSod;
1026         rcout(CD180_MCOR2, val);
1027
1028         /* enable i/o and interrupts */
1029         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1030                 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1031         WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1032
1033         rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1034         if (cflag & CCTS_OFLOW)
1035                 rc->rc_ier |= IER_CTS;
1036         if (cflag & CREAD)
1037                 rc->rc_ier |= IER_RxData;
1038         if (tp->t_state & TS_BUSY)
1039                 rc->rc_ier |= IER_TxRdy;
1040         if (ts->c_ospeed != 0)
1041                 rc_modctl(rc, TIOCM_DTR, DMBIS);
1042         if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1043                 rc->rc_flags |= RC_SEND_RDY;
1044         rcout(CD180_IER, rc->rc_ier);
1045         (void) splx(s);
1046         return 0;
1047 }
1048
1049 /* Re-initialize board after bogus interrupts */
1050 static void rc_reinit(rcb)
1051 struct rc_softc         *rcb;
1052 {
1053         register struct rc_chans       *rc, *rce;
1054         register int                    nec;
1055
1056         nec = rcb->rcb_addr;
1057         rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1058         rc  = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1059         rce = rc + CD180_NCHAN;
1060         for (; rc < rce; rc++)
1061                 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1062 }
1063
1064 static  int
1065 rcioctl(dev, cmd, data, flag, p)
1066 dev_t           dev;
1067 u_long          cmd;
1068 int             flag;
1069 caddr_t         data;
1070 struct proc     *p;
1071 {
1072         register struct rc_chans       *rc = &rc_chans[GET_UNIT(dev)];
1073         register int                    s, error;
1074         struct tty                     *tp = rc->rc_tp;
1075
1076         error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
1077         if (error != ENOIOCTL)
1078                 return (error);
1079         error = ttioctl(tp, cmd, data, flag);
1080         disc_optim(tp, &tp->t_termios, rc);
1081         if (error != ENOIOCTL)
1082                 return (error);
1083         s = spltty();
1084
1085         switch (cmd) {
1086             case TIOCSBRK:
1087                 rc->rc_pendcmd = CD180_C_SBRK;
1088                 break;
1089
1090             case TIOCCBRK:
1091                 rc->rc_pendcmd = CD180_C_EBRK;
1092                 break;
1093
1094             case TIOCSDTR:
1095                 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1096                 break;
1097
1098             case TIOCCDTR:
1099                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1100                 break;
1101
1102             case TIOCMGET:
1103                 *(int *) data = rc_modctl(rc, 0, DMGET);
1104                 break;
1105
1106             case TIOCMSET:
1107                 (void) rc_modctl(rc, *(int *) data, DMSET);
1108                 break;
1109
1110             case TIOCMBIC:
1111                 (void) rc_modctl(rc, *(int *) data, DMBIC);
1112                 break;
1113
1114             case TIOCMBIS:
1115                 (void) rc_modctl(rc, *(int *) data, DMBIS);
1116                 break;
1117
1118             case TIOCMSDTRWAIT:
1119                 error = suser(td);
1120                 if (error != 0) {
1121                         splx(s);
1122                         return (error);
1123                 }
1124                 rc->rc_dtrwait = *(int *)data * hz / 100;
1125                 break;
1126
1127             case TIOCMGDTRWAIT:
1128                 *(int *)data = rc->rc_dtrwait * 100 / hz;
1129                 break;
1130
1131             default:
1132                 (void) splx(s);
1133                 return ENOTTY;
1134         }
1135         (void) splx(s);
1136         return 0;
1137 }
1138
1139
1140 /* Modem control routines */
1141
1142 static int rc_modctl(rc, bits, cmd)
1143 register struct rc_chans       *rc;
1144 int                             bits, cmd;
1145 {
1146         register int    nec = rc->rc_rcb->rcb_addr;
1147         u_char         *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1148
1149         rcout(CD180_CAR, rc->rc_chan);
1150
1151         switch (cmd) {
1152             case DMSET:
1153                 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1154                                 ~(*dtr |= 1 << rc->rc_chan) :
1155                                 ~(*dtr &= ~(1 << rc->rc_chan)));
1156                 msvr = rcin(CD180_MSVR);
1157                 if (bits & TIOCM_RTS)
1158                         msvr |= MSVR_RTS;
1159                 else
1160                         msvr &= ~MSVR_RTS;
1161                 if (bits & TIOCM_DTR)
1162                         msvr |= MSVR_DTR;
1163                 else
1164                         msvr &= ~MSVR_DTR;
1165                 rcout(CD180_MSVR, msvr);
1166                 break;
1167
1168             case DMBIS:
1169                 if (bits & TIOCM_DTR)
1170                         rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1171                 msvr = rcin(CD180_MSVR);
1172                 if (bits & TIOCM_RTS)
1173                         msvr |= MSVR_RTS;
1174                 if (bits & TIOCM_DTR)
1175                         msvr |= MSVR_DTR;
1176                 rcout(CD180_MSVR, msvr);
1177                 break;
1178
1179             case DMGET:
1180                 bits = TIOCM_LE;
1181                 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1182
1183                 if (msvr & MSVR_RTS)
1184                         bits |= TIOCM_RTS;
1185                 if (msvr & MSVR_CTS)
1186                         bits |= TIOCM_CTS;
1187                 if (msvr & MSVR_DSR)
1188                         bits |= TIOCM_DSR;
1189                 if (msvr & MSVR_DTR)
1190                         bits |= TIOCM_DTR;
1191                 if (msvr & MSVR_CD)
1192                         bits |= TIOCM_CD;
1193                 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1194                         bits |= TIOCM_RI;
1195                 return bits;
1196
1197             case DMBIC:
1198                 if (bits & TIOCM_DTR)
1199                         rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1200                 msvr = rcin(CD180_MSVR);
1201                 if (bits & TIOCM_RTS)
1202                         msvr &= ~MSVR_RTS;
1203                 if (bits & TIOCM_DTR)
1204                         msvr &= ~MSVR_DTR;
1205                 rcout(CD180_MSVR, msvr);
1206                 break;
1207         }
1208         rc->rc_msvr = rcin(CD180_MSVR);
1209         return 0;
1210 }
1211
1212 /* Test the board. */
1213 int rc_test(nec, unit)
1214         register int    nec;
1215         int             unit;
1216 {
1217         int     chan = 0;
1218         int     i = 0, rcnt, old_level;
1219         unsigned int    iack, chipid;
1220         unsigned short  divs;
1221         static  u_char  ctest[] = "\377\125\252\045\244\0\377";
1222 #define CTLEN   8
1223 #define ERR(s)  { \
1224                 printf("rc%d: ", unit); printf s ; printf("\n"); \
1225                 (void) splx(old_level); return 1; }
1226
1227         struct rtest {
1228                 u_char  txbuf[CD180_NFIFO];     /* TX buffer  */
1229                 u_char  rxbuf[CD180_NFIFO];     /* RX buffer  */
1230                 int     rxptr;                  /* RX pointer */
1231                 int     txptr;                  /* TX pointer */
1232         } tchans[CD180_NCHAN];
1233
1234         old_level = spltty();
1235
1236         chipid = RC_FAKEID;
1237
1238         /* First, reset board to inital state */
1239         rc_hwreset(unit, nec, chipid);
1240
1241         divs = RC_BRD(19200);
1242
1243         /* Initialize channels */
1244         for (chan = 0; chan < CD180_NCHAN; chan++) {
1245
1246                 /* Select and reset channel */
1247                 rcout(CD180_CAR, chan);
1248                 CCRCMD(unit, chan, CCR_ResetChan);
1249                 WAITFORCCR(unit, chan);
1250
1251                 /* Set speed */
1252                 rcout(CD180_RBPRL, divs & 0xFF);
1253                 rcout(CD180_RBPRH, divs >> 8);
1254                 rcout(CD180_TBPRL, divs & 0xFF);
1255                 rcout(CD180_TBPRH, divs >> 8);
1256
1257                 /* set timeout value */
1258                 rcout(CD180_RTPR,  0);
1259
1260                 /* Establish local loopback */
1261                 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1262                 rcout(CD180_COR2, COR2_LLM);
1263                 rcout(CD180_COR3, CD180_NFIFO);
1264                 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1265                 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1266                 WAITFORCCR(unit, chan);
1267                 rcout(CD180_MSVR, MSVR_RTS);
1268
1269                 /* Fill TXBUF with test data */
1270                 for (i = 0; i < CD180_NFIFO; i++) {
1271                         tchans[chan].txbuf[i] = ctest[i];
1272                         tchans[chan].rxbuf[i] = 0;
1273                 }
1274                 tchans[chan].txptr = tchans[chan].rxptr = 0;
1275
1276                 /* Now, start transmit */
1277                 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1278         }
1279         /* Pseudo-interrupt poll stuff */
1280         for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1281                 i = ~(rcin(RC_BSR));
1282                 if (i & RC_BSR_TOUT)
1283                         ERR(("BSR timeout bit set\n"))
1284                 else if (i & RC_BSR_TXINT) {
1285                         iack = rcin(RC_PILR_TX);
1286                         if (iack != (GIVR_IT_TDI | chipid))
1287                                 ERR(("Bad TX intr ack (%02x != %02x)\n",
1288                                         iack, GIVR_IT_TDI | chipid));
1289                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1290                         /* If no more data to transmit, disable TX intr */
1291                         if (tchans[chan].txptr >= CD180_NFIFO) {
1292                                 iack = rcin(CD180_IER);
1293                                 rcout(CD180_IER, iack & ~IER_TxMpty);
1294                         } else {
1295                                 for (iack = tchans[chan].txptr;
1296                                     iack < CD180_NFIFO; iack++)
1297                                         rcout(CD180_TDR,
1298                                             tchans[chan].txbuf[iack]);
1299                                 tchans[chan].txptr = iack;
1300                         }
1301                         rcout(CD180_EOIR, 0);
1302                 } else if (i & RC_BSR_RXINT) {
1303                         u_char ucnt;
1304
1305                         iack = rcin(RC_PILR_RX);
1306                         if (iack != (GIVR_IT_RGDI | chipid) &&
1307                             iack != (GIVR_IT_REI  | chipid))
1308                                 ERR(("Bad RX intr ack (%02x != %02x)\n",
1309                                         iack, GIVR_IT_RGDI | chipid))
1310                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1311                         ucnt = rcin(CD180_RDCR) & 0xF;
1312                         while (ucnt-- > 0) {
1313                                 iack = rcin(CD180_RCSR);
1314                                 if (iack & RCSR_Timeout)
1315                                         break;
1316                                 if (iack & 0xF)
1317                                         ERR(("Bad char chan %d (RCSR = %02X)\n",
1318                                             chan, iack))
1319                                 if (tchans[chan].rxptr > CD180_NFIFO)
1320                                         ERR(("Got extra chars chan %d\n",
1321                                             chan))
1322                                 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1323                                         rcin(CD180_RDR);
1324                         }
1325                         rcout(CD180_EOIR, 0);
1326                 }
1327                 rcout(RC_CTOUT, 0);
1328                 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1329                         if (tchans[chan].rxptr >= CD180_NFIFO)
1330                                 iack++;
1331                 if (iack == CD180_NCHAN)
1332                         break;
1333         }
1334         for (chan = 0; chan < CD180_NCHAN; chan++) {
1335                 /* Select and reset channel */
1336                 rcout(CD180_CAR, chan);
1337                 CCRCMD(unit, chan, CCR_ResetChan);
1338         }
1339
1340         if (!rcnt)
1341                 ERR(("looses characters during local loopback\n"))
1342         /* Now, check data */
1343         for (chan = 0; chan < CD180_NCHAN; chan++)
1344                 for (i = 0; i < CD180_NFIFO; i++)
1345                         if (ctest[i] != tchans[chan].rxbuf[i])
1346                                 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1347                                     chan, i, ctest[i], tchans[chan].rxbuf[i]))
1348         (void) splx(old_level);
1349         return 0;
1350 }
1351
1352 #ifdef RCDEBUG
1353 static void printrcflags(rc, comment)
1354 struct rc_chans  *rc;
1355 char             *comment;
1356 {
1357         u_short f = rc->rc_flags;
1358         register int    nec = rc->rc_rcb->rcb_addr;
1359
1360         printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1361                 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1362                 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1363                 (f & RC_ACTOUT) ?"ACTOUT " :"",
1364                 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1365                 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1366                 (f & RC_DORXFER)?"DORXFER " :"",
1367                 (f & RC_DOXXFER)?"DOXXFER " :"",
1368                 (f & RC_MODCHG) ?"MODCHG "  :"",
1369                 (f & RC_OSUSP)  ?"OSUSP " :"",
1370                 (f & RC_OSBUSY) ?"OSBUSY " :"",
1371                 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1372                 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1373                 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1374
1375         rcout(CD180_CAR, rc->rc_chan);
1376
1377         printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1378                 rc->rc_rcb->rcb_unit, rc->rc_chan,
1379                 rcin(CD180_MSVR),
1380                 rcin(CD180_IER),
1381                 rcin(CD180_CCSR));
1382 }
1383 #endif /* RCDEBUG */
1384
1385 static void
1386 rc_dtrwakeup(chan)
1387         void    *chan;
1388 {
1389         struct rc_chans  *rc;
1390
1391         rc = (struct rc_chans *)chan;
1392         rc->rc_flags &= ~RC_DTR_OFF;
1393         wakeup(&rc->rc_dtrwait);
1394 }
1395
1396 static void
1397 rc_discard_output(rc)
1398         struct rc_chans  *rc;
1399 {
1400         disable_intr();
1401         if (rc->rc_flags & RC_DOXXFER) {
1402                 rc_scheduled_event -= LOTS_OF_EVENTS;
1403                 rc->rc_flags &= ~RC_DOXXFER;
1404         }
1405         rc->rc_optr = rc->rc_obufend;
1406         rc->rc_tp->t_state &= ~TS_BUSY;
1407         enable_intr();
1408         ttwwakeup(rc->rc_tp);
1409 }
1410
1411 static void
1412 rc_wakeup(chan)
1413         void    *chan;
1414 {
1415         timeout(rc_wakeup, (caddr_t)NULL, 1);
1416
1417         if (rc_scheduled_event != 0) {
1418                 int     s;
1419
1420                 s = splsofttty();
1421                 rcpoll();
1422                 splx(s);
1423         }
1424 }
1425
1426 static void
1427 disc_optim(tp, t, rc)
1428         struct tty      *tp;
1429         struct termios  *t;
1430         struct rc_chans *rc;
1431 {
1432
1433         if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1434             && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1435             && (!(t->c_iflag & PARMRK)
1436                 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1437             && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1438             && linesw[tp->t_line].l_rint == ttyinput)
1439                 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1440         else
1441                 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1442         rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1443 }
1444
1445 static void
1446 rc_wait0(nec, unit, chan, line)
1447         int     nec, unit, chan, line;
1448 {
1449         int rcnt;
1450
1451         for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1452                 DELAY(30);
1453         if (rcnt == 0)
1454                 printf("rc%d/%d: channel command timeout, rc.c line: %d\n",
1455                       unit, chan, line);
1456 }