2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $
33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.7 2004/01/24 06:34:02 dillon Exp $
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
79 * The 3c90x series chips use a bus-master DMA interface for transfering
80 * packets to and from the controller chip. Some of the "vortex" cards
81 * (3c59x) also supported a bus master mode, however for those chips
82 * you could only DMA packets to/from a contiguous memory buffer. For
83 * transmission this would mean copying the contents of the queued mbuf
84 * chain into an mbuf cluster and then DMAing the cluster. This extra
85 * copy would sort of defeat the purpose of the bus master support for
86 * any packet that doesn't fit into a single mbuf.
88 * By contrast, the 3c90x cards support a fragment-based bus master
89 * mode where mbuf chains can be encapsulated using TX descriptors.
90 * This is similar to other PCI chips such as the Texas Instruments
91 * ThunderLAN and the Intel 82557/82558.
93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
94 * bus master chips because they maintain the old PIO interface for
95 * backwards compatibility, but starting with the 3c905B and the
96 * "cyclone" chips, the compatibility interface has been dropped.
97 * Since using bus master DMA is a big win, we use this driver to
98 * support the PCI "boomerang" chips even though they work with the
99 * "vortex" driver in order to obtain better performance.
101 * This driver is in the /sys/pci directory because it only supports
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/sockio.h>
108 #include <sys/endian.h>
109 #include <sys/mbuf.h>
110 #include <sys/kernel.h>
111 #include <sys/socket.h>
114 #include <net/if_arp.h>
115 #include <net/ethernet.h>
116 #include <net/if_dl.h>
117 #include <net/if_media.h>
118 #include <net/vlan/if_vlan_var.h>
122 #include <machine/bus_memio.h>
123 #include <machine/bus_pio.h>
124 #include <machine/bus.h>
125 #include <machine/clock.h> /* for DELAY */
126 #include <machine/resource.h>
128 #include <sys/rman.h>
130 #include "../mii_layer/mii.h"
131 #include "../mii_layer/miivar.h"
133 #include <bus/pci/pcireg.h>
134 #include <bus/pci/pcivar.h>
136 /* "controller miibus0" required. See GENERIC if you get errors here. */
137 #include "miibus_if.h"
139 #include "if_xlreg.h"
141 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
144 * Various supported device vendors/types and their names.
146 static struct xl_type xl_devs[] = {
147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
148 "3Com 3c900-TPO Etherlink XL" },
149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
150 "3Com 3c900-COMBO Etherlink XL" },
151 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
152 "3Com 3c905-TX Fast Etherlink XL" },
153 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
154 "3Com 3c905-T4 Fast Etherlink XL" },
155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
156 "3Com 3c900B-TPO Etherlink XL" },
157 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
158 "3Com 3c900B-COMBO Etherlink XL" },
159 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
160 "3Com 3c900B-TPC Etherlink XL" },
161 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
162 "3Com 3c900B-FL Etherlink XL" },
163 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
164 "3Com 3c905B-TX Fast Etherlink XL" },
165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
166 "3Com 3c905B-T4 Fast Etherlink XL" },
167 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
168 "3Com 3c905B-FX/SC Fast Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
170 "3Com 3c905B-COMBO Fast Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
172 "3Com 3c905C-TX Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
174 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
176 "3Com 3c980 Fast Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
178 "3Com 3c980C Fast Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
180 "3Com 3cSOHO100-TX OfficeConnect" },
181 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
182 "3Com 3c450-TX HomeConnect" },
183 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
184 "3Com 3c555 Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
186 "3Com 3c556 Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
188 "3Com 3c556B Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
190 "3Com 3c575TX Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
192 "3Com 3c575B Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
194 "3Com 3c575C Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
196 "3Com 3c656 Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
198 "3Com 3c656B Fast Etherlink XL" },
199 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
200 "3Com 3c656C Fast Etherlink XL" },
204 static int xl_probe (device_t);
205 static int xl_attach (device_t);
206 static int xl_detach (device_t);
208 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *);
209 static void xl_stats_update (void *);
210 static int xl_encap (struct xl_softc *, struct xl_chain *,
212 static void xl_rxeof (struct xl_softc *);
213 static int xl_rx_resync (struct xl_softc *);
214 static void xl_txeof (struct xl_softc *);
215 static void xl_txeof_90xB (struct xl_softc *);
216 static void xl_txeoc (struct xl_softc *);
217 static void xl_intr (void *);
218 static void xl_start (struct ifnet *);
219 static void xl_start_90xB (struct ifnet *);
220 static int xl_ioctl (struct ifnet *, u_long, caddr_t);
221 static void xl_init (void *);
222 static void xl_stop (struct xl_softc *);
223 static void xl_watchdog (struct ifnet *);
224 static void xl_shutdown (device_t);
225 static int xl_suspend (device_t);
226 static int xl_resume (device_t);
228 static int xl_ifmedia_upd (struct ifnet *);
229 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
231 static int xl_eeprom_wait (struct xl_softc *);
232 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
233 static void xl_mii_sync (struct xl_softc *);
234 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
235 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
236 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
238 static void xl_setcfg (struct xl_softc *);
239 static void xl_setmode (struct xl_softc *, int);
240 static u_int8_t xl_calchash (caddr_t);
241 static void xl_setmulti (struct xl_softc *);
242 static void xl_setmulti_hash (struct xl_softc *);
243 static void xl_reset (struct xl_softc *);
244 static int xl_list_rx_init (struct xl_softc *);
245 static int xl_list_tx_init (struct xl_softc *);
246 static int xl_list_tx_init_90xB (struct xl_softc *);
247 static void xl_wait (struct xl_softc *);
248 static void xl_mediacheck (struct xl_softc *);
249 static void xl_choose_xcvr (struct xl_softc *, int);
250 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int);
251 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t,
253 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t,
256 static void xl_testpacket (struct xl_softc *);
259 static int xl_miibus_readreg (device_t, int, int);
260 static int xl_miibus_writereg (device_t, int, int, int);
261 static void xl_miibus_statchg (device_t);
262 static void xl_miibus_mediainit (device_t);
264 static device_method_t xl_methods[] = {
265 /* Device interface */
266 DEVMETHOD(device_probe, xl_probe),
267 DEVMETHOD(device_attach, xl_attach),
268 DEVMETHOD(device_detach, xl_detach),
269 DEVMETHOD(device_shutdown, xl_shutdown),
270 DEVMETHOD(device_suspend, xl_suspend),
271 DEVMETHOD(device_resume, xl_resume),
274 DEVMETHOD(bus_print_child, bus_generic_print_child),
275 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
278 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
279 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
280 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
281 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
286 static driver_t xl_driver = {
289 sizeof(struct xl_softc)
292 static devclass_t xl_devclass;
294 DECLARE_DUMMY_MODULE(if_xl);
295 MODULE_DEPEND(if_xl, miibus, 1, 1, 1);
296 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
297 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
300 xl_dma_map_addr(arg, segs, nseg, error)
302 bus_dma_segment_t *segs;
308 *paddr = segs->ds_addr;
312 xl_dma_map_rxbuf(arg, segs, nseg, mapsize, error)
314 bus_dma_segment_t *segs;
323 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
325 *paddr = segs->ds_addr;
329 xl_dma_map_txbuf(arg, segs, nseg, mapsize, error)
331 bus_dma_segment_t *segs;
342 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
346 for (i = 0; i < nseg; i++) {
347 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
348 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
349 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
350 total_len += segs[i].ds_len;
352 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
354 l->xl_status = htole32(total_len);
359 * Murphy's law says that it's possible the chip can wedge and
360 * the 'command in progress' bit may never clear. Hence, we wait
361 * only a finite amount of time to avoid getting caught in an
362 * infinite loop. Normally this delay routine would be a macro,
363 * but it isn't called during normal operation so we can afford
364 * to make it a function.
372 for (i = 0; i < XL_TIMEOUT; i++) {
373 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
378 printf("xl%d: command never completed!\n", sc->xl_unit);
384 * MII access routines are provided for adapters with external
385 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
386 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
387 * Note: if you don't perform the MDIO operations just right,
388 * it's possible to end up with code that works correctly with
389 * some chips/CPUs/processor speeds/bus speeds/etc but not
393 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
394 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
397 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
398 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
401 * Sync the PHYs by setting data bit and strobing the clock 32 times.
410 MII_SET(XL_MII_DIR|XL_MII_DATA);
412 for (i = 0; i < 32; i++) {
414 MII_SET(XL_MII_DATA);
415 MII_SET(XL_MII_DATA);
417 MII_SET(XL_MII_DATA);
418 MII_SET(XL_MII_DATA);
425 * Clock a series of bits through the MII.
428 xl_mii_send(sc, bits, cnt)
438 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
440 MII_SET(XL_MII_DATA);
442 MII_CLR(XL_MII_DATA);
450 * Read an PHY register through the MII.
453 xl_mii_readreg(sc, frame)
455 struct xl_mii_frame *frame;
463 * Set up frame for RX.
465 frame->mii_stdelim = XL_MII_STARTDELIM;
466 frame->mii_opcode = XL_MII_READOP;
467 frame->mii_turnaround = 0;
471 * Select register window 4.
476 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
485 * Send command/address info.
487 xl_mii_send(sc, frame->mii_stdelim, 2);
488 xl_mii_send(sc, frame->mii_opcode, 2);
489 xl_mii_send(sc, frame->mii_phyaddr, 5);
490 xl_mii_send(sc, frame->mii_regaddr, 5);
493 MII_CLR((XL_MII_CLK|XL_MII_DATA));
501 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
505 * Now try reading data bits. If the ack failed, we still
506 * need to clock through 16 cycles to keep the PHY(s) in sync.
509 for(i = 0; i < 16; i++) {
516 for (i = 0x8000; i; i >>= 1) {
519 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
520 frame->mii_data |= i;
538 * Write to a PHY register through the MII.
541 xl_mii_writereg(sc, frame)
543 struct xl_mii_frame *frame;
551 * Set up frame for TX.
554 frame->mii_stdelim = XL_MII_STARTDELIM;
555 frame->mii_opcode = XL_MII_WRITEOP;
556 frame->mii_turnaround = XL_MII_TURNAROUND;
559 * Select the window 4.
564 * Turn on data output.
570 xl_mii_send(sc, frame->mii_stdelim, 2);
571 xl_mii_send(sc, frame->mii_opcode, 2);
572 xl_mii_send(sc, frame->mii_phyaddr, 5);
573 xl_mii_send(sc, frame->mii_regaddr, 5);
574 xl_mii_send(sc, frame->mii_turnaround, 2);
575 xl_mii_send(sc, frame->mii_data, 16);
592 xl_miibus_readreg(dev, phy, reg)
597 struct xl_mii_frame frame;
599 sc = device_get_softc(dev);
602 * Pretend that PHYs are only available at MII address 24.
603 * This is to guard against problems with certain 3Com ASIC
604 * revisions that incorrectly map the internal transceiver
605 * control registers at all MII addresses. This can cause
606 * the miibus code to attach the same PHY several times over.
608 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
611 bzero((char *)&frame, sizeof(frame));
613 frame.mii_phyaddr = phy;
614 frame.mii_regaddr = reg;
615 xl_mii_readreg(sc, &frame);
617 return(frame.mii_data);
621 xl_miibus_writereg(dev, phy, reg, data)
626 struct xl_mii_frame frame;
628 sc = device_get_softc(dev);
630 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
633 bzero((char *)&frame, sizeof(frame));
635 frame.mii_phyaddr = phy;
636 frame.mii_regaddr = reg;
637 frame.mii_data = data;
639 xl_mii_writereg(sc, &frame);
645 xl_miibus_statchg(dev)
649 struct mii_data *mii;
652 sc = device_get_softc(dev);
653 mii = device_get_softc(sc->xl_miibus);
657 /* Set ASIC's duplex mode to match the PHY. */
659 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
660 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
662 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
663 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
669 * Special support for the 3c905B-COMBO. This card has 10/100 support
670 * plus BNC and AUI ports. This means we will have both an miibus attached
671 * plus some non-MII media settings. In order to allow this, we have to
672 * add the extra media to the miibus's ifmedia struct, but we can't do
673 * that during xl_attach() because the miibus hasn't been attached yet.
674 * So instead, we wait until the miibus probe/attach is done, at which
675 * point we will get a callback telling is that it's safe to add our
679 xl_miibus_mediainit(dev)
683 struct mii_data *mii;
686 sc = device_get_softc(dev);
687 mii = device_get_softc(sc->xl_miibus);
688 ifm = &mii->mii_media;
690 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
692 * Check for a 10baseFL board in disguise.
694 if (sc->xl_type == XL_TYPE_905B &&
695 sc->xl_media == XL_MEDIAOPT_10FL) {
697 printf("xl%d: found 10baseFL\n", sc->xl_unit);
698 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
699 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
700 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
702 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
705 printf("xl%d: found AUI\n", sc->xl_unit);
706 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
710 if (sc->xl_media & XL_MEDIAOPT_BNC) {
712 printf("xl%d: found BNC\n", sc->xl_unit);
713 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
720 * The EEPROM is slow: give it time to come ready after issuing
729 for (i = 0; i < 100; i++) {
730 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
737 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit);
745 * Read a sequence of words from the EEPROM. Note that ethernet address
746 * data is stored in the EEPROM in network byte order.
749 xl_read_eeprom(sc, dest, off, cnt, swap)
757 u_int16_t word = 0, *ptr;
758 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
759 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
761 * It's easy to accidentally overwrite the rom content!
762 * Note: the 3c575 uses 8bit EEPROM offsets.
766 if (xl_eeprom_wait(sc))
769 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
772 for (i = 0; i < cnt; i++) {
773 if (sc->xl_flags & XL_FLAG_8BITROM)
774 CSR_WRITE_2(sc, XL_W0_EE_CMD,
775 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
777 CSR_WRITE_2(sc, XL_W0_EE_CMD,
778 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
779 err = xl_eeprom_wait(sc);
782 word = CSR_READ_2(sc, XL_W0_EE_DATA);
783 ptr = (u_int16_t *)(dest + (i * 2));
794 * This routine is taken from the 3Com Etherlink XL manual,
795 * page 10-7. It calculates a CRC of the supplied multicast
796 * group address and returns the lower 8 bits, which are used
797 * as the multicast filter position.
798 * Note: the 3c905B currently only supports a 64-bit hash table,
799 * which means we really only need 6 bits, but the manual indicates
800 * that future chip revisions will have a 256-bit hash table,
801 * hence the routine is set up to calculate 8 bits of position
802 * info in case we need it some day.
803 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a
804 * 256 bit hash table. This means we have to use all 8 bits regardless.
805 * On older cards, the upper 2 bits will be ignored. Grrrr....
807 static u_int8_t xl_calchash(addr)
810 u_int32_t crc, carry;
814 /* Compute CRC for the address value. */
815 crc = 0xFFFFFFFF; /* initial value */
817 for (i = 0; i < 6; i++) {
819 for (j = 0; j < 8; j++) {
820 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
824 crc = (crc ^ 0x04c11db6) | carry;
828 /* return the filter bit position */
829 return(crc & 0x000000FF);
833 * NICs older than the 3c905B have only one multicast option, which
834 * is to enable reception of all multicast frames.
841 struct ifmultiaddr *ifma;
845 ifp = &sc->arpcom.ac_if;
848 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
850 if (ifp->if_flags & IFF_ALLMULTI) {
851 rxfilt |= XL_RXFILTER_ALLMULTI;
852 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
856 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
857 ifma = ifma->ifma_link.le_next)
861 rxfilt |= XL_RXFILTER_ALLMULTI;
863 rxfilt &= ~XL_RXFILTER_ALLMULTI;
865 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
871 * 3c905B adapters have a hash filter that we can program.
879 struct ifmultiaddr *ifma;
883 ifp = &sc->arpcom.ac_if;
886 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
888 if (ifp->if_flags & IFF_ALLMULTI) {
889 rxfilt |= XL_RXFILTER_ALLMULTI;
890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
893 rxfilt &= ~XL_RXFILTER_ALLMULTI;
896 /* first, zot all the existing hash bits */
897 for (i = 0; i < XL_HASHFILT_SIZE; i++)
898 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
900 /* now program new ones */
901 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
902 ifma = ifma->ifma_link.le_next) {
903 if (ifma->ifma_addr->sa_family != AF_LINK)
905 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
906 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
911 rxfilt |= XL_RXFILTER_MULTIHASH;
913 rxfilt &= ~XL_RXFILTER_MULTIHASH;
915 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
928 ifp = &sc->arpcom.ac_if;
930 MGETHDR(m, M_DONTWAIT, MT_DATA);
935 bcopy(&sc->arpcom.ac_enaddr,
936 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
937 bcopy(&sc->arpcom.ac_enaddr,
938 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
939 mtod(m, struct ether_header *)->ether_type = htons(3);
940 mtod(m, unsigned char *)[14] = 0;
941 mtod(m, unsigned char *)[15] = 0;
942 mtod(m, unsigned char *)[16] = 0xE3;
943 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
944 IF_ENQUEUE(&ifp->if_snd, m);
958 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
959 icfg &= ~XL_ICFG_CONNECTOR_MASK;
960 if (sc->xl_media & XL_MEDIAOPT_MII ||
961 sc->xl_media & XL_MEDIAOPT_BT4)
962 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
963 if (sc->xl_media & XL_MEDIAOPT_BTX)
964 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
966 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
967 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
973 xl_setmode(sc, media)
980 printf("xl%d: selecting ", sc->xl_unit);
983 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
985 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
987 if (sc->xl_media & XL_MEDIAOPT_BT) {
988 if (IFM_SUBTYPE(media) == IFM_10_T) {
989 printf("10baseT transceiver, ");
990 sc->xl_xcvr = XL_XCVR_10BT;
991 icfg &= ~XL_ICFG_CONNECTOR_MASK;
992 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
993 mediastat |= XL_MEDIASTAT_LINKBEAT|
994 XL_MEDIASTAT_JABGUARD;
995 mediastat &= ~XL_MEDIASTAT_SQEENB;
999 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1000 if (IFM_SUBTYPE(media) == IFM_100_FX) {
1001 printf("100baseFX port, ");
1002 sc->xl_xcvr = XL_XCVR_100BFX;
1003 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1004 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
1005 mediastat |= XL_MEDIASTAT_LINKBEAT;
1006 mediastat &= ~XL_MEDIASTAT_SQEENB;
1010 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1011 if (IFM_SUBTYPE(media) == IFM_10_5) {
1012 printf("AUI port, ");
1013 sc->xl_xcvr = XL_XCVR_AUI;
1014 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1015 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
1016 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1017 XL_MEDIASTAT_JABGUARD);
1018 mediastat |= ~XL_MEDIASTAT_SQEENB;
1020 if (IFM_SUBTYPE(media) == IFM_10_FL) {
1021 printf("10baseFL transceiver, ");
1022 sc->xl_xcvr = XL_XCVR_AUI;
1023 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1024 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
1025 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1026 XL_MEDIASTAT_JABGUARD);
1027 mediastat |= ~XL_MEDIASTAT_SQEENB;
1031 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1032 if (IFM_SUBTYPE(media) == IFM_10_2) {
1033 printf("BNC port, ");
1034 sc->xl_xcvr = XL_XCVR_COAX;
1035 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1036 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
1037 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1038 XL_MEDIASTAT_JABGUARD|
1039 XL_MEDIASTAT_SQEENB);
1043 if ((media & IFM_GMASK) == IFM_FDX ||
1044 IFM_SUBTYPE(media) == IFM_100_FX) {
1045 printf("full duplex\n");
1047 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
1049 printf("half duplex\n");
1051 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
1052 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
1055 if (IFM_SUBTYPE(media) == IFM_10_2)
1056 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1058 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1059 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1061 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1070 struct xl_softc *sc;
1075 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1076 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1077 XL_RESETOPT_DISADVFD:0));
1080 * If we're using memory mapped register mode, pause briefly
1081 * after issuing the reset command before trying to access any
1082 * other registers. With my 3c575C cardbus card, failing to do
1083 * this results in the system locking up while trying to poll
1084 * the command busy bit in the status register.
1086 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1089 for (i = 0; i < XL_TIMEOUT; i++) {
1091 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1095 if (i == XL_TIMEOUT)
1096 printf("xl%d: reset didn't complete\n", sc->xl_unit);
1098 /* Reset TX and RX. */
1099 /* Note: the RX reset takes an absurd amount of time
1100 * on newer versions of the Tornado chips such as those
1101 * on the 3c905CX and newer 3c908C cards. We wait an
1102 * extra amount of time so that xl_wait() doesn't complain
1103 * and annoy the users.
1105 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1108 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1111 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1112 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1114 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1115 XL_W2_RESET_OPTIONS)
1116 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1117 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1121 /* Wait a little while for the chip to get its brains in order. */
1127 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1128 * IDs against our list and return a device name if we find a match.
1138 while(t->xl_name != NULL) {
1139 if ((pci_get_vendor(dev) == t->xl_vid) &&
1140 (pci_get_device(dev) == t->xl_did)) {
1141 device_set_desc(dev, t->xl_name);
1151 * This routine is a kludge to work around possible hardware faults
1152 * or manufacturing defects that can cause the media options register
1153 * (or reset options register, as it's called for the first generation
1154 * 3c90x adapters) to return an incorrect result. I have encountered
1155 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1156 * which doesn't have any of the 'mediaopt' bits set. This screws up
1157 * the attach routine pretty badly because it doesn't know what media
1158 * to look for. If we find ourselves in this predicament, this routine
1159 * will try to guess the media options values and warn the user of a
1160 * possible manufacturing defect with his adapter/system/whatever.
1164 struct xl_softc *sc;
1168 * If some of the media options bits are set, assume they are
1169 * correct. If not, try to figure it out down below.
1170 * XXX I should check for 10baseFL, but I don't have an adapter
1173 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1175 * Check the XCVR value. If it's not in the normal range
1176 * of values, we need to fake it up here.
1178 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1181 printf("xl%d: bogus xcvr value "
1182 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr);
1183 printf("xl%d: choosing new default based "
1184 "on card type\n", sc->xl_unit);
1187 if (sc->xl_type == XL_TYPE_905B &&
1188 sc->xl_media & XL_MEDIAOPT_10FL)
1190 printf("xl%d: WARNING: no media options bits set in "
1191 "the media options register!!\n", sc->xl_unit);
1192 printf("xl%d: this could be a manufacturing defect in "
1193 "your adapter or system\n", sc->xl_unit);
1194 printf("xl%d: attempting to guess media type; you "
1195 "should probably consult your vendor\n", sc->xl_unit);
1198 xl_choose_xcvr(sc, 1);
1204 xl_choose_xcvr(sc, verbose)
1205 struct xl_softc *sc;
1211 * Read the device ID from the EEPROM.
1212 * This is what's loaded into the PCI device ID register, so it has
1213 * to be correct otherwise we wouldn't have gotten this far.
1215 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1218 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1219 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1220 sc->xl_media = XL_MEDIAOPT_BT;
1221 sc->xl_xcvr = XL_XCVR_10BT;
1223 printf("xl%d: guessing 10BaseT "
1224 "transceiver\n", sc->xl_unit);
1226 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1227 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1228 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1229 sc->xl_xcvr = XL_XCVR_10BT;
1231 printf("xl%d: guessing COMBO "
1232 "(AUI/BNC/TP)\n", sc->xl_unit);
1234 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1235 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1236 sc->xl_xcvr = XL_XCVR_10BT;
1238 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit);
1240 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1241 sc->xl_media = XL_MEDIAOPT_10FL;
1242 sc->xl_xcvr = XL_XCVR_AUI;
1244 printf("xl%d: guessing 10baseFL\n", sc->xl_unit);
1246 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1247 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1248 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1249 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1250 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1251 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1252 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1253 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1254 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1255 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1256 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1257 sc->xl_media = XL_MEDIAOPT_MII;
1258 sc->xl_xcvr = XL_XCVR_MII;
1260 printf("xl%d: guessing MII\n", sc->xl_unit);
1262 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1263 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1264 sc->xl_media = XL_MEDIAOPT_BT4;
1265 sc->xl_xcvr = XL_XCVR_MII;
1267 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit);
1269 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1270 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1271 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1272 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1273 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1274 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1275 sc->xl_media = XL_MEDIAOPT_BTX;
1276 sc->xl_xcvr = XL_XCVR_AUTO;
1278 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit);
1280 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1281 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1282 sc->xl_xcvr = XL_XCVR_AUTO;
1284 printf("xl%d: guessing 10/100 "
1285 "plus BNC/AUI\n", sc->xl_unit);
1288 printf("xl%d: unknown device ID: %x -- "
1289 "defaulting to 10baseT\n", sc->xl_unit, devid);
1290 sc->xl_media = XL_MEDIAOPT_BT;
1298 * Attach the interface. Allocate softc structures, do ifmedia
1299 * setup and ethernet/BPF attach.
1306 u_char eaddr[ETHER_ADDR_LEN];
1309 struct xl_softc *sc;
1311 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1312 int unit, error = 0, rid, res;
1316 sc = device_get_softc(dev);
1317 unit = device_get_unit(dev);
1319 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1322 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555)
1323 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1324 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 ||
1325 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1326 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1327 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1328 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1329 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 ||
1330 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556)
1331 sc->xl_flags |= XL_FLAG_8BITROM;
1332 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1333 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1335 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A ||
1336 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1337 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1338 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B ||
1339 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1340 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1341 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM;
1342 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656)
1343 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1344 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B)
1345 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1346 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C)
1347 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1348 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1349 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1350 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 ||
1351 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B)
1352 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1353 XL_FLAG_INVERT_LED_PWR;
1354 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B)
1355 sc->xl_flags |= XL_FLAG_PHYOK;
1356 #ifndef BURN_BRIDGES
1358 * If this is a 3c905B, we have to check one extra thing.
1359 * The 905B supports power management and may be placed in
1360 * a low-power mode (D3 mode), typically by certain operating
1361 * systems which shall not be named. The PCI BIOS is supposed
1362 * to reset the NIC and bring it out of low-power mode, but
1363 * some do not. Consequently, we have to see if this chip
1364 * supports power management, and if so, make sure it's not
1365 * in low-power mode. If power management is available, the
1366 * capid byte will be 0x01.
1368 * I _think_ that what actually happens is that the chip
1369 * loses its PCI configuration during the transition from
1370 * D3 back to D0; this means that it should be possible for
1371 * us to save the PCI iobase, membase and IRQ, put the chip
1372 * back in the D0 state, then restore the PCI config ourselves.
1375 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1376 u_int32_t iobase, membase, irq;
1378 /* Save important PCI config data. */
1379 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1380 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1381 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1383 /* Reset the power state. */
1384 printf("xl%d: chip is in D%d power mode "
1385 "-- setting to D0\n", unit,
1386 pci_get_powerstate(dev));
1388 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1390 /* Restore PCI config data. */
1391 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1392 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1393 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1397 * Map control/status registers.
1399 pci_enable_busmaster(dev);
1400 pci_enable_io(dev, SYS_RES_IOPORT);
1401 pci_enable_io(dev, SYS_RES_MEMORY);
1402 command = pci_read_config(dev, PCIR_COMMAND, 4);
1404 if (!(command & PCIM_CMD_PORTEN) && !(command & PCIM_CMD_MEMEN)) {
1405 printf("xl%d: failed to enable I/O ports and memory mappings!\n", unit);
1411 res = SYS_RES_MEMORY;
1414 sc->xl_res = bus_alloc_resource(dev, res, &rid,
1415 0, ~0, 1, RF_ACTIVE);
1418 if (sc->xl_res != NULL) {
1419 sc->xl_flags |= XL_FLAG_USE_MMIO;
1421 printf("xl%d: using memory mapped I/O\n", unit);
1424 res = SYS_RES_IOPORT;
1425 sc->xl_res = bus_alloc_resource(dev, res, &rid,
1426 0, ~0, 1, RF_ACTIVE);
1427 if (sc->xl_res == NULL) {
1428 printf ("xl%d: couldn't map ports/memory\n", unit);
1433 printf("xl%d: using port I/O\n", unit);
1436 sc->xl_btag = rman_get_bustag(sc->xl_res);
1437 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1439 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1440 rid = XL_PCI_FUNCMEM;
1441 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1442 0, ~0, 1, RF_ACTIVE);
1444 if (sc->xl_fres == NULL) {
1445 printf ("xl%d: couldn't map ports/memory\n", unit);
1450 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1451 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1454 /* Allocate interrupt */
1456 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1457 RF_SHAREABLE | RF_ACTIVE);
1458 if (sc->xl_irq == NULL) {
1459 printf("xl%d: couldn't map interrupt\n", unit);
1464 /* Reset the adapter. */
1468 * Get station address from the EEPROM.
1470 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1471 printf("xl%d: failed to read station address\n", sc->xl_unit);
1477 * A 3Com chip was detected. Inform the world.
1479 printf("xl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1482 callout_handle_init(&sc->xl_stat_ch);
1483 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1486 * Now allocate a tag for the DMA descriptor lists and a chunk
1487 * of DMA-able memory based on the tag. Also obtain the DMA
1488 * addresses of the RX and TX ring, which we'll need later.
1489 * All of our lists are allocated as a contiguous block
1492 error = bus_dma_tag_create(NULL, 8, 0,
1493 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1494 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0,
1495 &sc->xl_ldata.xl_rx_tag);
1497 printf("xl%d: failed to allocate rx dma tag\n", unit);
1501 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1502 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT,
1503 &sc->xl_ldata.xl_rx_dmamap);
1505 printf("xl%d: no memory for rx list buffers!\n", unit);
1506 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1507 sc->xl_ldata.xl_rx_tag = NULL;
1511 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1512 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1513 XL_RX_LIST_SZ, xl_dma_map_addr,
1514 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1516 printf("xl%d: cannot get dma address of the rx ring!\n", unit);
1517 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1518 sc->xl_ldata.xl_rx_dmamap);
1519 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1520 sc->xl_ldata.xl_rx_tag = NULL;
1524 error = bus_dma_tag_create(NULL, 8, 0,
1525 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1526 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0,
1527 &sc->xl_ldata.xl_tx_tag);
1529 printf("xl%d: failed to allocate tx dma tag\n", unit);
1533 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1534 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT,
1535 &sc->xl_ldata.xl_tx_dmamap);
1537 printf("xl%d: no memory for list buffers!\n", unit);
1538 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1539 sc->xl_ldata.xl_tx_tag = NULL;
1543 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1544 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1545 XL_TX_LIST_SZ, xl_dma_map_addr,
1546 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1548 printf("xl%d: cannot get dma address of the tx ring!\n", unit);
1549 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1550 sc->xl_ldata.xl_tx_dmamap);
1551 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1552 sc->xl_ldata.xl_tx_tag = NULL;
1557 * Allocate a DMA tag for the mapping of mbufs.
1559 error = bus_dma_tag_create(NULL, 1, 0,
1560 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1561 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0,
1564 printf("xl%d: failed to allocate mbuf dma tag\n", unit);
1568 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
1569 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
1571 /* We need a spare DMA map for the RX ring. */
1572 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1577 * Figure out the card type. 3c905B adapters have the
1578 * 'supportsNoTxLength' bit set in the capabilities
1579 * word in the EEPROM.
1580 * Note: my 3c575C cardbus card lies. It returns a value
1581 * of 0x1578 for its capabilities word, which is somewhat
1582 * nonsensical. Another way to distinguish a 3c90x chip
1583 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1584 * bit. This will only be set for 3c90x boomerage chips.
1586 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1587 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1588 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1589 sc->xl_type = XL_TYPE_905B;
1591 sc->xl_type = XL_TYPE_90X;
1593 ifp = &sc->arpcom.ac_if;
1595 if_initname(ifp, "xl", unit);
1596 ifp->if_mtu = ETHERMTU;
1597 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1598 ifp->if_ioctl = xl_ioctl;
1599 ifp->if_output = ether_output;
1600 ifp->if_capabilities = 0;
1601 if (sc->xl_type == XL_TYPE_905B) {
1602 ifp->if_start = xl_start_90xB;
1603 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1604 ifp->if_capabilities |= IFCAP_HWCSUM;
1606 ifp->if_start = xl_start;
1608 ifp->if_watchdog = xl_watchdog;
1609 ifp->if_init = xl_init;
1610 ifp->if_baudrate = 10000000;
1611 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1;
1612 ifp->if_capenable = ifp->if_capabilities;
1615 * Now we have to see what sort of media we have.
1616 * This includes probing for an MII interace and a
1620 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1622 printf("xl%d: media options word: %x\n", sc->xl_unit,
1625 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1626 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1627 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1628 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1632 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1633 || sc->xl_media & XL_MEDIAOPT_BT4) {
1635 printf("xl%d: found MII/AUTO\n", sc->xl_unit);
1637 if (mii_phy_probe(dev, &sc->xl_miibus,
1638 xl_ifmedia_upd, xl_ifmedia_sts)) {
1639 printf("xl%d: no PHY found!\n", sc->xl_unit);
1648 * Sanity check. If the user has selected "auto" and this isn't
1649 * a 10/100 card of some kind, we need to force the transceiver
1650 * type to something sane.
1652 if (sc->xl_xcvr == XL_XCVR_AUTO)
1653 xl_choose_xcvr(sc, bootverbose);
1658 if (sc->xl_media & XL_MEDIAOPT_BT) {
1660 printf("xl%d: found 10baseT\n", sc->xl_unit);
1661 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1662 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1663 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1664 ifmedia_add(&sc->ifmedia,
1665 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1668 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1670 * Check for a 10baseFL board in disguise.
1672 if (sc->xl_type == XL_TYPE_905B &&
1673 sc->xl_media == XL_MEDIAOPT_10FL) {
1675 printf("xl%d: found 10baseFL\n", sc->xl_unit);
1676 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1677 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1679 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1680 ifmedia_add(&sc->ifmedia,
1681 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1684 printf("xl%d: found AUI\n", sc->xl_unit);
1685 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1689 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1691 printf("xl%d: found BNC\n", sc->xl_unit);
1692 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1695 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1697 printf("xl%d: found 100baseFX\n", sc->xl_unit);
1698 ifp->if_baudrate = 100000000;
1699 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1702 /* Choose a default media. */
1703 switch(sc->xl_xcvr) {
1705 media = IFM_ETHER|IFM_10_T;
1706 xl_setmode(sc, media);
1709 if (sc->xl_type == XL_TYPE_905B &&
1710 sc->xl_media == XL_MEDIAOPT_10FL) {
1711 media = IFM_ETHER|IFM_10_FL;
1712 xl_setmode(sc, media);
1714 media = IFM_ETHER|IFM_10_5;
1715 xl_setmode(sc, media);
1719 media = IFM_ETHER|IFM_10_2;
1720 xl_setmode(sc, media);
1723 case XL_XCVR_100BTX:
1725 /* Chosen by miibus */
1727 case XL_XCVR_100BFX:
1728 media = IFM_ETHER|IFM_100_FX;
1731 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit,
1734 * This will probably be wrong, but it prevents
1735 * the ifmedia code from panicking.
1737 media = IFM_ETHER|IFM_10_T;
1741 if (sc->xl_miibus == NULL)
1742 ifmedia_set(&sc->ifmedia, media);
1746 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1748 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1752 * Call MI attach routine.
1754 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1757 * Tell the upper layer(s) we support long frames.
1759 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1761 /* Hook interrupt last to avoid having to lock softc */
1762 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET,
1763 xl_intr, sc, &sc->xl_intrhand);
1765 printf("xl%d: couldn't set up irq\n", unit);
1766 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1780 * Shutdown hardware and free up resources. This can be called any
1781 * time after the mutex has been initialized. It is called in both
1782 * the error case in attach and the normal detach case so it needs
1783 * to be careful about only freeing resources that have actually been
1790 struct xl_softc *sc;
1797 sc = device_get_softc(dev);
1798 ifp = &sc->arpcom.ac_if;
1800 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1802 res = SYS_RES_MEMORY;
1805 res = SYS_RES_IOPORT;
1810 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1813 device_delete_child(dev, sc->xl_miibus);
1814 bus_generic_detach(dev);
1815 ifmedia_removeall(&sc->ifmedia);
1817 if (sc->xl_intrhand)
1818 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1820 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1821 if (sc->xl_fres != NULL)
1822 bus_release_resource(dev, SYS_RES_MEMORY,
1823 XL_PCI_FUNCMEM, sc->xl_fres);
1825 bus_release_resource(dev, res, rid, sc->xl_res);
1828 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1829 bus_dma_tag_destroy(sc->xl_mtag);
1831 if (sc->xl_ldata.xl_rx_tag) {
1832 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1833 sc->xl_ldata.xl_rx_dmamap);
1834 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1835 sc->xl_ldata.xl_rx_dmamap);
1836 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1838 if (sc->xl_ldata.xl_tx_tag) {
1839 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1840 sc->xl_ldata.xl_tx_dmamap);
1841 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1842 sc->xl_ldata.xl_tx_dmamap);
1843 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1852 * Initialize the transmit descriptors.
1856 struct xl_softc *sc;
1858 struct xl_chain_data *cd;
1859 struct xl_list_data *ld;
1864 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1865 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1866 error = bus_dmamap_create(sc->xl_mtag, 0,
1867 &cd->xl_tx_chain[i].xl_map);
1870 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1871 i * sizeof(struct xl_list);
1872 if (i == (XL_TX_LIST_CNT - 1))
1873 cd->xl_tx_chain[i].xl_next = NULL;
1875 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1878 cd->xl_tx_free = &cd->xl_tx_chain[0];
1879 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1881 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1886 * Initialize the transmit descriptors.
1889 xl_list_tx_init_90xB(sc)
1890 struct xl_softc *sc;
1892 struct xl_chain_data *cd;
1893 struct xl_list_data *ld;
1898 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1899 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1900 error = bus_dmamap_create(sc->xl_mtag, 0,
1901 &cd->xl_tx_chain[i].xl_map);
1904 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1905 i * sizeof(struct xl_list);
1906 if (i == (XL_TX_LIST_CNT - 1))
1907 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1909 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1911 cd->xl_tx_chain[i].xl_prev =
1912 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1914 cd->xl_tx_chain[i].xl_prev =
1915 &cd->xl_tx_chain[i - 1];
1918 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1919 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1925 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1930 * Initialize the RX descriptors and allocate mbufs for them. Note that
1931 * we arrange the descriptors in a closed ring, so that the last descriptor
1932 * points back to the first.
1936 struct xl_softc *sc;
1938 struct xl_chain_data *cd;
1939 struct xl_list_data *ld;
1946 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1947 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1948 error = bus_dmamap_create(sc->xl_mtag, 0,
1949 &cd->xl_rx_chain[i].xl_map);
1952 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1955 if (i == (XL_RX_LIST_CNT - 1))
1959 nextptr = ld->xl_rx_dmaaddr +
1960 next * sizeof(struct xl_list_onefrag);
1961 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1962 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1965 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1966 cd->xl_rx_head = &cd->xl_rx_chain[0];
1972 * Initialize an RX descriptor and attach an MBUF cluster.
1973 * If we fail to do so, we need to leave the old mbuf and
1974 * the old DMA map untouched so that it can be reused.
1978 struct xl_softc *sc;
1979 struct xl_chain_onefrag *c;
1981 struct mbuf *m_new = NULL;
1986 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1990 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1992 /* Force longword alignment for packet payload. */
1993 m_adj(m_new, ETHER_ALIGN);
1995 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
1996 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
1999 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error);
2003 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
2005 c->xl_map = sc->xl_tmpmap;
2006 sc->xl_tmpmap = map;
2008 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
2009 c->xl_ptr->xl_status = 0;
2010 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
2011 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
2017 struct xl_softc *sc;
2019 struct xl_chain_onefrag *pos;
2022 pos = sc->xl_cdata.xl_rx_head;
2024 for (i = 0; i < XL_RX_LIST_CNT; i++) {
2025 if (pos->xl_ptr->xl_status)
2030 if (i == XL_RX_LIST_CNT)
2033 sc->xl_cdata.xl_rx_head = pos;
2039 * A frame has been uploaded: pass the resulting mbuf chain up to
2040 * the higher level protocols.
2044 struct xl_softc *sc;
2046 struct ether_header *eh;
2049 struct xl_chain_onefrag *cur_rx;
2053 ifp = &sc->arpcom.ac_if;
2057 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
2058 BUS_DMASYNC_POSTREAD);
2059 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
2060 cur_rx = sc->xl_cdata.xl_rx_head;
2061 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
2062 total_len = rxstat & XL_RXSTAT_LENMASK;
2065 * Since we have told the chip to allow large frames,
2066 * we need to trap giant frame errors in software. We allow
2067 * a little more than the normal frame size to account for
2068 * frames with VLAN tags.
2070 if (total_len > XL_MAX_FRAMELEN)
2071 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
2074 * If an error occurs, update stats, clear the
2075 * status word and leave the mbuf cluster in place:
2076 * it should simply get re-used next time this descriptor
2077 * comes up in the ring.
2079 if (rxstat & XL_RXSTAT_UP_ERROR) {
2081 cur_rx->xl_ptr->xl_status = 0;
2082 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2083 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2088 * If the error bit was not set, the upload complete
2089 * bit should be set which means we have a valid packet.
2090 * If not, something truly strange has happened.
2092 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2093 printf("xl%d: bad receive status -- "
2094 "packet dropped\n", sc->xl_unit);
2096 cur_rx->xl_ptr->xl_status = 0;
2097 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2098 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2102 /* No errors; receive the packet. */
2103 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2104 BUS_DMASYNC_POSTREAD);
2105 m = cur_rx->xl_mbuf;
2108 * Try to conjure up a new mbuf cluster. If that
2109 * fails, it means we have an out of memory condition and
2110 * should leave the buffer in place and continue. This will
2111 * result in a lost packet, but there's little else we
2112 * can do in this situation.
2114 if (xl_newbuf(sc, cur_rx)) {
2116 cur_rx->xl_ptr->xl_status = 0;
2117 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2118 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2121 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2122 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2125 eh = mtod(m, struct ether_header *);
2126 m->m_pkthdr.rcvif = ifp;
2127 m->m_pkthdr.len = m->m_len = total_len;
2129 /* Remove header from mbuf and pass it on. */
2130 m_adj(m, sizeof(struct ether_header));
2132 if (ifp->if_capenable & IFCAP_RXCSUM) {
2133 /* Do IP checksum checking. */
2134 if (rxstat & XL_RXSTAT_IPCKOK)
2135 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2136 if (!(rxstat & XL_RXSTAT_IPCKERR))
2137 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2138 if ((rxstat & XL_RXSTAT_TCPCOK &&
2139 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2140 (rxstat & XL_RXSTAT_UDPCKOK &&
2141 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2142 m->m_pkthdr.csum_flags |=
2143 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2144 m->m_pkthdr.csum_data = 0xffff;
2148 ether_input(ifp, eh, m);
2152 * Handle the 'end of channel' condition. When the upload
2153 * engine hits the end of the RX ring, it will stall. This
2154 * is our cue to flush the RX ring, reload the uplist pointer
2155 * register and unstall the engine.
2156 * XXX This is actually a little goofy. With the ThunderLAN
2157 * chip, you get an interrupt when the receiver hits the end
2158 * of the receive ring, which tells you exactly when you
2159 * you need to reload the ring pointer. Here we have to
2160 * fake it. I'm mad at myself for not being clever enough
2161 * to avoid the use of a goto here.
2163 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2164 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2167 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2168 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2169 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2177 * A frame was downloaded to the chip. It's safe for us to clean up
2182 struct xl_softc *sc;
2184 struct xl_chain *cur_tx;
2187 ifp = &sc->arpcom.ac_if;
2189 /* Clear the timeout timer. */
2193 * Go through our tx list and free mbufs for those
2194 * frames that have been uploaded. Note: the 3c905B
2195 * sets a special bit in the status word to let us
2196 * know that a frame has been downloaded, but the
2197 * original 3c900/3c905 adapters don't do that.
2198 * Consequently, we have to use a different test if
2199 * xl_type != XL_TYPE_905B.
2201 while(sc->xl_cdata.xl_tx_head != NULL) {
2202 cur_tx = sc->xl_cdata.xl_tx_head;
2204 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2207 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2208 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2209 BUS_DMASYNC_POSTWRITE);
2210 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2211 m_freem(cur_tx->xl_mbuf);
2212 cur_tx->xl_mbuf = NULL;
2215 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2216 sc->xl_cdata.xl_tx_free = cur_tx;
2219 if (sc->xl_cdata.xl_tx_head == NULL) {
2220 ifp->if_flags &= ~IFF_OACTIVE;
2221 sc->xl_cdata.xl_tx_tail = NULL;
2223 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2224 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2225 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2226 sc->xl_cdata.xl_tx_head->xl_phys);
2227 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2236 struct xl_softc *sc;
2238 struct xl_chain *cur_tx = NULL;
2242 ifp = &sc->arpcom.ac_if;
2244 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2245 BUS_DMASYNC_POSTREAD);
2246 idx = sc->xl_cdata.xl_tx_cons;
2247 while(idx != sc->xl_cdata.xl_tx_prod) {
2249 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2251 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2252 XL_TXSTAT_DL_COMPLETE))
2255 if (cur_tx->xl_mbuf != NULL) {
2256 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2257 BUS_DMASYNC_POSTWRITE);
2258 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2259 m_freem(cur_tx->xl_mbuf);
2260 cur_tx->xl_mbuf = NULL;
2265 sc->xl_cdata.xl_tx_cnt--;
2266 XL_INC(idx, XL_TX_LIST_CNT);
2270 sc->xl_cdata.xl_tx_cons = idx;
2273 ifp->if_flags &= ~IFF_OACTIVE;
2279 * TX 'end of channel' interrupt handler. Actually, we should
2280 * only get a 'TX complete' interrupt if there's a transmit error,
2281 * so this is really TX error handler.
2285 struct xl_softc *sc;
2289 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2290 if (txstat & XL_TXSTATUS_UNDERRUN ||
2291 txstat & XL_TXSTATUS_JABBER ||
2292 txstat & XL_TXSTATUS_RECLAIM) {
2293 printf("xl%d: transmission error: %x\n",
2294 sc->xl_unit, txstat);
2295 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2297 if (sc->xl_type == XL_TYPE_905B) {
2298 if (sc->xl_cdata.xl_tx_cnt) {
2301 i = sc->xl_cdata.xl_tx_cons;
2302 c = &sc->xl_cdata.xl_tx_chain[i];
2303 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2305 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2308 if (sc->xl_cdata.xl_tx_head != NULL)
2309 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2310 sc->xl_cdata.xl_tx_head->xl_phys);
2313 * Remember to set this for the
2314 * first generation 3c90X chips.
2316 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2317 if (txstat & XL_TXSTATUS_UNDERRUN &&
2318 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2319 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2320 printf("xl%d: tx underrun, increasing tx start"
2321 " threshold to %d bytes\n", sc->xl_unit,
2324 CSR_WRITE_2(sc, XL_COMMAND,
2325 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2326 if (sc->xl_type == XL_TYPE_905B) {
2327 CSR_WRITE_2(sc, XL_COMMAND,
2328 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2330 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2331 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2333 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2334 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2337 * Write an arbitrary byte to the TX_STATUS register
2338 * to clear this interrupt/error and advance to the next.
2340 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2350 struct xl_softc *sc;
2355 ifp = &sc->arpcom.ac_if;
2357 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) {
2359 CSR_WRITE_2(sc, XL_COMMAND,
2360 XL_CMD_INTR_ACK|(status & XL_INTRS));
2362 if (status & XL_STAT_UP_COMPLETE) {
2365 curpkts = ifp->if_ipackets;
2367 if (curpkts == ifp->if_ipackets) {
2368 while (xl_rx_resync(sc))
2373 if (status & XL_STAT_DOWN_COMPLETE) {
2374 if (sc->xl_type == XL_TYPE_905B)
2380 if (status & XL_STAT_TX_COMPLETE) {
2385 if (status & XL_STAT_ADFAIL) {
2390 if (status & XL_STAT_STATSOFLOW) {
2391 sc->xl_stats_no_timeout = 1;
2392 xl_stats_update(sc);
2393 sc->xl_stats_no_timeout = 0;
2397 if (ifp->if_snd.ifq_head != NULL)
2398 (*ifp->if_start)(ifp);
2404 xl_stats_update(xsc)
2407 struct xl_softc *sc;
2409 struct xl_stats xl_stats;
2412 struct mii_data *mii = NULL;
2414 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2417 ifp = &sc->arpcom.ac_if;
2418 if (sc->xl_miibus != NULL)
2419 mii = device_get_softc(sc->xl_miibus);
2421 p = (u_int8_t *)&xl_stats;
2423 /* Read all the stats registers. */
2426 for (i = 0; i < 16; i++)
2427 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2429 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2431 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2432 xl_stats.xl_tx_single_collision +
2433 xl_stats.xl_tx_late_collision;
2436 * Boomerang and cyclone chips have an extra stats counter
2437 * in window 4 (BadSSD). We have to read this too in order
2438 * to clear out all the stats registers and avoid a statsoflow
2442 CSR_READ_1(sc, XL_W4_BADSSD);
2444 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2449 if (!sc->xl_stats_no_timeout)
2450 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2456 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2457 * pointers to the fragment pointers.
2460 xl_encap(sc, c, m_head)
2461 struct xl_softc *sc;
2463 struct mbuf *m_head;
2469 ifp = &sc->arpcom.ac_if;
2472 * Start packing the mbufs in this chain into
2473 * the fragment pointers. Stop when we run out
2474 * of fragments or hit the end of the mbuf chain.
2476 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2477 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2479 if (error && error != EFBIG) {
2481 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error);
2486 * Handle special case: we used up all 63 fragments,
2487 * but we have more mbufs left in the chain. Copy the
2488 * data into an mbuf cluster. Note that we don't
2489 * bother clearing the values in the other fragment
2490 * pointers/counters; it wouldn't gain us anything,
2491 * and would waste cycles.
2496 m_new = m_defrag(m_head, M_DONTWAIT);
2497 if (m_new == NULL) {
2504 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2505 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2508 printf("xl%d: can't map mbuf (error %d)\n",
2509 sc->xl_unit, error);
2514 if (sc->xl_type == XL_TYPE_905B) {
2515 status = XL_TXSTAT_RND_DEFEAT;
2517 if (m_head->m_pkthdr.csum_flags) {
2518 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2519 status |= XL_TXSTAT_IPCKSUM;
2520 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2521 status |= XL_TXSTAT_TCPCKSUM;
2522 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2523 status |= XL_TXSTAT_UDPCKSUM;
2525 c->xl_ptr->xl_status = htole32(status);
2528 c->xl_mbuf = m_head;
2529 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2534 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2535 * to the mbuf data regions directly in the transmit lists. We also save a
2536 * copy of the pointers since the transmit list fragment pointers are
2537 * physical addresses.
2543 struct xl_softc *sc;
2544 struct mbuf *m_head = NULL;
2545 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2546 struct xl_chain *prev_tx;
2552 * Check for an available queue slot. If there are none,
2555 if (sc->xl_cdata.xl_tx_free == NULL) {
2558 if (sc->xl_cdata.xl_tx_free == NULL) {
2559 ifp->if_flags |= IFF_OACTIVE;
2564 start_tx = sc->xl_cdata.xl_tx_free;
2566 while(sc->xl_cdata.xl_tx_free != NULL) {
2567 IF_DEQUEUE(&ifp->if_snd, m_head);
2571 /* Pick a descriptor off the free list. */
2573 cur_tx = sc->xl_cdata.xl_tx_free;
2575 /* Pack the data into the descriptor. */
2576 error = xl_encap(sc, cur_tx, m_head);
2582 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2583 cur_tx->xl_next = NULL;
2585 /* Chain it together. */
2587 prev->xl_next = cur_tx;
2588 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2593 * If there's a BPF listener, bounce a copy of this frame
2597 bpf_mtap(ifp, cur_tx->xl_mbuf);
2601 * If there are no packets queued, bail.
2603 if (cur_tx == NULL) {
2608 * Place the request for the upload interrupt
2609 * in the last descriptor in the chain. This way, if
2610 * we're chaining several packets at once, we'll only
2611 * get an interupt once for the whole chain rather than
2612 * once for each packet.
2614 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2616 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2617 BUS_DMASYNC_PREWRITE);
2620 * Queue the packets. If the TX channel is clear, update
2621 * the downlist pointer register.
2623 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2626 if (sc->xl_cdata.xl_tx_head != NULL) {
2627 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2628 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2629 htole32(start_tx->xl_phys);
2630 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2631 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2632 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2633 sc->xl_cdata.xl_tx_tail = cur_tx;
2635 sc->xl_cdata.xl_tx_head = start_tx;
2636 sc->xl_cdata.xl_tx_tail = cur_tx;
2638 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2639 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2641 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2646 * Set a timeout in case the chip goes out to lunch.
2651 * XXX Under certain conditions, usually on slower machines
2652 * where interrupts may be dropped, it's possible for the
2653 * adapter to chew up all the buffers in the receive ring
2654 * and stall, without us being able to do anything about it.
2655 * To guard against this, we need to make a pass over the
2656 * RX queue to make sure there aren't any packets pending.
2657 * Doing it here means we can flush the receive ring at the
2658 * same time the chip is DMAing the transmit descriptors we
2661 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2662 * nature of their chips in all their marketing literature;
2663 * we may as well take advantage of it. :)
2674 struct xl_softc *sc;
2675 struct mbuf *m_head = NULL;
2676 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2677 struct xl_chain *prev_tx;
2682 if (ifp->if_flags & IFF_OACTIVE) {
2686 idx = sc->xl_cdata.xl_tx_prod;
2687 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2689 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2691 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2692 ifp->if_flags |= IFF_OACTIVE;
2696 IF_DEQUEUE(&ifp->if_snd, m_head);
2701 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2703 /* Pack the data into the descriptor. */
2704 error = xl_encap(sc, cur_tx, m_head);
2710 /* Chain it together. */
2712 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2716 * If there's a BPF listener, bounce a copy of this frame
2720 bpf_mtap(ifp, cur_tx->xl_mbuf);
2722 XL_INC(idx, XL_TX_LIST_CNT);
2723 sc->xl_cdata.xl_tx_cnt++;
2727 * If there are no packets queued, bail.
2729 if (cur_tx == NULL) {
2734 * Place the request for the upload interrupt
2735 * in the last descriptor in the chain. This way, if
2736 * we're chaining several packets at once, we'll only
2737 * get an interupt once for the whole chain rather than
2738 * once for each packet.
2740 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2742 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2743 BUS_DMASYNC_PREWRITE);
2745 /* Start transmission */
2746 sc->xl_cdata.xl_tx_prod = idx;
2747 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2750 * Set a timeout in case the chip goes out to lunch.
2761 struct xl_softc *sc = xsc;
2762 struct ifnet *ifp = &sc->arpcom.ac_if;
2764 u_int16_t rxfilt = 0;
2765 struct mii_data *mii = NULL;
2771 * Cancel pending I/O and free all RX/TX buffers.
2775 if (sc->xl_miibus == NULL) {
2776 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2779 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2783 if (sc->xl_miibus != NULL)
2784 mii = device_get_softc(sc->xl_miibus);
2786 /* Init our MAC address */
2788 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2789 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2790 sc->arpcom.ac_enaddr[i]);
2793 /* Clear the station mask. */
2794 for (i = 0; i < 3; i++)
2795 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2797 /* Reset TX and RX. */
2798 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2800 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2803 /* Init circular RX list. */
2804 error = xl_list_rx_init(sc);
2806 printf("xl%d: initialization of the rx ring failed (%d)\n",
2807 sc->xl_unit, error);
2813 /* Init TX descriptors. */
2814 if (sc->xl_type == XL_TYPE_905B)
2815 error = xl_list_tx_init_90xB(sc);
2817 error = xl_list_tx_init(sc);
2819 printf("xl%d: initialization of the tx ring failed (%d)\n",
2820 sc->xl_unit, error);
2826 * Set the TX freethresh value.
2827 * Note that this has no effect on 3c905B "cyclone"
2828 * cards but is required for 3c900/3c905 "boomerang"
2829 * cards in order to enable the download engine.
2831 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2833 /* Set the TX start threshold for best performance. */
2834 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2835 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2838 * If this is a 3c905B, also set the tx reclaim threshold.
2839 * This helps cut down on the number of tx reclaim errors
2840 * that could happen on a busy network. The chip multiplies
2841 * the register value by 16 to obtain the actual threshold
2842 * in bytes, so we divide by 16 when setting the value here.
2843 * The existing threshold value can be examined by reading
2844 * the register at offset 9 in window 5.
2846 if (sc->xl_type == XL_TYPE_905B) {
2847 CSR_WRITE_2(sc, XL_COMMAND,
2848 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2851 /* Set RX filter bits. */
2853 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2855 /* Set the individual bit to receive frames for this host only. */
2856 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2858 /* If we want promiscuous mode, set the allframes bit. */
2859 if (ifp->if_flags & IFF_PROMISC) {
2860 rxfilt |= XL_RXFILTER_ALLFRAMES;
2861 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2863 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2868 * Set capture broadcast bit to capture broadcast frames.
2870 if (ifp->if_flags & IFF_BROADCAST) {
2871 rxfilt |= XL_RXFILTER_BROADCAST;
2872 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2874 rxfilt &= ~XL_RXFILTER_BROADCAST;
2875 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2879 * Program the multicast filter, if necessary.
2881 if (sc->xl_type == XL_TYPE_905B)
2882 xl_setmulti_hash(sc);
2887 * Load the address of the RX list. We have to
2888 * stall the upload engine before we can manipulate
2889 * the uplist pointer register, then unstall it when
2890 * we're finished. We also have to wait for the
2891 * stall command to complete before proceeding.
2892 * Note that we have to do this after any RX resets
2893 * have completed since the uplist register is cleared
2896 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2898 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2899 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2903 if (sc->xl_type == XL_TYPE_905B) {
2904 /* Set polling interval */
2905 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2906 /* Load the address of the TX list */
2907 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2909 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2910 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2911 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2916 * If the coax transceiver is on, make sure to enable
2917 * the DC-DC converter.
2920 if (sc->xl_xcvr == XL_XCVR_COAX)
2921 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2923 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2926 * increase packet size to allow reception of 802.1q or ISL packets.
2927 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2928 * control register. For 3c90xB/C chips, use the RX packet size
2932 if (sc->xl_type == XL_TYPE_905B)
2933 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2936 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2937 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2938 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2941 /* Clear out the stats counters. */
2942 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2943 sc->xl_stats_no_timeout = 1;
2944 xl_stats_update(sc);
2945 sc->xl_stats_no_timeout = 0;
2947 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2948 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2951 * Enable interrupts.
2953 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2954 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2955 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2956 if (sc->xl_flags & XL_FLAG_FUNCREG)
2957 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2959 /* Set the RX early threshold */
2960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2961 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2963 /* Enable receiver and transmitter. */
2964 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2966 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2972 /* Select window 7 for normal operations. */
2975 ifp->if_flags |= IFF_RUNNING;
2976 ifp->if_flags &= ~IFF_OACTIVE;
2978 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2986 * Set media options.
2992 struct xl_softc *sc;
2993 struct ifmedia *ifm = NULL;
2994 struct mii_data *mii = NULL;
2997 if (sc->xl_miibus != NULL)
2998 mii = device_get_softc(sc->xl_miibus);
3002 ifm = &mii->mii_media;
3004 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3009 xl_setmode(sc, ifm->ifm_media);
3016 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
3017 || sc->xl_media & XL_MEDIAOPT_BT4) {
3020 xl_setmode(sc, ifm->ifm_media);
3027 * Report current media status.
3030 xl_ifmedia_sts(ifp, ifmr)
3032 struct ifmediareq *ifmr;
3034 struct xl_softc *sc;
3036 struct mii_data *mii = NULL;
3039 if (sc->xl_miibus != NULL)
3040 mii = device_get_softc(sc->xl_miibus);
3043 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3044 icfg >>= XL_ICFG_CONNECTOR_BITS;
3046 ifmr->ifm_active = IFM_ETHER;
3050 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3051 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3052 ifmr->ifm_active |= IFM_FDX;
3054 ifmr->ifm_active |= IFM_HDX;
3057 if (sc->xl_type == XL_TYPE_905B &&
3058 sc->xl_media == XL_MEDIAOPT_10FL) {
3059 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3060 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3061 ifmr->ifm_active |= IFM_FDX;
3063 ifmr->ifm_active |= IFM_HDX;
3065 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3068 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3071 * XXX MII and BTX/AUTO should be separate cases.
3074 case XL_XCVR_100BTX:
3079 ifmr->ifm_active = mii->mii_media_active;
3080 ifmr->ifm_status = mii->mii_media_status;
3083 case XL_XCVR_100BFX:
3084 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3087 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg);
3095 xl_ioctl(ifp, command, data)
3100 struct xl_softc *sc = ifp->if_softc;
3101 struct ifreq *ifr = (struct ifreq *) data;
3103 struct mii_data *mii = NULL;
3113 error = ether_ioctl(ifp, command, data);
3117 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3118 if (ifp->if_flags & IFF_UP) {
3119 if (ifp->if_flags & IFF_RUNNING &&
3120 ifp->if_flags & IFF_PROMISC &&
3121 !(sc->xl_if_flags & IFF_PROMISC)) {
3122 rxfilt |= XL_RXFILTER_ALLFRAMES;
3123 CSR_WRITE_2(sc, XL_COMMAND,
3124 XL_CMD_RX_SET_FILT|rxfilt);
3126 } else if (ifp->if_flags & IFF_RUNNING &&
3127 !(ifp->if_flags & IFF_PROMISC) &&
3128 sc->xl_if_flags & IFF_PROMISC) {
3129 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3130 CSR_WRITE_2(sc, XL_COMMAND,
3131 XL_CMD_RX_SET_FILT|rxfilt);
3136 if (ifp->if_flags & IFF_RUNNING)
3139 sc->xl_if_flags = ifp->if_flags;
3144 if (sc->xl_type == XL_TYPE_905B)
3145 xl_setmulti_hash(sc);
3152 if (sc->xl_miibus != NULL)
3153 mii = device_get_softc(sc->xl_miibus);
3155 error = ifmedia_ioctl(ifp, ifr,
3156 &sc->ifmedia, command);
3158 error = ifmedia_ioctl(ifp, ifr,
3159 &mii->mii_media, command);
3162 ifp->if_capenable = ifr->ifr_reqcap;
3163 if (ifp->if_capenable & IFCAP_TXCSUM)
3164 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3166 ifp->if_hwassist = 0;
3181 struct xl_softc *sc;
3182 u_int16_t status = 0;
3188 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3189 printf("xl%d: watchdog timeout\n", sc->xl_unit);
3191 if (status & XL_MEDIASTAT_CARRIER)
3192 printf("xl%d: no carrier - transceiver cable problem?\n",
3200 if (ifp->if_snd.ifq_head != NULL)
3201 (*ifp->if_start)(ifp);
3207 * Stop the adapter and free any mbufs allocated to the
3212 struct xl_softc *sc;
3217 ifp = &sc->arpcom.ac_if;
3220 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3221 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3222 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3223 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3225 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3226 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3230 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3232 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3236 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3237 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3238 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3239 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3241 /* Stop the stats updater. */
3242 untimeout(xl_stats_update, sc, sc->xl_stat_ch);
3245 * Free data in the RX lists.
3247 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3248 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3249 bus_dmamap_unload(sc->xl_mtag,
3250 sc->xl_cdata.xl_rx_chain[i].xl_map);
3251 bus_dmamap_destroy(sc->xl_mtag,
3252 sc->xl_cdata.xl_rx_chain[i].xl_map);
3253 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3254 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3257 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3259 * Free the TX list buffers.
3261 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3262 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3263 bus_dmamap_unload(sc->xl_mtag,
3264 sc->xl_cdata.xl_tx_chain[i].xl_map);
3265 bus_dmamap_destroy(sc->xl_mtag,
3266 sc->xl_cdata.xl_tx_chain[i].xl_map);
3267 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3268 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3271 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3273 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3279 * Stop all chip I/O so that the kernel's probe routines don't
3280 * get confused by errant DMAs when rebooting.
3286 struct xl_softc *sc;
3288 sc = device_get_softc(dev);
3300 struct xl_softc *sc;
3305 sc = device_get_softc(dev);
3318 struct xl_softc *sc;
3324 sc = device_get_softc(dev);
3325 ifp = &sc->arpcom.ac_if;
3328 if (ifp->if_flags & IFF_UP)