2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.39 2005/09/10 06:46:05 dillon Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
40 #include <vm/vm_param.h>
42 #include <vm/vm_kern.h>
43 #include <vm/vm_extern.h>
45 #include <vm/vm_map.h>
51 #include <machine/smptests.h>
52 #include <machine/smp.h>
53 #include <machine/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
60 #include <machine/tss.h>
61 #include <machine/specialreg.h>
62 #include <machine/globaldata.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <i386/isa/icu.h> /* IPIs */
67 #include <i386/isa/intr_machdep.h> /* IPIs */
70 #if defined(TEST_DEFAULT_CONFIG)
71 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
73 #define MPFPS_MPFB1 mpfps->mpfb1
74 #endif /* TEST_DEFAULT_CONFIG */
76 #define WARMBOOT_TARGET 0
77 #define WARMBOOT_OFF (KERNBASE + 0x0467)
78 #define WARMBOOT_SEG (KERNBASE + 0x0469)
80 #define BIOS_BASE (0xf0000)
81 #define BIOS_SIZE (0x10000)
82 #define BIOS_COUNT (BIOS_SIZE/4)
84 #define CMOS_REG (0x70)
85 #define CMOS_DATA (0x71)
86 #define BIOS_RESET (0x0f)
87 #define BIOS_WARM (0x0a)
89 #define PROCENTRY_FLAG_EN 0x01
90 #define PROCENTRY_FLAG_BP 0x02
91 #define IOAPICENTRY_FLAG_EN 0x01
94 /* MP Floating Pointer Structure */
95 typedef struct MPFPS {
108 /* MP Configuration Table Header */
109 typedef struct MPCTH {
111 u_short base_table_length;
115 u_char product_id[12];
116 void *oem_table_pointer;
117 u_short oem_table_size;
120 u_short extended_table_length;
121 u_char extended_table_checksum;
126 typedef struct PROCENTRY {
131 u_long cpu_signature;
132 u_long feature_flags;
137 typedef struct BUSENTRY {
143 typedef struct IOAPICENTRY {
149 } *io_apic_entry_ptr;
151 typedef struct INTENTRY {
161 /* descriptions of MP basetable entries */
162 typedef struct BASETABLE_ENTRY {
169 * this code MUST be enabled here and in mpboot.s.
170 * it follows the very early stages of AP boot by placing values in CMOS ram.
171 * it NORMALLY will never be needed and thus the primitive method for enabling.
174 #if defined(CHECK_POINTS)
175 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
176 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
178 #define CHECK_INIT(D); \
179 CHECK_WRITE(0x34, (D)); \
180 CHECK_WRITE(0x35, (D)); \
181 CHECK_WRITE(0x36, (D)); \
182 CHECK_WRITE(0x37, (D)); \
183 CHECK_WRITE(0x38, (D)); \
184 CHECK_WRITE(0x39, (D));
186 #define CHECK_PRINT(S); \
187 printf("%s: %d, %d, %d, %d, %d, %d\n", \
196 #else /* CHECK_POINTS */
198 #define CHECK_INIT(D)
199 #define CHECK_PRINT(S)
201 #endif /* CHECK_POINTS */
204 * Values to send to the POST hardware.
206 #define MP_BOOTADDRESS_POST 0x10
207 #define MP_PROBE_POST 0x11
208 #define MPTABLE_PASS1_POST 0x12
210 #define MP_START_POST 0x13
211 #define MP_ENABLE_POST 0x14
212 #define MPTABLE_PASS2_POST 0x15
214 #define START_ALL_APS_POST 0x16
215 #define INSTALL_AP_TRAMP_POST 0x17
216 #define START_AP_POST 0x18
218 #define MP_ANNOUNCE_POST 0x19
220 static int need_hyperthreading_fixup;
221 static u_int logical_cpus;
222 u_int logical_cpus_mask;
224 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
225 int current_postcode;
227 /** XXX FIXME: what system files declare these??? */
228 extern struct region_descriptor r_gdt, r_idt;
230 int bsp_apic_ready = 0; /* flags useability of BSP apic */
231 int mp_naps; /* # of Applications processors */
232 int mp_nbusses; /* # of busses */
233 int mp_napics; /* # of IO APICs */
234 int boot_cpu_id; /* designated BSP */
235 vm_offset_t cpu_apic_address;
236 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
239 u_int32_t cpu_apic_versions[MAXCPU];
240 u_int32_t *io_apic_versions;
242 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
244 #ifdef APIC_INTR_REORDER
246 volatile int *location;
248 } apic_isrbit_location[32];
253 * APIC ID logical/physical mapping structures.
254 * We oversize these to simplify boot-time config.
256 int cpu_num_to_apic_id[NAPICID];
257 int io_num_to_apic_id[NAPICID];
258 int apic_id_to_logical[NAPICID];
260 /* AP uses this during bootstrap. Do not staticize. */
264 /* Hotwire a 0->4MB V==P mapping */
265 extern pt_entry_t *KPTphys;
267 /* SMP page table page */
268 extern pt_entry_t *SMPpt;
270 struct pcb stoppcbs[MAXCPU];
273 * Local data and functions.
276 static int mp_capable;
277 static u_int boot_address;
278 static u_int base_memory;
279 static int mp_finish;
281 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
282 static mpfps_t mpfps;
283 static int search_for_sig(u_int32_t target, int count);
284 static void mp_enable(u_int boot_addr);
286 static void mptable_hyperthread_fixup(u_int id_mask);
287 static void mptable_pass1(void);
288 static int mptable_pass2(void);
289 static void default_mp_table(int type);
290 static void fix_mp_table(void);
291 static void setup_apic_irq_mapping(void);
292 static int start_all_aps(u_int boot_addr);
293 static void install_ap_tramp(u_int boot_addr);
294 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
295 static int apic_int_is_bus_type(int intr, int bus_type);
297 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
298 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
299 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
302 * Calculate usable address in base memory for AP trampoline code.
305 mp_bootaddress(u_int basemem)
307 POSTCODE(MP_BOOTADDRESS_POST);
309 base_memory = basemem * 1024; /* convert to bytes */
311 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
312 if ((base_memory - boot_address) < bootMP_size)
313 boot_address -= 4096; /* not enough, lower by 4k */
320 * Look for an Intel MP spec table (ie, SMP capable hardware).
329 POSTCODE(MP_PROBE_POST);
331 /* see if EBDA exists */
332 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
333 /* search first 1K of EBDA */
334 target = (u_int32_t) (segment << 4);
335 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
338 /* last 1K of base memory, effective 'top of base' passed in */
339 target = (u_int32_t) (base_memory - 0x400);
340 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
344 /* search the BIOS */
345 target = (u_int32_t) BIOS_BASE;
346 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
355 /* calculate needed resources */
359 /* flag fact that we are running multiple processors */
366 * Startup the SMP processors.
371 POSTCODE(MP_START_POST);
373 /* look for MP capable motherboard */
375 mp_enable(boot_address);
377 panic("MP hardware not found!");
382 * Print various information about the SMP system hardware and setup.
389 POSTCODE(MP_ANNOUNCE_POST);
391 printf("DragonFly/MP: Multiprocessor motherboard\n");
392 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
393 printf(", version: 0x%08x", cpu_apic_versions[0]);
394 printf(", at 0x%08x\n", cpu_apic_address);
395 for (x = 1; x <= mp_naps; ++x) {
396 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
397 printf(", version: 0x%08x", cpu_apic_versions[x]);
398 printf(", at 0x%08x\n", cpu_apic_address);
402 for (x = 0; x < mp_napics; ++x) {
403 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
404 printf(", version: 0x%08x", io_apic_versions[x]);
405 printf(", at 0x%08x\n", io_apic_address[x]);
408 printf(" Warning: APIC I/O disabled\n");
413 * AP cpu's call this to sync up protected mode.
415 * WARNING! We must ensure that the cpu is sufficiently initialized to
416 * be able to use to the FP for our optimized bzero/bcopy code before
417 * we enter more mainstream C code.
419 * WARNING! %fs is not set up on entry. This routine sets up %fs.
425 int x, myid = bootAP;
427 struct mdglobaldata *md;
428 struct privatespace *ps;
430 ps = &CPU_prvspace[myid];
432 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
433 gdt_segs[GPROC0_SEL].ssd_base =
434 (int) &ps->mdglobaldata.gd_common_tss;
435 ps->mdglobaldata.mi.gd_prvspace = ps;
437 for (x = 0; x < NGDT; x++) {
438 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
441 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
442 r_gdt.rd_base = (int) &gdt[myid * NGDT];
443 lgdt(&r_gdt); /* does magic intra-segment return */
448 mdcpu->gd_currentldt = _default_ldt;
450 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
451 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
453 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
455 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
456 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
457 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
458 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
459 md->gd_common_tssd = *md->gd_tss_gdt;
463 * Set to a known state:
464 * Set by mpboot.s: CR0_PG, CR0_PE
465 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
468 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
470 pmap_set_opt(); /* PSE/4MB pages, etc */
472 /* set up CPU registers and state */
475 /* set up FPU state on the AP */
476 npxinit(__INITIAL_NPXCW__);
478 /* set up SSE registers */
485 * Final configuration of the BSP's local APIC:
486 * - disable 'pic mode'.
487 * - disable 'virtual wire mode'.
491 bsp_apic_configure(void)
496 /* leave 'pic mode' if necessary */
498 outb(0x22, 0x70); /* select IMCR */
499 byte = inb(0x23); /* current contents */
500 byte |= 0x01; /* mask external INTR */
501 outb(0x23, byte); /* disconnect 8259s/NMI */
504 /* mask lint0 (the 8259 'virtual wire' connection) */
505 temp = lapic.lvt_lint0;
506 temp |= APIC_LVT_M; /* set the mask */
507 lapic.lvt_lint0 = temp;
509 /* setup lint1 to handle NMI */
510 temp = lapic.lvt_lint1;
511 temp &= ~APIC_LVT_M; /* clear the mask */
512 lapic.lvt_lint1 = temp;
515 apic_dump("bsp_apic_configure()");
520 /*******************************************************************
521 * local functions and data
525 * start the SMP system
528 mp_enable(u_int boot_addr)
536 POSTCODE(MP_ENABLE_POST);
538 /* turn on 4MB of V == P addressing so we can get to MP table */
539 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
542 /* examine the MP table for needed info, uses physical addresses */
548 /* can't process default configs till the CPU APIC is pmapped */
552 /* post scan cleanup */
554 setup_apic_irq_mapping();
558 /* fill the LOGICAL io_apic_versions table */
559 for (apic = 0; apic < mp_napics; ++apic) {
560 ux = io_apic_read(apic, IOAPIC_VER);
561 io_apic_versions[apic] = ux;
562 io_apic_set_id(apic, IO_TO_ID(apic));
565 /* program each IO APIC in the system */
566 for (apic = 0; apic < mp_napics; ++apic)
567 if (io_apic_setup(apic) < 0)
568 panic("IO APIC setup failure");
570 /* install a 'Spurious INTerrupt' vector */
571 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
572 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
574 /* install an inter-CPU IPI for TLB invalidation */
575 setidt(XINVLTLB_OFFSET, Xinvltlb,
576 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
578 /* install an inter-CPU IPI for IPIQ messaging */
579 setidt(XIPIQ_OFFSET, Xipiq,
580 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
582 /* install an inter-CPU IPI for CPU stop/restart */
583 setidt(XCPUSTOP_OFFSET, Xcpustop,
584 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
586 #if defined(TEST_TEST1)
587 /* install a "fake hardware INTerrupt" vector */
588 setidt(XTEST1_OFFSET, Xtest1,
589 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
590 #endif /** TEST_TEST1 */
594 /* start each Application Processor */
595 start_all_aps(boot_addr);
600 * look for the MP spec signature
603 /* string defined by the Intel MP Spec as identifying the MP table */
604 #define MP_SIG 0x5f504d5f /* _MP_ */
605 #define NEXT(X) ((X) += 4)
607 search_for_sig(u_int32_t target, int count)
610 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
612 for (x = 0; x < count; NEXT(x))
613 if (addr[x] == MP_SIG)
614 /* make array index a byte index */
615 return (target + (x * sizeof(u_int32_t)));
621 static basetable_entry basetable_entry_types[] =
623 {0, 20, "Processor"},
630 typedef struct BUSDATA {
632 enum busTypes bus_type;
635 typedef struct INTDATA {
645 typedef struct BUSTYPENAME {
650 static bus_type_name bus_type_table[] =
656 {UNKNOWN_BUSTYPE, "---"},
659 {UNKNOWN_BUSTYPE, "---"},
660 {UNKNOWN_BUSTYPE, "---"},
661 {UNKNOWN_BUSTYPE, "---"},
662 {UNKNOWN_BUSTYPE, "---"},
663 {UNKNOWN_BUSTYPE, "---"},
665 {UNKNOWN_BUSTYPE, "---"},
666 {UNKNOWN_BUSTYPE, "---"},
667 {UNKNOWN_BUSTYPE, "---"},
668 {UNKNOWN_BUSTYPE, "---"},
670 {UNKNOWN_BUSTYPE, "---"}
672 /* from MP spec v1.4, table 5-1 */
673 static int default_data[7][5] =
675 /* nbus, id0, type0, id1, type1 */
676 {1, 0, ISA, 255, 255},
677 {1, 0, EISA, 255, 255},
678 {1, 0, EISA, 255, 255},
679 {1, 0, MCA, 255, 255},
681 {2, 0, EISA, 1, PCI},
687 static bus_datum *bus_data;
689 /* the IO INT data, one entry per possible APIC INTerrupt */
690 static io_int *io_apic_ints;
694 static int processor_entry (proc_entry_ptr entry, int cpu);
695 static int bus_entry (bus_entry_ptr entry, int bus);
696 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
697 static int int_entry (int_entry_ptr entry, int intr);
698 static int lookup_bus_type (char *name);
702 * 1st pass on motherboard's Intel MP specification table.
708 * cpu_apic_address (common to all CPUs)
726 POSTCODE(MPTABLE_PASS1_POST);
728 /* clear various tables */
729 for (x = 0; x < NAPICID; ++x) {
730 io_apic_address[x] = ~0; /* IO APIC address table */
733 /* init everything to empty */
740 /* check for use of 'default' configuration */
741 if (MPFPS_MPFB1 != 0) {
742 /* use default addresses */
743 cpu_apic_address = DEFAULT_APIC_BASE;
744 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
746 /* fill in with defaults */
747 mp_naps = 2; /* includes BSP */
748 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
755 if ((cth = mpfps->pap) == 0)
756 panic("MP Configuration Table Header MISSING!");
758 cpu_apic_address = (vm_offset_t) cth->apic_address;
760 /* walk the table, recording info of interest */
761 totalSize = cth->base_table_length - sizeof(struct MPCTH);
762 position = (u_char *) cth + sizeof(struct MPCTH);
763 count = cth->entry_count;
766 switch (type = *(u_char *) position) {
767 case 0: /* processor_entry */
768 if (((proc_entry_ptr)position)->cpu_flags
769 & PROCENTRY_FLAG_EN) {
772 ((proc_entry_ptr)position)->apic_id;
775 case 1: /* bus_entry */
778 case 2: /* io_apic_entry */
779 if (((io_apic_entry_ptr)position)->apic_flags
780 & IOAPICENTRY_FLAG_EN)
781 io_apic_address[mp_napics++] =
782 (vm_offset_t)((io_apic_entry_ptr)
783 position)->apic_address;
785 case 3: /* int_entry */
788 case 4: /* int_entry */
791 panic("mpfps Base Table HOSED!");
795 totalSize -= basetable_entry_types[type].length;
796 position = (uint8_t *)position +
797 basetable_entry_types[type].length;
801 /* qualify the numbers */
802 if (mp_naps > MAXCPU) {
803 printf("Warning: only using %d of %d available CPUs!\n",
808 /* See if we need to fixup HT logical CPUs. */
809 mptable_hyperthread_fixup(id_mask);
813 * This is also used as a counter while starting the APs.
817 --mp_naps; /* subtract the BSP */
822 * 2nd pass on motherboard's Intel MP specification table.
826 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
827 * CPU_TO_ID(N), logical CPU to APIC ID table
828 * IO_TO_ID(N), logical IO to APIC ID table
835 struct PROCENTRY proc;
842 int apic, bus, cpu, intr;
846 POSTCODE(MPTABLE_PASS2_POST);
848 /* Initialize fake proc entry for use with HT fixup. */
849 bzero(&proc, sizeof(proc));
851 proc.cpu_flags = PROCENTRY_FLAG_EN;
853 pgeflag = 0; /* XXX - Not used under SMP yet. */
855 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
857 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
859 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
861 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
864 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
866 for (i = 0; i < mp_napics; i++) {
867 for (j = 0; j < mp_napics; j++) {
868 /* same page frame as a previous IO apic? */
869 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
870 (io_apic_address[i] & PG_FRAME)) {
871 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
872 + (NPTEPG-2-j) * PAGE_SIZE
873 + (io_apic_address[i] & PAGE_MASK));
876 /* use this slot if available */
877 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
878 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
879 pgeflag | (io_apic_address[i] & PG_FRAME));
880 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
881 + (NPTEPG-2-j) * PAGE_SIZE
882 + (io_apic_address[i] & PAGE_MASK));
888 /* clear various tables */
889 for (x = 0; x < NAPICID; ++x) {
890 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
891 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
892 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
895 /* clear bus data table */
896 for (x = 0; x < mp_nbusses; ++x)
897 bus_data[x].bus_id = 0xff;
899 /* clear IO APIC INT table */
900 for (x = 0; x < (nintrs + 1); ++x) {
901 io_apic_ints[x].int_type = 0xff;
902 io_apic_ints[x].int_vector = 0xff;
905 /* setup the cpu/apic mapping arrays */
908 /* record whether PIC or virtual-wire mode */
909 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
911 /* check for use of 'default' configuration */
912 if (MPFPS_MPFB1 != 0)
913 return MPFPS_MPFB1; /* return default configuration type */
915 if ((cth = mpfps->pap) == 0)
916 panic("MP Configuration Table Header MISSING!");
918 /* walk the table, recording info of interest */
919 totalSize = cth->base_table_length - sizeof(struct MPCTH);
920 position = (u_char *) cth + sizeof(struct MPCTH);
921 count = cth->entry_count;
922 apic = bus = intr = 0;
923 cpu = 1; /* pre-count the BSP */
926 switch (type = *(u_char *) position) {
928 if (processor_entry(position, cpu))
931 if (need_hyperthreading_fixup) {
933 * Create fake mptable processor entries
934 * and feed them to processor_entry() to
935 * enumerate the logical CPUs.
937 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
938 for (i = 1; i < logical_cpus; i++) {
940 (void)processor_entry(&proc, cpu);
941 logical_cpus_mask |= (1 << cpu);
947 if (bus_entry(position, bus))
951 if (io_apic_entry(position, apic))
955 if (int_entry(position, intr))
959 /* int_entry(position); */
962 panic("mpfps Base Table HOSED!");
966 totalSize -= basetable_entry_types[type].length;
967 position = (uint8_t *)position + basetable_entry_types[type].length;
970 if (boot_cpu_id == -1)
971 panic("NO BSP found!");
973 /* report fact that its NOT a default configuration */
978 * Check if we should perform a hyperthreading "fix-up" to
979 * enumerate any logical CPU's that aren't already listed
982 * XXX: We assume that all of the physical CPUs in the
983 * system have the same number of logical CPUs.
985 * XXX: We assume that APIC ID's are allocated such that
986 * the APIC ID's for a physical processor are aligned
987 * with the number of logical CPU's in the processor.
990 mptable_hyperthread_fixup(u_int id_mask)
994 /* Nothing to do if there is no HTT support. */
995 if ((cpu_feature & CPUID_HTT) == 0)
997 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
998 if (logical_cpus <= 1)
1002 * For each APIC ID of a CPU that is set in the mask,
1003 * scan the other candidate APIC ID's for this
1004 * physical processor. If any of those ID's are
1005 * already in the table, then kill the fixup.
1007 for (id = 0; id <= MAXCPU; id++) {
1008 if ((id_mask & 1 << id) == 0)
1010 /* First, make sure we are on a logical_cpus boundary. */
1011 if (id % logical_cpus != 0)
1013 for (i = id + 1; i < id + logical_cpus; i++)
1014 if ((id_mask & 1 << i) != 0)
1019 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1020 * mp_naps right now.
1022 need_hyperthreading_fixup = 1;
1023 mp_naps *= logical_cpus;
1027 assign_apic_irq(int apic, int intpin, int irq)
1031 if (int_to_apicintpin[irq].ioapic != -1)
1032 panic("assign_apic_irq: inconsistent table");
1034 int_to_apicintpin[irq].ioapic = apic;
1035 int_to_apicintpin[irq].int_pin = intpin;
1036 int_to_apicintpin[irq].apic_address = ioapic[apic];
1037 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1039 for (x = 0; x < nintrs; x++) {
1040 if ((io_apic_ints[x].int_type == 0 ||
1041 io_apic_ints[x].int_type == 3) &&
1042 io_apic_ints[x].int_vector == 0xff &&
1043 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1044 io_apic_ints[x].dst_apic_int == intpin)
1045 io_apic_ints[x].int_vector = irq;
1050 revoke_apic_irq(int irq)
1056 if (int_to_apicintpin[irq].ioapic == -1)
1057 panic("revoke_apic_irq: inconsistent table");
1059 oldapic = int_to_apicintpin[irq].ioapic;
1060 oldintpin = int_to_apicintpin[irq].int_pin;
1062 int_to_apicintpin[irq].ioapic = -1;
1063 int_to_apicintpin[irq].int_pin = 0;
1064 int_to_apicintpin[irq].apic_address = NULL;
1065 int_to_apicintpin[irq].redirindex = 0;
1067 for (x = 0; x < nintrs; x++) {
1068 if ((io_apic_ints[x].int_type == 0 ||
1069 io_apic_ints[x].int_type == 3) &&
1070 io_apic_ints[x].int_vector != 0xff &&
1071 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1072 io_apic_ints[x].dst_apic_int == oldintpin)
1073 io_apic_ints[x].int_vector = 0xff;
1079 allocate_apic_irq(int intr)
1085 if (io_apic_ints[intr].int_vector != 0xff)
1086 return; /* Interrupt handler already assigned */
1088 if (io_apic_ints[intr].int_type != 0 &&
1089 (io_apic_ints[intr].int_type != 3 ||
1090 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1091 io_apic_ints[intr].dst_apic_int == 0)))
1092 return; /* Not INT or ExtInt on != (0, 0) */
1095 while (irq < APIC_INTMAPSIZE &&
1096 int_to_apicintpin[irq].ioapic != -1)
1099 if (irq >= APIC_INTMAPSIZE)
1100 return; /* No free interrupt handlers */
1102 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1103 intpin = io_apic_ints[intr].dst_apic_int;
1105 assign_apic_irq(apic, intpin, irq);
1106 io_apic_setup_intpin(apic, intpin);
1111 swap_apic_id(int apic, int oldid, int newid)
1118 return; /* Nothing to do */
1120 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1121 apic, oldid, newid);
1123 /* Swap physical APIC IDs in interrupt entries */
1124 for (x = 0; x < nintrs; x++) {
1125 if (io_apic_ints[x].dst_apic_id == oldid)
1126 io_apic_ints[x].dst_apic_id = newid;
1127 else if (io_apic_ints[x].dst_apic_id == newid)
1128 io_apic_ints[x].dst_apic_id = oldid;
1131 /* Swap physical APIC IDs in IO_TO_ID mappings */
1132 for (oapic = 0; oapic < mp_napics; oapic++)
1133 if (IO_TO_ID(oapic) == newid)
1136 if (oapic < mp_napics) {
1137 printf("Changing APIC ID for IO APIC #%d from "
1138 "%d to %d in MP table\n",
1139 oapic, newid, oldid);
1140 IO_TO_ID(oapic) = oldid;
1142 IO_TO_ID(apic) = newid;
1147 fix_id_to_io_mapping(void)
1151 for (x = 0; x < NAPICID; x++)
1154 for (x = 0; x <= mp_naps; x++)
1155 if (CPU_TO_ID(x) < NAPICID)
1156 ID_TO_IO(CPU_TO_ID(x)) = x;
1158 for (x = 0; x < mp_napics; x++)
1159 if (IO_TO_ID(x) < NAPICID)
1160 ID_TO_IO(IO_TO_ID(x)) = x;
1165 first_free_apic_id(void)
1169 for (freeid = 0; freeid < NAPICID; freeid++) {
1170 for (x = 0; x <= mp_naps; x++)
1171 if (CPU_TO_ID(x) == freeid)
1175 for (x = 0; x < mp_napics; x++)
1176 if (IO_TO_ID(x) == freeid)
1187 io_apic_id_acceptable(int apic, int id)
1189 int cpu; /* Logical CPU number */
1190 int oapic; /* Logical IO APIC number for other IO APIC */
1193 return 0; /* Out of range */
1195 for (cpu = 0; cpu <= mp_naps; cpu++)
1196 if (CPU_TO_ID(cpu) == id)
1197 return 0; /* Conflict with CPU */
1199 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1200 if (IO_TO_ID(oapic) == id)
1201 return 0; /* Conflict with other APIC */
1203 return 1; /* ID is acceptable for IO APIC */
1208 * parse an Intel MP specification table
1215 int bus_0 = 0; /* Stop GCC warning */
1216 int bus_pci = 0; /* Stop GCC warning */
1218 int apic; /* IO APIC unit number */
1219 int freeid; /* Free physical APIC ID */
1220 int physid; /* Current physical IO APIC ID */
1223 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1224 * did it wrong. The MP spec says that when more than 1 PCI bus
1225 * exists the BIOS must begin with bus entries for the PCI bus and use
1226 * actual PCI bus numbering. This implies that when only 1 PCI bus
1227 * exists the BIOS can choose to ignore this ordering, and indeed many
1228 * MP motherboards do ignore it. This causes a problem when the PCI
1229 * sub-system makes requests of the MP sub-system based on PCI bus
1230 * numbers. So here we look for the situation and renumber the
1231 * busses and associated INTs in an effort to "make it right".
1234 /* find bus 0, PCI bus, count the number of PCI busses */
1235 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1236 if (bus_data[x].bus_id == 0) {
1239 if (bus_data[x].bus_type == PCI) {
1245 * bus_0 == slot of bus with ID of 0
1246 * bus_pci == slot of last PCI bus encountered
1249 /* check the 1 PCI bus case for sanity */
1250 /* if it is number 0 all is well */
1251 if (num_pci_bus == 1 &&
1252 bus_data[bus_pci].bus_id != 0) {
1254 /* mis-numbered, swap with whichever bus uses slot 0 */
1256 /* swap the bus entry types */
1257 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1258 bus_data[bus_0].bus_type = PCI;
1260 /* swap each relavant INTerrupt entry */
1261 id = bus_data[bus_pci].bus_id;
1262 for (x = 0; x < nintrs; ++x) {
1263 if (io_apic_ints[x].src_bus_id == id) {
1264 io_apic_ints[x].src_bus_id = 0;
1266 else if (io_apic_ints[x].src_bus_id == 0) {
1267 io_apic_ints[x].src_bus_id = id;
1272 /* Assign IO APIC IDs.
1274 * First try the existing ID. If a conflict is detected, try
1275 * the ID in the MP table. If a conflict is still detected, find
1278 * We cannot use the ID_TO_IO table before all conflicts has been
1279 * resolved and the table has been corrected.
1281 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1283 /* First try to use the value set by the BIOS */
1284 physid = io_apic_get_id(apic);
1285 if (io_apic_id_acceptable(apic, physid)) {
1286 if (IO_TO_ID(apic) != physid)
1287 swap_apic_id(apic, IO_TO_ID(apic), physid);
1291 /* Then check if the value in the MP table is acceptable */
1292 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1295 /* Last resort, find a free APIC ID and use it */
1296 freeid = first_free_apic_id();
1297 if (freeid >= NAPICID)
1298 panic("No free physical APIC IDs found");
1300 if (io_apic_id_acceptable(apic, freeid)) {
1301 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1304 panic("Free physical APIC ID not usable");
1306 fix_id_to_io_mapping();
1308 /* detect and fix broken Compaq MP table */
1309 if (apic_int_type(0, 0) == -1) {
1310 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1311 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1312 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1313 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1314 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1315 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1317 } else if (apic_int_type(0, 0) == 0) {
1318 printf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1319 for (x = 0; x < nintrs; ++x)
1320 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1321 (0 == io_apic_ints[x].dst_apic_int)) {
1322 io_apic_ints[x].int_type = 3;
1323 io_apic_ints[x].int_vector = 0xff;
1330 /* Assign low level interrupt handlers */
1332 setup_apic_irq_mapping(void)
1338 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1339 int_to_apicintpin[x].ioapic = -1;
1340 int_to_apicintpin[x].int_pin = 0;
1341 int_to_apicintpin[x].apic_address = NULL;
1342 int_to_apicintpin[x].redirindex = 0;
1345 /* First assign ISA/EISA interrupts */
1346 for (x = 0; x < nintrs; x++) {
1347 int_vector = io_apic_ints[x].src_bus_irq;
1348 if (int_vector < APIC_INTMAPSIZE &&
1349 io_apic_ints[x].int_vector == 0xff &&
1350 int_to_apicintpin[int_vector].ioapic == -1 &&
1351 (apic_int_is_bus_type(x, ISA) ||
1352 apic_int_is_bus_type(x, EISA)) &&
1353 io_apic_ints[x].int_type == 0) {
1354 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1355 io_apic_ints[x].dst_apic_int,
1360 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1361 for (x = 0; x < nintrs; x++) {
1362 if (io_apic_ints[x].dst_apic_int == 0 &&
1363 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1364 io_apic_ints[x].int_vector == 0xff &&
1365 int_to_apicintpin[0].ioapic == -1 &&
1366 io_apic_ints[x].int_type == 3) {
1367 assign_apic_irq(0, 0, 0);
1371 /* PCI interrupt assignment is deferred */
1376 processor_entry(proc_entry_ptr entry, int cpu)
1378 /* check for usability */
1379 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1382 if(entry->apic_id >= NAPICID)
1383 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1384 /* check for BSP flag */
1385 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1386 boot_cpu_id = entry->apic_id;
1387 CPU_TO_ID(0) = entry->apic_id;
1388 ID_TO_CPU(entry->apic_id) = 0;
1389 return 0; /* its already been counted */
1392 /* add another AP to list, if less than max number of CPUs */
1393 else if (cpu < MAXCPU) {
1394 CPU_TO_ID(cpu) = entry->apic_id;
1395 ID_TO_CPU(entry->apic_id) = cpu;
1404 bus_entry(bus_entry_ptr entry, int bus)
1409 /* encode the name into an index */
1410 for (x = 0; x < 6; ++x) {
1411 if ((c = entry->bus_type[x]) == ' ')
1417 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1418 panic("unknown bus type: '%s'", name);
1420 bus_data[bus].bus_id = entry->bus_id;
1421 bus_data[bus].bus_type = x;
1428 io_apic_entry(io_apic_entry_ptr entry, int apic)
1430 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1433 IO_TO_ID(apic) = entry->apic_id;
1434 if (entry->apic_id < NAPICID)
1435 ID_TO_IO(entry->apic_id) = apic;
1442 lookup_bus_type(char *name)
1446 for (x = 0; x < MAX_BUSTYPE; ++x)
1447 if (strcmp(bus_type_table[x].name, name) == 0)
1448 return bus_type_table[x].type;
1450 return UNKNOWN_BUSTYPE;
1455 int_entry(int_entry_ptr entry, int intr)
1459 io_apic_ints[intr].int_type = entry->int_type;
1460 io_apic_ints[intr].int_flags = entry->int_flags;
1461 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1462 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1463 if (entry->dst_apic_id == 255) {
1464 /* This signal goes to all IO APICS. Select an IO APIC
1465 with sufficient number of interrupt pins */
1466 for (apic = 0; apic < mp_napics; apic++)
1467 if (((io_apic_read(apic, IOAPIC_VER) &
1468 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1469 entry->dst_apic_int)
1471 if (apic < mp_napics)
1472 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1474 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1476 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1477 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1484 apic_int_is_bus_type(int intr, int bus_type)
1488 for (bus = 0; bus < mp_nbusses; ++bus)
1489 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1490 && ((int) bus_data[bus].bus_type == bus_type))
1498 * Given a traditional ISA INT mask, return an APIC mask.
1501 isa_apic_mask(u_int isa_mask)
1506 #if defined(SKIP_IRQ15_REDIRECT)
1507 if (isa_mask == (1 << 15)) {
1508 printf("skipping ISA IRQ15 redirect\n");
1511 #endif /* SKIP_IRQ15_REDIRECT */
1513 isa_irq = ffs(isa_mask); /* find its bit position */
1514 if (isa_irq == 0) /* doesn't exist */
1516 --isa_irq; /* make it zero based */
1518 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1522 return (1 << apic_pin); /* convert pin# to a mask */
1527 * Determine which APIC pin an ISA/EISA INT is attached to.
1529 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1530 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1531 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1532 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1534 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1536 isa_apic_irq(int isa_irq)
1540 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1541 if (INTTYPE(intr) == 0) { /* standard INT */
1542 if (SRCBUSIRQ(intr) == isa_irq) {
1543 if (apic_int_is_bus_type(intr, ISA) ||
1544 apic_int_is_bus_type(intr, EISA)) {
1545 if (INTIRQ(intr) == 0xff)
1546 return -1; /* unassigned */
1547 return INTIRQ(intr); /* found */
1552 return -1; /* NOT found */
1557 * Determine which APIC pin a PCI INT is attached to.
1559 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1560 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1561 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1563 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1567 --pciInt; /* zero based */
1569 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1570 if ((INTTYPE(intr) == 0) /* standard INT */
1571 && (SRCBUSID(intr) == pciBus)
1572 && (SRCBUSDEVICE(intr) == pciDevice)
1573 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1574 if (apic_int_is_bus_type(intr, PCI)) {
1575 if (INTIRQ(intr) == 0xff)
1576 allocate_apic_irq(intr);
1577 if (INTIRQ(intr) == 0xff)
1578 return -1; /* unassigned */
1579 return INTIRQ(intr); /* exact match */
1582 return -1; /* NOT found */
1586 next_apic_irq(int irq)
1593 for (intr = 0; intr < nintrs; intr++) {
1594 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1596 bus = SRCBUSID(intr);
1597 bustype = apic_bus_type(bus);
1598 if (bustype != ISA &&
1604 if (intr >= nintrs) {
1607 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1608 if (INTTYPE(ointr) != 0)
1610 if (bus != SRCBUSID(ointr))
1612 if (bustype == PCI) {
1613 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1615 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1618 if (bustype == ISA || bustype == EISA) {
1619 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1622 if (INTPIN(intr) == INTPIN(ointr))
1626 if (ointr >= nintrs) {
1629 return INTIRQ(ointr);
1643 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1646 * Exactly what this means is unclear at this point. It is a solution
1647 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1648 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1649 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1653 undirect_isa_irq(int rirq)
1657 printf("Freeing redirected ISA irq %d.\n", rirq);
1658 /** FIXME: tickle the MB redirector chip */
1662 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1669 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1672 undirect_pci_irq(int rirq)
1676 printf("Freeing redirected PCI irq %d.\n", rirq);
1678 /** FIXME: tickle the MB redirector chip */
1682 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1690 * given a bus ID, return:
1691 * the bus type if found
1695 apic_bus_type(int id)
1699 for (x = 0; x < mp_nbusses; ++x)
1700 if (bus_data[x].bus_id == id)
1701 return bus_data[x].bus_type;
1708 * given a LOGICAL APIC# and pin#, return:
1709 * the associated src bus ID if found
1713 apic_src_bus_id(int apic, int pin)
1717 /* search each of the possible INTerrupt sources */
1718 for (x = 0; x < nintrs; ++x)
1719 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1720 (pin == io_apic_ints[x].dst_apic_int))
1721 return (io_apic_ints[x].src_bus_id);
1723 return -1; /* NOT found */
1728 * given a LOGICAL APIC# and pin#, return:
1729 * the associated src bus IRQ if found
1733 apic_src_bus_irq(int apic, int pin)
1737 for (x = 0; x < nintrs; x++)
1738 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1739 (pin == io_apic_ints[x].dst_apic_int))
1740 return (io_apic_ints[x].src_bus_irq);
1742 return -1; /* NOT found */
1747 * given a LOGICAL APIC# and pin#, return:
1748 * the associated INTerrupt type if found
1752 apic_int_type(int apic, int pin)
1756 /* search each of the possible INTerrupt sources */
1757 for (x = 0; x < nintrs; ++x)
1758 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1759 (pin == io_apic_ints[x].dst_apic_int))
1760 return (io_apic_ints[x].int_type);
1762 return -1; /* NOT found */
1766 apic_irq(int apic, int pin)
1771 for (x = 0; x < nintrs; ++x)
1772 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1773 (pin == io_apic_ints[x].dst_apic_int)) {
1774 res = io_apic_ints[x].int_vector;
1777 if (apic != int_to_apicintpin[res].ioapic)
1778 panic("apic_irq: inconsistent table");
1779 if (pin != int_to_apicintpin[res].int_pin)
1780 panic("apic_irq inconsistent table (2)");
1788 * given a LOGICAL APIC# and pin#, return:
1789 * the associated trigger mode if found
1793 apic_trigger(int apic, int pin)
1797 /* search each of the possible INTerrupt sources */
1798 for (x = 0; x < nintrs; ++x)
1799 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1800 (pin == io_apic_ints[x].dst_apic_int))
1801 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1803 return -1; /* NOT found */
1808 * given a LOGICAL APIC# and pin#, return:
1809 * the associated 'active' level if found
1813 apic_polarity(int apic, int pin)
1817 /* search each of the possible INTerrupt sources */
1818 for (x = 0; x < nintrs; ++x)
1819 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1820 (pin == io_apic_ints[x].dst_apic_int))
1821 return (io_apic_ints[x].int_flags & 0x03);
1823 return -1; /* NOT found */
1828 * set data according to MP defaults
1829 * FIXME: probably not complete yet...
1832 default_mp_table(int type)
1835 #if defined(APIC_IO)
1838 #endif /* APIC_IO */
1841 printf(" MP default config type: %d\n", type);
1844 printf(" bus: ISA, APIC: 82489DX\n");
1847 printf(" bus: EISA, APIC: 82489DX\n");
1850 printf(" bus: EISA, APIC: 82489DX\n");
1853 printf(" bus: MCA, APIC: 82489DX\n");
1856 printf(" bus: ISA+PCI, APIC: Integrated\n");
1859 printf(" bus: EISA+PCI, APIC: Integrated\n");
1862 printf(" bus: MCA+PCI, APIC: Integrated\n");
1865 printf(" future type\n");
1871 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1872 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1875 CPU_TO_ID(0) = boot_cpu_id;
1876 ID_TO_CPU(boot_cpu_id) = 0;
1878 /* one and only AP */
1879 CPU_TO_ID(1) = ap_cpu_id;
1880 ID_TO_CPU(ap_cpu_id) = 1;
1882 #if defined(APIC_IO)
1883 /* one and only IO APIC */
1884 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1887 * sanity check, refer to MP spec section 3.6.6, last paragraph
1888 * necessary as some hardware isn't properly setting up the IO APIC
1890 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1891 if (io_apic_id != 2) {
1893 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1894 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1895 io_apic_set_id(0, 2);
1898 IO_TO_ID(0) = io_apic_id;
1899 ID_TO_IO(io_apic_id) = 0;
1900 #endif /* APIC_IO */
1902 /* fill out bus entries */
1911 bus_data[0].bus_id = default_data[type - 1][1];
1912 bus_data[0].bus_type = default_data[type - 1][2];
1913 bus_data[1].bus_id = default_data[type - 1][3];
1914 bus_data[1].bus_type = default_data[type - 1][4];
1917 /* case 4: case 7: MCA NOT supported */
1918 default: /* illegal/reserved */
1919 panic("BAD default MP config: %d", type);
1923 #if defined(APIC_IO)
1924 /* general cases from MP v1.4, table 5-2 */
1925 for (pin = 0; pin < 16; ++pin) {
1926 io_apic_ints[pin].int_type = 0;
1927 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1928 io_apic_ints[pin].src_bus_id = 0;
1929 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1930 io_apic_ints[pin].dst_apic_id = io_apic_id;
1931 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1934 /* special cases from MP v1.4, table 5-2 */
1936 io_apic_ints[2].int_type = 0xff; /* N/C */
1937 io_apic_ints[13].int_type = 0xff; /* N/C */
1938 #if !defined(APIC_MIXED_MODE)
1940 panic("sorry, can't support type 2 default yet");
1941 #endif /* APIC_MIXED_MODE */
1944 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1947 io_apic_ints[0].int_type = 0xff; /* N/C */
1949 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1950 #endif /* APIC_IO */
1954 * start each AP in our list
1957 start_all_aps(u_int boot_addr)
1960 u_char mpbiosreason;
1961 u_long mpbioswarmvec;
1962 struct mdglobaldata *gd;
1963 struct privatespace *ps;
1967 POSTCODE(START_ALL_APS_POST);
1969 /* initialize BSP's local APIC */
1973 /* install the AP 1st level boot code */
1974 install_ap_tramp(boot_addr);
1977 /* save the current value of the warm-start vector */
1978 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1979 outb(CMOS_REG, BIOS_RESET);
1980 mpbiosreason = inb(CMOS_DATA);
1982 /* set up temporary P==V mapping for AP boot */
1983 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
1984 kptbase = (uintptr_t)(void *)KPTphys;
1985 for (x = 0; x < NKPT; x++) {
1986 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
1987 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
1992 for (x = 1; x <= mp_naps; ++x) {
1994 /* This is a bit verbose, it will go away soon. */
1996 /* first page of AP's private space */
1997 pg = x * i386_btop(sizeof(struct privatespace));
1999 /* allocate a new private data page */
2000 gd = (struct mdglobaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
2002 /* wire it into the private page table page */
2003 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys_pte(gd));
2005 /* allocate and set up an idle stack data page */
2006 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
2007 for (i = 0; i < UPAGES; i++) {
2008 SMPpt[pg + 5 + i] = (pt_entry_t)
2009 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2012 SMPpt[pg + 1] = 0; /* *gd_CMAP1 */
2013 SMPpt[pg + 2] = 0; /* *gd_CMAP2 */
2014 SMPpt[pg + 3] = 0; /* *gd_CMAP3 */
2015 SMPpt[pg + 4] = 0; /* *gd_PMAP1 */
2017 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2018 bzero(gd, sizeof(*gd));
2019 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2021 /* prime data page for it to use */
2022 mi_gdinit(&gd->mi, x);
2024 gd->gd_CMAP1 = &SMPpt[pg + 1];
2025 gd->gd_CMAP2 = &SMPpt[pg + 2];
2026 gd->gd_CMAP3 = &SMPpt[pg + 3];
2027 gd->gd_PMAP1 = &SMPpt[pg + 4];
2028 gd->gd_CADDR1 = ps->CPAGE1;
2029 gd->gd_CADDR2 = ps->CPAGE2;
2030 gd->gd_CADDR3 = ps->CPAGE3;
2031 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2032 gd->mi.gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2033 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2035 /* setup a vector to our boot code */
2036 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2037 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2038 outb(CMOS_REG, BIOS_RESET);
2039 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2042 * Setup the AP boot stack
2044 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2047 /* attempt to start the Application Processor */
2048 CHECK_INIT(99); /* setup checkpoints */
2049 if (!start_ap(gd, boot_addr)) {
2050 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2051 CHECK_PRINT("trace"); /* show checkpoints */
2052 /* better panic as the AP may be running loose */
2053 printf("panic y/n? [y] ");
2054 if (cngetc() != 'n')
2057 CHECK_PRINT("trace"); /* show checkpoints */
2059 /* record its version info */
2060 cpu_apic_versions[x] = cpu_apic_versions[0];
2063 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2066 /* round ncpus down to power of 2 */
2070 ncpus2 = 1 << ncpus2_shift;
2071 ncpus2_mask = ncpus2 - 1;
2073 /* build our map of 'other' CPUs */
2074 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2075 mycpu->gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * ncpus);
2076 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2078 /* fill in our (BSP) APIC version */
2079 cpu_apic_versions[0] = lapic.version;
2081 /* restore the warmstart vector */
2082 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2083 outb(CMOS_REG, BIOS_RESET);
2084 outb(CMOS_DATA, mpbiosreason);
2087 * NOTE! The idlestack for the BSP was setup by locore. Finish
2088 * up, clean out the P==V mapping we did earlier.
2090 for (x = 0; x < NKPT; x++)
2094 /* number of APs actually started */
2100 * load the 1st level AP boot code into base memory.
2103 /* targets for relocation */
2104 extern void bigJump(void);
2105 extern void bootCodeSeg(void);
2106 extern void bootDataSeg(void);
2107 extern void MPentry(void);
2108 extern u_int MP_GDT;
2109 extern u_int mp_gdtbase;
2112 install_ap_tramp(u_int boot_addr)
2115 int size = *(int *) ((u_long) & bootMP_size);
2116 u_char *src = (u_char *) ((u_long) bootMP);
2117 u_char *dst = (u_char *) boot_addr + KERNBASE;
2118 u_int boot_base = (u_int) bootMP;
2123 POSTCODE(INSTALL_AP_TRAMP_POST);
2125 for (x = 0; x < size; ++x)
2129 * modify addresses in code we just moved to basemem. unfortunately we
2130 * need fairly detailed info about mpboot.s for this to work. changes
2131 * to mpboot.s might require changes here.
2134 /* boot code is located in KERNEL space */
2135 dst = (u_char *) boot_addr + KERNBASE;
2137 /* modify the lgdt arg */
2138 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2139 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2141 /* modify the ljmp target for MPentry() */
2142 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2143 *dst32 = ((u_int) MPentry - KERNBASE);
2145 /* modify the target for boot code segment */
2146 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2147 dst8 = (u_int8_t *) (dst16 + 1);
2148 *dst16 = (u_int) boot_addr & 0xffff;
2149 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2151 /* modify the target for boot data segment */
2152 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2153 dst8 = (u_int8_t *) (dst16 + 1);
2154 *dst16 = (u_int) boot_addr & 0xffff;
2155 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2160 * this function starts the AP (application processor) identified
2161 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2162 * to accomplish this. This is necessary because of the nuances
2163 * of the different hardware we might encounter. It ain't pretty,
2164 * but it seems to work.
2166 * NOTE: eventually an AP gets to ap_init(), which is called just
2167 * before the AP goes into the LWKT scheduler's idle loop.
2170 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2174 u_long icr_lo, icr_hi;
2176 POSTCODE(START_AP_POST);
2178 /* get the PHYSICAL APIC ID# */
2179 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2181 /* calculate the vector */
2182 vector = (boot_addr >> 12) & 0xff;
2184 /* Make sure the target cpu sees everything */
2188 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2189 * and running the target CPU. OR this INIT IPI might be latched (P5
2190 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2194 /* setup the address for the target AP */
2195 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2196 icr_hi |= (physical_cpu << 24);
2197 lapic.icr_hi = icr_hi;
2199 /* do an INIT IPI: assert RESET */
2200 icr_lo = lapic.icr_lo & 0xfff00000;
2201 lapic.icr_lo = icr_lo | 0x0000c500;
2203 /* wait for pending status end */
2204 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2207 /* do an INIT IPI: deassert RESET */
2208 lapic.icr_lo = icr_lo | 0x00008500;
2210 /* wait for pending status end */
2211 u_sleep(10000); /* wait ~10mS */
2212 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2216 * next we do a STARTUP IPI: the previous INIT IPI might still be
2217 * latched, (P5 bug) this 1st STARTUP would then terminate
2218 * immediately, and the previously started INIT IPI would continue. OR
2219 * the previous INIT IPI has already run. and this STARTUP IPI will
2220 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2224 /* do a STARTUP IPI */
2225 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2226 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2228 u_sleep(200); /* wait ~200uS */
2231 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2232 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2233 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2234 * recognized after hardware RESET or INIT IPI.
2237 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2238 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2240 u_sleep(200); /* wait ~200uS */
2242 /* wait for it to start, see ap_init() */
2243 set_apic_timer(5000000);/* == 5 seconds */
2244 while (read_apic_timer()) {
2245 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2246 return 1; /* return SUCCESS */
2248 return 0; /* return FAILURE */
2253 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2255 * If for some reason we were unable to start all cpus we cannot safely
2256 * use broadcast IPIs.
2261 #if defined(APIC_IO)
2262 if (smp_startup_mask == smp_active_mask) {
2263 all_but_self_ipi(XINVLTLB_OFFSET);
2265 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2266 APIC_DELMODE_FIXED);
2268 #endif /* APIC_IO */
2272 * When called the executing CPU will send an IPI to all other CPUs
2273 * requesting that they halt execution.
2275 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2277 * - Signals all CPUs in map to stop.
2278 * - Waits for each to stop.
2285 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2286 * from executing at same time.
2289 stop_cpus(u_int map)
2291 map &= smp_active_mask;
2293 /* send the Xcpustop IPI to all CPUs in map */
2294 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2296 while ((stopped_cpus & map) != map)
2304 * Called by a CPU to restart stopped CPUs.
2306 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2308 * - Signals all CPUs in map to restart.
2309 * - Waits for each to restart.
2317 restart_cpus(u_int map)
2319 /* signal other cpus to restart */
2320 started_cpus = map & smp_active_mask;
2322 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2329 * This is called once the mpboot code has gotten us properly relocated
2330 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2331 * and when it returns the scheduler will call the real cpu_idle() main
2332 * loop for the idlethread. Interrupts are disabled on entry and should
2333 * remain disabled at return.
2341 * Adjust smp_startup_mask to signal the BSP that we have started
2342 * up successfully. Note that we do not yet hold the BGL. The BSP
2343 * is waiting for our signal.
2345 * We can't set our bit in smp_active_mask yet because we are holding
2346 * interrupts physically disabled and remote cpus could deadlock
2347 * trying to send us an IPI.
2349 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2353 * Interlock for finalization. Wait until mp_finish is non-zero,
2354 * then get the MP lock.
2356 * Note: We are in a critical section.
2358 * Note: We have to synchronize td_mpcount to our desired MP state
2359 * before calling cpu_try_mplock().
2361 * Note: we are the idle thread, we can only spin.
2363 * Note: The load fence is memory volatile and prevents the compiler
2364 * from improperly caching mp_finish, and the cpu from improperly
2367 while (mp_finish == 0)
2369 ++curthread->td_mpcount;
2370 while (cpu_try_mplock() == 0)
2373 /* BSP may have changed PTD while we're waiting for the lock */
2376 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2380 /* Build our map of 'other' CPUs. */
2381 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2383 printf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2385 /* A quick check from sanity claus */
2386 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2387 if (mycpu->gd_cpuid != apic_id) {
2388 printf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2389 printf("SMP: apic_id = %d\n", apic_id);
2390 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2391 panic("cpuid mismatch! boom!!");
2394 /* Init local apic for irq's */
2397 /* Set memory range attributes for this CPU to match the BSP */
2398 mem_range_AP_init();
2401 * Once we go active we must process any IPIQ messages that may
2402 * have been queued, because no actual IPI will occur until we
2403 * set our bit in the smp_active_mask. If we don't the IPI
2404 * message interlock could be left set which would also prevent
2407 * The idle loop doesn't expect the BGL to be held and while
2408 * lwkt_switch() normally cleans things up this is a special case
2409 * because we returning almost directly into the idle loop.
2411 * The idle thread is never placed on the runq, make sure
2412 * nothing we've done put it there.
2414 KKASSERT(curthread->td_mpcount == 1);
2415 smp_active_mask |= 1 << mycpu->gd_cpuid;
2416 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2417 lwkt_process_ipiq();
2419 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2423 * Get SMP fully working before we start initializing devices.
2431 printf("Finish MP startup\n");
2433 while (smp_active_mask != smp_startup_mask)
2435 while (try_mplock() == 0)
2438 printf("Active CPU Mask: %08x\n", smp_active_mask);
2441 SYSINIT(finishsmp, SI_SUB_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2443 #if defined(APIC_IO) && defined(APIC_INTR_REORDER)
2445 * Maintain mapping from softintr vector to isr bit in local apic.
2448 set_lapic_isrloc(int intr, int vector)
2450 if (intr < 0 || intr > 32)
2451 panic("set_apic_isrloc: bad intr argument: %d",intr);
2452 if (vector < ICU_OFFSET || vector > 255)
2453 panic("set_apic_isrloc: bad vector argument: %d",vector);
2454 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2455 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2460 cpu_send_ipiq(int dcpu)
2462 if ((1 << dcpu) & smp_active_mask)
2463 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2466 #if 0 /* single_apic_ipi_passive() not working yet */
2468 * Returns 0 on failure, 1 on success
2471 cpu_send_ipiq_passive(int dcpu)
2474 if ((1 << dcpu) & smp_active_mask) {
2475 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2476 APIC_DELMODE_FIXED);