2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-dma.c,v 1.35.2.31 2003/05/07 16:46:11 jhb Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-dma.c,v 1.15 2004/02/18 04:08:49 dillon Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/mpipe.h>
40 #include <sys/devicestat.h>
43 #include <bus/pci/pcivar.h>
44 #include <machine/bus.h>
49 static void cyrix_timing(struct ata_device *, int, int);
50 static void promise_timing(struct ata_device *, int, int);
51 static void hpt_timing(struct ata_device *, int, int);
52 static int hpt_cable80(struct ata_device *);
57 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
59 #define ATAPI_DEVICE(atadev) \
60 ((atadev->unit == ATA_MASTER && \
61 atadev->channel->devices & ATA_ATAPI_MASTER) || \
62 (atadev->unit == ATA_SLAVE && \
63 atadev->channel->devices & ATA_ATAPI_SLAVE))
66 ata_dmaalloc(struct ata_device *atadev, int flags)
68 struct ata_channel *ch = atadev->channel;
70 KKASSERT(ch->dma_mpipe.max_count != 0);
71 atadev->dmastate.dmatab = mpipe_alloc(&ch->dma_mpipe, flags);
72 KKASSERT(((uintptr_t)atadev->dmastate.dmatab & PAGE_MASK) == 0);
73 if (atadev->dmastate.dmatab)
79 ata_dmafree(struct ata_device *atadev)
81 struct ata_channel *ch = atadev->channel;
83 if (atadev->dmastate.dmatab) {
84 mpipe_free(&ch->dma_mpipe, atadev->dmastate.dmatab);
85 atadev->dmastate.dmatab = NULL;
90 ata_dmafreetags(struct ata_channel *ch)
95 ata_dmacreate(struct ata_device *atadev, int apiomode, int mode)
101 ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode)
103 device_t parent = device_get_parent(atadev->channel->dev);
104 int chiptype = atadev->channel->chiptype;
105 int chiprev = pci_get_revid(parent);
106 int channel = atadev->channel->unit;
107 int device = ATA_DEV(atadev->unit);
108 int devno = (channel << 1) + device;
111 /* set our most pessimistic default mode */
112 atadev->mode = ATA_PIO;
114 if (!atadev->channel->r_bmio)
117 /* if simplex controller, only allow DMA on primary channel */
119 ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT,
120 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
121 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
122 if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
123 ATA_BMSTAT_DMA_SIMPLEX) {
124 ata_prtdev(atadev, "simplex device, DMA on primary only\n");
129 /* DMA engine address alignment is usually 1 word (2 bytes) */
130 atadev->channel->alignment = 0x1;
133 if (udmamode > 2 && !atadev->param->hwres_cblid) {
134 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
140 case 0x24db8086: /* Intel ICH5 */
141 case 0x24d18086: /* Intel ICH5 SATA */
142 case 0x24ca8086: /* Intel ICH4 mobile */
143 case 0x24cb8086: /* Intel ICH4 */
144 case 0x248a8086: /* Intel ICH3 mobile */
145 case 0x248b8086: /* Intel ICH3 */
146 case 0x244a8086: /* Intel ICH2 mobile */
147 case 0x244b8086: /* Intel ICH2 */
149 int32_t mask48, new48;
152 word54 = pci_read_config(parent, 0x54, 2);
153 if (word54 & (0x10 << devno)) {
154 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
155 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
157 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
158 (error) ? "failed" : "success");
160 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
161 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
162 pci_write_config(parent, 0x48,
163 (pci_read_config(parent, 0x48, 4) &
164 ~mask48) | new48, 4);
165 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
166 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
171 /* make sure eventual ATA100 mode from the BIOS is disabled */
172 pci_write_config(parent, 0x54,
173 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
176 case 0x24118086: /* Intel ICH */
177 case 0x76018086: /* Intel ICH */
179 int32_t mask48, new48;
182 word54 = pci_read_config(parent, 0x54, 2);
183 if (word54 & (0x10 << devno)) {
184 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
185 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
187 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
188 (error) ? "failed" : "success");
190 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
191 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
192 pci_write_config(parent, 0x48,
193 (pci_read_config(parent, 0x48, 4) &
194 ~mask48) | new48, 4);
195 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
196 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
201 /* make sure eventual ATA66 mode from the BIOS is disabled */
202 pci_write_config(parent, 0x54,
203 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
206 case 0x71118086: /* Intel PIIX4 */
207 case 0x84CA8086: /* Intel PIIX4 */
208 case 0x71998086: /* Intel PIIX4e */
209 case 0x24218086: /* Intel ICH0 */
211 int32_t mask48, new48;
213 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
214 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
216 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
217 (error) ? "failed" : "success");
219 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
220 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
221 pci_write_config(parent, 0x48,
222 (pci_read_config(parent, 0x48, 4) &
223 ~mask48) | new48, 4);
224 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
228 /* make sure eventual ATA33 mode from the BIOS is disabled */
229 pci_write_config(parent, 0x48,
230 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
233 case 0x70108086: /* Intel PIIX3 */
234 if (wdmamode >= 2 && apiomode >= 4) {
235 int32_t mask40, new40, mask44, new44;
237 /* if SITRE not set doit for both channels */
238 if (!((pci_read_config(parent,0x40,4)>>(channel<<8))&0x4000)) {
239 new40 = pci_read_config(parent, 0x40, 4);
240 new44 = pci_read_config(parent, 0x44, 4);
241 if (!(new40 & 0x00004000)) {
242 new44 &= ~0x0000000f;
243 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
245 if (!(new40 & 0x40000000)) {
246 new44 &= ~0x000000f0;
247 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
250 pci_write_config(parent, 0x40, new40, 4);
251 pci_write_config(parent, 0x44, new44, 4);
253 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
254 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
256 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
257 (error) ? "failed" : "success");
259 if (device == ATA_MASTER) {
277 pci_write_config(parent, 0x40,
278 (pci_read_config(parent, 0x40, 4) & ~mask40)|
280 pci_write_config(parent, 0x44,
281 (pci_read_config(parent, 0x44, 4) & ~mask44)|
283 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
287 /* we could set PIO mode timings, but we assume the BIOS did that */
290 case 0x12308086: /* Intel PIIX */
291 if (wdmamode >= 2 && apiomode >= 4) {
294 word40 = pci_read_config(parent, 0x40, 4);
295 word40 >>= channel * 16;
297 /* Check for timing config usable for DMA on controller */
298 if (!((word40 & 0x3300) == 0x2300 &&
299 ((word40 >> (device ? 4 : 0)) & 1) == 1))
302 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
303 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
305 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
306 (error) ? "failed" : "success");
308 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
314 case 0x522910b9: /* AcerLabs Aladdin IV/V */
315 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
316 if (chiprev < 0xc2 &&
317 atadev->channel->devices & ATA_ATAPI_MASTER &&
318 atadev->channel->devices & ATA_ATAPI_SLAVE) {
319 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
322 #if !defined(NO_ATANG)
323 pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4);
325 if (udmamode >= 5 && chiprev >= 0xc4) {
326 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
327 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
329 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
330 (error) ? "failed" : "success");
332 int32_t word54 = pci_read_config(parent, 0x54, 4);
334 pci_write_config(parent, 0x4b,
335 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
336 word54 &= ~(0x000f000f << (devno << 2));
337 word54 |= (0x000f0005 << (devno << 2));
338 pci_write_config(parent, 0x54, word54, 4);
339 pci_write_config(parent, 0x53,
340 pci_read_config(parent, 0x53, 1) | 0x03, 1);
341 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
345 if (udmamode >= 4 && chiprev >= 0xc2) {
346 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
347 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
349 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
350 (error) ? "failed" : "success");
352 int32_t word54 = pci_read_config(parent, 0x54, 4);
354 pci_write_config(parent, 0x4b,
355 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
356 word54 &= ~(0x000f000f << (devno << 2));
357 word54 |= (0x00080005 << (devno << 2));
358 pci_write_config(parent, 0x54, word54, 4);
359 pci_write_config(parent, 0x53,
360 pci_read_config(parent, 0x53, 1) | 0x03, 1);
361 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
365 if (udmamode >= 2 && chiprev >= 0x20) {
366 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
367 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
369 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
370 (error) ? "failed" : "success");
372 int32_t word54 = pci_read_config(parent, 0x54, 4);
374 word54 &= ~(0x000f000f << (devno << 2));
375 word54 |= (0x000a0005 << (devno << 2));
376 pci_write_config(parent, 0x54, word54, 4);
377 pci_write_config(parent, 0x53,
378 pci_read_config(parent, 0x53, 1) | 0x03, 1);
379 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
380 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
385 /* make sure eventual UDMA mode from the BIOS is disabled */
386 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
387 ~(0x0008 << (devno << 2)), 2);
389 if (wdmamode >= 2 && apiomode >= 4) {
390 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
391 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
393 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
394 (error) ? "failed" : "success");
396 pci_write_config(parent, 0x53,
397 pci_read_config(parent, 0x53, 1) | 0x03, 1);
398 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
399 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
403 pci_write_config(parent, 0x53,
404 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
405 #if !defined(NO_ATANG)
406 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
408 ATA_C_F_SETXFER, ATA_WAIT_READY);
410 ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n",
411 (error) ? "failed" : "success",
412 (apiomode >= 0) ? apiomode : 0);
414 int32_t word54 = pci_read_config(parent, 0x54, 4);
417 switch(ATA_PIO0 + apiomode) {
418 case ATA_PIO0: timing = 0x006d0003; break;
419 case ATA_PIO1: timing = 0x00580002; break;
420 case ATA_PIO2: timing = 0x00440001; break;
421 case ATA_PIO3: timing = 0x00330001; break;
422 case ATA_PIO4: timing = 0x00310001; break;
423 default: timing = 0x006d0003; break;
425 pci_write_config(parent, 0x58 + (channel << 2), timing, 4);
426 word54 &= ~(0x000f000f << (devno << 2));
427 word54 |= (0x00000004 << (devno << 2));
428 pci_write_config(parent, 0x54, word54, 4);
429 atadev->mode = ATA_PIO0 + apiomode;
435 case 0x31491106: /* VIA 8237 SATA part */
437 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
439 ATA_C_F_SETXFER, ATA_WAIT_READY);
441 ata_prtdev(atadev, "%s setting UDMA%d on VIA chip\n",
442 (error) ? "failed" : "success", udmamode);
444 ata_dmacreate(atadev, apiomode, ATA_UDMA + udmamode);
448 /* we could set PIO mode timings, but we assume the BIOS did that */
451 case 0x01bc10de: /* NVIDIA nForce */
452 case 0x006510de: /* NVIDIA nForce2 */
453 case 0x74691022: /* AMD 8111 */
454 case 0x74411022: /* AMD 768 */
455 case 0x74111022: /* AMD 766 */
456 case 0x74091022: /* AMD 756 */
457 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */
459 int via_modes[5][7] = {
460 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
461 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
462 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
463 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
464 { 0x00, 0x00, 0xc0, 0x00, 0xc5, 0xc6, 0xc7 }}; /* AMD/NVIDIA */
469 if (ata_find_dev(parent, 0x31471106, 0) || /* 8233a */
470 ata_find_dev(parent, 0x31771106, 0) || /* 8235 */
471 ata_find_dev(parent, 0x31491106, 0)) { /* 8237 */
472 udmamode = imin(udmamode, 6);
473 reg_val = via_modes[3];
475 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */
476 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */
477 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */
478 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */
479 udmamode = imin(udmamode, 5);
480 reg_val = via_modes[2];
482 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */
483 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
484 udmamode = imin(udmamode, 4);
485 reg_val = via_modes[1];
487 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */
488 udmamode = imin(udmamode, 2);
489 reg_val = via_modes[1];
491 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
492 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
493 udmamode = imin(udmamode, 2);
494 reg_val = via_modes[0];
496 else if (chiptype == 0x74691022 || /* AMD 8111 */
497 chiptype == 0x74411022 || /* AMD 768 */
498 chiptype == 0x74111022) { /* AMD 766 */
499 udmamode = imin(udmamode, 5);
500 reg_val = via_modes[4];
503 else if (chiptype == 0x74091022) { /* AMD 756 */
504 udmamode = imin(udmamode, 4);
505 reg_val = via_modes[4];
508 else if (chiptype == 0x01bc10de) { /* nForce */
509 udmamode = imin(udmamode, 5);
510 reg_val = via_modes[4];
511 #if !defined(NO_ATANG)
516 else if (chiptype == 0x006510de) { /* nForce2 */
517 udmamode = imin(udmamode, 6);
518 reg_val = via_modes[4];
519 #if !defined(NO_ATANG)
528 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
529 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
531 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n",
532 (error) ? "failed" : "success", chip);
534 pci_write_config(parent, reg_off - devno, reg_val[6], 1);
535 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
540 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
541 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
543 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n",
544 (error) ? "failed" : "success", chip);
546 pci_write_config(parent, reg_off - devno, reg_val[5], 1);
547 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
552 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
553 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
555 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n",
556 (error) ? "failed" : "success", chip);
558 pci_write_config(parent, reg_off - devno, reg_val[4], 1);
559 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
564 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
565 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
567 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n",
568 (error) ? "failed" : "success", chip);
570 pci_write_config(parent, reg_off - devno, reg_val[2], 1);
571 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
575 if (wdmamode >= 2 && apiomode >= 4) {
576 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
577 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
579 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
580 (error) ? "failed" : "success", chip);
582 pci_write_config(parent, reg_off - devno, 0x0b, 1);
583 pci_write_config(parent, (reg_off - 8) - devno, 0x31, 1);
584 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
589 /* we could set PIO mode timings, but we assume the BIOS did that */
592 case 0x55131039: /* SiS 5591 */
593 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
594 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */
595 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */
596 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */
597 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */
598 ata_find_dev(parent, 0x06461039, 0) || /* SiS 645DX */
599 ata_find_dev(parent, 0x06481039, 0) || /* SiS 648 */
600 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */
601 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */
602 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */
603 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */
604 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */
605 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */
606 ata_find_dev(parent, 0x07461039, 0) || /* SiS 746 */
607 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */
608 int8_t reg = 0x40 + (devno << 1);
609 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
612 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
613 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
615 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
616 (error) ? "failed" : "success");
618 pci_write_config(parent, reg, val | 0x8000, 2);
619 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
624 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
625 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
627 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
628 (error) ? "failed" : "success");
630 pci_write_config(parent, reg, val | 0x9000, 2);
631 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
636 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
637 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
639 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
640 (error) ? "failed" : "success");
642 pci_write_config(parent, reg, val | 0xb000, 2);
643 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
647 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
648 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
649 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
650 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
651 int8_t reg = 0x40 + (devno << 1);
652 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
655 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
656 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
658 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
659 (error) ? "failed" : "success");
661 pci_write_config(parent, reg, val | 0x9000, 2);
662 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
667 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
668 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
670 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
671 (error) ? "failed" : "success");
673 pci_write_config(parent, reg, val | 0xa000, 2);
674 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
678 } else if (udmamode >= 2 && chiprev > 0xc1) {
679 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
680 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
682 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
683 (error) ? "failed" : "success");
685 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
686 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
690 if (wdmamode >=2 && apiomode >= 4) {
691 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
692 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
694 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
695 (error) ? "failed" : "success");
697 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
698 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
702 /* we could set PIO mode timings, but we assume the BIOS did that */
705 case 0x06801095: /* SiI 0680 ATA133 controller */
707 u_int8_t ureg = 0xac + (device * 0x02) + (channel * 0x10);
708 u_int8_t uval = pci_read_config(parent, ureg, 1);
709 u_int8_t mreg = channel ? 0x84 : 0x80;
710 u_int8_t mask = device ? 0x30 : 0x03;
711 u_int8_t mode = pci_read_config(parent, mreg, 1);
713 /* enable UDMA mode */
714 pci_write_config(parent, mreg,
715 (mode & ~mask) | (device ? 0x30 : 0x03), 1);
717 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
718 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
720 ata_prtdev(atadev, "%s setting UDMA6 on SiI chip\n",
721 (error) ? "failed" : "success");
723 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x01, 1);
724 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
729 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
730 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
732 ata_prtdev(atadev, "%s setting UDMA5 on SiI chip\n",
733 (error) ? "failed" : "success");
735 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x02, 1);
736 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
741 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
742 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
744 ata_prtdev(atadev, "%s setting UDMA4 on SiI chip\n",
745 (error) ? "failed" : "success");
747 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x03, 1);
748 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
753 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
754 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
756 ata_prtdev(atadev, "%s setting UDMA2 on SiI chip\n",
757 (error) ? "failed" : "success");
759 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x07, 1);
760 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
765 /* disable UDMA mode and enable WDMA mode */
766 pci_write_config(parent, mreg,
767 (mode & ~mask) | (device ? 0x20 : 0x02), 1);
768 if (wdmamode >= 2 && apiomode >= 4) {
769 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
770 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
772 ata_prtdev(atadev, "%s setting WDMA2 on SiI chip\n",
773 (error) ? "failed" : "success");
775 pci_write_config(parent, ureg - 0x4, 0x10c1, 2);
776 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
781 /* restore PIO mode */
782 pci_write_config(parent, mreg, mode, 1);
784 /* we could set PIO mode timings, but we assume the BIOS did that */
787 case 0x06491095: /* CMD 649 ATA100 controller */
791 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
792 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
794 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
795 (error) ? "failed" : "success");
797 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
798 umode &= ~(device ? 0xca : 0x35);
799 umode |= (device ? 0x0a : 0x05);
800 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
801 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
807 case 0x06481095: /* CMD 648 ATA66 controller */
811 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
812 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
814 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
815 (error) ? "failed" : "success");
817 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
818 umode &= ~(device ? 0xca : 0x35);
819 umode |= (device ? 0x4a : 0x15);
820 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
821 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
828 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
829 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
831 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
832 (error) ? "failed" : "success");
834 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
835 umode &= ~(device ? 0xca : 0x35);
836 umode |= (device ? 0x42 : 0x11);
837 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
838 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
842 /* make sure eventual UDMA mode from the BIOS is disabled */
843 pci_write_config(parent, channel ? 0x7b : 0x73,
844 pci_read_config(parent, channel ? 0x7b : 0x73, 1)&
845 #if !defined(NO_ATANG)
846 ~(device ? 0xca : 0x53), 1);
848 ~(device ? 0xca : 0x35), 1);
852 case 0x06461095: /* CMD 646 ATA controller */
853 if (wdmamode >= 2 && apiomode >= 4) {
854 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
855 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
857 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
858 error ? "failed" : "success");
860 int32_t offset = (devno < 3) ? (devno << 1) : 7;
862 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
863 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
867 /* we could set PIO mode timings, but we assume the BIOS did that */
870 case 0xc6931080: /* Cypress 82c693 ATA controller */
871 if (wdmamode >= 2 && apiomode >= 4) {
872 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
873 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
875 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
876 error ? "failed" : "success");
878 pci_write_config(atadev->channel->dev,
879 channel ? 0x4e:0x4c, 0x2020, 2);
880 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
884 /* we could set PIO mode timings, but we assume the BIOS did that */
887 case 0x01021078: /* Cyrix 5530 ATA33 controller */
888 atadev->channel->alignment = 0xf; /* DMA engine requires 16 byte alignment */
890 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
891 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
893 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
894 (error) ? "failed" : "success");
896 cyrix_timing(atadev, devno, ATA_UDMA2);
897 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
901 if (wdmamode >= 2 && apiomode >= 4) {
902 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
903 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
905 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
906 (error) ? "failed" : "success");
908 cyrix_timing(atadev, devno, ATA_WDMA2);
909 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
913 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
914 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
917 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
918 (error) ? "failed" : "success",
919 ata_mode2str(ATA_PIO0 + apiomode));
920 cyrix_timing(atadev, devno, ATA_PIO0 + apiomode);
921 atadev->mode = ATA_PIO0 + apiomode;
924 #if !defined(NO_ATANG)
925 case 0x02131166: /* ServerWorks CSB6 ATA 100 controller (chan 0+1) */
927 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */
928 #if !defined(NO_ATANG)
929 if (udmamode >= 5 && (chiptype == 0x02131166 ||
930 (chiptype == 0x02121166 &&
933 if (udmamode >= 5 && chiprev >= 0x92) {
935 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
936 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
938 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
939 (error) ? "failed" : "success");
943 pci_write_config(parent, 0x54,
944 pci_read_config(parent, 0x54, 1) |
946 reg56 = pci_read_config(parent, 0x56, 2);
947 reg56 &= ~(0xf << (devno * 4));
948 reg56 |= (0x5 << (devno * 4));
949 pci_write_config(parent, 0x56, reg56, 2);
950 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
954 #if !defined(NO_ATANG)
956 case 0x02171166: /* Server Works CSB6 ATA 66 controller chan 2 */
959 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
960 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
962 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
963 (error) ? "failed" : "success");
967 pci_write_config(parent, 0x54,
968 pci_read_config(parent, 0x54, 1) |
970 reg56 = pci_read_config(parent, 0x56, 2);
971 reg56 &= ~(0xf << (devno * 4));
972 reg56 |= (0x4 << (devno * 4));
973 pci_write_config(parent, 0x56, reg56, 2);
974 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
980 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
982 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
983 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
985 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
986 (error) ? "failed" : "success");
990 pci_write_config(parent, 0x54,
991 pci_read_config(parent, 0x54, 1) |
993 reg56 = pci_read_config(parent, 0x56, 2);
994 reg56 &= ~(0xf << (devno * 4));
995 reg56 |= (0x2 << (devno * 4));
996 pci_write_config(parent, 0x56, reg56, 2);
997 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1001 if (wdmamode >= 2 && apiomode >= 4) {
1002 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1003 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1005 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
1006 (error) ? "failed" : "success");
1008 int offset = devno ^ 0x01; /* (chan*2) + (dev==ATA_MASTER)*/
1009 int word44 = pci_read_config(parent, 0x44, 4);
1011 pci_write_config(parent, 0x54,
1012 pci_read_config(parent, 0x54, 1) &
1013 ~(0x01 << devno), 1);
1014 word44 &= ~(0xff << (offset << 8));
1015 word44 |= (0x20 << (offset << 8));
1016 pci_write_config(parent, 0x44, 0x20, 4);
1017 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1021 /* we could set PIO mode timings, but we assume the BIOS did that */
1024 case 0x4d69105a: /* Promise TX2 ATA133 controllers */
1025 case 0x5275105a: /* Promise TX2 ATA133 controllers */
1026 case 0x6269105a: /* Promise TX2 ATA133 controllers */
1027 case 0x7275105a: /* Promise TX2 ATA133 controllers */
1028 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1029 if (udmamode >= 6 &&
1030 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1031 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1032 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1034 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
1035 (error) ? "failed" : "success");
1037 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1043 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
1044 case 0x6268105a: /* Promise TX2 ATA100 controllers */
1045 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1046 if (udmamode >= 5 &&
1047 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1048 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1049 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1051 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1052 (error) ? "failed" : "success");
1054 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1058 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1059 if (udmamode >= 4 &&
1060 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1061 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1062 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1064 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1065 (error) ? "failed" : "success");
1067 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1071 if (udmamode >= 2) {
1072 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1073 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1075 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
1076 (error) ? "failed" : "success");
1078 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1082 if (wdmamode >= 2 && apiomode >= 4) {
1083 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1084 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1086 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1087 (error) ? "failed" : "success");
1089 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1095 case 0x0d30105a: /* Promise OEM ATA100 controllers */
1096 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
1097 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 &&
1098 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1099 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1100 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1102 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1103 (error) ? "failed" : "success");
1105 promise_timing(atadev, devno, ATA_UDMA5);
1106 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1112 case 0x0d38105a: /* Promise FastTrak 66 controllers */
1113 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
1114 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 &&
1115 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1116 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1117 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1119 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1120 (error) ? "failed" : "success");
1122 promise_timing(atadev, devno, ATA_UDMA4);
1123 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1129 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
1130 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1131 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1132 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1134 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
1135 (error) ? "failed" : "success");
1137 promise_timing(atadev, devno, ATA_UDMA2);
1138 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1142 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1143 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1144 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1146 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1147 (error) ? "failed" : "success");
1149 promise_timing(atadev, devno, ATA_WDMA2);
1150 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1154 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1155 ATA_PIO0 + apiomode,
1156 ATA_C_F_SETXFER, ATA_WAIT_READY);
1158 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
1159 (error) ? "failed" : "success",
1160 (apiomode >= 0) ? apiomode : 0);
1161 promise_timing(atadev, devno, ATA_PIO0 + apiomode);
1162 atadev->mode = ATA_PIO0 + apiomode;
1165 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
1166 case 0x00051103: /* HighPoint HPT372 controllers */
1167 case 0x00081103: /* HighPoint HPT374 controllers */
1168 if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) &&
1169 ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1170 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1171 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1172 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1173 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1175 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
1176 (error) ? "failed" : "success");
1178 hpt_timing(atadev, devno, ATA_UDMA6);
1179 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1183 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) &&
1184 ((chiptype == 0x00041103 && chiprev >= 0x03) ||
1185 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1186 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1187 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1188 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1190 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
1191 (error) ? "failed" : "success");
1193 hpt_timing(atadev, devno, ATA_UDMA5);
1194 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1198 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) {
1199 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1200 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1202 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
1203 (error) ? "failed" : "success");
1205 hpt_timing(atadev, devno, ATA_UDMA4);
1206 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1210 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1211 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1212 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1214 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
1215 (error) ? "failed" : "success");
1217 hpt_timing(atadev, devno, ATA_UDMA2);
1218 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1222 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1223 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1224 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1226 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
1227 (error) ? "failed" : "success");
1229 hpt_timing(atadev, devno, ATA_WDMA2);
1230 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1234 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1235 ATA_PIO0 + apiomode,
1236 ATA_C_F_SETXFER, ATA_WAIT_READY);
1238 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
1239 (error) ? "failed" : "success",
1240 (apiomode >= 0) ? apiomode : 0);
1241 hpt_timing(atadev, devno, ATA_PIO0 + apiomode);
1242 atadev->mode = ATA_PIO0 + apiomode;
1245 case 0x000116ca: /* Cenatek Rocket Drive controller */
1246 if (wdmamode >= 0 &&
1247 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1248 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER)))
1249 ata_dmacreate(atadev, apiomode, ATA_DMA);
1251 atadev->mode = ATA_PIO;
1254 default: /* unknown controller chip */
1255 /* better not try generic DMA on ATAPI devices it almost never works */
1256 if (ATAPI_DEVICE(atadev))
1259 /* if controller says its setup for DMA take the easy way out */
1260 /* the downside is we dont know what DMA mode we are in */
1261 if ((udmamode >= 0 || wdmamode >= 2) &&
1262 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1263 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) {
1264 ata_dmacreate(atadev, apiomode, ATA_DMA);
1268 /* well, we have no support for this, but try anyways */
1269 if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) {
1270 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1271 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1273 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
1274 (error) ? "failed" : "success");
1276 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1281 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1282 ATA_C_F_SETXFER, ATA_WAIT_READY);
1284 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
1285 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1287 atadev->mode = ATA_PIO0 + apiomode;
1290 ata_prtdev(atadev, "using PIO mode set by BIOS\n");
1291 atadev->mode = ATA_PIO;
1296 ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count)
1298 struct ata_channel *ch = atadev->channel;
1299 struct ata_dmastate *ds = &atadev->dmastate;
1300 u_int32_t dma_count, dma_base;
1303 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
1304 ata_prtdev(atadev, "non aligned DMA transfer attempted\n");
1309 ata_prtdev(atadev, "zero length DMA transfer attempted\n");
1313 dma_base = vtophys(data);
1314 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1319 ds->dmatab[i].base = dma_base;
1320 ds->dmatab[i].count = (dma_count & 0xffff);
1322 if (i >= ATA_DMA_ENTRIES) {
1323 ata_prtdev(atadev, "too many segments in DMA table\n");
1326 dma_base = vtophys(data);
1327 dma_count = imin(count, PAGE_SIZE);
1328 data += imin(count, PAGE_SIZE);
1329 count -= imin(count, PAGE_SIZE);
1331 ds->dmatab[i].base = dma_base;
1332 ds->dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1337 ata_dmastart(struct ata_device *atadev, caddr_t data, int32_t count, int dir)
1339 struct ata_channel *ch = atadev->channel;
1340 struct ata_dmastate *ds = &atadev->dmastate;
1342 ch->flags |= ATA_DMA_ACTIVE;
1343 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(ds->dmatab));
1344 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1345 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1346 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1347 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1348 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1349 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1354 ata_dmadone(struct ata_device *atadev)
1356 struct ata_channel *ch;
1357 struct ata_dmastate *ds;
1360 ch = atadev->channel;
1361 ds = &atadev->dmastate;
1363 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1364 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1365 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1366 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1367 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1368 ch->flags &= ~ATA_DMA_ACTIVE;
1370 return error & ATA_BMSTAT_MASK;
1374 ata_dmastatus(struct ata_channel *ch)
1376 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1380 cyrix_timing(struct ata_device *atadev, int devno, int mode)
1382 u_int32_t reg20 = 0x0000e132;
1383 u_int32_t reg24 = 0x00017771;
1386 case ATA_PIO0: reg20 = 0x0000e132; break;
1387 case ATA_PIO1: reg20 = 0x00018121; break;
1388 case ATA_PIO2: reg20 = 0x00024020; break;
1389 case ATA_PIO3: reg20 = 0x00032010; break;
1390 case ATA_PIO4: reg20 = 0x00040010; break;
1391 case ATA_WDMA2: reg24 = 0x00002020; break;
1392 case ATA_UDMA2: reg24 = 0x00911030; break;
1394 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20);
1395 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24);
1399 promise_timing(struct ata_device *atadev, int devno, int mode)
1401 u_int32_t timing = 0;
1402 /* XXX: Endianess */
1403 struct promise_timing {
1405 u_int8_t prefetch:1;
1416 u_int8_t reserved:8;
1417 } *t = (struct promise_timing*)&timing;
1419 t->iordy = 1; t->iordyp = 1;
1420 if (mode >= ATA_DMA) {
1421 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1424 switch (atadev->channel->chiptype) {
1425 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1428 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1429 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1430 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1431 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1432 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1433 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1434 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1438 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1439 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1440 case 0x0d30105a: /* Promise OEM ATA 100 */
1443 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1444 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1445 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1446 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1447 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1448 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1449 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1450 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1451 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1455 pci_write_config(device_get_parent(atadev->channel->dev),
1456 0x60 + (devno<<2), timing, 4);
1460 hpt_timing(struct ata_device *atadev, int devno, int mode)
1462 device_t parent = device_get_parent(atadev->channel->dev);
1463 u_int32_t chiptype = atadev->channel->chiptype;
1464 int chiprev = pci_get_revid(parent);
1467 if (chiptype == 0x00081103 && chiprev >= 0x07) {
1468 switch (mode) { /* HPT374 */
1469 case ATA_PIO0: timing = 0x0ac1f48a; break;
1470 case ATA_PIO1: timing = 0x0ac1f465; break;
1471 case ATA_PIO2: timing = 0x0a81f454; break;
1472 case ATA_PIO3: timing = 0x0a81f443; break;
1473 case ATA_PIO4: timing = 0x0a81f442; break;
1474 case ATA_WDMA2: timing = 0x22808242; break;
1475 case ATA_UDMA2: timing = 0x120c8242; break;
1476 case ATA_UDMA4: timing = 0x12ac8242; break;
1477 case ATA_UDMA5: timing = 0x12848242; break;
1478 case ATA_UDMA6: timing = 0x12808242; break;
1479 default: timing = 0x0d029d5e;
1482 else if ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1483 (chiptype == 0x00051103 && chiprev >= 0x01)) {
1484 switch (mode) { /* HPT372 */
1485 case ATA_PIO0: timing = 0x0d029d5e; break;
1486 case ATA_PIO1: timing = 0x0d029d26; break;
1487 case ATA_PIO2: timing = 0x0c829ca6; break;
1488 case ATA_PIO3: timing = 0x0c829c84; break;
1489 case ATA_PIO4: timing = 0x0c829c62; break;
1490 case ATA_WDMA2: timing = 0x2c829262; break;
1491 case ATA_UDMA2: timing = 0x1c91dc62; break;
1492 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1493 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1494 case ATA_UDMA6: timing = 0x1c81dc62; break;
1495 default: timing = 0x0d029d5e;
1498 else if (chiptype == 0x00041103 && chiprev >= 0x03) {
1499 switch (mode) { /* HPT370 */
1500 case ATA_PIO0: timing = 0x06914e57; break;
1501 case ATA_PIO1: timing = 0x06914e43; break;
1502 case ATA_PIO2: timing = 0x06514e33; break;
1503 case ATA_PIO3: timing = 0x06514e22; break;
1504 case ATA_PIO4: timing = 0x06514e21; break;
1505 case ATA_WDMA2: timing = 0x26514e21; break;
1506 case ATA_UDMA2: timing = 0x16494e31; break;
1507 case ATA_UDMA4: timing = 0x16454e31; break;
1508 case ATA_UDMA5: timing = 0x16454e31; break;
1509 default: timing = 0x06514e57;
1511 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1513 else { /* HPT36[68] */
1514 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1515 case 0x85: /* 25Mhz */
1517 case ATA_PIO0: timing = 0x40d08585; break;
1518 case ATA_PIO1: timing = 0x40d08572; break;
1519 case ATA_PIO2: timing = 0x40ca8542; break;
1520 case ATA_PIO3: timing = 0x40ca8532; break;
1521 case ATA_PIO4: timing = 0x40ca8521; break;
1522 case ATA_WDMA2: timing = 0x20ca8521; break;
1523 case ATA_UDMA2: timing = 0x10cf8521; break;
1524 case ATA_UDMA4: timing = 0x10c98521; break;
1525 default: timing = 0x01208585;
1529 case 0xa7: /* 33MHz */
1531 case ATA_PIO0: timing = 0x40d0a7aa; break;
1532 case ATA_PIO1: timing = 0x40d0a7a3; break;
1533 case ATA_PIO2: timing = 0x40d0a753; break;
1534 case ATA_PIO3: timing = 0x40c8a742; break;
1535 case ATA_PIO4: timing = 0x40c8a731; break;
1536 case ATA_WDMA2: timing = 0x20c8a731; break;
1537 case ATA_UDMA2: timing = 0x10caa731; break;
1538 case ATA_UDMA4: timing = 0x10c9a731; break;
1539 default: timing = 0x0120a7a7;
1542 case 0xd9: /* 40Mhz */
1544 case ATA_PIO0: timing = 0x4018d9d9; break;
1545 case ATA_PIO1: timing = 0x4010d9c7; break;
1546 case ATA_PIO2: timing = 0x4010d997; break;
1547 case ATA_PIO3: timing = 0x4010d974; break;
1548 case ATA_PIO4: timing = 0x4008d963; break;
1549 case ATA_WDMA2: timing = 0x2008d943; break;
1550 case ATA_UDMA2: timing = 0x100bd943; break;
1551 case ATA_UDMA4: timing = 0x100fd943; break;
1552 default: timing = 0x0120d9d9;
1556 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1560 hpt_cable80(struct ata_device *atadev)
1562 device_t parent = device_get_parent(atadev->channel->dev);
1563 u_int8_t reg, val, res;
1565 if (atadev->channel->chiptype == 0x00081103 && pci_get_function(parent) == 1) {
1566 reg = atadev->channel->unit ? 0x57 : 0x53;
1567 val = pci_read_config(parent, reg, 1);
1568 pci_write_config(parent, reg, val | 0x80, 1);
1572 val = pci_read_config(parent, reg, 1);
1573 pci_write_config(parent, reg, val & 0xfe, 1);
1575 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x01 : 0x02);
1576 pci_write_config(parent, reg, val, 1);