2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-pci.c,v 1.10 2004/02/18 04:08:49 dillon Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/devicestat.h>
41 #include <sys/sysctl.h>
42 #include <machine/stdarg.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
45 #include <machine/clock.h>
47 #include <machine/md_var.h>
50 #include <bus/pci/pcivar.h>
51 #include <bus/pci/pcireg.h>
54 /* device structures */
55 struct ata_pci_controller {
56 struct resource *bmio;
63 #define IOMASK 0xfffffffc
64 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
65 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
66 (pci_get_progif(dev) & 0x05) != 0x05)
69 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
74 if (device_get_children(device_get_parent(dev), &children, &nchildren))
77 for (i = 0; i < nchildren; i++) {
78 if (pci_get_devid(children[i]) == devid &&
79 pci_get_revid(children[i]) >= revid) {
80 free(children, M_TEMP);
84 free(children, M_TEMP);
89 ata_via_southbridge_fixup(device_t dev)
94 if (device_get_children(device_get_parent(dev), &children, &nchildren))
97 for (i = 0; i < nchildren; i++) {
98 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
99 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
100 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
101 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
102 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
104 if ((reg76 & 0xf0) != 0xd0) {
106 "Correcting VIA config for southbridge data corruption bug\n");
107 pci_write_config(children[i], 0x75, 0x80, 1);
108 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
113 free(children, M_TEMP);
117 ata_pci_match(device_t dev)
119 if (pci_get_class(dev) != PCIC_STORAGE)
122 switch (pci_get_devid(dev)) {
123 /* supported chipsets */
125 return "Intel PIIX ATA controller";
128 return "Intel PIIX3 ATA controller";
133 return "Intel PIIX4 ATA33 controller";
136 return "Intel ICH0 ATA33 controller";
140 return "Intel ICH ATA66 controller";
144 return "Intel ICH2 ATA100 controller";
148 return "Intel ICH3 ATA100 controller";
152 return "Intel ICH4 ATA100 controller";
155 return "Intel ICH5 SATA150 controller";
158 return "Intel ICH5 ATA100 controller";
161 if (pci_get_revid(dev) >= 0xc4)
162 return "AcerLabs Aladdin ATA100 controller";
163 else if (pci_get_revid(dev) >= 0xc2)
164 return "AcerLabs Aladdin ATA66 controller";
165 else if (pci_get_revid(dev) >= 0x20)
166 return "AcerLabs Aladdin ATA33 controller";
168 return "AcerLabs Aladdin ATA controller";
171 if (ata_find_dev(dev, 0x05861106, 0x02))
172 return "VIA 82C586 ATA33 controller";
173 if (ata_find_dev(dev, 0x05861106, 0))
174 return "VIA 82C586 ATA controller";
175 if (ata_find_dev(dev, 0x05961106, 0x12))
176 return "VIA 82C596 ATA66 controller";
177 if (ata_find_dev(dev, 0x05961106, 0))
178 return "VIA 82C596 ATA33 controller";
179 if (ata_find_dev(dev, 0x06861106, 0x40))
180 return "VIA 82C686 ATA100 controller";
181 if (ata_find_dev(dev, 0x06861106, 0x10))
182 return "VIA 82C686 ATA66 controller";
183 if (ata_find_dev(dev, 0x06861106, 0))
184 return "VIA 82C686 ATA33 controller";
185 if (ata_find_dev(dev, 0x82311106, 0))
186 return "VIA 8231 ATA100 controller";
187 if (ata_find_dev(dev, 0x30741106, 0) ||
188 ata_find_dev(dev, 0x31091106, 0))
189 return "VIA 8233 ATA100 controller";
190 if (ata_find_dev(dev, 0x31471106, 0))
191 return "VIA 8233 ATA133 controller";
192 if (ata_find_dev(dev, 0x31771106, 0))
193 return "VIA 8235 ATA133 controller";
194 if (ata_find_dev(dev, 0x31491106, 0))
195 return "VIA 8237 ATA133 controller";
196 return "VIA Apollo ATA controller";
199 return "VIA 8237 SATA 150 controller";
202 if (ata_find_dev(dev, 0x07461039, 0))
203 return "SiS 5591 ATA133 controller";
204 if (ata_find_dev(dev, 0x06301039, 0x30) ||
205 ata_find_dev(dev, 0x06331039, 0) ||
206 ata_find_dev(dev, 0x06351039, 0) ||
207 ata_find_dev(dev, 0x06401039, 0) ||
208 ata_find_dev(dev, 0x06451039, 0) ||
209 ata_find_dev(dev, 0x06461039, 0) ||
210 ata_find_dev(dev, 0x06481039, 0) ||
211 ata_find_dev(dev, 0x06501039, 0) ||
212 ata_find_dev(dev, 0x07301039, 0) ||
213 ata_find_dev(dev, 0x07331039, 0) ||
214 ata_find_dev(dev, 0x07351039, 0) ||
215 ata_find_dev(dev, 0x07401039, 0) ||
216 ata_find_dev(dev, 0x07451039, 0) ||
217 ata_find_dev(dev, 0x07501039, 0))
218 return "SiS 5591 ATA100 controller";
219 else if (ata_find_dev(dev, 0x05301039, 0) ||
220 ata_find_dev(dev, 0x05401039, 0) ||
221 ata_find_dev(dev, 0x06201039, 0) ||
222 ata_find_dev(dev, 0x06301039, 0))
223 return "SiS 5591 ATA66 controller";
225 return "SiS 5591 ATA33 controller";
228 return "SiI 0680 ATA133 controller";
231 return "CMD 649 ATA100 controller";
234 return "CMD 648 ATA66 controller";
237 return "CMD 646 ATA controller";
240 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
241 return "Cypress 82C693 ATA controller";
245 return "Cyrix 5530 ATA33 controller";
248 return "AMD 756 ATA66 controller";
251 return "AMD 766 ATA100 controller";
254 return "AMD 768 ATA100 controller";
257 return "AMD 8111 UltraATA/133 controller";
260 return "nVIDIA nForce ATA100 controller";
263 return "nVIDIA nForce ATA133 controller";
266 return "nVIDIA nForce2 ATA133 controller";
269 return "ServerWorks ROSB4 ATA33 controller";
272 if (pci_get_revid(dev) >= 0x92)
273 return "ServerWorks CSB5 ATA100 controller";
275 return "ServerWorks CSB5 ATA66 controller";
278 return "ServerWorks CSB6 ATA100 controller (channel 0+1)";
281 return "ServerWorks CSB6 ATA66 controller (channel 2)";
284 return "Promise ATA33 controller";
288 return "Promise ATA66 controller";
292 return "Promise ATA100 controller";
296 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
297 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
298 static long start = 0, end = 0;
300 /* we belive we are on a TX4, now do our (simple) magic */
301 if (pci_get_slot(dev) == 1) {
302 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
303 return "Promise TX4 ATA100 controller (channel 0+1)";
305 else if (pci_get_slot(dev) == 2 && start && end) {
306 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
308 return "Promise TX4 ATA100 controller (channel 2+3)";
313 return "Promise TX2 ATA100 controller";
319 return "Promise TX2 ATA133 controller";
322 switch (pci_get_revid(dev)) {
325 return "HighPoint HPT366 ATA66 controller";
327 return "HighPoint HPT368 ATA66 controller";
330 return "HighPoint HPT370 ATA100 controller";
332 return "HighPoint HPT372 ATA133 controller";
337 switch (pci_get_revid(dev)) {
340 return "HighPoint HPT372 ATA133 controller";
345 switch (pci_get_revid(dev)) {
347 return "HighPoint HPT374 ATA133 controller";
352 return "Cenatek Rocket Drive controller";
354 /* unsupported but known chipsets, generic DMA only */
357 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
360 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
362 /* unknown chipsets, try generic DMA if it seems possible */
364 if (pci_get_class(dev) == PCIC_STORAGE &&
365 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
366 return "Generic PCI ATA controller";
372 ata_pci_probe(device_t dev)
374 const char *desc = ata_pci_match(dev);
377 device_set_desc(dev, desc);
385 ata_pci_add_child(device_t dev, int unit)
389 /* check if this is located at one of the std addresses */
390 if (ATA_MASTERDEV(dev)) {
391 if (!(child = device_add_child(dev, "ata", unit)))
395 if (!(child = device_add_child(dev, "ata", 2)))
402 ata_pci_attach(device_t dev)
404 struct ata_pci_controller *controller = device_get_softc(dev);
405 u_int8_t class, subclass;
409 /* set up vendor-specific stuff */
410 type = pci_get_devid(dev);
411 class = pci_get_class(dev);
412 subclass = pci_get_subclass(dev);
413 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
415 if (!(cmd & PCIM_CMD_PORTEN)) {
416 device_printf(dev, "ATA channel disabled by BIOS\n");
420 /* is busmastering supported ? */
421 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
422 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
424 /* is there a valid port range to connect to ? */
426 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
427 0, ~0, 1, RF_ACTIVE);
428 if (!controller->bmio)
429 device_printf(dev, "Busmastering DMA not configured\n");
432 device_printf(dev, "Busmastering DMA not supported\n");
434 /* do extra chipset specific setups */
436 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
437 pci_write_config(dev, 0x53,
438 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
441 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
444 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
447 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
448 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
451 case 0x00041103: /* HighPoint HPT366/368/370/372 */
452 if (pci_get_revid(dev) < 2) { /* HPT 366 */
453 /* turn off interrupt prediction */
454 pci_write_config(dev, 0x51,
455 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
458 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
459 /* turn off interrupt prediction */
460 pci_write_config(dev, 0x51,
461 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
462 pci_write_config(dev, 0x55,
463 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
465 /* turn on interrupts */
466 pci_write_config(dev, 0x5a,
467 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
470 pci_write_config(dev, 0x5b, 0x22, 1);
475 case 0x00051103: /* HighPoint HPT372 */
476 case 0x00081103: /* HighPoint HPT374 */
477 /* turn off interrupt prediction */
478 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
479 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
481 /* turn on interrupts */
482 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
485 pci_write_config(dev, 0x5b,
486 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
489 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
490 /* prepare for ATA-66 on the 82C686a and 82C596b */
491 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
492 !ata_find_dev(dev, 0x06861106, 0x40)) ||
493 ata_find_dev(dev, 0x05961106, 0x12))
494 pci_write_config(dev, 0x50, 0x030b030b, 4);
496 /* the southbridge might need the data corruption fix */
497 if (ata_find_dev(dev, 0x06861106, 0x40) ||
498 ata_find_dev(dev, 0x82311106, 0x10))
499 ata_via_southbridge_fixup(dev);
502 case 0x74091022: /* AMD 756 default setup */
503 case 0x74111022: /* AMD 766 default setup */
504 case 0x74411022: /* AMD 768 default setup */
505 case 0x746d1022: /* AMD 8111 default setup */
506 case 0x01bc10de: /* NVIDIA nForce default setup */
507 case 0x006510de: /* NVIDIA nForce2 default setup */
508 /* set prefetch, postwrite */
509 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
511 /* set fifo configuration half'n'half */
512 pci_write_config(dev, 0x43,
513 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
515 /* set status register read retry */
516 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
518 /* set DMA read & end-of-sector fifo flush */
519 pci_write_config(dev, 0x46,
520 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
522 /* set sector size */
523 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
524 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
527 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
528 pci_write_config(dev, 0x64,
529 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
533 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
534 pci_write_config(dev, 0x5a,
535 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
536 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
539 case 0x06801095: /* SiI 0680 set ATA reference clock speed */
540 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
541 pci_write_config(dev, 0x8a,
542 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
543 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
544 device_printf(dev, "SiI 0680 could not set clock\n");
549 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
550 pci_write_config(dev, 0x71, 0x01, 1);
553 case 0x10001042: /* RZ 100? known bad, no DMA */
555 case 0x06401095: /* CMD 640 known bad, no DMA */
556 controller->bmio = NULL;
557 device_printf(dev, "Busmastering DMA disabled\n");
560 if (controller->bmio) {
561 controller->bmaddr = rman_get_start(controller->bmio);
562 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
563 SYS_RES_IOPORT, rid, controller->bmio);
564 controller->bmio = NULL;
568 * the Cypress chip is a mess, it contains two ATA functions, but
569 * both channels are visible on the first one.
570 * simply ignore the second function for now, as the right
571 * solution (ignoring the second channel on the first function)
572 * doesn't work with the crappy ATA interrupt setup on the alpha.
574 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
577 ata_pci_add_child(dev, 0);
579 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
580 ata_pci_add_child(dev, 1);
582 return bus_generic_attach(dev);
586 ata_pci_intr(struct ata_channel *ch)
591 * since we might share the IRQ with another device, and in some
592 * cases with our twin channel, we only want to process interrupts
593 * that we know this channel generated.
595 switch (ch->chiptype) {
596 case 0x00041103: /* HighPoint HPT366/368/370/372 */
597 case 0x00051103: /* HighPoint HPT372 */
598 case 0x00081103: /* HighPoint HPT374 */
599 if (((dmastat = ata_dmastatus(ch)) &
600 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
602 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
606 case 0x06481095: /* CMD 648 */
607 case 0x06491095: /* CMD 649 */
608 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
609 (ch->unit ? 0x08 : 0x04)))
611 #if !defined(NO_ATANG)
612 pci_write_config(device_get_parent(ch->dev), 0x71,
613 pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
614 ~(ch->unit ? 0x04 : 0x08), 1);
618 case 0x06801095: /* SiI 680 */
619 if (!(pci_read_config(device_get_parent(ch->dev),
620 (ch->unit ? 0xb1 : 0xa1), 1) & 0x08))
624 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
625 case 0x0d38105a: /* Promise Fasttrak 66 */
626 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
627 case 0x0d30105a: /* Promise OEM ATA100 */
628 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
629 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
630 (ch->unit ? 0x00004000 : 0x00000400)))
634 case 0x4d68105a: /* Promise TX2 ATA100 */
635 case 0x6268105a: /* Promise TX2 ATA100 */
636 case 0x4d69105a: /* Promise TX2 ATA133 */
637 case 0x5275105a: /* Promise TX2 ATA133 */
638 case 0x6269105a: /* Promise TX2 ATA133 */
639 case 0x7275105a: /* Promise TX2 ATA133 */
640 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
641 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
645 case 0x24d18086: /* Intel ICH5 SATA150 */
646 dmastat = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
647 if ((dmastat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
648 ATA_BMSTAT_INTERRUPT)
650 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat &
651 ~(ATA_BMSTAT_DMA_SIMPLEX | ATA_BMSTAT_ERROR));
657 if (ch->flags & ATA_DMA_ACTIVE) {
658 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
660 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
667 ata_pci_print_child(device_t dev, device_t child)
669 struct ata_channel *ch = device_get_softc(child);
672 retval += bus_print_child_header(dev, child);
673 retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
675 if (ATA_MASTERDEV(dev))
676 retval += printf(" irq %d", 14 + ch->unit);
678 retval += bus_print_child_footer(dev, child);
683 static struct resource *
684 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
685 u_long start, u_long end, u_long count, u_int flags)
687 struct ata_pci_controller *controller = device_get_softc(dev);
688 struct resource *res = NULL;
689 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
692 if (type == SYS_RES_IOPORT) {
695 if (ATA_MASTERDEV(dev)) {
697 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
698 end = start + ATA_IOSIZE - 1;
700 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
701 SYS_RES_IOPORT, &myrid,
702 start, end, count, flags);
705 myrid = 0x10 + 8 * unit;
706 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
707 SYS_RES_IOPORT, &myrid,
708 start, end, count, flags);
712 case ATA_ALTADDR_RID:
713 if (ATA_MASTERDEV(dev)) {
715 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
716 end = start + ATA_ALTIOSIZE - 1;
717 count = ATA_ALTIOSIZE;
718 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
719 SYS_RES_IOPORT, &myrid,
720 start, end, count, flags);
723 myrid = 0x14 + 8 * unit;
724 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
725 SYS_RES_IOPORT, &myrid,
726 start, end, count, flags);
728 start = rman_get_start(res) + 2;
729 end = rman_get_start(res) + ATA_ALTIOSIZE - 1;
730 count = ATA_ALTIOSIZE;
731 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
732 SYS_RES_IOPORT, myrid, res);
733 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
734 SYS_RES_IOPORT, &myrid,
735 start, end, count, flags);
741 if (controller->bmaddr) {
744 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
745 end = start + ATA_BMIOSIZE - 1;
746 count = ATA_BMIOSIZE;
747 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
748 SYS_RES_IOPORT, &myrid,
749 start, end, count, flags);
755 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
756 if (ATA_MASTERDEV(dev)) {
758 return alpha_platform_alloc_ide_intr(unit);
760 int irq = (unit == 0 ? 14 : 15);
762 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
763 SYS_RES_IRQ, rid, irq, irq, 1, flags);
767 /* primary and secondary channels share interrupt, keep track */
768 if (!controller->irq)
769 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
771 rid, 0, ~0, 1, flags);
772 controller->irqcnt++;
773 return controller->irq;
780 ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
783 struct ata_pci_controller *controller = device_get_softc(dev);
784 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
786 if (type == SYS_RES_IOPORT) {
789 if (ATA_MASTERDEV(dev))
790 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
791 SYS_RES_IOPORT, 0x0, r);
793 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
794 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
797 case ATA_ALTADDR_RID:
798 if (ATA_MASTERDEV(dev))
799 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
800 SYS_RES_IOPORT, 0x0, r);
802 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
803 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
807 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
808 SYS_RES_IOPORT, 0x20, r);
813 if (type == SYS_RES_IRQ) {
814 if (rid != ATA_IRQ_RID)
817 if (ATA_MASTERDEV(dev)) {
819 return alpha_platform_release_ide_intr(unit, r);
821 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
822 SYS_RES_IRQ, rid, r);
826 /* primary and secondary channels share interrupt, keep track */
827 if (--controller->irqcnt)
829 controller->irq = NULL;
830 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
831 SYS_RES_IRQ, rid, r);
838 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
839 int flags, driver_intr_t *intr, void *arg,
842 if (ATA_MASTERDEV(dev)) {
844 return alpha_platform_setup_ide_intr(irq, intr, arg, cookiep);
846 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
847 flags, intr, arg, cookiep);
851 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
852 flags, intr, arg, cookiep);
856 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
859 if (ATA_MASTERDEV(dev)) {
861 return alpha_platform_teardown_ide_intr(irq, cookie);
863 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
867 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
870 static device_method_t ata_pci_methods[] = {
871 /* device interface */
872 DEVMETHOD(device_probe, ata_pci_probe),
873 DEVMETHOD(device_attach, ata_pci_attach),
874 DEVMETHOD(device_shutdown, bus_generic_shutdown),
875 DEVMETHOD(device_suspend, bus_generic_suspend),
876 DEVMETHOD(device_resume, bus_generic_resume),
879 DEVMETHOD(bus_print_child, ata_pci_print_child),
880 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
881 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
882 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
883 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
884 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
885 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
889 static driver_t ata_pci_driver = {
892 sizeof(struct ata_pci_controller),
895 static devclass_t ata_pci_devclass;
897 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
900 ata_pcisub_probe(device_t dev)
902 struct ata_channel *ch = device_get_softc(dev);
906 /* find channel number on this controller */
907 device_get_children(device_get_parent(dev), &children, &count);
908 for (i = 0; i < count; i++) {
909 if (children[i] == dev)
912 free(children, M_TEMP);
913 ch->chiptype = pci_get_devid(device_get_parent(dev));
914 ch->intr_func = ata_pci_intr;
915 return ata_probe(dev);
918 static device_method_t ata_pcisub_methods[] = {
919 /* device interface */
920 DEVMETHOD(device_probe, ata_pcisub_probe),
921 DEVMETHOD(device_attach, ata_attach),
922 DEVMETHOD(device_detach, ata_detach),
923 DEVMETHOD(device_resume, ata_resume),
927 static driver_t ata_pcisub_driver = {
930 sizeof(struct ata_channel),
933 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);