sys/dev/drm/radeon/sumo_dpm.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include "radeon.h"
  26 #include "radeon_asic.h"
  27 #include "sumod.h"
  28 #include "r600_dpm.h"
  29 #include "cypress_dpm.h"
  30 #include "sumo_dpm.h"
  31 #include <linux/seq_file.h>
  32
  33 #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
  34 #define SUMO_MINIMUM_ENGINE_CLOCK 800
  35 #define BOOST_DPM_LEVEL 7
  36
  37 static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
  38 {
  39         SUMO_UTC_DFLT_00,
  40         SUMO_UTC_DFLT_01,
  41         SUMO_UTC_DFLT_02,
  42         SUMO_UTC_DFLT_03,
  43         SUMO_UTC_DFLT_04,
  44         SUMO_UTC_DFLT_05,
  45         SUMO_UTC_DFLT_06,
  46         SUMO_UTC_DFLT_07,
  47         SUMO_UTC_DFLT_08,
  48         SUMO_UTC_DFLT_09,
  49         SUMO_UTC_DFLT_10,
  50         SUMO_UTC_DFLT_11,
  51         SUMO_UTC_DFLT_12,
  52         SUMO_UTC_DFLT_13,
  53         SUMO_UTC_DFLT_14,
  54 };
  55
  56 static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
  57 {
  58         SUMO_DTC_DFLT_00,
  59         SUMO_DTC_DFLT_01,
  60         SUMO_DTC_DFLT_02,
  61         SUMO_DTC_DFLT_03,
  62         SUMO_DTC_DFLT_04,
  63         SUMO_DTC_DFLT_05,
  64         SUMO_DTC_DFLT_06,
  65         SUMO_DTC_DFLT_07,
  66         SUMO_DTC_DFLT_08,
  67         SUMO_DTC_DFLT_09,
  68         SUMO_DTC_DFLT_10,
  69         SUMO_DTC_DFLT_11,
  70         SUMO_DTC_DFLT_12,
  71         SUMO_DTC_DFLT_13,
  72         SUMO_DTC_DFLT_14,
  73 };
  74
  75 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev);
  76
  77 static struct sumo_ps *sumo_get_ps(struct radeon_ps *rps)
  78 {
  79         struct sumo_ps *ps = rps->ps_priv;
  80
  81         return ps;
  82 }
  83
  84 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev)
  85 {
  86         struct sumo_power_info *pi = rdev->pm.dpm.priv;
  87
  88         return pi;
  89 }
  90
  91 static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
  92 {
  93         if (enable)
  94                 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
  95         else {
  96                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
  97                 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
  98                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
  99                 RREG32(GB_ADDR_CONFIG);
 100         }
 101 }
 102
 103 #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF
 104 #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF
 105
 106 static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
 107 {
 108         u32 local0;
 109         u32 local1;
 110
 111         local0 = RREG32(CG_CGTT_LOCAL_0);
 112         local1 = RREG32(CG_CGTT_LOCAL_1);
 113
 114         if (enable) {
 115                 WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
 116                 WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
 117         } else {
 118                 WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
 119                 WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
 120         }
 121 }
 122
 123 static void sumo_program_git(struct radeon_device *rdev)
 124 {
 125         u32 p, u;
 126         u32 xclk = radeon_get_xclk(rdev);
 127
 128         r600_calculate_u_and_p(SUMO_GICST_DFLT,
 129                                xclk, 16, &p, &u);
 130
 131         WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);
 132 }
 133
 134 static void sumo_program_grsd(struct radeon_device *rdev)
 135 {
 136         u32 p, u;
 137         u32 xclk = radeon_get_xclk(rdev);
 138         u32 grs = 256 * 25 / 100;
 139
 140         r600_calculate_u_and_p(1, xclk, 14, &p, &u);
 141
 142         WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u));
 143 }
 144
 145 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev)
 146 {
 147         sumo_program_git(rdev);
 148         sumo_program_grsd(rdev);
 149 }
 150
 151 static void sumo_gfx_powergating_initialize(struct radeon_device *rdev)
 152 {
 153         u32 rcu_pwr_gating_cntl;
 154         u32 p, u;
 155         u32 p_c, p_p, d_p;
 156         u32 r_t, i_t;
 157         u32 xclk = radeon_get_xclk(rdev);
 158
 159         if (rdev->family == CHIP_PALM) {
 160                 p_c = 4;
 161                 d_p = 10;
 162                 r_t = 10;
 163                 i_t = 4;
 164                 p_p = 50 + 1000/200 + 6 * 32;
 165         } else {
 166                 p_c = 16;
 167                 d_p = 50;
 168                 r_t = 50;
 169                 i_t  = 50;
 170                 p_p = 113;
 171         }
 172
 173         WREG32(CG_SCRATCH2, 0x01B60A17);
 174
 175         r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT,
 176                                xclk, 16, &p, &u);
 177
 178         WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),
 179                  ~(PGP_MASK | PGU_MASK));
 180
 181         r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT,
 182                                xclk, 16, &p, &u);
 183
 184         WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),
 185                  ~(PGP_MASK | PGU_MASK));
 186
 187         if (rdev->family == CHIP_PALM) {
 188                 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210);
 189                 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010);
 190         } else {
 191                 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210);
 192                 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98);
 193         }
 194
 195         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
 196         rcu_pwr_gating_cntl &=
 197                 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
 198         rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN;
 199         if (rdev->family == CHIP_PALM) {
 200                 rcu_pwr_gating_cntl &= ~PCP_MASK;
 201                 rcu_pwr_gating_cntl |= PCP(0x77);
 202         }
 203         WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
 204
 205         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
 206         rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
 207         rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50);
 208         WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
 209
 210         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
 211         rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
 212         rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50);
 213         WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
 214
 215         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4);
 216         rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK);
 217         rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t);
 218         WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl);
 219
 220         if (rdev->family == CHIP_PALM)
 221                 WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02);
 222
 223         sumo_smu_pg_init(rdev);
 224
 225         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
 226         rcu_pwr_gating_cntl &=
 227                 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
 228         rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN;
 229         if (rdev->family == CHIP_PALM) {
 230                 rcu_pwr_gating_cntl &= ~PCP_MASK;
 231                 rcu_pwr_gating_cntl |= PCP(0x77);
 232         }
 233         WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
 234
 235         if (rdev->family == CHIP_PALM) {
 236                 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
 237                 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
 238                 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
 239                 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
 240
 241                 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
 242                 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
 243                 rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50);
 244                 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
 245         }
 246
 247         sumo_smu_pg_init(rdev);
 248
 249         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
 250         rcu_pwr_gating_cntl &=
 251                 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
 252         rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN;
 253
 254         if (rdev->family == CHIP_PALM) {
 255                 rcu_pwr_gating_cntl |= PCV(4);
 256                 rcu_pwr_gating_cntl &= ~PCP_MASK;
 257                 rcu_pwr_gating_cntl |= PCP(0x77);
 258         } else
 259                 rcu_pwr_gating_cntl |= PCV(11);
 260         WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
 261
 262         if (rdev->family == CHIP_PALM) {
 263                 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
 264                 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
 265                 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
 266                 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
 267
 268                 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
 269                 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
 270                 rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50);
 271                 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
 272         }
 273
 274         sumo_smu_pg_init(rdev);
 275 }
 276
 277 static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)
 278 {
 279         if (enable)
 280                 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
 281         else {
 282                 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);
 283                 RREG32(GB_ADDR_CONFIG);
 284         }
 285 }
 286
 287 static int sumo_enable_clock_power_gating(struct radeon_device *rdev)
 288 {
 289         struct sumo_power_info *pi = sumo_get_pi(rdev);
 290
 291         if (pi->enable_gfx_clock_gating)
 292                 sumo_gfx_clockgating_initialize(rdev);
 293         if (pi->enable_gfx_power_gating)
 294                 sumo_gfx_powergating_initialize(rdev);
 295         if (pi->enable_mg_clock_gating)
 296                 sumo_mg_clockgating_enable(rdev, true);
 297         if (pi->enable_gfx_clock_gating)
 298                 sumo_gfx_clockgating_enable(rdev, true);
 299         if (pi->enable_gfx_power_gating)
 300                 sumo_gfx_powergating_enable(rdev, true);
 301
 302         return 0;
 303 }
 304
 305 static void sumo_disable_clock_power_gating(struct radeon_device *rdev)
 306 {
 307         struct sumo_power_info *pi = sumo_get_pi(rdev);
 308
 309         if (pi->enable_gfx_clock_gating)
 310                 sumo_gfx_clockgating_enable(rdev, false);
 311         if (pi->enable_gfx_power_gating)
 312                 sumo_gfx_powergating_enable(rdev, false);
 313         if (pi->enable_mg_clock_gating)
 314                 sumo_mg_clockgating_enable(rdev, false);
 315 }
 316
 317 static void sumo_calculate_bsp(struct radeon_device *rdev,
 318                                u32 high_clk)
 319 {
 320         struct sumo_power_info *pi = sumo_get_pi(rdev);
 321         u32 xclk = radeon_get_xclk(rdev);
 322
 323         pi->pasi = 65535 * 100 / high_clk;
 324         pi->asi = 65535 * 100 / high_clk;
 325
 326         r600_calculate_u_and_p(pi->asi,
 327                                xclk, 16, &pi->bsp, &pi->bsu);
 328
 329         r600_calculate_u_and_p(pi->pasi,
 330                                xclk, 16, &pi->pbsp, &pi->pbsu);
 331
 332         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
 333         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
 334 }
 335
 336 static void sumo_init_bsp(struct radeon_device *rdev)
 337 {
 338         struct sumo_power_info *pi = sumo_get_pi(rdev);
 339
 340         WREG32(CG_BSP_0, pi->psp);
 341 }
 342
 343
 344 static void sumo_program_bsp(struct radeon_device *rdev,
 345                              struct radeon_ps *rps)
 346 {
 347         struct sumo_power_info *pi = sumo_get_pi(rdev);
 348         struct sumo_ps *ps = sumo_get_ps(rps);
 349         u32 i;
 350         u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
 351
 352         if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 353                 highest_engine_clock = pi->boost_pl.sclk;
 354
 355         sumo_calculate_bsp(rdev, highest_engine_clock);
 356
 357         for (i = 0; i < ps->num_levels - 1; i++)
 358                 WREG32(CG_BSP_0 + (i * 4), pi->dsp);
 359
 360         WREG32(CG_BSP_0 + (i * 4), pi->psp);
 361
 362         if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 363                 WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp);
 364 }
 365
 366 static void sumo_write_at(struct radeon_device *rdev,
 367                           u32 index, u32 value)
 368 {
 369         if (index == 0)
 370                 WREG32(CG_AT_0, value);
 371         else if (index == 1)
 372                 WREG32(CG_AT_1, value);
 373         else if (index == 2)
 374                 WREG32(CG_AT_2, value);
 375         else if (index == 3)
 376                 WREG32(CG_AT_3, value);
 377         else if (index == 4)
 378                 WREG32(CG_AT_4, value);
 379         else if (index == 5)
 380                 WREG32(CG_AT_5, value);
 381         else if (index == 6)
 382                 WREG32(CG_AT_6, value);
 383         else if (index == 7)
 384                 WREG32(CG_AT_7, value);
 385 }
 386
 387 static void sumo_program_at(struct radeon_device *rdev,
 388                             struct radeon_ps *rps)
 389 {
 390         struct sumo_power_info *pi = sumo_get_pi(rdev);
 391         struct sumo_ps *ps = sumo_get_ps(rps);
 392         u32 asi;
 393         u32 i;
 394         u32 m_a;
 395         u32 a_t;
 396         u32 r[SUMO_MAX_HARDWARE_POWERLEVELS];
 397         u32 l[SUMO_MAX_HARDWARE_POWERLEVELS];
 398
 399         r[0] = SUMO_R_DFLT0;
 400         r[1] = SUMO_R_DFLT1;
 401         r[2] = SUMO_R_DFLT2;
 402         r[3] = SUMO_R_DFLT3;
 403         r[4] = SUMO_R_DFLT4;
 404
 405         l[0] = SUMO_L_DFLT0;
 406         l[1] = SUMO_L_DFLT1;
 407         l[2] = SUMO_L_DFLT2;
 408         l[3] = SUMO_L_DFLT3;
 409         l[4] = SUMO_L_DFLT4;
 410
 411         for (i = 0; i < ps->num_levels; i++) {
 412                 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi;
 413
 414                 m_a = asi * ps->levels[i].sclk / 100;
 415
 416                 a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100);
 417
 418                 sumo_write_at(rdev, i, a_t);
 419         }
 420
 421         if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
 422                 asi = pi->pasi;
 423
 424                 m_a = asi * pi->boost_pl.sclk / 100;
 425
 426                 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) |
 427                         CG_L(m_a * l[ps->num_levels - 1] / 100);
 428
 429                 sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t);
 430         }
 431 }
 432
 433 static void sumo_program_tp(struct radeon_device *rdev)
 434 {
 435         int i;
 436         enum r600_td td = R600_TD_DFLT;
 437
 438         for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) {
 439                 WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK);
 440                 WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK);
 441         }
 442
 443         if (td == R600_TD_AUTO)
 444                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
 445         else
 446                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
 447
 448         if (td == R600_TD_UP)
 449                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
 450
 451         if (td == R600_TD_DOWN)
 452                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
 453 }
 454
 455 void sumo_program_vc(struct radeon_device *rdev, u32 vrc)
 456 {
 457         WREG32(CG_FTV, vrc);
 458 }
 459
 460 void sumo_clear_vc(struct radeon_device *rdev)
 461 {
 462         WREG32(CG_FTV, 0);
 463 }
 464
 465 void sumo_program_sstp(struct radeon_device *rdev)
 466 {
 467         u32 p, u;
 468         u32 xclk = radeon_get_xclk(rdev);
 469
 470         r600_calculate_u_and_p(SUMO_SST_DFLT,
 471                                xclk, 16, &p, &u);
 472
 473         WREG32(CG_SSP, SSTU(u) | SST(p));
 474 }
 475
 476 static void sumo_set_divider_value(struct radeon_device *rdev,
 477                                    u32 index, u32 divider)
 478 {
 479         u32 reg_index = index / 4;
 480         u32 field_index = index % 4;
 481
 482         if (field_index == 0)
 483                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 484                          SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
 485         else if (field_index == 1)
 486                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 487                          SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
 488         else if (field_index == 2)
 489                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 490                          SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
 491         else if (field_index == 3)
 492                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 493                          SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
 494 }
 495
 496 static void sumo_set_ds_dividers(struct radeon_device *rdev,
 497                                  u32 index, u32 divider)
 498 {
 499         struct sumo_power_info *pi = sumo_get_pi(rdev);
 500
 501         if (pi->enable_sclk_ds) {
 502                 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);
 503
 504                 dpm_ctrl &= ~(0x7 << (index * 3));
 505                 dpm_ctrl |= (divider << (index * 3));
 506                 WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl);
 507         }
 508 }
 509
 510 static void sumo_set_ss_dividers(struct radeon_device *rdev,
 511                                  u32 index, u32 divider)
 512 {
 513         struct sumo_power_info *pi = sumo_get_pi(rdev);
 514
 515         if (pi->enable_sclk_ds) {
 516                 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);
 517
 518                 dpm_ctrl &= ~(0x7 << (index * 3));
 519                 dpm_ctrl |= (divider << (index * 3));
 520                 WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl);
 521         }
 522 }
 523
 524 static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
 525 {
 526         u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);
 527
 528         voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2));
 529         voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2));
 530         WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl);
 531 }
 532
 533 static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow)
 534 {
 535         struct sumo_power_info *pi = sumo_get_pi(rdev);
 536         u32 temp = gnb_slow;
 537         u32 cg_sclk_dpm_ctrl_3;
 538
 539         if (pi->driver_nbps_policy_disable)
 540                 temp = 1;
 541
 542         cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
 543         cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index);
 544         cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index));
 545
 546         WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
 547 }
 548
 549 static void sumo_program_power_level(struct radeon_device *rdev,
 550                                      struct sumo_pl *pl, u32 index)
 551 {
 552         struct sumo_power_info *pi = sumo_get_pi(rdev);
 553         int ret;
 554         struct atom_clock_dividers dividers;
 555         u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;
 556
 557         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 558                                              pl->sclk, false, &dividers);
 559         if (ret)
 560                 return;
 561
 562         sumo_set_divider_value(rdev, index, dividers.post_div);
 563
 564         sumo_set_vid(rdev, index, pl->vddc_index);
 565
 566         if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) {
 567                 if (ds_en)
 568                         WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
 569         } else {
 570                 sumo_set_ss_dividers(rdev, index, pl->ss_divider_index);
 571                 sumo_set_ds_dividers(rdev, index, pl->ds_divider_index);
 572
 573                 if (!ds_en)
 574                         WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS);
 575         }
 576
 577         sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
 578
 579         if (pi->enable_boost)
 580                 sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit);
 581 }
 582
 583 static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)
 584 {
 585         u32 reg_index = index / 4;
 586         u32 field_index = index % 4;
 587
 588         if (field_index == 0)
 589                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 590                          enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD);
 591         else if (field_index == 1)
 592                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 593                          enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD);
 594         else if (field_index == 2)
 595                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 596                          enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD);
 597         else if (field_index == 3)
 598                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 599                          enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD);
 600 }
 601
 602 static bool sumo_dpm_enabled(struct radeon_device *rdev)
 603 {
 604         if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
 605                 return true;
 606         else
 607                 return false;
 608 }
 609
 610 static void sumo_start_dpm(struct radeon_device *rdev)
 611 {
 612         WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);
 613 }
 614
 615 static void sumo_stop_dpm(struct radeon_device *rdev)
 616 {
 617         WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);
 618 }
 619
 620 static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)
 621 {
 622         if (enable)
 623                 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);
 624         else
 625                 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);
 626 }
 627
 628 static void sumo_set_forced_mode_enabled(struct radeon_device *rdev)
 629 {
 630         int i;
 631
 632         sumo_set_forced_mode(rdev, true);
 633         for (i = 0; i < rdev->usec_timeout; i++) {
 634                 if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)
 635                         break;
 636                 udelay(1);
 637         }
 638 }
 639
 640 static void sumo_wait_for_level_0(struct radeon_device *rdev)
 641 {
 642         int i;
 643
 644         for (i = 0; i < rdev->usec_timeout; i++) {
 645                 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)
 646                         break;
 647                 udelay(1);
 648         }
 649         for (i = 0; i < rdev->usec_timeout; i++) {
 650                 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)
 651                         break;
 652                 udelay(1);
 653         }
 654 }
 655
 656 static void sumo_set_forced_mode_disabled(struct radeon_device *rdev)
 657 {
 658         sumo_set_forced_mode(rdev, false);
 659 }
 660
 661 static void sumo_enable_power_level_0(struct radeon_device *rdev)
 662 {
 663         sumo_power_level_enable(rdev, 0, true);
 664 }
 665
 666 static void sumo_patch_boost_state(struct radeon_device *rdev,
 667                                    struct radeon_ps *rps)
 668 {
 669         struct sumo_power_info *pi = sumo_get_pi(rdev);
 670         struct sumo_ps *new_ps = sumo_get_ps(rps);
 671
 672         if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
 673                 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
 674                 pi->boost_pl.sclk = pi->sys_info.boost_sclk;
 675                 pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit;
 676                 pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost;
 677         }
 678 }
 679
 680 static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev,
 681                                              struct radeon_ps *new_rps,
 682                                              struct radeon_ps *old_rps)
 683 {
 684         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 685         struct sumo_ps *old_ps = sumo_get_ps(old_rps);
 686         u32 nbps1_old = 0;
 687         u32 nbps1_new = 0;
 688
 689         if (old_ps != NULL)
 690                 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
 691
 692         nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
 693
 694         if (nbps1_old == 1 && nbps1_new == 0)
 695                 sumo_smu_notify_alt_vddnb_change(rdev, 0, 0);
 696 }
 697
 698 static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev,
 699                                               struct radeon_ps *new_rps,
 700                                               struct radeon_ps *old_rps)
 701 {
 702         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 703         struct sumo_ps *old_ps = sumo_get_ps(old_rps);
 704         u32 nbps1_old = 0;
 705         u32 nbps1_new = 0;
 706
 707         if (old_ps != NULL)
 708                 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
 709
 710         nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
 711
 712         if (nbps1_old == 0 && nbps1_new == 1)
 713                 sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);
 714 }
 715
 716 static void sumo_enable_boost(struct radeon_device *rdev,
 717                               struct radeon_ps *rps,
 718                               bool enable)
 719 {
 720         struct sumo_ps *new_ps = sumo_get_ps(rps);
 721
 722         if (enable) {
 723                 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 724                         sumo_boost_state_enable(rdev, true);
 725         } else
 726                 sumo_boost_state_enable(rdev, false);
 727 }
 728
 729 static void sumo_set_forced_level(struct radeon_device *rdev, u32 index)
 730 {
 731         WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);
 732 }
 733
 734 static void sumo_set_forced_level_0(struct radeon_device *rdev)
 735 {
 736         sumo_set_forced_level(rdev, 0);
 737 }
 738
 739 static void sumo_program_wl(struct radeon_device *rdev,
 740                             struct radeon_ps *rps)
 741 {
 742         struct sumo_ps *new_ps = sumo_get_ps(rps);
 743         u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
 744
 745         dpm_ctrl4 &= 0xFFFFFF00;
 746         dpm_ctrl4 |= (1 << (new_ps->num_levels - 1));
 747
 748         if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 749                 dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL);
 750
 751         WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
 752 }
 753
 754 static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev,
 755                                              struct radeon_ps *new_rps,
 756                                              struct radeon_ps *old_rps)
 757 {
 758         struct sumo_power_info *pi = sumo_get_pi(rdev);
 759         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 760         struct sumo_ps *old_ps = sumo_get_ps(old_rps);
 761         u32 i;
 762         u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
 763
 764         for (i = 0; i < new_ps->num_levels; i++) {
 765                 sumo_program_power_level(rdev, &new_ps->levels[i], i);
 766                 sumo_power_level_enable(rdev, i, true);
 767         }
 768
 769         for (i = new_ps->num_levels; i < n_current_state_levels; i++)
 770                 sumo_power_level_enable(rdev, i, false);
 771
 772         if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 773                 sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL);
 774 }
 775
 776 static void sumo_enable_acpi_pm(struct radeon_device *rdev)
 777 {
 778         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
 779 }
 780
 781 static void sumo_program_power_level_enter_state(struct radeon_device *rdev)
 782 {
 783         WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK);
 784 }
 785
 786 static void sumo_program_acpi_power_level(struct radeon_device *rdev)
 787 {
 788         struct sumo_power_info *pi = sumo_get_pi(rdev);
 789         struct atom_clock_dividers dividers;
 790         int ret;
 791
 792         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 793                                              pi->acpi_pl.sclk,
 794                                              false, &dividers);
 795         if (ret)
 796                 return;
 797
 798         WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);
 799         WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN);
 800 }
 801
 802 static void sumo_program_bootup_state(struct radeon_device *rdev)
 803 {
 804         struct sumo_power_info *pi = sumo_get_pi(rdev);
 805         u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
 806         u32 i;
 807
 808         sumo_program_power_level(rdev, &pi->boot_pl, 0);
 809
 810         dpm_ctrl4 &= 0xFFFFFF00;
 811         WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
 812
 813         for (i = 1; i < 8; i++)
 814                 sumo_power_level_enable(rdev, i, false);
 815 }
 816
 817 static void sumo_setup_uvd_clocks(struct radeon_device *rdev,
 818                                   struct radeon_ps *new_rps,
 819                                   struct radeon_ps *old_rps)
 820 {
 821         struct sumo_power_info *pi = sumo_get_pi(rdev);
 822
 823         if (pi->enable_gfx_power_gating) {
 824                 sumo_gfx_powergating_enable(rdev, false);
 825         }
 826
 827         radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
 828
 829         if (pi->enable_gfx_power_gating) {
 830                 if (!pi->disable_gfx_power_gating_in_uvd ||
 831                     !r600_is_uvd_state(new_rps->class, new_rps->class2))
 832                         sumo_gfx_powergating_enable(rdev, true);
 833         }
 834 }
 835
 836 static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
 837                                                     struct radeon_ps *new_rps,
 838                                                     struct radeon_ps *old_rps)
 839 {
 840         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 841         struct sumo_ps *current_ps = sumo_get_ps(old_rps);
 842
 843         if ((new_rps->vclk == old_rps->vclk) &&
 844             (new_rps->dclk == old_rps->dclk))
 845                 return;
 846
 847         if (new_ps->levels[new_ps->num_levels - 1].sclk >=
 848             current_ps->levels[current_ps->num_levels - 1].sclk)
 849                 return;
 850
 851         sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
 852 }
 853
 854 static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
 855                                                    struct radeon_ps *new_rps,
 856                                                    struct radeon_ps *old_rps)
 857 {
 858         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 859         struct sumo_ps *current_ps = sumo_get_ps(old_rps);
 860
 861         if ((new_rps->vclk == old_rps->vclk) &&
 862             (new_rps->dclk == old_rps->dclk))
 863                 return;
 864
 865         if (new_ps->levels[new_ps->num_levels - 1].sclk <
 866             current_ps->levels[current_ps->num_levels - 1].sclk)
 867                 return;
 868
 869         sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
 870 }
 871
 872 void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
 873 {
 874 /* This bit selects who handles display phy powergating.
 875  * Clear the bit to let atom handle it.
 876  * Set it to let the driver handle it.
 877  * For now we just let atom handle it.
 878  */
 879 #if 0
 880         u32 v = RREG32(DOUT_SCRATCH3);
 881
 882         if (enable)
 883                 v |= 0x4;
 884         else
 885                 v &= 0xFFFFFFFB;
 886
 887         WREG32(DOUT_SCRATCH3, v);
 888 #endif
 889 }
 890
 891 static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
 892 {
 893         if (enable) {
 894                 u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);
 895                 u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);
 896                 u32 t = 1;
 897
 898                 deep_sleep_cntl &= ~R_DIS;
 899                 deep_sleep_cntl &= ~HS_MASK;
 900                 deep_sleep_cntl |= HS(t > 4095 ? 4095 : t);
 901
 902                 deep_sleep_cntl2 |= LB_UFP_EN;
 903                 deep_sleep_cntl2 &= INOUT_C_MASK;
 904                 deep_sleep_cntl2 |= INOUT_C(0xf);
 905
 906                 WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2);
 907                 WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl);
 908         } else
 909                 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
 910 }
 911
 912 static void sumo_program_bootup_at(struct radeon_device *rdev)
 913 {
 914         WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK);
 915         WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK);
 916 }
 917
 918 static void sumo_reset_am(struct radeon_device *rdev)
 919 {
 920         WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
 921 }
 922
 923 static void sumo_start_am(struct radeon_device *rdev)
 924 {
 925         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET);
 926 }
 927
 928 static void sumo_program_ttp(struct radeon_device *rdev)
 929 {
 930         u32 xclk = radeon_get_xclk(rdev);
 931         u32 p, u;
 932         u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
 933
 934         r600_calculate_u_and_p(1000,
 935                                xclk, 16, &p, &u);
 936
 937         cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK);
 938         cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u);
 939
 940         WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);
 941 }
 942
 943 static void sumo_program_ttt(struct radeon_device *rdev)
 944 {
 945         u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
 946         struct sumo_power_info *pi = sumo_get_pi(rdev);
 947
 948         cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK);
 949         cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49);
 950
 951         WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
 952 }
 953
 954
 955 static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)
 956 {
 957         if (enable) {
 958                 WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN);
 959                 WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN);
 960         } else {
 961                 WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN);
 962                 WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN);
 963         }
 964 }
 965
 966 static void sumo_override_cnb_thermal_events(struct radeon_device *rdev)
 967 {
 968         WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,
 969                  ~CNB_THERMTHRO_MASK_SCLK);
 970 }
 971
 972 static void sumo_program_dc_hto(struct radeon_device *rdev)
 973 {
 974         u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
 975         u32 p, u;
 976         u32 xclk = radeon_get_xclk(rdev);
 977
 978         r600_calculate_u_and_p(100000,
 979                                xclk, 14, &p, &u);
 980
 981         cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK);
 982         cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u);
 983
 984         WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4);
 985 }
 986
 987 static void sumo_force_nbp_state(struct radeon_device *rdev,
 988                                  struct radeon_ps *rps)
 989 {
 990         struct sumo_power_info *pi = sumo_get_pi(rdev);
 991         struct sumo_ps *new_ps = sumo_get_ps(rps);
 992
 993         if (!pi->driver_nbps_policy_disable) {
 994                 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
 995                         WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);
 996                 else
 997                         WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);
 998         }
 999 }
1000
1001 u32 sumo_get_sleep_divider_from_id(u32 id)
1002 {
1003         return 1 << id;
1004 }
1005
1006 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1007                                          u32 sclk,
1008                                          u32 min_sclk_in_sr)
1009 {
1010         struct sumo_power_info *pi = sumo_get_pi(rdev);
1011         u32 i;
1012         u32 temp;
1013         u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ?
1014                 min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK;
1015
1016         if (sclk < min)
1017                 return 0;
1018
1019         if (!pi->enable_sclk_ds)
1020                 return 0;
1021
1022         for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1023                 temp = sclk / sumo_get_sleep_divider_from_id(i);
1024
1025                 if (temp >= min || i == 0)
1026                         break;
1027         }
1028         return i;
1029 }
1030
1031 static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev,
1032                                        u32 lower_limit)
1033 {
1034         struct sumo_power_info *pi = sumo_get_pi(rdev);
1035         u32 i;
1036
1037         for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {
1038                 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)
1039                         return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;
1040         }
1041
1042         return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency;
1043 }
1044
1045 static void sumo_patch_thermal_state(struct radeon_device *rdev,
1046                                      struct sumo_ps *ps,
1047                                      struct sumo_ps *current_ps)
1048 {
1049         struct sumo_power_info *pi = sumo_get_pi(rdev);
1050         u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1051         u32 current_vddc;
1052         u32 current_sclk;
1053         u32 current_index = 0;
1054
1055         if (current_ps) {
1056                 current_vddc = current_ps->levels[current_index].vddc_index;
1057                 current_sclk = current_ps->levels[current_index].sclk;
1058         } else {
1059                 current_vddc = pi->boot_pl.vddc_index;
1060                 current_sclk = pi->boot_pl.sclk;
1061         }
1062
1063         ps->levels[0].vddc_index = current_vddc;
1064
1065         if (ps->levels[0].sclk > current_sclk)
1066                 ps->levels[0].sclk = current_sclk;
1067
1068         ps->levels[0].ss_divider_index =
1069                 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
1070
1071         ps->levels[0].ds_divider_index =
1072                 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1073
1074         if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)
1075                 ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;
1076
1077         if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {
1078                 if (ps->levels[0].ss_divider_index > 1)
1079                         ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;
1080         }
1081
1082         if (ps->levels[0].ss_divider_index == 0)
1083                 ps->levels[0].ds_divider_index = 0;
1084
1085         if (ps->levels[0].ds_divider_index == 0)
1086                 ps->levels[0].ss_divider_index = 0;
1087 }
1088
1089 static void sumo_apply_state_adjust_rules(struct radeon_device *rdev,
1090                                           struct radeon_ps *new_rps,
1091                                           struct radeon_ps *old_rps)
1092 {
1093         struct sumo_ps *ps = sumo_get_ps(new_rps);
1094         struct sumo_ps *current_ps = sumo_get_ps(old_rps);
1095         struct sumo_power_info *pi = sumo_get_pi(rdev);
1096         u32 min_voltage = 0; /* ??? */
1097         u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
1098         u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1099         u32 i;
1100
1101         if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1102                 return sumo_patch_thermal_state(rdev, ps, current_ps);
1103
1104         if (pi->enable_boost) {
1105                 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE)
1106                         ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE;
1107         }
1108
1109         if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) ||
1110             (new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) ||
1111             (new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE))
1112                 ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE;
1113
1114         for (i = 0; i < ps->num_levels; i++) {
1115                 if (ps->levels[i].vddc_index < min_voltage)
1116                         ps->levels[i].vddc_index = min_voltage;
1117
1118                 if (ps->levels[i].sclk < min_sclk)
1119                         ps->levels[i].sclk =
1120                                 sumo_get_valid_engine_clock(rdev, min_sclk);
1121
1122                 ps->levels[i].ss_divider_index =
1123                         sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
1124
1125                 ps->levels[i].ds_divider_index =
1126                         sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1127
1128                 if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)
1129                         ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;
1130
1131                 if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {
1132                         if (ps->levels[i].ss_divider_index > 1)
1133                                 ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;
1134                 }
1135
1136                 if (ps->levels[i].ss_divider_index == 0)
1137                         ps->levels[i].ds_divider_index = 0;
1138
1139                 if (ps->levels[i].ds_divider_index == 0)
1140                         ps->levels[i].ss_divider_index = 0;
1141
1142                 if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
1143                         ps->levels[i].allow_gnb_slow = 1;
1144                 else if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) ||
1145                          (new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC))
1146                         ps->levels[i].allow_gnb_slow = 0;
1147                 else if (i == ps->num_levels - 1)
1148                         ps->levels[i].allow_gnb_slow = 0;
1149                 else
1150                         ps->levels[i].allow_gnb_slow = 1;
1151         }
1152 }
1153
1154 static void sumo_cleanup_asic(struct radeon_device *rdev)
1155 {
1156         sumo_take_smu_control(rdev, false);
1157 }
1158
1159 static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
1160                                               int min_temp, int max_temp)
1161 {
1162         int low_temp = 0 * 1000;
1163         int high_temp = 255 * 1000;
1164
1165         if (low_temp < min_temp)
1166                 low_temp = min_temp;
1167         if (high_temp > max_temp)
1168                 high_temp = max_temp;
1169         if (high_temp < low_temp) {
1170                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1171                 return -EINVAL;
1172         }
1173
1174         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
1175         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
1176
1177         rdev->pm.dpm.thermal.min_temp = low_temp;
1178         rdev->pm.dpm.thermal.max_temp = high_temp;
1179
1180         return 0;
1181 }
1182
1183 static void sumo_update_current_ps(struct radeon_device *rdev,
1184                                    struct radeon_ps *rps)
1185 {
1186         struct sumo_ps *new_ps = sumo_get_ps(rps);
1187         struct sumo_power_info *pi = sumo_get_pi(rdev);
1188
1189         pi->current_rps = *rps;
1190         pi->current_ps = *new_ps;
1191         pi->current_rps.ps_priv = &pi->current_ps;
1192 }
1193
1194 static void sumo_update_requested_ps(struct radeon_device *rdev,
1195                                      struct radeon_ps *rps)
1196 {
1197         struct sumo_ps *new_ps = sumo_get_ps(rps);
1198         struct sumo_power_info *pi = sumo_get_pi(rdev);
1199
1200         pi->requested_rps = *rps;
1201         pi->requested_ps = *new_ps;
1202         pi->requested_rps.ps_priv = &pi->requested_ps;
1203 }
1204
1205 int sumo_dpm_enable(struct radeon_device *rdev)
1206 {
1207         struct sumo_power_info *pi = sumo_get_pi(rdev);
1208
1209         if (sumo_dpm_enabled(rdev))
1210                 return -EINVAL;
1211
1212         sumo_program_bootup_state(rdev);
1213         sumo_init_bsp(rdev);
1214         sumo_reset_am(rdev);
1215         sumo_program_tp(rdev);
1216         sumo_program_bootup_at(rdev);
1217         sumo_start_am(rdev);
1218         if (pi->enable_auto_thermal_throttling) {
1219                 sumo_program_ttp(rdev);
1220                 sumo_program_ttt(rdev);
1221         }
1222         sumo_program_dc_hto(rdev);
1223         sumo_program_power_level_enter_state(rdev);
1224         sumo_enable_voltage_scaling(rdev, true);
1225         sumo_program_sstp(rdev);
1226         sumo_program_vc(rdev, SUMO_VRC_DFLT);
1227         sumo_override_cnb_thermal_events(rdev);
1228         sumo_start_dpm(rdev);
1229         sumo_wait_for_level_0(rdev);
1230         if (pi->enable_sclk_ds)
1231                 sumo_enable_sclk_ds(rdev, true);
1232         if (pi->enable_boost)
1233                 sumo_enable_boost_timer(rdev);
1234
1235         sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1236
1237         return 0;
1238 }
1239
1240 int sumo_dpm_late_enable(struct radeon_device *rdev)
1241 {
1242         int ret;
1243
1244         ret = sumo_enable_clock_power_gating(rdev);
1245         if (ret)
1246                 return ret;
1247
1248         if (rdev->irq.installed &&
1249             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1250                 ret = sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1251                 if (ret)
1252                         return ret;
1253                 rdev->irq.dpm_thermal = true;
1254                 radeon_irq_set(rdev);
1255         }
1256
1257         return 0;
1258 }
1259
1260 void sumo_dpm_disable(struct radeon_device *rdev)
1261 {
1262         struct sumo_power_info *pi = sumo_get_pi(rdev);
1263
1264         if (!sumo_dpm_enabled(rdev))
1265                 return;
1266         sumo_disable_clock_power_gating(rdev);
1267         if (pi->enable_sclk_ds)
1268                 sumo_enable_sclk_ds(rdev, false);
1269         sumo_clear_vc(rdev);
1270         sumo_wait_for_level_0(rdev);
1271         sumo_stop_dpm(rdev);
1272         sumo_enable_voltage_scaling(rdev, false);
1273
1274         if (rdev->irq.installed &&
1275             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1276                 rdev->irq.dpm_thermal = false;
1277                 radeon_irq_set(rdev);
1278         }
1279
1280         sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1281 }
1282
1283 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev)
1284 {
1285         struct sumo_power_info *pi = sumo_get_pi(rdev);
1286         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1287         struct radeon_ps *new_ps = &requested_ps;
1288
1289         sumo_update_requested_ps(rdev, new_ps);
1290
1291         if (pi->enable_dynamic_patch_ps)
1292                 sumo_apply_state_adjust_rules(rdev,
1293                                               &pi->requested_rps,
1294                                               &pi->current_rps);
1295
1296         return 0;
1297 }
1298
1299 int sumo_dpm_set_power_state(struct radeon_device *rdev)
1300 {
1301         struct sumo_power_info *pi = sumo_get_pi(rdev);
1302         struct radeon_ps *new_ps = &pi->requested_rps;
1303         struct radeon_ps *old_ps = &pi->current_rps;
1304
1305         if (pi->enable_dpm)
1306                 sumo_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1307         if (pi->enable_boost) {
1308                 sumo_enable_boost(rdev, new_ps, false);
1309                 sumo_patch_boost_state(rdev, new_ps);
1310         }
1311         if (pi->enable_dpm) {
1312                 sumo_pre_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1313                 sumo_enable_power_level_0(rdev);
1314                 sumo_set_forced_level_0(rdev);
1315                 sumo_set_forced_mode_enabled(rdev);
1316                 sumo_wait_for_level_0(rdev);
1317                 sumo_program_power_levels_0_to_n(rdev, new_ps, old_ps);
1318                 sumo_program_wl(rdev, new_ps);
1319                 sumo_program_bsp(rdev, new_ps);
1320                 sumo_program_at(rdev, new_ps);
1321                 sumo_force_nbp_state(rdev, new_ps);
1322                 sumo_set_forced_mode_disabled(rdev);
1323                 sumo_set_forced_mode_enabled(rdev);
1324                 sumo_set_forced_mode_disabled(rdev);
1325                 sumo_post_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1326         }
1327         if (pi->enable_boost)
1328                 sumo_enable_boost(rdev, new_ps, true);
1329         if (pi->enable_dpm)
1330                 sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1331
1332         return 0;
1333 }
1334
1335 void sumo_dpm_post_set_power_state(struct radeon_device *rdev)
1336 {
1337         struct sumo_power_info *pi = sumo_get_pi(rdev);
1338         struct radeon_ps *new_ps = &pi->requested_rps;
1339
1340         sumo_update_current_ps(rdev, new_ps);
1341 }
1342
1343 #if 0
1344 void sumo_dpm_reset_asic(struct radeon_device *rdev)
1345 {
1346         sumo_program_bootup_state(rdev);
1347         sumo_enable_power_level_0(rdev);
1348         sumo_set_forced_level_0(rdev);
1349         sumo_set_forced_mode_enabled(rdev);
1350         sumo_wait_for_level_0(rdev);
1351         sumo_set_forced_mode_disabled(rdev);
1352         sumo_set_forced_mode_enabled(rdev);
1353         sumo_set_forced_mode_disabled(rdev);
1354 }
1355 #endif
1356
1357 void sumo_dpm_setup_asic(struct radeon_device *rdev)
1358 {
1359         struct sumo_power_info *pi = sumo_get_pi(rdev);
1360
1361         sumo_initialize_m3_arb(rdev);
1362         pi->fw_version = sumo_get_running_fw_version(rdev);
1363         DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version);
1364         sumo_program_acpi_power_level(rdev);
1365         sumo_enable_acpi_pm(rdev);
1366         sumo_take_smu_control(rdev, true);
1367 }
1368
1369 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev)
1370 {
1371
1372 }
1373
1374 union power_info {
1375         struct _ATOM_POWERPLAY_INFO info;
1376         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1377         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1378         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1379         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1380         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1381 };
1382
1383 union pplib_clock_info {
1384         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1385         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1386         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1387         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1388 };
1389
1390 union pplib_power_state {
1391         struct _ATOM_PPLIB_STATE v1;
1392         struct _ATOM_PPLIB_STATE_V2 v2;
1393 };
1394
1395 static void sumo_patch_boot_state(struct radeon_device *rdev,
1396                                   struct sumo_ps *ps)
1397 {
1398         struct sumo_power_info *pi = sumo_get_pi(rdev);
1399
1400         ps->num_levels = 1;
1401         ps->flags = 0;
1402         ps->levels[0] = pi->boot_pl;
1403 }
1404
1405 static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev,
1406                                             struct radeon_ps *rps,
1407                                             struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
1408                                             u8 table_rev)
1409 {
1410         struct sumo_ps *ps = sumo_get_ps(rps);
1411
1412         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1413         rps->class = le16_to_cpu(non_clock_info->usClassification);
1414         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1415
1416         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
1417                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
1418                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1419         } else {
1420                 rps->vclk = 0;
1421                 rps->dclk = 0;
1422         }
1423
1424         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1425                 rdev->pm.dpm.boot_ps = rps;
1426                 sumo_patch_boot_state(rdev, ps);
1427         }
1428         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1429                 rdev->pm.dpm.uvd_ps = rps;
1430 }
1431
1432 static void sumo_parse_pplib_clock_info(struct radeon_device *rdev,
1433                                         struct radeon_ps *rps, int index,
1434                                         union pplib_clock_info *clock_info)
1435 {
1436         struct sumo_power_info *pi = sumo_get_pi(rdev);
1437         struct sumo_ps *ps = sumo_get_ps(rps);
1438         struct sumo_pl *pl = &ps->levels[index];
1439         u32 sclk;
1440
1441         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
1442         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
1443         pl->sclk = sclk;
1444         pl->vddc_index = clock_info->sumo.vddcIndex;
1445         pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit;
1446
1447         ps->num_levels = index + 1;
1448
1449         if (pi->enable_sclk_ds) {
1450                 pl->ds_divider_index = 5;
1451                 pl->ss_divider_index = 4;
1452         }
1453 }
1454
1455 static int sumo_parse_power_table(struct radeon_device *rdev)
1456 {
1457         struct radeon_mode_info *mode_info = &rdev->mode_info;
1458         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1459         union pplib_power_state *power_state;
1460         int i, j, k, non_clock_array_index, clock_array_index;
1461         union pplib_clock_info *clock_info;
1462         struct _StateArray *state_array;
1463         struct _ClockInfoArray *clock_info_array;
1464         struct _NonClockInfoArray *non_clock_info_array;
1465         union power_info *power_info;
1466         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1467         u16 data_offset;
1468         u8 frev, crev;
1469         u8 *power_state_offset;
1470         struct sumo_ps *ps;
1471
1472         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1473                                    &frev, &crev, &data_offset))
1474                 return -EINVAL;
1475         power_info = (union power_info *)((uint8_t*)mode_info->atom_context->bios + data_offset);
1476
1477         state_array = (struct _StateArray *)
1478                 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1479                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
1480         clock_info_array = (struct _ClockInfoArray *)
1481                 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1482                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
1483         non_clock_info_array = (struct _NonClockInfoArray *)
1484                 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1485                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
1486
1487         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
1488                                   state_array->ucNumEntries, GFP_KERNEL);
1489         if (!rdev->pm.dpm.ps)
1490                 return -ENOMEM;
1491         power_state_offset = (u8 *)state_array->states;
1492         for (i = 0; i < state_array->ucNumEntries; i++) {
1493                 u8 *idx;
1494                 power_state = (union pplib_power_state *)power_state_offset;
1495                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
1496                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1497                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
1498                 if (!rdev->pm.power_state[i].clock_info)
1499                         return -EINVAL;
1500                 ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
1501                 if (ps == NULL) {
1502                         kfree(rdev->pm.dpm.ps);
1503                         return -ENOMEM;
1504                 }
1505                 rdev->pm.dpm.ps[i].ps_priv = ps;
1506                 k = 0;
1507                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
1508                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
1509                         clock_array_index = idx[j];
1510                         if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
1511                                 break;
1512
1513                         clock_info = (union pplib_clock_info *)
1514                                 ((u8 *)&clock_info_array->clockInfo[0] +
1515                                  (clock_array_index * clock_info_array->ucEntrySize));
1516                         sumo_parse_pplib_clock_info(rdev,
1517                                                     &rdev->pm.dpm.ps[i], k,
1518                                                     clock_info);
1519                         k++;
1520                 }
1521                 sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1522                                                 non_clock_info,
1523                                                 non_clock_info_array->ucEntrySize);
1524                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
1525         }
1526         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
1527         return 0;
1528 }
1529
1530 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
1531                               struct sumo_vid_mapping_table *vid_mapping_table,
1532                               u32 vid_2bit)
1533 {
1534         u32 i;
1535
1536         for (i = 0; i < vid_mapping_table->num_entries; i++) {
1537                 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
1538                         return vid_mapping_table->entries[i].vid_7bit;
1539         }
1540
1541         return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
1542 }
1543
1544 #if 0
1545 u32 sumo_convert_vid7_to_vid2(struct radeon_device *rdev,
1546                               struct sumo_vid_mapping_table *vid_mapping_table,
1547                               u32 vid_7bit)
1548 {
1549         u32 i;
1550
1551         for (i = 0; i < vid_mapping_table->num_entries; i++) {
1552                 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
1553                         return vid_mapping_table->entries[i].vid_2bit;
1554         }
1555
1556         return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
1557 }
1558 #endif
1559
1560 static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev,
1561                                                u32 vid_2bit)
1562 {
1563         struct sumo_power_info *pi = sumo_get_pi(rdev);
1564         u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
1565
1566         if (vid_7bit > 0x7C)
1567                 return 0;
1568
1569         return (15500 - vid_7bit * 125 + 5) / 10;
1570 }
1571
1572 static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev,
1573                                                          struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table,
1574                                                          ATOM_CLK_VOLT_CAPABILITY *table)
1575 {
1576         u32 i;
1577
1578         for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1579                 if (table[i].ulMaximumSupportedCLK == 0)
1580                         break;
1581
1582                 disp_clk_voltage_mapping_table->display_clock_frequency[i] =
1583                         table[i].ulMaximumSupportedCLK;
1584         }
1585
1586         disp_clk_voltage_mapping_table->num_max_voltage_levels = i;
1587
1588         if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) {
1589                 disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000;
1590                 disp_clk_voltage_mapping_table->num_max_voltage_levels = 1;
1591         }
1592 }
1593
1594 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
1595                                                struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
1596                                                ATOM_AVAILABLE_SCLK_LIST *table)
1597 {
1598         u32 i;
1599         u32 n = 0;
1600         u32 prev_sclk = 0;
1601
1602         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1603                 if (table[i].ulSupportedSCLK > prev_sclk) {
1604                         sclk_voltage_mapping_table->entries[n].sclk_frequency =
1605                                 table[i].ulSupportedSCLK;
1606                         sclk_voltage_mapping_table->entries[n].vid_2bit =
1607                                 table[i].usVoltageIndex;
1608                         prev_sclk = table[i].ulSupportedSCLK;
1609                         n++;
1610                 }
1611         }
1612
1613         sclk_voltage_mapping_table->num_max_dpm_entries = n;
1614 }
1615
1616 void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
1617                                       struct sumo_vid_mapping_table *vid_mapping_table,
1618                                       ATOM_AVAILABLE_SCLK_LIST *table)
1619 {
1620         u32 i, j;
1621
1622         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1623                 if (table[i].ulSupportedSCLK != 0) {
1624                         vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
1625                                 table[i].usVoltageID;
1626                         vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
1627                                 table[i].usVoltageIndex;
1628                 }
1629         }
1630
1631         for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1632                 if (vid_mapping_table->entries[i].vid_7bit == 0) {
1633                         for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
1634                                 if (vid_mapping_table->entries[j].vid_7bit != 0) {
1635                                         vid_mapping_table->entries[i] =
1636                                                 vid_mapping_table->entries[j];
1637                                         vid_mapping_table->entries[j].vid_7bit = 0;
1638                                         break;
1639                                 }
1640                         }
1641
1642                         if (j == SUMO_MAX_NUMBER_VOLTAGES)
1643                                 break;
1644                 }
1645         }
1646
1647         vid_mapping_table->num_entries = i;
1648 }
1649
1650 union igp_info {
1651         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1652         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1653         struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
1654         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1655 };
1656
1657 static int sumo_parse_sys_info_table(struct radeon_device *rdev)
1658 {
1659         struct sumo_power_info *pi = sumo_get_pi(rdev);
1660         struct radeon_mode_info *mode_info = &rdev->mode_info;
1661         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1662         union igp_info *igp_info;
1663         u8 frev, crev;
1664         u16 data_offset;
1665         int i;
1666
1667         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1668                                    &frev, &crev, &data_offset)) {
1669                 igp_info = (union igp_info *)((uint8_t*)mode_info->atom_context->bios +
1670                                               data_offset);
1671
1672                 if (crev != 6) {
1673                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1674                         return -EINVAL;
1675                 }
1676                 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock);
1677                 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock);
1678                 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock);
1679                 pi->sys_info.bootup_nb_voltage_index =
1680                         le16_to_cpu(igp_info->info_6.usBootUpNBVoltage);
1681                 if (igp_info->info_6.ucHtcTmpLmt == 0)
1682                         pi->sys_info.htc_tmp_lmt = 203;
1683                 else
1684                         pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt;
1685                 if (igp_info->info_6.ucHtcHystLmt == 0)
1686                         pi->sys_info.htc_hyst_lmt = 5;
1687                 else
1688                         pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt;
1689                 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
1690                         DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
1691                 }
1692                 for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) {
1693                         pi->sys_info.csr_m3_arb_cntl_default[i] =
1694                                 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]);
1695                         pi->sys_info.csr_m3_arb_cntl_uvd[i] =
1696                                 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]);
1697                         pi->sys_info.csr_m3_arb_cntl_fs3d[i] =
1698                                 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]);
1699                 }
1700                 pi->sys_info.sclk_dpm_boost_margin =
1701                         le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin);
1702                 pi->sys_info.sclk_dpm_throttle_margin =
1703                         le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin);
1704                 pi->sys_info.sclk_dpm_tdp_limit_pg =
1705                         le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG);
1706                 pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit);
1707                 pi->sys_info.sclk_dpm_tdp_limit_boost =
1708                         le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost);
1709                 pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock);
1710                 pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit;
1711                 if (igp_info->info_6.EnableBoost)
1712                         pi->sys_info.enable_boost = true;
1713                 else
1714                         pi->sys_info.enable_boost = false;
1715                 sumo_construct_display_voltage_mapping_table(rdev,
1716                                                              &pi->sys_info.disp_clk_voltage_mapping_table,
1717                                                              igp_info->info_6.sDISPCLK_Voltage);
1718                 sumo_construct_sclk_voltage_mapping_table(rdev,
1719                                                           &pi->sys_info.sclk_voltage_mapping_table,
1720                                                           igp_info->info_6.sAvail_SCLK);
1721                 sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
1722                                                  igp_info->info_6.sAvail_SCLK);
1723
1724         }
1725         return 0;
1726 }
1727
1728 static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev)
1729 {
1730         struct sumo_power_info *pi = sumo_get_pi(rdev);
1731
1732         pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1733         pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1734         pi->boot_pl.ds_divider_index = 0;
1735         pi->boot_pl.ss_divider_index = 0;
1736         pi->boot_pl.allow_gnb_slow = 1;
1737         pi->acpi_pl = pi->boot_pl;
1738         pi->current_ps.num_levels = 1;
1739         pi->current_ps.levels[0] = pi->boot_pl;
1740 }
1741
1742 int sumo_dpm_init(struct radeon_device *rdev)
1743 {
1744         struct sumo_power_info *pi;
1745         u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
1746         int ret;
1747
1748         pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL);
1749         if (pi == NULL)
1750                 return -ENOMEM;
1751         rdev->pm.dpm.priv = pi;
1752
1753         pi->driver_nbps_policy_disable = false;
1754         if ((rdev->family == CHIP_PALM) && (hw_rev < 3))
1755                 pi->disable_gfx_power_gating_in_uvd = true;
1756         else
1757                 pi->disable_gfx_power_gating_in_uvd = false;
1758         pi->enable_alt_vddnb = true;
1759         pi->enable_sclk_ds = true;
1760         pi->enable_dynamic_m3_arbiter = false;
1761         pi->enable_dynamic_patch_ps = true;
1762         /* Some PALM chips don't seem to properly ungate gfx when UVD is in use;
1763          * for now just disable gfx PG.
1764          */
1765         if (rdev->family == CHIP_PALM)
1766                 pi->enable_gfx_power_gating = false;
1767         else
1768                 pi->enable_gfx_power_gating = true;
1769         pi->enable_gfx_clock_gating = true;
1770         pi->enable_mg_clock_gating = true;
1771         pi->enable_auto_thermal_throttling = true;
1772
1773         ret = sumo_parse_sys_info_table(rdev);
1774         if (ret)
1775                 return ret;
1776
1777         sumo_construct_boot_and_acpi_state(rdev);
1778
1779         ret = r600_get_platform_caps(rdev);
1780         if (ret)
1781                 return ret;
1782
1783         ret = sumo_parse_power_table(rdev);
1784         if (ret)
1785                 return ret;
1786
1787         pi->pasi = CYPRESS_HASI_DFLT;
1788         pi->asi = RV770_ASI_DFLT;
1789         pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;
1790         pi->enable_boost = pi->sys_info.enable_boost;
1791         pi->enable_dpm = true;
1792
1793         return 0;
1794 }
1795
1796 void sumo_dpm_print_power_state(struct radeon_device *rdev,
1797                                 struct radeon_ps *rps)
1798 {
1799         int i;
1800         struct sumo_ps *ps = sumo_get_ps(rps);
1801
1802         r600_dpm_print_class_info(rps->class, rps->class2);
1803         r600_dpm_print_cap_info(rps->caps);
1804         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1805         for (i = 0; i < ps->num_levels; i++) {
1806                 struct sumo_pl *pl = &ps->levels[i];
1807                 printk("\t\tpower level %d    sclk: %u vddc: %u\n",
1808                        i, pl->sclk,
1809                        sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1810         }
1811         r600_dpm_print_ps_status(rdev, rps);
1812 }
1813
1814 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
1815                                                       struct seq_file *m)
1816 {
1817         struct sumo_power_info *pi = sumo_get_pi(rdev);
1818         struct radeon_ps *rps = &pi->current_rps;
1819         struct sumo_ps *ps = sumo_get_ps(rps);
1820         struct sumo_pl *pl;
1821         u32 current_index =
1822                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
1823                 CURR_INDEX_SHIFT;
1824
1825         if (current_index == BOOST_DPM_LEVEL) {
1826                 pl = &pi->boost_pl;
1827                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1828                 seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
1829                            current_index, pl->sclk,
1830                            sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1831         } else if (current_index >= ps->num_levels) {
1832                 seq_printf(m, "invalid dpm profile %d\n", current_index);
1833         } else {
1834                 pl = &ps->levels[current_index];
1835                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1836                 seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
1837                            current_index, pl->sclk,
1838                            sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1839         }
1840 }
1841
1842 u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev)
1843 {
1844         struct sumo_power_info *pi = sumo_get_pi(rdev);
1845         struct radeon_ps *rps = &pi->current_rps;
1846         struct sumo_ps *ps = sumo_get_ps(rps);
1847         struct sumo_pl *pl;
1848         u32 current_index =
1849                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
1850                 CURR_INDEX_SHIFT;
1851
1852         if (current_index == BOOST_DPM_LEVEL) {
1853                 pl = &pi->boost_pl;
1854                 return pl->sclk;
1855         } else if (current_index >= ps->num_levels) {
1856                 return 0;
1857         } else {
1858                 pl = &ps->levels[current_index];
1859                 return pl->sclk;
1860         }
1861 }
1862
1863 u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev)
1864 {
1865         struct sumo_power_info *pi = sumo_get_pi(rdev);
1866
1867         return pi->sys_info.bootup_uma_clk;
1868 }
1869
1870 void sumo_dpm_fini(struct radeon_device *rdev)
1871 {
1872         int i;
1873
1874         sumo_cleanup_asic(rdev); /* ??? */
1875
1876         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1877                 kfree(rdev->pm.dpm.ps[i].ps_priv);
1878         }
1879         kfree(rdev->pm.dpm.ps);
1880         kfree(rdev->pm.dpm.priv);
1881 }
1882
1883 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)
1884 {
1885         struct sumo_power_info *pi = sumo_get_pi(rdev);
1886         struct sumo_ps *requested_state = sumo_get_ps(&pi->requested_rps);
1887
1888         if (low)
1889                 return requested_state->levels[0].sclk;
1890         else
1891                 return requested_state->levels[requested_state->num_levels - 1].sclk;
1892 }
1893
1894 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)
1895 {
1896         struct sumo_power_info *pi = sumo_get_pi(rdev);
1897
1898         return pi->sys_info.bootup_uma_clk;
1899 }
1900
1901 int sumo_dpm_force_performance_level(struct radeon_device *rdev,
1902                                      enum radeon_dpm_forced_level level)
1903 {
1904         struct sumo_power_info *pi = sumo_get_pi(rdev);
1905         struct radeon_ps *rps = &pi->current_rps;
1906         struct sumo_ps *ps = sumo_get_ps(rps);
1907         int i;
1908
1909         if (ps->num_levels <= 1)
1910                 return 0;
1911
1912         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1913                 if (pi->enable_boost)
1914                         sumo_enable_boost(rdev, rps, false);
1915                 sumo_power_level_enable(rdev, ps->num_levels - 1, true);
1916                 sumo_set_forced_level(rdev, ps->num_levels - 1);
1917                 sumo_set_forced_mode_enabled(rdev);
1918                 for (i = 0; i < ps->num_levels - 1; i++) {
1919                         sumo_power_level_enable(rdev, i, false);
1920                 }
1921                 sumo_set_forced_mode(rdev, false);
1922                 sumo_set_forced_mode_enabled(rdev);
1923                 sumo_set_forced_mode(rdev, false);
1924         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1925                 if (pi->enable_boost)
1926                         sumo_enable_boost(rdev, rps, false);
1927                 sumo_power_level_enable(rdev, 0, true);
1928                 sumo_set_forced_level(rdev, 0);
1929                 sumo_set_forced_mode_enabled(rdev);
1930                 for (i = 1; i < ps->num_levels; i++) {
1931                         sumo_power_level_enable(rdev, i, false);
1932                 }
1933                 sumo_set_forced_mode(rdev, false);
1934                 sumo_set_forced_mode_enabled(rdev);
1935                 sumo_set_forced_mode(rdev, false);
1936         } else {
1937                 for (i = 0; i < ps->num_levels; i++) {
1938                         sumo_power_level_enable(rdev, i, true);
1939                 }
1940                 if (pi->enable_boost)
1941                         sumo_enable_boost(rdev, rps, true);
1942         }
1943
1944         rdev->pm.dpm.forced_level = level;
1945
1946         return 0;
1947 }