2 * Copyright (c) 1999 Michael Smith <msmith@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/param.h>
28 #include <sys/kernel.h>
29 #include <sys/systm.h>
30 #include <sys/malloc.h>
31 #include <sys/memrange.h>
32 #include <sys/sysctl.h>
33 #include <sys/thread.h>
36 #include <vm/vm_param.h>
39 #include <sys/thread2.h>
41 #include <machine/cputypes.h>
42 #include <machine/md_var.h>
43 #include <machine/specialreg.h>
44 #include <machine/smp.h>
47 * amd64 memory range operations
49 * This code will probably be impenetrable without reference to the
50 * Intel Pentium Pro documentation or x86-64 programmers manual vol 2.
53 static char *mem_owner_bios = "BIOS";
55 #define MR686_FIXMTRR (1<<0)
57 #define mrwithin(mr, a) \
58 (((a) >= (mr)->mr_base) && ((a) < ((mr)->mr_base + (mr)->mr_len)))
59 #define mroverlap(mra, mrb) \
60 (mrwithin(mra, mrb->mr_base) || mrwithin(mrb, mra->mr_base))
62 #define mrvalid(base, len) \
63 ((!(base & ((1 << 12) - 1))) && /* base is multiple of 4k */ \
64 ((len) >= (1 << 12)) && /* length is >= 4k */ \
65 powerof2((len)) && /* ... and power of two */ \
66 !((base) & ((len) - 1))) /* range is not discontiuous */
68 #define mrcopyflags(curr, new) \
69 (((curr) & ~MDF_ATTRMASK) | ((new) & MDF_ATTRMASK))
71 static int mtrrs_disabled;
72 TUNABLE_INT("machdep.disable_mtrrs", &mtrrs_disabled);
73 SYSCTL_INT(_machdep, OID_AUTO, disable_mtrrs, CTLFLAG_RD,
74 &mtrrs_disabled, 0, "Disable amd64 MTRRs.");
76 static void amd64_mrinit(struct mem_range_softc *sc);
77 static int amd64_mrset(struct mem_range_softc *sc,
78 struct mem_range_desc *mrd, int *arg);
79 static void amd64_mrAPinit(struct mem_range_softc *sc);
80 static void amd64_mrreinit(struct mem_range_softc *sc);
82 static struct mem_range_ops amd64_mrops = {
89 /* XXX for AP startup hook */
90 static u_int64_t mtrrcap, mtrrdef;
92 /* The bitmask for the PhysBase and PhysMask fields of the variable MTRRs. */
93 static u_int64_t mtrr_physmask;
95 static struct mem_range_desc *mem_range_match(struct mem_range_softc *sc,
96 struct mem_range_desc *mrd);
97 static void amd64_mrfetch(struct mem_range_softc *sc);
98 static int amd64_mtrrtype(int flags);
99 static int amd64_mrt2mtrr(int flags, int oldval);
100 static int amd64_mtrrconflict(int flag1, int flag2);
101 static void amd64_mrstore(struct mem_range_softc *sc);
102 static void amd64_mrstoreone(void *arg);
103 static struct mem_range_desc *amd64_mtrrfixsearch(struct mem_range_softc *sc,
105 static int amd64_mrsetlow(struct mem_range_softc *sc,
106 struct mem_range_desc *mrd, int *arg);
107 static int amd64_mrsetvariable(struct mem_range_softc *sc,
108 struct mem_range_desc *mrd, int *arg);
110 /* amd64 MTRR type to memory range type conversion */
111 static int amd64_mtrrtomrt[] = {
121 #define MTRRTOMRTLEN NELEM(amd64_mtrrtomrt)
124 amd64_mtrr2mrt(int val)
127 if (val < 0 || val >= MTRRTOMRTLEN)
128 return (MDF_UNKNOWN);
129 return (amd64_mtrrtomrt[val]);
133 * amd64 MTRR conflicts. Writeback and uncachable may overlap.
136 amd64_mtrrconflict(int flag1, int flag2)
139 flag1 &= MDF_ATTRMASK;
140 flag2 &= MDF_ATTRMASK;
141 if ((flag1 & MDF_UNKNOWN) || (flag2 & MDF_UNKNOWN))
143 if (flag1 == flag2 ||
144 (flag1 == MDF_WRITEBACK && flag2 == MDF_UNCACHEABLE) ||
145 (flag2 == MDF_WRITEBACK && flag1 == MDF_UNCACHEABLE))
151 * Look for an exactly-matching range.
153 static struct mem_range_desc *
154 mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd)
156 struct mem_range_desc *cand;
159 for (i = 0, cand = sc->mr_desc; i < sc->mr_ndesc; i++, cand++)
160 if ((cand->mr_base == mrd->mr_base) &&
161 (cand->mr_len == mrd->mr_len))
167 * Fetch the current mtrr settings from the current CPU (assumed to
168 * all be in sync in the SMP case). Note that if we are here, we
169 * assume that MTRRs are enabled, and we may or may not have fixed
173 amd64_mrfetch(struct mem_range_softc *sc)
175 struct mem_range_desc *mrd;
181 /* Get fixed-range MTRRs. */
182 if (sc->mr_cap & MR686_FIXMTRR) {
183 msr = MSR_MTRR64kBase;
184 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
186 for (j = 0; j < 8; j++, mrd++) {
188 (mrd->mr_flags & ~MDF_ATTRMASK) |
189 amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
190 if (mrd->mr_owner[0] == 0)
191 strcpy(mrd->mr_owner, mem_owner_bios);
195 msr = MSR_MTRR16kBase;
196 for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
198 for (j = 0; j < 8; j++, mrd++) {
200 (mrd->mr_flags & ~MDF_ATTRMASK) |
201 amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
202 if (mrd->mr_owner[0] == 0)
203 strcpy(mrd->mr_owner, mem_owner_bios);
207 msr = MSR_MTRR4kBase;
208 for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
210 for (j = 0; j < 8; j++, mrd++) {
212 (mrd->mr_flags & ~MDF_ATTRMASK) |
213 amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
214 if (mrd->mr_owner[0] == 0)
215 strcpy(mrd->mr_owner, mem_owner_bios);
221 /* Get remainder which must be variable MTRRs. */
222 msr = MSR_MTRRVarBase;
223 for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
225 mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) |
226 amd64_mtrr2mrt(msrv & MTRR_PHYSBASE_TYPE);
227 mrd->mr_base = msrv & mtrr_physmask;
228 msrv = rdmsr(msr + 1);
229 mrd->mr_flags = (msrv & MTRR_PHYSMASK_VALID) ?
230 (mrd->mr_flags | MDF_ACTIVE) :
231 (mrd->mr_flags & ~MDF_ACTIVE);
233 /* Compute the range from the mask. Ick. */
234 mrd->mr_len = (~(msrv & mtrr_physmask) &
235 (mtrr_physmask | 0xfffL)) + 1;
236 if (!mrvalid(mrd->mr_base, mrd->mr_len))
237 mrd->mr_flags |= MDF_BOGUS;
239 /* If unclaimed and active, must be the BIOS. */
240 if ((mrd->mr_flags & MDF_ACTIVE) && (mrd->mr_owner[0] == 0))
241 strcpy(mrd->mr_owner, mem_owner_bios);
246 * Return the MTRR memory type matching a region's flags
249 amd64_mtrrtype(int flags)
253 flags &= MDF_ATTRMASK;
255 for (i = 0; i < MTRRTOMRTLEN; i++) {
256 if (amd64_mtrrtomrt[i] == MDF_UNKNOWN)
258 if (flags == amd64_mtrrtomrt[i])
265 amd64_mrt2mtrr(int flags, int oldval)
269 if ((val = amd64_mtrrtype(flags)) == -1)
270 return (oldval & 0xff);
275 * Update running CPU(s) MTRRs to match the ranges in the descriptor
278 * XXX Must be called with interrupts enabled.
281 amd64_mrstore(struct mem_range_softc *sc)
284 * We should use ipi_all_but_self() to call other CPUs into a
285 * locking gate, then call a target function to do this work.
286 * The "proper" solution involves a generalised locking gate
287 * implementation, not ready yet.
289 lwkt_send_ipiq_mask(smp_active_mask, (void *)amd64_mrstoreone, sc);
293 * Update the current CPU's MTRRs with those represented in the
294 * descriptor list. Note that we do this wholesale rather than just
295 * stuffing one entry; this is simpler (but slower, of course).
298 amd64_mrstoreone(void *arg)
300 struct mem_range_softc *sc = arg;
301 struct mem_range_desc *mrd;
302 u_int64_t omsrv, msrv;
312 load_cr4(cr4 & ~CR4_PGE);
314 /* Disable caches (CD = 1, NW = 0). */
316 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
318 /* Flushes caches and TLBs. */
322 /* Disable MTRRs (E = 0). */
323 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE);
325 /* Set fixed-range MTRRs. */
326 if (sc->mr_cap & MR686_FIXMTRR) {
327 msr = MSR_MTRR64kBase;
328 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
331 for (j = 7; j >= 0; j--) {
333 msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags,
339 msr = MSR_MTRR16kBase;
340 for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
343 for (j = 7; j >= 0; j--) {
345 msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags,
351 msr = MSR_MTRR4kBase;
352 for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
355 for (j = 7; j >= 0; j--) {
357 msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags,
365 /* Set remainder which must be variable MTRRs. */
366 msr = MSR_MTRRVarBase;
367 for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
368 /* base/type register */
370 if (mrd->mr_flags & MDF_ACTIVE) {
371 msrv = mrd->mr_base & mtrr_physmask;
372 msrv |= amd64_mrt2mtrr(mrd->mr_flags, omsrv);
378 /* mask/active register */
379 if (mrd->mr_flags & MDF_ACTIVE) {
380 msrv = MTRR_PHYSMASK_VALID |
381 rounddown2(mtrr_physmask, mrd->mr_len);
385 wrmsr(msr + 1, msrv);
388 /* Flush caches and TLBs. */
393 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
395 /* Restore caches and PGE. */
403 * Hunt for the fixed MTRR referencing (addr)
405 static struct mem_range_desc *
406 amd64_mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr)
408 struct mem_range_desc *mrd;
411 for (i = 0, mrd = sc->mr_desc; i < (MTRR_N64K + MTRR_N16K + MTRR_N4K);
413 if ((addr >= mrd->mr_base) &&
414 (addr < (mrd->mr_base + mrd->mr_len)))
420 * Try to satisfy the given range request by manipulating the fixed
421 * MTRRs that cover low memory.
423 * Note that we try to be generous here; we'll bloat the range out to
424 * the next higher/lower boundary to avoid the consumer having to know
425 * too much about the mechanisms here.
427 * XXX note that this will have to be updated when we start supporting
431 amd64_mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
433 struct mem_range_desc *first_md, *last_md, *curr_md;
436 if (((first_md = amd64_mtrrfixsearch(sc, mrd->mr_base)) == NULL) ||
437 ((last_md = amd64_mtrrfixsearch(sc, mrd->mr_base + mrd->mr_len - 1)) == NULL))
440 /* Check that we aren't doing something risky. */
441 if (!(mrd->mr_flags & MDF_FORCE))
442 for (curr_md = first_md; curr_md <= last_md; curr_md++) {
443 if ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN)
447 /* Set flags, clear set-by-firmware flag. */
448 for (curr_md = first_md; curr_md <= last_md; curr_md++) {
449 curr_md->mr_flags = mrcopyflags(curr_md->mr_flags &
450 ~MDF_FIRMWARE, mrd->mr_flags);
451 bcopy(mrd->mr_owner, curr_md->mr_owner, sizeof(mrd->mr_owner));
458 * Modify/add a variable MTRR to satisfy the request.
460 * XXX needs to be updated to properly support "busy" ranges.
463 amd64_mrsetvariable(struct mem_range_softc *sc, struct mem_range_desc *mrd,
466 struct mem_range_desc *curr_md, *free_md;
470 * Scan the currently active variable descriptors, look for
471 * one we exactly match (straight takeover) and for possible
472 * accidental overlaps.
474 * Keep track of the first empty variable descriptor in case
475 * we can't perform a takeover.
477 i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0;
478 curr_md = sc->mr_desc + i;
480 for (; i < sc->mr_ndesc; i++, curr_md++) {
481 if (curr_md->mr_flags & MDF_ACTIVE) {
483 if ((curr_md->mr_base == mrd->mr_base) &&
484 (curr_md->mr_len == mrd->mr_len)) {
486 /* Whoops, owned by someone. */
487 if (curr_md->mr_flags & MDF_BUSY)
490 /* Check that we aren't doing something risky */
491 if (!(mrd->mr_flags & MDF_FORCE) &&
492 ((curr_md->mr_flags & MDF_ATTRMASK) ==
496 /* Ok, just hijack this entry. */
501 /* Non-exact overlap? */
502 if (mroverlap(curr_md, mrd)) {
503 /* Between conflicting region types? */
504 if (amd64_mtrrconflict(curr_md->mr_flags,
508 } else if (free_md == NULL) {
513 /* Got somewhere to put it? */
517 /* Set up new descriptor. */
518 free_md->mr_base = mrd->mr_base;
519 free_md->mr_len = mrd->mr_len;
520 free_md->mr_flags = mrcopyflags(MDF_ACTIVE, mrd->mr_flags);
521 bcopy(mrd->mr_owner, free_md->mr_owner, sizeof(mrd->mr_owner));
526 * Handle requests to set memory range attributes by manipulating MTRRs.
529 amd64_mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
531 struct mem_range_desc *targ;
535 case MEMRANGE_SET_UPDATE:
537 * Make sure that what's being asked for is even
540 if (!mrvalid(mrd->mr_base, mrd->mr_len) ||
541 amd64_mtrrtype(mrd->mr_flags) == -1)
544 #define FIXTOP ((MTRR_N64K * 0x10000) + (MTRR_N16K * 0x4000) + (MTRR_N4K * 0x1000))
546 /* Are the "low memory" conditions applicable? */
547 if ((sc->mr_cap & MR686_FIXMTRR) &&
548 ((mrd->mr_base + mrd->mr_len) <= FIXTOP)) {
549 if ((error = amd64_mrsetlow(sc, mrd, arg)) != 0)
552 /* It's time to play with variable MTRRs. */
553 if ((error = amd64_mrsetvariable(sc, mrd, arg)) != 0)
558 case MEMRANGE_SET_REMOVE:
559 if ((targ = mem_range_match(sc, mrd)) == NULL)
561 if (targ->mr_flags & MDF_FIXACTIVE)
563 if (targ->mr_flags & MDF_BUSY)
565 targ->mr_flags &= ~MDF_ACTIVE;
566 targ->mr_owner[0] = 0;
576 * Ensure that the direct map region does not contain any mappings
577 * that span MTRRs of different types. However, the fixed MTRRs can
578 * be ignored, because a large page mapping the first 1 MB of physical
579 * memory is a special case that the processor handles. The entire
580 * TLB will be invalidated by amd64_mrstore(), so pmap_demote_DMAP()
585 i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0;
586 mrd = sc->mr_desc + i;
587 for (; i < sc->mr_ndesc; i++, mrd++) {
588 if ((mrd->mr_flags & (MDF_ACTIVE | MDF_BOGUS)) == MDF_ACTIVE)
589 pmap_demote_DMAP(mrd->mr_base, mrd->mr_len, FALSE);
593 /* Update the hardware. */
596 /* Refetch to see where we're at. */
602 * Work out how many ranges we support, initialise storage for them,
603 * and fetch the initial settings.
606 amd64_mrinit(struct mem_range_softc *sc)
608 struct mem_range_desc *mrd;
610 int i, nmdesc = 0, pabits;
612 mtrrcap = rdmsr(MSR_MTRRcap);
613 mtrrdef = rdmsr(MSR_MTRRdefType);
615 /* For now, bail out if MTRRs are not enabled. */
616 if (!(mtrrdef & MTRR_DEF_ENABLE)) {
618 kprintf("CPU supports MTRRs but not enabled\n");
621 nmdesc = mtrrcap & MTRR_CAP_VCNT;
624 * Determine the size of the PhysMask and PhysBase fields in
625 * the variable range MTRRs. If the extended CPUID 0x80000008
626 * is present, use that to figure out how many physical
627 * address bits the CPU supports. Otherwise, default to 36
630 if (cpu_exthigh >= 0x80000008) {
631 do_cpuid(0x80000008, regs);
632 pabits = regs[0] & 0xff;
635 mtrr_physmask = ((1UL << pabits) - 1) & ~0xfffUL;
637 /* If fixed MTRRs supported and enabled. */
638 if ((mtrrcap & MTRR_CAP_FIXED) && (mtrrdef & MTRR_DEF_FIXED_ENABLE)) {
639 sc->mr_cap = MR686_FIXMTRR;
640 nmdesc += MTRR_N64K + MTRR_N16K + MTRR_N4K;
643 sc->mr_desc = kmalloc(nmdesc * sizeof(struct mem_range_desc),
644 M_MEMDESC, M_WAITOK | M_ZERO);
645 sc->mr_ndesc = nmdesc;
649 /* Populate the fixed MTRR entries' base/length. */
650 if (sc->mr_cap & MR686_FIXMTRR) {
651 for (i = 0; i < MTRR_N64K; i++, mrd++) {
652 mrd->mr_base = i * 0x10000;
653 mrd->mr_len = 0x10000;
654 mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
657 for (i = 0; i < MTRR_N16K; i++, mrd++) {
658 mrd->mr_base = i * 0x4000 + 0x80000;
659 mrd->mr_len = 0x4000;
660 mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
663 for (i = 0; i < MTRR_N4K; i++, mrd++) {
664 mrd->mr_base = i * 0x1000 + 0xc0000;
665 mrd->mr_len = 0x1000;
666 mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
672 * Get current settings, anything set now is considered to
673 * have been set by the firmware. (XXX has something already
678 for (i = 0; i < sc->mr_ndesc; i++, mrd++) {
679 if (mrd->mr_flags & MDF_ACTIVE)
680 mrd->mr_flags |= MDF_FIRMWARE;
685 * Ensure that the direct map region does not contain any mappings
686 * that span MTRRs of different types. However, the fixed MTRRs can
687 * be ignored, because a large page mapping the first 1 MB of physical
688 * memory is a special case that the processor handles. Invalidate
689 * any old TLB entries that might hold inconsistent memory type
692 i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0;
693 mrd = sc->mr_desc + i;
694 for (; i < sc->mr_ndesc; i++, mrd++) {
695 if ((mrd->mr_flags & (MDF_ACTIVE | MDF_BOGUS)) == MDF_ACTIVE)
696 pmap_demote_DMAP(mrd->mr_base, mrd->mr_len, TRUE);
702 * Initialise MTRRs on an AP after the BSP has run the init code.
705 amd64_mrAPinit(struct mem_range_softc *sc)
707 amd64_mrstoreone(sc);
708 wrmsr(MSR_MTRRdefType, mtrrdef);
712 * Re-initialise running CPU(s) MTRRs to match the ranges in the descriptor
715 * XXX Must be called with interrupts enabled.
718 amd64_mrreinit(struct mem_range_softc *sc)
721 * We should use ipi_all_but_self() to call other CPUs into a
722 * locking gate, then call a target function to do this work.
723 * The "proper" solution involves a generalised locking gate
724 * implementation, not ready yet.
726 lwkt_send_ipiq_mask(smp_active_mask, (void *)amd64_mrAPinit, sc);
730 amd64_mem_drvinit(void *unused)
735 if (!(cpu_feature & CPUID_MTRR))
737 if ((cpu_id & 0xf00) != 0x600 && (cpu_id & 0xf00) != 0xf00)
739 switch (cpu_vendor_id) {
740 case CPU_VENDOR_INTEL:
742 case CPU_VENDOR_CENTAUR:
747 mem_range_softc.mr_op = &amd64_mrops;
749 SYSINIT(amd64memdev, SI_SUB_DRIVERS, SI_ORDER_FIRST, amd64_mem_drvinit, NULL);