2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
25 #include <linux/firmware.h>
30 #include "radeon_ucode.h"
32 int si_set_smc_sram_address(struct radeon_device *rdev,
33 u32 smc_address, u32 limit);
34 int si_copy_bytes_to_smc(struct radeon_device *rdev,
35 u32 smc_start_address,
36 const u8 *src, u32 byte_count, u32 limit);
37 void si_start_smc(struct radeon_device *rdev);
38 void si_reset_smc(struct radeon_device *rdev);
39 int si_program_jump_on_start(struct radeon_device *rdev);
40 void si_stop_smc_clock(struct radeon_device *rdev);
41 void si_start_smc_clock(struct radeon_device *rdev);
42 bool si_is_smc_running(struct radeon_device *rdev);
43 PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
44 PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev);
45 int si_load_smc_ucode(struct radeon_device *rdev, u32 limit);
46 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
47 u32 *value, u32 limit);
48 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
49 u32 value, u32 limit);
51 int si_set_smc_sram_address(struct radeon_device *rdev,
52 u32 smc_address, u32 limit)
56 if ((smc_address + 3) > limit)
59 WREG32(SMC_IND_INDEX_0, smc_address);
60 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
65 int si_copy_bytes_to_smc(struct radeon_device *rdev,
66 u32 smc_start_address,
67 const u8 *src, u32 byte_count, u32 limit)
70 u32 data, original_data, addr, extra_shift;
72 if (smc_start_address & 3)
74 if ((smc_start_address + byte_count) > limit)
77 addr = smc_start_address;
79 while (byte_count >= 4) {
80 /* SMC address space is BE */
81 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
83 ret = si_set_smc_sram_address(rdev, addr, limit);
87 WREG32(SMC_IND_DATA_0, data);
94 /* RMW for the final bytes */
98 ret = si_set_smc_sram_address(rdev, addr, limit);
102 original_data = RREG32(SMC_IND_DATA_0);
104 extra_shift = 8 * (4 - byte_count);
106 while (byte_count > 0) {
107 /* SMC address space is BE */
108 data = (data << 8) + *src++;
112 data <<= extra_shift;
114 data |= (original_data & ~((~0UL) << extra_shift));
116 ret = si_set_smc_sram_address(rdev, addr, limit);
120 WREG32(SMC_IND_DATA_0, data);
125 void si_start_smc(struct radeon_device *rdev)
127 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
131 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
134 void si_reset_smc(struct radeon_device *rdev)
138 RREG32(CB_CGTT_SCLK_CTRL);
139 RREG32(CB_CGTT_SCLK_CTRL);
140 RREG32(CB_CGTT_SCLK_CTRL);
141 RREG32(CB_CGTT_SCLK_CTRL);
143 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
145 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
148 int si_program_jump_on_start(struct radeon_device *rdev)
150 static u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };
152 return si_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1);
155 void si_stop_smc_clock(struct radeon_device *rdev)
157 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
161 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
164 void si_start_smc_clock(struct radeon_device *rdev)
166 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
170 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
173 bool si_is_smc_running(struct radeon_device *rdev)
175 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
176 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
178 if (!(rst & RST_REG) && !(clk & CK_DISABLE))
184 PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
189 if (!si_is_smc_running(rdev))
190 return PPSMC_Result_Failed;
192 WREG32(SMC_MESSAGE_0, msg);
194 for (i = 0; i < rdev->usec_timeout; i++) {
195 tmp = RREG32(SMC_RESP_0);
200 tmp = RREG32(SMC_RESP_0);
202 return (PPSMC_Result)tmp;
205 PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev)
210 if (!si_is_smc_running(rdev))
211 return PPSMC_Result_OK;
213 for (i = 0; i < rdev->usec_timeout; i++) {
214 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
215 if ((tmp & CKEN) == 0)
220 return PPSMC_Result_OK;
223 int si_load_smc_ucode(struct radeon_device *rdev, u32 limit)
225 u32 ucode_start_address;
233 switch (rdev->family) {
235 ucode_start_address = TAHITI_SMC_UCODE_START;
236 ucode_size = TAHITI_SMC_UCODE_SIZE;
239 ucode_start_address = PITCAIRN_SMC_UCODE_START;
240 ucode_size = PITCAIRN_SMC_UCODE_SIZE;
243 ucode_start_address = VERDE_SMC_UCODE_START;
244 ucode_size = VERDE_SMC_UCODE_SIZE;
247 ucode_start_address = OLAND_SMC_UCODE_START;
248 ucode_size = OLAND_SMC_UCODE_SIZE;
251 ucode_start_address = HAINAN_SMC_UCODE_START;
252 ucode_size = HAINAN_SMC_UCODE_SIZE;
255 DRM_ERROR("unknown asic in smc ucode loader\n");
262 src = (const u8 *)rdev->smc_fw->data;
263 WREG32(SMC_IND_INDEX_0, ucode_start_address);
264 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
265 while (ucode_size >= 4) {
266 /* SMC address space is BE */
267 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
269 WREG32(SMC_IND_DATA_0, data);
274 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
279 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
280 u32 *value, u32 limit)
284 ret = si_set_smc_sram_address(rdev, smc_address, limit);
288 *value = RREG32(SMC_IND_DATA_0);
292 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
293 u32 value, u32 limit)
297 ret = si_set_smc_sram_address(rdev, smc_address, limit);
301 WREG32(SMC_IND_DATA_0, value);