sys/dev/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  32  * them for both DP and FDI transports, allowing those ports to
  33  * automatically adapt to HDMI connections as well
  34  */
  35 static const u32 hsw_ddi_translations_dp[] = {
  36         0x00FFFFFF, 0x0006000E,         /* DP parameters */
  37         0x00D75FFF, 0x0005000A,
  38         0x00C30FFF, 0x00040006,
  39         0x80AAAFFF, 0x000B0000,
  40         0x00FFFFFF, 0x0005000A,
  41         0x00D75FFF, 0x000C0004,
  42         0x80C30FFF, 0x000B0000,
  43         0x00FFFFFF, 0x00040006,
  44         0x80D75FFF, 0x000B0000,
  45 };
  46
  47 static const u32 hsw_ddi_translations_fdi[] = {
  48         0x00FFFFFF, 0x0007000E,         /* FDI parameters */
  49         0x00D75FFF, 0x000F000A,
  50         0x00C30FFF, 0x00060006,
  51         0x00AAAFFF, 0x001E0000,
  52         0x00FFFFFF, 0x000F000A,
  53         0x00D75FFF, 0x00160004,
  54         0x00C30FFF, 0x001E0000,
  55         0x00FFFFFF, 0x00060006,
  56         0x00D75FFF, 0x001E0000,
  57 };
  58
  59 static const u32 hsw_ddi_translations_hdmi[] = {
  60                                 /* Idx  NT mV diff      T mV diff       db  */
  61         0x00FFFFFF, 0x0006000E, /* 0:   400             400             0   */
  62         0x00E79FFF, 0x000E000C, /* 1:   400             500             2   */
  63         0x00D75FFF, 0x0005000A, /* 2:   400             600             3.5 */
  64         0x00FFFFFF, 0x0005000A, /* 3:   600             600             0   */
  65         0x00E79FFF, 0x001D0007, /* 4:   600             750             2   */
  66         0x00D75FFF, 0x000C0004, /* 5:   600             900             3.5 */
  67         0x00FFFFFF, 0x00040006, /* 6:   800             800             0   */
  68         0x80E79FFF, 0x00030002, /* 7:   800             1000            2   */
  69         0x00FFFFFF, 0x00140005, /* 8:   850             850             0   */
  70         0x00FFFFFF, 0x000C0004, /* 9:   900             900             0   */
  71         0x00FFFFFF, 0x001C0003, /* 10:  950             950             0   */
  72         0x80FFFFFF, 0x00030002, /* 11:  1000            1000            0   */
  73 };
  74
  75 static const u32 bdw_ddi_translations_edp[] = {
  76         0x00FFFFFF, 0x00000012,         /* eDP parameters */
  77         0x00EBAFFF, 0x00020011,
  78         0x00C71FFF, 0x0006000F,
  79         0x00FFFFFF, 0x00020011,
  80         0x00DB6FFF, 0x0005000F,
  81         0x00BEEFFF, 0x000A000C,
  82         0x00FFFFFF, 0x0005000F,
  83         0x00DB6FFF, 0x000A000C,
  84         0x00FFFFFF, 0x000A000C,
  85         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
  86 };
  87
  88 static const u32 bdw_ddi_translations_dp[] = {
  89         0x00FFFFFF, 0x0007000E,         /* DP parameters */
  90         0x00D75FFF, 0x000E000A,
  91         0x00BEFFFF, 0x00140006,
  92         0x00FFFFFF, 0x000E000A,
  93         0x00D75FFF, 0x00180004,
  94         0x80CB2FFF, 0x001B0002,
  95         0x00F7DFFF, 0x00180004,
  96         0x80D75FFF, 0x001B0002,
  97         0x80FFFFFF, 0x001B0002,
  98         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
  99 };
 100
 101 static const u32 bdw_ddi_translations_fdi[] = {
 102         0x00FFFFFF, 0x0001000E,         /* FDI parameters */
 103         0x00D75FFF, 0x0004000A,
 104         0x00C30FFF, 0x00070006,
 105         0x00AAAFFF, 0x000C0000,
 106         0x00FFFFFF, 0x0004000A,
 107         0x00D75FFF, 0x00090004,
 108         0x00C30FFF, 0x000C0000,
 109         0x00FFFFFF, 0x00070006,
 110         0x00D75FFF, 0x000C0000,
 111         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
 112 };
 113
 114 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 115 {
 116         struct drm_encoder *encoder = &intel_encoder->base;
 117         int type = intel_encoder->type;
 118
 119         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
 120             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
 121                 struct intel_digital_port *intel_dig_port =
 122                         enc_to_dig_port(encoder);
 123                 return intel_dig_port->port;
 124
 125         } else if (type == INTEL_OUTPUT_ANALOG) {
 126                 return PORT_E;
 127
 128         } else {
 129                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
 130                 BUG();
 131         }
 132 }
 133
 134 /*
 135  * Starting with Haswell, DDI port buffers must be programmed with correct
 136  * values in advance. The buffer values are different for FDI and DP modes,
 137  * but the HDMI/DVI fields are shared among those. So we program the DDI
 138  * in either FDI or DP modes only, as HDMI connections will work with both
 139  * of those
 140  */
 141 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 142 {
 143         struct drm_i915_private *dev_priv = dev->dev_private;
 144         u32 reg;
 145         int i;
 146         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 147         const u32 *ddi_translations_fdi;
 148         const u32 *ddi_translations_dp;
 149         const u32 *ddi_translations_edp;
 150         const u32 *ddi_translations;
 151
 152         if (IS_BROADWELL(dev)) {
 153                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 154                 ddi_translations_dp = bdw_ddi_translations_dp;
 155                 ddi_translations_edp = bdw_ddi_translations_edp;
 156         } else if (IS_HASWELL(dev)) {
 157                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 158                 ddi_translations_dp = hsw_ddi_translations_dp;
 159                 ddi_translations_edp = hsw_ddi_translations_dp;
 160         } else {
 161                 WARN(1, "ddi translation table missing\n");
 162                 ddi_translations_edp = bdw_ddi_translations_dp;
 163                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 164                 ddi_translations_dp = bdw_ddi_translations_dp;
 165         }
 166
 167         switch (port) {
 168         case PORT_A:
 169                 ddi_translations = ddi_translations_edp;
 170                 break;
 171         case PORT_B:
 172         case PORT_C:
 173                 ddi_translations = ddi_translations_dp;
 174                 break;
 175         case PORT_D:
 176                 if (intel_dp_is_edp(dev, PORT_D))
 177                         ddi_translations = ddi_translations_edp;
 178                 else
 179                         ddi_translations = ddi_translations_dp;
 180                 break;
 181         case PORT_E:
 182                 ddi_translations = ddi_translations_fdi;
 183                 break;
 184         default:
 185                 BUG();
 186         }
 187
 188         for (i = 0, reg = DDI_BUF_TRANS(port);
 189              i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 190                 I915_WRITE(reg, ddi_translations[i]);
 191                 reg += 4;
 192         }
 193         /* Entry 9 is for HDMI: */
 194         for (i = 0; i < 2; i++) {
 195                 I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
 196                 reg += 4;
 197         }
 198 }
 199
 200 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 201  * mode and port E for FDI.
 202  */
 203 void intel_prepare_ddi(struct drm_device *dev)
 204 {
 205         int port;
 206
 207         if (!HAS_DDI(dev))
 208                 return;
 209
 210         for (port = PORT_A; port <= PORT_E; port++)
 211                 intel_prepare_ddi_buffers(dev, port);
 212 }
 213
 214 static const long hsw_ddi_buf_ctl_values[] = {
 215         DDI_BUF_EMP_400MV_0DB_HSW,
 216         DDI_BUF_EMP_400MV_3_5DB_HSW,
 217         DDI_BUF_EMP_400MV_6DB_HSW,
 218         DDI_BUF_EMP_400MV_9_5DB_HSW,
 219         DDI_BUF_EMP_600MV_0DB_HSW,
 220         DDI_BUF_EMP_600MV_3_5DB_HSW,
 221         DDI_BUF_EMP_600MV_6DB_HSW,
 222         DDI_BUF_EMP_800MV_0DB_HSW,
 223         DDI_BUF_EMP_800MV_3_5DB_HSW
 224 };
 225
 226 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 227                                     enum port port)
 228 {
 229         uint32_t reg = DDI_BUF_CTL(port);
 230         int i;
 231
 232         for (i = 0; i < 8; i++) {
 233                 udelay(1);
 234                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 235                         return;
 236         }
 237         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 238 }
 239
 240 /* Starting with Haswell, different DDI ports can work in FDI mode for
 241  * connection to the PCH-located connectors. For this, it is necessary to train
 242  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 243  *
 244  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 245  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 246  * DDI A (which is used for eDP)
 247  */
 248
 249 void hsw_fdi_link_train(struct drm_crtc *crtc)
 250 {
 251         struct drm_device *dev = crtc->dev;
 252         struct drm_i915_private *dev_priv = dev->dev_private;
 253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 254         u32 temp, i, rx_ctl_val;
 255
 256         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 257          * mode set "sequence for CRT port" document:
 258          * - TP1 to TP2 time with the default value
 259          * - FDI delay to 90h
 260          *
 261          * WaFDIAutoLinkSetTimingOverrride:hsw
 262          */
 263         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 264                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 265                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 266
 267         /* Enable the PCH Receiver FDI PLL */
 268         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 269                      FDI_RX_PLL_ENABLE |
 270                      FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
 271         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 272         POSTING_READ(_FDI_RXA_CTL);
 273         udelay(220);
 274
 275         /* Switch from Rawclk to PCDclk */
 276         rx_ctl_val |= FDI_PCDCLK;
 277         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 278
 279         /* Configure Port Clock Select */
 280         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
 281
 282         /* Start the training iterating through available voltages and emphasis,
 283          * testing each value twice. */
 284         for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
 285                 /* Configure DP_TP_CTL with auto-training */
 286                 I915_WRITE(DP_TP_CTL(PORT_E),
 287                                         DP_TP_CTL_FDI_AUTOTRAIN |
 288                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 289                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 290                                         DP_TP_CTL_ENABLE);
 291
 292                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 293                  * DDI E does not support port reversal, the functionality is
 294                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 295                  * port reversal bit */
 296                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 297                            DDI_BUF_CTL_ENABLE |
 298                            ((intel_crtc->config.fdi_lanes - 1) << 1) |
 299                            hsw_ddi_buf_ctl_values[i / 2]);
 300                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 301
 302                 udelay(600);
 303
 304                 /* Program PCH FDI Receiver TU */
 305                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 306
 307                 /* Enable PCH FDI Receiver with auto-training */
 308                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 309                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 310                 POSTING_READ(_FDI_RXA_CTL);
 311
 312                 /* Wait for FDI receiver lane calibration */
 313                 udelay(30);
 314
 315                 /* Unset FDI_RX_MISC pwrdn lanes */
 316                 temp = I915_READ(_FDI_RXA_MISC);
 317                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 318                 I915_WRITE(_FDI_RXA_MISC, temp);
 319                 POSTING_READ(_FDI_RXA_MISC);
 320
 321                 /* Wait for FDI auto training time */
 322                 udelay(5);
 323
 324                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 325                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 326                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 327
 328                         /* Enable normal pixel sending for FDI */
 329                         I915_WRITE(DP_TP_CTL(PORT_E),
 330                                    DP_TP_CTL_FDI_AUTOTRAIN |
 331                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 332                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 333                                    DP_TP_CTL_ENABLE);
 334
 335                         return;
 336                 }
 337
 338                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 339                 temp &= ~DDI_BUF_CTL_ENABLE;
 340                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 341                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 342
 343                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 344                 temp = I915_READ(DP_TP_CTL(PORT_E));
 345                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 346                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 347                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 348                 POSTING_READ(DP_TP_CTL(PORT_E));
 349
 350                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 351
 352                 rx_ctl_val &= ~FDI_RX_ENABLE;
 353                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 354                 POSTING_READ(_FDI_RXA_CTL);
 355
 356                 /* Reset FDI_RX_MISC pwrdn lanes */
 357                 temp = I915_READ(_FDI_RXA_MISC);
 358                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 359                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 360                 I915_WRITE(_FDI_RXA_MISC, temp);
 361                 POSTING_READ(_FDI_RXA_MISC);
 362         }
 363
 364         DRM_ERROR("FDI link training failed!\n");
 365 }
 366
 367 static struct intel_encoder *
 368 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 369 {
 370         struct drm_device *dev = crtc->dev;
 371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 372         struct intel_encoder *intel_encoder, *ret = NULL;
 373         int num_encoders = 0;
 374
 375         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 376                 ret = intel_encoder;
 377                 num_encoders++;
 378         }
 379
 380         if (num_encoders != 1)
 381                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 382                      pipe_name(intel_crtc->pipe));
 383
 384         BUG_ON(ret == NULL);
 385         return ret;
 386 }
 387
 388 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 389 {
 390         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 391         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 393         uint32_t val;
 394
 395         switch (intel_crtc->ddi_pll_sel) {
 396         case PORT_CLK_SEL_SPLL:
 397                 plls->spll_refcount--;
 398                 if (plls->spll_refcount == 0) {
 399                         DRM_DEBUG_KMS("Disabling SPLL\n");
 400                         val = I915_READ(SPLL_CTL);
 401                         WARN_ON(!(val & SPLL_PLL_ENABLE));
 402                         I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
 403                         POSTING_READ(SPLL_CTL);
 404                 }
 405                 break;
 406         case PORT_CLK_SEL_WRPLL1:
 407                 plls->wrpll1_refcount--;
 408                 if (plls->wrpll1_refcount == 0) {
 409                         DRM_DEBUG_KMS("Disabling WRPLL 1\n");
 410                         val = I915_READ(WRPLL_CTL1);
 411                         WARN_ON(!(val & WRPLL_PLL_ENABLE));
 412                         I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
 413                         POSTING_READ(WRPLL_CTL1);
 414                 }
 415                 break;
 416         case PORT_CLK_SEL_WRPLL2:
 417                 plls->wrpll2_refcount--;
 418                 if (plls->wrpll2_refcount == 0) {
 419                         DRM_DEBUG_KMS("Disabling WRPLL 2\n");
 420                         val = I915_READ(WRPLL_CTL2);
 421                         WARN_ON(!(val & WRPLL_PLL_ENABLE));
 422                         I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
 423                         POSTING_READ(WRPLL_CTL2);
 424                 }
 425                 break;
 426         }
 427
 428         WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
 429         WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
 430         WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
 431
 432         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
 433 }
 434
 435 #define LC_FREQ 2700
 436 #define LC_FREQ_2K (LC_FREQ * 2000)
 437
 438 #define P_MIN 2
 439 #define P_MAX 64
 440 #define P_INC 2
 441
 442 /* Constraints for PLL good behavior */
 443 #define REF_MIN 48
 444 #define REF_MAX 400
 445 #define VCO_MIN 2400
 446 #define VCO_MAX 4800
 447
 448 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
 449
 450 struct wrpll_rnp {
 451         unsigned p, n2, r2;
 452 };
 453
 454 static unsigned wrpll_get_budget_for_freq(int clock)
 455 {
 456         unsigned budget;
 457
 458         switch (clock) {
 459         case 25175000:
 460         case 25200000:
 461         case 27000000:
 462         case 27027000:
 463         case 37762500:
 464         case 37800000:
 465         case 40500000:
 466         case 40541000:
 467         case 54000000:
 468         case 54054000:
 469         case 59341000:
 470         case 59400000:
 471         case 72000000:
 472         case 74176000:
 473         case 74250000:
 474         case 81000000:
 475         case 81081000:
 476         case 89012000:
 477         case 89100000:
 478         case 108000000:
 479         case 108108000:
 480         case 111264000:
 481         case 111375000:
 482         case 148352000:
 483         case 148500000:
 484         case 162000000:
 485         case 162162000:
 486         case 222525000:
 487         case 222750000:
 488         case 296703000:
 489         case 297000000:
 490                 budget = 0;
 491                 break;
 492         case 233500000:
 493         case 245250000:
 494         case 247750000:
 495         case 253250000:
 496         case 298000000:
 497                 budget = 1500;
 498                 break;
 499         case 169128000:
 500         case 169500000:
 501         case 179500000:
 502         case 202000000:
 503                 budget = 2000;
 504                 break;
 505         case 256250000:
 506         case 262500000:
 507         case 270000000:
 508         case 272500000:
 509         case 273750000:
 510         case 280750000:
 511         case 281250000:
 512         case 286000000:
 513         case 291750000:
 514                 budget = 4000;
 515                 break;
 516         case 267250000:
 517         case 268500000:
 518                 budget = 5000;
 519                 break;
 520         default:
 521                 budget = 1000;
 522                 break;
 523         }
 524
 525         return budget;
 526 }
 527
 528 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 529                              unsigned r2, unsigned n2, unsigned p,
 530                              struct wrpll_rnp *best)
 531 {
 532         uint64_t a, b, c, d, diff, diff_best;
 533
 534         /* No best (r,n,p) yet */
 535         if (best->p == 0) {
 536                 best->p = p;
 537                 best->n2 = n2;
 538                 best->r2 = r2;
 539                 return;
 540         }
 541
 542         /*
 543          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 544          * freq2k.
 545          *
 546          * delta = 1e6 *
 547          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 548          *         freq2k;
 549          *
 550          * and we would like delta <= budget.
 551          *
 552          * If the discrepancy is above the PPM-based budget, always prefer to
 553          * improve upon the previous solution.  However, if you're within the
 554          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 555          */
 556         a = freq2k * budget * p * r2;
 557         b = freq2k * budget * best->p * best->r2;
 558         diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
 559         diff_best = ABS_DIFF((freq2k * best->p * best->r2),
 560                              (LC_FREQ_2K * best->n2));
 561         c = 1000000 * diff;
 562         d = 1000000 * diff_best;
 563
 564         if (a < c && b < d) {
 565                 /* If both are above the budget, pick the closer */
 566                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 567                         best->p = p;
 568                         best->n2 = n2;
 569                         best->r2 = r2;
 570                 }
 571         } else if (a >= c && b < d) {
 572                 /* If A is below the threshold but B is above it?  Update. */
 573                 best->p = p;
 574                 best->n2 = n2;
 575                 best->r2 = r2;
 576         } else if (a >= c && b >= d) {
 577                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 578                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 579                         best->p = p;
 580                         best->n2 = n2;
 581                         best->r2 = r2;
 582                 }
 583         }
 584         /* Otherwise a < c && b >= d, do nothing */
 585 }
 586
 587 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 588                                      int reg)
 589 {
 590         int refclk = LC_FREQ;
 591         int n, p, r;
 592         u32 wrpll;
 593
 594         wrpll = I915_READ(reg);
 595         switch (wrpll & SPLL_PLL_REF_MASK) {
 596         case SPLL_PLL_SSC:
 597         case SPLL_PLL_NON_SSC:
 598                 /*
 599                  * We could calculate spread here, but our checking
 600                  * code only cares about 5% accuracy, and spread is a max of
 601                  * 0.5% downspread.
 602                  */
 603                 refclk = 135;
 604                 break;
 605         case SPLL_PLL_LCPLL:
 606                 refclk = LC_FREQ;
 607                 break;
 608         default:
 609                 WARN(1, "bad wrpll refclk\n");
 610                 return 0;
 611         }
 612
 613         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 614         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 615         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 616
 617         /* Convert to KHz, p & r have a fixed point portion */
 618         return (refclk * n * 100) / (p * r);
 619 }
 620
 621 static void intel_ddi_clock_get(struct intel_encoder *encoder,
 622                                 struct intel_crtc_config *pipe_config)
 623 {
 624         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 625         enum port port = intel_ddi_get_encoder_port(encoder);
 626         int link_clock = 0;
 627         u32 val, pll;
 628
 629         val = I915_READ(PORT_CLK_SEL(port));
 630         switch (val & PORT_CLK_SEL_MASK) {
 631         case PORT_CLK_SEL_LCPLL_810:
 632                 link_clock = 81000;
 633                 break;
 634         case PORT_CLK_SEL_LCPLL_1350:
 635                 link_clock = 135000;
 636                 break;
 637         case PORT_CLK_SEL_LCPLL_2700:
 638                 link_clock = 270000;
 639                 break;
 640         case PORT_CLK_SEL_WRPLL1:
 641                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
 642                 break;
 643         case PORT_CLK_SEL_WRPLL2:
 644                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
 645                 break;
 646         case PORT_CLK_SEL_SPLL:
 647                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 648                 if (pll == SPLL_PLL_FREQ_810MHz)
 649                         link_clock = 81000;
 650                 else if (pll == SPLL_PLL_FREQ_1350MHz)
 651                         link_clock = 135000;
 652                 else if (pll == SPLL_PLL_FREQ_2700MHz)
 653                         link_clock = 270000;
 654                 else {
 655                         WARN(1, "bad spll freq\n");
 656                         return;
 657                 }
 658                 break;
 659         default:
 660                 WARN(1, "bad port clock sel\n");
 661                 return;
 662         }
 663
 664         pipe_config->port_clock = link_clock * 2;
 665
 666         if (pipe_config->has_pch_encoder)
 667                 pipe_config->adjusted_mode.crtc_clock =
 668                         intel_dotclock_calculate(pipe_config->port_clock,
 669                                                  &pipe_config->fdi_m_n);
 670         else if (pipe_config->has_dp_encoder)
 671                 pipe_config->adjusted_mode.crtc_clock =
 672                         intel_dotclock_calculate(pipe_config->port_clock,
 673                                                  &pipe_config->dp_m_n);
 674         else
 675                 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
 676 }
 677
 678 static void
 679 intel_ddi_calculate_wrpll(int clock /* in Hz */,
 680                           unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 681 {
 682         uint64_t freq2k;
 683         unsigned p, n2, r2;
 684         struct wrpll_rnp best = { 0, 0, 0 };
 685         unsigned budget;
 686
 687         freq2k = clock / 100;
 688
 689         budget = wrpll_get_budget_for_freq(clock);
 690
 691         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
 692          * and directly pass the LC PLL to it. */
 693         if (freq2k == 5400000) {
 694                 *n2_out = 2;
 695                 *p_out = 1;
 696                 *r2_out = 2;
 697                 return;
 698         }
 699
 700         /*
 701          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
 702          * the WR PLL.
 703          *
 704          * We want R so that REF_MIN <= Ref <= REF_MAX.
 705          * Injecting R2 = 2 * R gives:
 706          *   REF_MAX * r2 > LC_FREQ * 2 and
 707          *   REF_MIN * r2 < LC_FREQ * 2
 708          *
 709          * Which means the desired boundaries for r2 are:
 710          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
 711          *
 712          */
 713         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
 714              r2 <= LC_FREQ * 2 / REF_MIN;
 715              r2++) {
 716
 717                 /*
 718                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 719                  *
 720                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 721                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 722                  *   VCO_MAX * r2 > n2 * LC_FREQ and
 723                  *   VCO_MIN * r2 < n2 * LC_FREQ)
 724                  *
 725                  * Which means the desired boundaries for n2 are:
 726                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 727                  */
 728                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 729                      n2 <= VCO_MAX * r2 / LC_FREQ;
 730                      n2++) {
 731
 732                         for (p = P_MIN; p <= P_MAX; p += P_INC)
 733                                 wrpll_update_rnp(freq2k, budget,
 734                                                  r2, n2, p, &best);
 735                 }
 736         }
 737
 738         *n2_out = best.n2;
 739         *p_out = best.p;
 740         *r2_out = best.r2;
 741 }
 742
 743 /*
 744  * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and
 745  * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to
 746  * steal the selected PLL. You need to call intel_ddi_pll_enable to actually
 747  * enable the PLL.
 748  */
 749 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 750 {
 751         struct drm_crtc *crtc = &intel_crtc->base;
 752         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 753         struct drm_encoder *encoder = &intel_encoder->base;
 754         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 755         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 756         int type = intel_encoder->type;
 757         enum i915_pipe pipe = intel_crtc->pipe;
 758         int clock = intel_crtc->config.port_clock;
 759
 760         intel_ddi_put_crtc_pll(crtc);
 761
 762         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 763                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 764
 765                 switch (intel_dp->link_bw) {
 766                 case DP_LINK_BW_1_62:
 767                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 768                         break;
 769                 case DP_LINK_BW_2_7:
 770                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 771                         break;
 772                 case DP_LINK_BW_5_4:
 773                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 774                         break;
 775                 default:
 776                         DRM_ERROR("Link bandwidth %d unsupported\n",
 777                                   intel_dp->link_bw);
 778                         return false;
 779                 }
 780
 781         } else if (type == INTEL_OUTPUT_HDMI) {
 782                 uint32_t reg, val;
 783                 unsigned p, n2, r2;
 784
 785                 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 786
 787                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
 788                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 789                       WRPLL_DIVIDER_POST(p);
 790
 791                 if (val == I915_READ(WRPLL_CTL1)) {
 792                         DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
 793                                       pipe_name(pipe));
 794                         reg = WRPLL_CTL1;
 795                 } else if (val == I915_READ(WRPLL_CTL2)) {
 796                         DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
 797                                       pipe_name(pipe));
 798                         reg = WRPLL_CTL2;
 799                 } else if (plls->wrpll1_refcount == 0) {
 800                         DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
 801                                       pipe_name(pipe));
 802                         reg = WRPLL_CTL1;
 803                 } else if (plls->wrpll2_refcount == 0) {
 804                         DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
 805                                       pipe_name(pipe));
 806                         reg = WRPLL_CTL2;
 807                 } else {
 808                         DRM_ERROR("No WRPLLs available!\n");
 809                         return false;
 810                 }
 811
 812                 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
 813                               clock, p, n2, r2);
 814
 815                 if (reg == WRPLL_CTL1) {
 816                         plls->wrpll1_refcount++;
 817                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
 818                 } else {
 819                         plls->wrpll2_refcount++;
 820                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
 821                 }
 822
 823         } else if (type == INTEL_OUTPUT_ANALOG) {
 824                 if (plls->spll_refcount == 0) {
 825                         DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
 826                                       pipe_name(pipe));
 827                         plls->spll_refcount++;
 828                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
 829                 } else {
 830                         DRM_ERROR("SPLL already in use\n");
 831                         return false;
 832                 }
 833
 834         } else {
 835                 WARN(1, "Invalid DDI encoder type %d\n", type);
 836                 return false;
 837         }
 838
 839         return true;
 840 }
 841
 842 /*
 843  * To be called after intel_ddi_pll_select(). That one selects the PLL to be
 844  * used, this one actually enables the PLL.
 845  */
 846 void intel_ddi_pll_enable(struct intel_crtc *crtc)
 847 {
 848         struct drm_device *dev = crtc->base.dev;
 849         struct drm_i915_private *dev_priv = dev->dev_private;
 850         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 851         int clock = crtc->config.port_clock;
 852         uint32_t reg, cur_val, new_val;
 853         int refcount;
 854         const char *pll_name;
 855         uint32_t enable_bit = (1 << 31);
 856         unsigned int p, n2, r2;
 857
 858 #if 0
 859         BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
 860         BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
 861 #endif
 862
 863         switch (crtc->ddi_pll_sel) {
 864         case PORT_CLK_SEL_LCPLL_2700:
 865         case PORT_CLK_SEL_LCPLL_1350:
 866         case PORT_CLK_SEL_LCPLL_810:
 867                 /*
 868                  * LCPLL should always be enabled at this point of the mode set
 869                  * sequence, so nothing to do.
 870                  */
 871                 return;
 872
 873         case PORT_CLK_SEL_SPLL:
 874                 pll_name = "SPLL";
 875                 reg = SPLL_CTL;
 876                 refcount = plls->spll_refcount;
 877                 new_val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz |
 878                           SPLL_PLL_SSC;
 879                 break;
 880
 881         case PORT_CLK_SEL_WRPLL1:
 882         case PORT_CLK_SEL_WRPLL2:
 883                 if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
 884                         pll_name = "WRPLL1";
 885                         reg = WRPLL_CTL1;
 886                         refcount = plls->wrpll1_refcount;
 887                 } else {
 888                         pll_name = "WRPLL2";
 889                         reg = WRPLL_CTL2;
 890                         refcount = plls->wrpll2_refcount;
 891                 }
 892
 893                 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 894
 895                 new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
 896                           WRPLL_DIVIDER_REFERENCE(r2) |
 897                           WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p);
 898
 899                 break;
 900
 901         case PORT_CLK_SEL_NONE:
 902                 WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
 903                 return;
 904         default:
 905                 WARN(1, "Bad selected pll: 0x%08x\n", crtc->ddi_pll_sel);
 906                 return;
 907         }
 908
 909         cur_val = I915_READ(reg);
 910
 911         WARN(refcount < 1, "Bad %s refcount: %d\n", pll_name, refcount);
 912         if (refcount == 1) {
 913                 WARN(cur_val & enable_bit, "%s already enabled\n", pll_name);
 914                 I915_WRITE(reg, new_val);
 915                 POSTING_READ(reg);
 916                 udelay(20);
 917         } else {
 918                 WARN((cur_val & enable_bit) == 0, "%s disabled\n", pll_name);
 919         }
 920 }
 921
 922 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
 923 {
 924         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 925         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 926         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 927         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 928         int type = intel_encoder->type;
 929         uint32_t temp;
 930
 931         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 932
 933                 temp = TRANS_MSA_SYNC_CLK;
 934                 switch (intel_crtc->config.pipe_bpp) {
 935                 case 18:
 936                         temp |= TRANS_MSA_6_BPC;
 937                         break;
 938                 case 24:
 939                         temp |= TRANS_MSA_8_BPC;
 940                         break;
 941                 case 30:
 942                         temp |= TRANS_MSA_10_BPC;
 943                         break;
 944                 case 36:
 945                         temp |= TRANS_MSA_12_BPC;
 946                         break;
 947                 default:
 948                         BUG();
 949                 }
 950                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 951         }
 952 }
 953
 954 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 955 {
 956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 957         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 958         struct drm_encoder *encoder = &intel_encoder->base;
 959         struct drm_device *dev = crtc->dev;
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961         enum i915_pipe pipe = intel_crtc->pipe;
 962         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 963         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 964         int type = intel_encoder->type;
 965         uint32_t temp;
 966
 967         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 968         temp = TRANS_DDI_FUNC_ENABLE;
 969         temp |= TRANS_DDI_SELECT_PORT(port);
 970
 971         switch (intel_crtc->config.pipe_bpp) {
 972         case 18:
 973                 temp |= TRANS_DDI_BPC_6;
 974                 break;
 975         case 24:
 976                 temp |= TRANS_DDI_BPC_8;
 977                 break;
 978         case 30:
 979                 temp |= TRANS_DDI_BPC_10;
 980                 break;
 981         case 36:
 982                 temp |= TRANS_DDI_BPC_12;
 983                 break;
 984         default:
 985                 BUG();
 986         }
 987
 988         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 989                 temp |= TRANS_DDI_PVSYNC;
 990         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 991                 temp |= TRANS_DDI_PHSYNC;
 992
 993         if (cpu_transcoder == TRANSCODER_EDP) {
 994                 switch (pipe) {
 995                 case PIPE_A:
 996                         /* On Haswell, can only use the always-on power well for
 997                          * eDP when not using the panel fitter, and when not
 998                          * using motion blur mitigation (which we don't
 999                          * support). */
1000                         if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled)
1001                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1002                         else
1003                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1004                         break;
1005                 case PIPE_B:
1006                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1007                         break;
1008                 case PIPE_C:
1009                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1010                         break;
1011                 default:
1012                         BUG();
1013                         break;
1014                 }
1015         }
1016
1017         if (type == INTEL_OUTPUT_HDMI) {
1018                 if (intel_crtc->config.has_hdmi_sink)
1019                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1020                 else
1021                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1022
1023         } else if (type == INTEL_OUTPUT_ANALOG) {
1024                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1025                 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
1026
1027         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1028                    type == INTEL_OUTPUT_EDP) {
1029                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1030
1031                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1032
1033                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1034         } else {
1035                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1036                      intel_encoder->type, pipe_name(pipe));
1037         }
1038
1039         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1040 }
1041
1042 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1043                                        enum transcoder cpu_transcoder)
1044 {
1045         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1046         uint32_t val = I915_READ(reg);
1047
1048         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1049         val |= TRANS_DDI_PORT_NONE;
1050         I915_WRITE(reg, val);
1051 }
1052
1053 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1054 {
1055         struct drm_device *dev = intel_connector->base.dev;
1056         struct drm_i915_private *dev_priv = dev->dev_private;
1057         struct intel_encoder *intel_encoder = intel_connector->encoder;
1058         int type = intel_connector->base.connector_type;
1059         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1060         enum i915_pipe pipe = 0;
1061         enum transcoder cpu_transcoder;
1062         enum intel_display_power_domain power_domain;
1063         uint32_t tmp;
1064
1065         power_domain = intel_display_port_power_domain(intel_encoder);
1066         if (!intel_display_power_enabled(dev_priv, power_domain))
1067                 return false;
1068
1069         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1070                 return false;
1071
1072         if (port == PORT_A)
1073                 cpu_transcoder = TRANSCODER_EDP;
1074         else
1075                 cpu_transcoder = (enum transcoder) pipe;
1076
1077         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1078
1079         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1080         case TRANS_DDI_MODE_SELECT_HDMI:
1081         case TRANS_DDI_MODE_SELECT_DVI:
1082                 return (type == DRM_MODE_CONNECTOR_HDMIA);
1083
1084         case TRANS_DDI_MODE_SELECT_DP_SST:
1085                 if (type == DRM_MODE_CONNECTOR_eDP)
1086                         return true;
1087         case TRANS_DDI_MODE_SELECT_DP_MST:
1088                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1089
1090         case TRANS_DDI_MODE_SELECT_FDI:
1091                 return (type == DRM_MODE_CONNECTOR_VGA);
1092
1093         default:
1094                 return false;
1095         }
1096 }
1097
1098 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1099                             enum i915_pipe *pipe)
1100 {
1101         struct drm_device *dev = encoder->base.dev;
1102         struct drm_i915_private *dev_priv = dev->dev_private;
1103         enum port port = intel_ddi_get_encoder_port(encoder);
1104         enum intel_display_power_domain power_domain;
1105         u32 tmp;
1106         int i;
1107
1108         power_domain = intel_display_port_power_domain(encoder);
1109         if (!intel_display_power_enabled(dev_priv, power_domain))
1110                 return false;
1111
1112         tmp = I915_READ(DDI_BUF_CTL(port));
1113
1114         if (!(tmp & DDI_BUF_CTL_ENABLE))
1115                 return false;
1116
1117         if (port == PORT_A) {
1118                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1119
1120                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1121                 case TRANS_DDI_EDP_INPUT_A_ON:
1122                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1123                         *pipe = PIPE_A;
1124                         break;
1125                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1126                         *pipe = PIPE_B;
1127                         break;
1128                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1129                         *pipe = PIPE_C;
1130                         break;
1131                 }
1132
1133                 return true;
1134         } else {
1135                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1136                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1137
1138                         if ((tmp & TRANS_DDI_PORT_MASK)
1139                             == TRANS_DDI_SELECT_PORT(port)) {
1140                                 *pipe = i;
1141                                 return true;
1142                         }
1143                 }
1144         }
1145
1146         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1147
1148         return false;
1149 }
1150
1151 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1152                                        enum i915_pipe pipe)
1153 {
1154         uint32_t temp, ret;
1155         enum port port = I915_MAX_PORTS;
1156         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1157                                                                       pipe);
1158         int i;
1159
1160         if (cpu_transcoder == TRANSCODER_EDP) {
1161                 port = PORT_A;
1162         } else {
1163                 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1164                 temp &= TRANS_DDI_PORT_MASK;
1165
1166                 for (i = PORT_B; i <= PORT_E; i++)
1167                         if (temp == TRANS_DDI_SELECT_PORT(i))
1168                                 port = i;
1169         }
1170
1171         if (port == I915_MAX_PORTS) {
1172                 WARN(1, "Pipe %c enabled on an unknown port\n",
1173                      pipe_name(pipe));
1174                 ret = PORT_CLK_SEL_NONE;
1175         } else {
1176                 ret = I915_READ(PORT_CLK_SEL(port));
1177                 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1178                               "0x%08x\n", pipe_name(pipe), port_name(port),
1179                               ret);
1180         }
1181
1182         return ret;
1183 }
1184
1185 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1186 {
1187         struct drm_i915_private *dev_priv = dev->dev_private;
1188         enum i915_pipe pipe;
1189         struct intel_crtc *intel_crtc;
1190
1191         dev_priv->ddi_plls.spll_refcount = 0;
1192         dev_priv->ddi_plls.wrpll1_refcount = 0;
1193         dev_priv->ddi_plls.wrpll2_refcount = 0;
1194
1195         for_each_pipe(pipe) {
1196                 intel_crtc =
1197                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1198
1199                 if (!intel_crtc->active) {
1200                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
1201                         continue;
1202                 }
1203
1204                 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1205                                                                  pipe);
1206
1207                 switch (intel_crtc->ddi_pll_sel) {
1208                 case PORT_CLK_SEL_SPLL:
1209                         dev_priv->ddi_plls.spll_refcount++;
1210                         break;
1211                 case PORT_CLK_SEL_WRPLL1:
1212                         dev_priv->ddi_plls.wrpll1_refcount++;
1213                         break;
1214                 case PORT_CLK_SEL_WRPLL2:
1215                         dev_priv->ddi_plls.wrpll2_refcount++;
1216                         break;
1217                 }
1218         }
1219 }
1220
1221 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1222 {
1223         struct drm_crtc *crtc = &intel_crtc->base;
1224         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1225         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1226         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1227         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1228
1229         if (cpu_transcoder != TRANSCODER_EDP)
1230                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1231                            TRANS_CLK_SEL_PORT(port));
1232 }
1233
1234 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1235 {
1236         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1237         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1238
1239         if (cpu_transcoder != TRANSCODER_EDP)
1240                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1241                            TRANS_CLK_SEL_DISABLED);
1242 }
1243
1244 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1245 {
1246         struct drm_encoder *encoder = &intel_encoder->base;
1247         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1248         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1249         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1250         int type = intel_encoder->type;
1251
1252         if (crtc->config.has_audio) {
1253                 DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
1254                                  pipe_name(crtc->pipe));
1255
1256                 /* write eld */
1257                 DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
1258                 intel_write_eld(encoder, &crtc->config.adjusted_mode);
1259         }
1260
1261         if (type == INTEL_OUTPUT_EDP) {
1262                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1263                 intel_edp_panel_on(intel_dp);
1264         }
1265
1266         WARN_ON(crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1267         I915_WRITE(PORT_CLK_SEL(port), crtc->ddi_pll_sel);
1268
1269         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1270                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1271                 struct intel_digital_port *intel_dig_port =
1272                         enc_to_dig_port(encoder);
1273
1274                 intel_dp->DP = intel_dig_port->saved_port_bits |
1275                                DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
1276                 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1277
1278                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1279                 intel_dp_start_link_train(intel_dp);
1280                 intel_dp_complete_link_train(intel_dp);
1281                 if (port != PORT_A)
1282                         intel_dp_stop_link_train(intel_dp);
1283         } else if (type == INTEL_OUTPUT_HDMI) {
1284                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1285
1286                 intel_hdmi->set_infoframes(encoder,
1287                                            crtc->config.has_hdmi_sink,
1288                                            &crtc->config.adjusted_mode);
1289         }
1290 }
1291
1292 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1293 {
1294         struct drm_encoder *encoder = &intel_encoder->base;
1295         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1296         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1297         int type = intel_encoder->type;
1298         uint32_t val;
1299         bool wait = false;
1300
1301         val = I915_READ(DDI_BUF_CTL(port));
1302         if (val & DDI_BUF_CTL_ENABLE) {
1303                 val &= ~DDI_BUF_CTL_ENABLE;
1304                 I915_WRITE(DDI_BUF_CTL(port), val);
1305                 wait = true;
1306         }
1307
1308         val = I915_READ(DP_TP_CTL(port));
1309         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1310         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1311         I915_WRITE(DP_TP_CTL(port), val);
1312
1313         if (wait)
1314                 intel_wait_ddi_buf_idle(dev_priv, port);
1315
1316         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1317                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1318                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1319                 intel_edp_panel_vdd_on(intel_dp);
1320                 intel_edp_panel_off(intel_dp);
1321         }
1322
1323         I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1324 }
1325
1326 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1327 {
1328         struct drm_encoder *encoder = &intel_encoder->base;
1329         struct drm_crtc *crtc = encoder->crtc;
1330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1331         int pipe = intel_crtc->pipe;
1332         struct drm_device *dev = encoder->dev;
1333         struct drm_i915_private *dev_priv = dev->dev_private;
1334         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1335         int type = intel_encoder->type;
1336         uint32_t tmp;
1337
1338         if (type == INTEL_OUTPUT_HDMI) {
1339                 struct intel_digital_port *intel_dig_port =
1340                         enc_to_dig_port(encoder);
1341
1342                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1343                  * are ignored so nothing special needs to be done besides
1344                  * enabling the port.
1345                  */
1346                 I915_WRITE(DDI_BUF_CTL(port),
1347                            intel_dig_port->saved_port_bits |
1348                            DDI_BUF_CTL_ENABLE);
1349         } else if (type == INTEL_OUTPUT_EDP) {
1350                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1351
1352                 if (port == PORT_A)
1353                         intel_dp_stop_link_train(intel_dp);
1354
1355                 intel_edp_backlight_on(intel_dp);
1356                 intel_edp_psr_enable(intel_dp);
1357         }
1358
1359         if (intel_crtc->config.has_audio) {
1360                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1361                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1362                 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1363                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1364         }
1365 }
1366
1367 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1368 {
1369         struct drm_encoder *encoder = &intel_encoder->base;
1370         struct drm_crtc *crtc = encoder->crtc;
1371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1372         int pipe = intel_crtc->pipe;
1373         int type = intel_encoder->type;
1374         struct drm_device *dev = encoder->dev;
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         uint32_t tmp;
1377
1378         /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this
1379          * register is part of the power well on Haswell. */
1380         if (intel_crtc->config.has_audio) {
1381                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1382                 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1383                          (pipe * 4));
1384                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1385                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1386         }
1387
1388         if (type == INTEL_OUTPUT_EDP) {
1389                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1390
1391                 intel_edp_psr_disable(intel_dp);
1392                 intel_edp_backlight_off(intel_dp);
1393         }
1394 }
1395
1396 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1397 {
1398         struct drm_device *dev = dev_priv->dev;
1399         uint32_t lcpll = I915_READ(LCPLL_CTL);
1400         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1401
1402         if (lcpll & LCPLL_CD_SOURCE_FCLK) {
1403                 return 800000;
1404         } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) {
1405                 return 450000;
1406         } else if (freq == LCPLL_CLK_FREQ_450) {
1407                 return 450000;
1408         } else if (IS_HASWELL(dev)) {
1409                 if (IS_ULT(dev))
1410                         return 337500;
1411                 else
1412                         return 540000;
1413         } else {
1414                 if (freq == LCPLL_CLK_FREQ_54O_BDW)
1415                         return 540000;
1416                 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1417                         return 337500;
1418                 else
1419                         return 675000;
1420         }
1421 }
1422
1423 void intel_ddi_pll_init(struct drm_device *dev)
1424 {
1425         struct drm_i915_private *dev_priv = dev->dev_private;
1426         uint32_t val = I915_READ(LCPLL_CTL);
1427
1428         /* The LCPLL register should be turned on by the BIOS. For now let's
1429          * just check its state and print errors in case something is wrong.
1430          * Don't even try to turn it on.
1431          */
1432
1433         DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1434                       intel_ddi_get_cdclk_freq(dev_priv));
1435
1436         if (val & LCPLL_CD_SOURCE_FCLK)
1437                 DRM_ERROR("CDCLK source is not LCPLL\n");
1438
1439         if (val & LCPLL_PLL_DISABLE)
1440                 DRM_ERROR("LCPLL is disabled\n");
1441 }
1442
1443 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1444 {
1445         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1446         struct intel_dp *intel_dp = &intel_dig_port->dp;
1447         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1448         enum port port = intel_dig_port->port;
1449         uint32_t val;
1450         bool wait = false;
1451
1452         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1453                 val = I915_READ(DDI_BUF_CTL(port));
1454                 if (val & DDI_BUF_CTL_ENABLE) {
1455                         val &= ~DDI_BUF_CTL_ENABLE;
1456                         I915_WRITE(DDI_BUF_CTL(port), val);
1457                         wait = true;
1458                 }
1459
1460                 val = I915_READ(DP_TP_CTL(port));
1461                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1462                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1463                 I915_WRITE(DP_TP_CTL(port), val);
1464                 POSTING_READ(DP_TP_CTL(port));
1465
1466                 if (wait)
1467                         intel_wait_ddi_buf_idle(dev_priv, port);
1468         }
1469
1470         val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1471               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1472         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1473                 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1474         I915_WRITE(DP_TP_CTL(port), val);
1475         POSTING_READ(DP_TP_CTL(port));
1476
1477         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1478         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1479         POSTING_READ(DDI_BUF_CTL(port));
1480
1481         udelay(600);
1482 }
1483
1484 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1485 {
1486         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1487         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1488         uint32_t val;
1489
1490         intel_ddi_post_disable(intel_encoder);
1491
1492         val = I915_READ(_FDI_RXA_CTL);
1493         val &= ~FDI_RX_ENABLE;
1494         I915_WRITE(_FDI_RXA_CTL, val);
1495
1496         val = I915_READ(_FDI_RXA_MISC);
1497         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1498         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1499         I915_WRITE(_FDI_RXA_MISC, val);
1500
1501         val = I915_READ(_FDI_RXA_CTL);
1502         val &= ~FDI_PCDCLK;
1503         I915_WRITE(_FDI_RXA_CTL, val);
1504
1505         val = I915_READ(_FDI_RXA_CTL);
1506         val &= ~FDI_RX_PLL_ENABLE;
1507         I915_WRITE(_FDI_RXA_CTL, val);
1508 }
1509
1510 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1511 {
1512         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1513         int type = intel_encoder->type;
1514
1515         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1516                 intel_dp_check_link_status(intel_dp);
1517 }
1518
1519 void intel_ddi_get_config(struct intel_encoder *encoder,
1520                           struct intel_crtc_config *pipe_config)
1521 {
1522         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1523         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1524         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1525         u32 temp, flags = 0;
1526
1527         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1528         if (temp & TRANS_DDI_PHSYNC)
1529                 flags |= DRM_MODE_FLAG_PHSYNC;
1530         else
1531                 flags |= DRM_MODE_FLAG_NHSYNC;
1532         if (temp & TRANS_DDI_PVSYNC)
1533                 flags |= DRM_MODE_FLAG_PVSYNC;
1534         else
1535                 flags |= DRM_MODE_FLAG_NVSYNC;
1536
1537         pipe_config->adjusted_mode.flags |= flags;
1538
1539         switch (temp & TRANS_DDI_BPC_MASK) {
1540         case TRANS_DDI_BPC_6:
1541                 pipe_config->pipe_bpp = 18;
1542                 break;
1543         case TRANS_DDI_BPC_8:
1544                 pipe_config->pipe_bpp = 24;
1545                 break;
1546         case TRANS_DDI_BPC_10:
1547                 pipe_config->pipe_bpp = 30;
1548                 break;
1549         case TRANS_DDI_BPC_12:
1550                 pipe_config->pipe_bpp = 36;
1551                 break;
1552         default:
1553                 break;
1554         }
1555
1556         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1557         case TRANS_DDI_MODE_SELECT_HDMI:
1558                 pipe_config->has_hdmi_sink = true;
1559         case TRANS_DDI_MODE_SELECT_DVI:
1560         case TRANS_DDI_MODE_SELECT_FDI:
1561                 break;
1562         case TRANS_DDI_MODE_SELECT_DP_SST:
1563         case TRANS_DDI_MODE_SELECT_DP_MST:
1564                 pipe_config->has_dp_encoder = true;
1565                 intel_dp_get_m_n(intel_crtc, pipe_config);
1566                 break;
1567         default:
1568                 break;
1569         }
1570
1571         if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1572                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1573                 if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
1574                         pipe_config->has_audio = true;
1575         }
1576
1577         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1578             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1579                 /*
1580                  * This is a big fat ugly hack.
1581                  *
1582                  * Some machines in UEFI boot mode provide us a VBT that has 18
1583                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1584                  * unknown we fail to light up. Yet the same BIOS boots up with
1585                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1586                  * max, not what it tells us to use.
1587                  *
1588                  * Note: This will still be broken if the eDP panel is not lit
1589                  * up by the BIOS, and thus we can't get the mode at module
1590                  * load.
1591                  */
1592                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1593                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1594                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1595         }
1596
1597         intel_ddi_clock_get(encoder, pipe_config);
1598 }
1599
1600 static void intel_ddi_destroy(struct drm_encoder *encoder)
1601 {
1602         /* HDMI has nothing special to destroy, so we can go with this. */
1603         intel_dp_encoder_destroy(encoder);
1604 }
1605
1606 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1607                                      struct intel_crtc_config *pipe_config)
1608 {
1609         int type = encoder->type;
1610         int port = intel_ddi_get_encoder_port(encoder);
1611
1612         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1613
1614         if (port == PORT_A)
1615                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1616
1617         if (type == INTEL_OUTPUT_HDMI)
1618                 return intel_hdmi_compute_config(encoder, pipe_config);
1619         else
1620                 return intel_dp_compute_config(encoder, pipe_config);
1621 }
1622
1623 static const struct drm_encoder_funcs intel_ddi_funcs = {
1624         .destroy = intel_ddi_destroy,
1625 };
1626
1627 static struct intel_connector *
1628 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1629 {
1630         struct intel_connector *connector;
1631         enum port port = intel_dig_port->port;
1632
1633         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1634         if (!connector)
1635                 return NULL;
1636
1637         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1638         if (!intel_dp_init_connector(intel_dig_port, connector)) {
1639                 kfree(connector);
1640                 return NULL;
1641         }
1642
1643         return connector;
1644 }
1645
1646 static struct intel_connector *
1647 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1648 {
1649         struct intel_connector *connector;
1650         enum port port = intel_dig_port->port;
1651
1652         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1653         if (!connector)
1654                 return NULL;
1655
1656         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1657         intel_hdmi_init_connector(intel_dig_port, connector);
1658
1659         return connector;
1660 }
1661
1662 void intel_ddi_init(struct drm_device *dev, enum port port)
1663 {
1664         struct drm_i915_private *dev_priv = dev->dev_private;
1665         struct intel_digital_port *intel_dig_port;
1666         struct intel_encoder *intel_encoder;
1667         struct drm_encoder *encoder;
1668         struct intel_connector *hdmi_connector = NULL;
1669         struct intel_connector *dp_connector = NULL;
1670         bool init_hdmi, init_dp;
1671
1672         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1673                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1674         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1675         if (!init_dp && !init_hdmi) {
1676                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
1677                               port_name(port));
1678                 init_hdmi = true;
1679                 init_dp = true;
1680         }
1681
1682         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1683         if (!intel_dig_port)
1684                 return;
1685
1686         intel_encoder = &intel_dig_port->base;
1687         encoder = &intel_encoder->base;
1688
1689         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1690                          DRM_MODE_ENCODER_TMDS);
1691
1692         intel_encoder->compute_config = intel_ddi_compute_config;
1693         intel_encoder->enable = intel_enable_ddi;
1694         intel_encoder->pre_enable = intel_ddi_pre_enable;
1695         intel_encoder->disable = intel_disable_ddi;
1696         intel_encoder->post_disable = intel_ddi_post_disable;
1697         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1698         intel_encoder->get_config = intel_ddi_get_config;
1699
1700         intel_dig_port->port = port;
1701         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1702                                           (DDI_BUF_PORT_REVERSAL |
1703                                            DDI_A_4_LANES);
1704
1705         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1706         intel_encoder->crtc_mask =  (1 << 0) | (1 << 1) | (1 << 2);
1707         intel_encoder->cloneable = 0;
1708         intel_encoder->hot_plug = intel_ddi_hot_plug;
1709
1710         if (init_dp)
1711                 dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
1712
1713         /* In theory we don't need the encoder->type check, but leave it just in
1714          * case we have some really bad VBTs... */
1715         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
1716                 hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
1717
1718         if (!dp_connector && !hdmi_connector) {
1719                 drm_encoder_cleanup(encoder);
1720                 kfree(intel_dig_port);
1721         }
1722 }