2 * ----------------------------------------------------------------------------
3 * "THE BEER-WARE LICENSE" (Revision 42):
4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you
5 * can do whatever you want with this stuff. If we meet some day, and you think
6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
7 * ----------------------------------------------------------------------------
9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $
11 * Driver for Siemens reference design card "Easy321-R1".
13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC
16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't
19 * The FALC54 and MUNICH32X have far too many registers and weird modes for
20 * comfort, so I have not bothered typing it all into a "fooreg.h" file,
21 * you will (badly!) need the documentation anyway if you want to mess with
24 * $FreeBSD: src/sys/pci/if_mn.c,v 1.11.2.3 2001/01/23 12:47:09 phk Exp $
28 * Stuff to describe the MUNIC32X and FALC54 chips.
31 #define M32_CHAN 32 /* We have 32 channels */
32 #define M32_TS 32 /* We have 32 timeslots */
34 #define NG_MN_NODE_TYPE "mn"
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/sysctl.h>
42 #include <sys/malloc.h>
45 #include <bus/pci/pcireg.h>
46 #include <bus/pci/pcivar.h>
49 #include <machine/clock.h>
54 #include <netgraph/ng_message.h>
55 #include <netgraph/netgraph.h>
58 static int mn_maxlatency = 1000;
59 SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW,
61 "The number of milliseconds a packet is allowed to spend in the output queue. "
62 "If the output queue is longer than this number of milliseconds when the packet "
63 "arrives for output, the packet will be dropped."
67 /* Most machines don't support more than 4 busmaster PCI slots, if even that many */
71 /* From: PEB 20321 data sheet, p187, table 22 */
73 u_int32_t conf, cmd, stat, imask;
74 u_int32_t fill10, piqba, piql, fill1c;
75 u_int32_t mode1, mode2, ccba, txpoll;
76 u_int32_t tiqba, tiql, riqba, riql;
77 u_int32_t lconf, lccba, fill48, ltran;
78 u_int32_t ltiqba, ltiql, lriqba, lriql;
79 u_int32_t lreg0, lreg1, lreg2, lreg3;
80 u_int32_t lreg4, lreg5, lre6, lstat;
81 u_int32_t gpdir, gpdata, gpod, fill8c;
82 u_int32_t ssccon, sscbr, ssctb, sscrb;
83 u_int32_t ssccse, sscim, fillab, fillac;
84 u_int32_t iomcon1, iomcon2, iomstat, fillbc;
85 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1;
86 u_int32_t iomtmo, iomrmo, filld8, filldc;
87 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3;
88 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7;
91 /* From: PEB 2254 data sheet, p80, table 10 */
94 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2;
95 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
96 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
97 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
98 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
99 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3;
100 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
101 u_int8_t lim2, fill39[7];
106 u_int8_t dec, fill61, test2, fill63[5];
111 /* From: PEB 2254 data sheet, p117, table 10 */
114 u_int8_t fill2, mode, rah1, rah2, ral1, ral2;
115 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
116 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
117 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
118 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
119 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13;
120 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
121 u_int8_t lim2, fill39[7];
123 u_int8_t fill48[4], frs0, frs1, rsw, rsp;
124 u_int16_t fec, cvc, cec1, ebc;
125 u_int16_t cec2, cec3;
126 u_int8_t rsa4, rsa5, rsa6, rsa7;
127 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis;
129 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr;
133 /* Transmit & receive descriptors */
138 u_int32_t status; /* only used for receive */
139 struct mbuf *m; /* software use only */
140 struct trxd *vnext; /* software use only */
143 /* Channel specification */
154 u_int32_t reserve1[2];
155 u_int32_t ts[M32_TS];
156 struct cspec cs[M32_CHAN];
157 vm_offset_t crxd[M32_CHAN];
158 vm_offset_t ctxd[M32_CHAN];
165 static int mn_probe (device_t self);
166 static int mn_attach (device_t self);
167 static void mn_create_channel(struct softc *sc, int chan);
168 static int mn_reset(struct softc *sc);
169 static struct trxd * mn_alloc_desc(void);
170 static void mn_free_desc(struct trxd *dp);
171 static void mn_intr(void *xsc);
172 static u_int32_t mn_parse_ts(const char *s, int *nbit);
174 static void m32_dump(struct softc *sc);
175 static void f54_dump(struct softc *sc);
176 static void mn_fmt_ts(char *p, u_int32_t ts);
178 static void f54_init(struct softc *sc);
180 static ng_constructor_t ngmn_constructor;
181 static ng_rcvmsg_t ngmn_rcvmsg;
182 static ng_shutdown_t ngmn_shutdown;
183 static ng_newhook_t ngmn_newhook;
184 static ng_connect_t ngmn_connect;
185 static ng_rcvdata_t ngmn_rcvdata;
186 static ng_disconnect_t ngmn_disconnect;
188 static struct ng_type mntypestruct = {
204 static MALLOC_DEFINE(M_MN, "mn", "Mx driver related");
209 enum {DOWN, UP} state;
214 struct trxd *r1, *rl;
215 struct trxd *x1, *xl;
226 u_long dribble_error;
229 u_long overflow_error;
238 enum framing {WHOKNOWS, E1, E1U, T1, T1U};
243 struct resource *irq;
245 enum framing framing;
248 vm_offset_t m0p, m1p;
249 struct m32xreg *m32x;
250 struct f54wreg *f54w;
251 struct f54rreg *f54r;
252 struct m32_mem m32_mem;
253 u_int32_t tiqb[NIQB];
254 u_int32_t riqb[NIQB];
255 u_int32_t piqb[NIQB];
256 u_int32_t ltiqb[NIQB];
257 u_int32_t lriqb[NIQB];
259 u_int32_t falc_irq, falc_state, framer_state;
260 struct schan *ch[M32_CHAN];
261 char nodename[NG_NODESIZ];
274 ngmn_constructor(node_p *nodep)
281 ngmn_shutdown(node_p nodep)
288 ngmn_config(node_p node, char *set, char *ret)
291 enum framing wframing;
296 if (!strncmp(set, "line ", 5)) {
297 wframing = sc->framing;
298 if (!strcmp(set, "line e1")) {
300 } else if (!strcmp(set, "line e1u")) {
303 strcat(ret, "ENOGROK\n");
306 if (wframing == sc->framing)
308 if (sc->nhooks > 0) {
309 ksprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks);
312 sc->framing = wframing;
319 kprintf("%s CONFIG SET [%s]\n", sc->nodename, set);
320 strcat(ret, "ENOGROK\n");
328 ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
337 if (msg->header.typecookie != NGM_GENERIC_COOKIE) {
340 FREE(msg, M_NETGRAPH);
344 if (msg->header.cmd != NGM_TEXT_CONFIG &&
345 msg->header.cmd != NGM_TEXT_STATUS) {
348 FREE(msg, M_NETGRAPH);
352 NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE,
355 FREE(msg, M_NETGRAPH);
359 if (msg->header.arglen)
360 s = (char *)msg->data;
363 r = (char *)(*resp)->data;
366 if (msg->header.cmd == NGM_TEXT_CONFIG) {
367 ngmn_config(node, s, r);
368 (*resp)->header.arglen = strlen(r) + 1;
369 FREE(msg, M_NETGRAPH);
374 pos += ksprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\20"
375 "\40LOS\37AIS\36LFA\35RRA"
376 "\34AUXP\33NMF\32LMFA\31frs0.0"
377 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
378 "\24TS16LFA\23frs1.2\22XLS\21XLO"
379 "\20RS1\17rsw.6\16RRA\15RY0"
380 "\14RY1\13RY2\12RY3\11RY4"
381 "\10SI1\7SI2\6rsp.5\5rsp.4"
382 "\4rsp.3\3RSIF\2RS13\1RS15");
383 pos += ksprintf(pos + r," Framing errors: %lu", sc->cnt_fec);
384 pos += ksprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc);
386 pos += ksprintf(pos + r," Falc State %b;\n", sc->falc_state, "\20"
387 "\40LOS\37AIS\36LFA\35RRA"
388 "\34AUXP\33NMF\32LMFA\31frs0.0"
389 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
390 "\24TS16LFA\23frs1.2\22XLS\21XLO"
391 "\20RS1\17rsw.6\16RRA\15RY0"
392 "\14RY1\13RY2\12RY3\11RY4"
393 "\10SI1\7SI2\6rsp.5\5rsp.4"
394 "\4rsp.3\3RSIF\2RS13\1RS15");
395 pos += ksprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\20"
396 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
397 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
398 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
399 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
400 for (i = 0; i < M32_CHAN; i++) {
405 pos += ksprintf(r + pos, " Chan %d <%s> ",
408 pos += ksprintf(r + pos, " Last Rx: ");
410 pos += ksprintf(r + pos, "%lu s", time_second - sch->last_recv);
412 pos += ksprintf(r + pos, "never");
414 pos += ksprintf(r + pos, ", last RxErr: ");
416 pos += ksprintf(r + pos, "%lu s", time_second - sch->last_rxerr);
418 pos += ksprintf(r + pos, "never");
420 pos += ksprintf(r + pos, ", last Tx: ");
422 pos += ksprintf(r + pos, "%lu s\n", time_second - sch->last_xmit);
424 pos += ksprintf(r + pos, "never\n");
426 pos += ksprintf(r + pos, " RX error(s) %lu", sch->rx_error);
427 pos += ksprintf(r + pos, " Short: %lu", sch->short_error);
428 pos += ksprintf(r + pos, " CRC: %lu", sch->crc_error);
429 pos += ksprintf(r + pos, " Mod8: %lu", sch->dribble_error);
430 pos += ksprintf(r + pos, " Long: %lu", sch->long_error);
431 pos += ksprintf(r + pos, " Abort: %lu", sch->abort_error);
432 pos += ksprintf(r + pos, " Overflow: %lu\n", sch->overflow_error);
434 pos += ksprintf(r + pos, " Last error: %b Prev error: %b\n",
435 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN",
436 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN");
437 pos += ksprintf(r + pos, " Xmit bytes pending %ld\n",
440 (*resp)->header.arglen = pos + 1;
441 FREE(msg, M_NETGRAPH);
446 ngmn_newhook(node_p node, hook_p hook, const char *name)
454 if (name[0] != 't' || name[1] != 's')
457 ts = mn_parse_ts(name + 2, &nbit);
458 kprintf("%d bits %x\n", nbit, ts);
459 if (sc->framing == E1 && (ts & 1))
461 if (sc->framing == E1U && nbit != 32)
465 if (sc->framing == E1)
470 mn_create_channel(sc, chan);
471 else if (sc->ch[chan]->state == UP)
473 sc->ch[chan]->ts = ts;
474 sc->ch[chan]->hook = hook;
475 sc->ch[chan]->tx_limit = nbit * 8;
476 hook->private = sc->ch[chan];
482 static struct trxd *mn_desc_free;
491 mn_desc_free = dp->vnext;
493 dp = (struct trxd *)kmalloc(sizeof *dp, M_MN, M_INTWAIT);
498 mn_free_desc(struct trxd *dp)
500 dp->vnext = mn_desc_free;
505 mn_parse_ts(const char *s, int *nbit)
515 i = strtol(s, &p, 0);
518 while (j != -1 && j < i) {
528 } else if (*p == '-') {
543 mn_fmt_ts(char *p, u_int32_t ts)
550 for (j = 0; j < 32; j++) {
551 if (!(ts & (1 << j)))
553 ksprintf(p, "%s%d", s, j);
556 if (!(ts & (1 << (j+1))))
559 if (!(ts & (1 << (j+1))))
561 ksprintf(p, "-%d", j);
573 ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
576 struct trxd *dp, *dp2;
579 int chan, pitch, len;
585 if (sch->state != UP) {
586 NG_FREE_DATA(m, meta);
589 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) {
590 NG_FREE_DATA(m, meta);
596 dp2 = sc->ch[chan]->xl;
597 len = m->m_pkthdr.len;
599 dp = mn_alloc_desc();
603 sc->ch[chan]->xl = dp2;
610 sc->ch[chan]->xl->vnext = 0;
613 dp->data = vtophys(m2->m_data);
614 dp->flags = m2->m_len << 16;
617 dp->next = vtophys(dp);
619 sc->ch[chan]->xl->next = vtophys(dp);
620 sc->ch[chan]->xl->vnext = dp;
621 sc->ch[chan]->xl = dp;
624 dp->flags |= 0xc0000000;
625 dp2->flags &= ~0x40000000;
632 kprintf("%s%d: Short on mem, pitched %d packets\n",
633 sc->name, chan, pitch);
636 kprintf("%d = %d + %d (%p)\n",
637 sch->tx_pending + m->m_pkthdr.len,
638 sch->tx_pending , m->m_pkthdr.len, m);
640 sch->tx_pending += m->m_pkthdr.len;
641 sc->m32x->txpoll &= ~(1 << chan);
650 ngmn_connect(hook_p hook)
653 struct trxd *dp, *dp2;
663 if (sch->state == UP)
667 /* Count and configure the timeslots for this channel */
668 for (nts = i = 0; i < 32; i++)
669 if (sch->ts & (1 << i)) {
670 sc->m32_mem.ts[i] = 0x00ff00ff |
671 (chan << 24) | (chan << 8);
675 /* Init the receiver & xmitter to HDLC */
676 sc->m32_mem.cs[chan].flags = 0x80e90006;
677 /* Allocate two buffers per timeslot */
679 sc->m32_mem.cs[chan].itbs = 63;
681 sc->m32_mem.cs[chan].itbs = nts * 2;
683 /* Setup a transmit chain with one descriptor */
684 /* XXX: we actually send a 1 byte packet */
685 dp = mn_alloc_desc();
686 MGETHDR(m, MB_WAIT, MT_DATA);
691 dp->flags = 0xc0000000 + (1 << 16);
692 dp->next = vtophys(dp);
694 dp->data = vtophys(sc->name);
695 sc->m32_mem.cs[chan].tdesc = vtophys(dp);
696 sc->ch[chan]->x1 = dp;
697 sc->ch[chan]->xl = dp;
699 /* Setup a receive chain with 5 + NTS descriptors */
701 dp = mn_alloc_desc();
703 MGETHDR(m, MB_WAIT, MT_DATA);
709 if ((m->m_flags & M_EXT) == 0) {
715 dp->data = vtophys(m->m_data);
716 dp->flags = 0x40000000;
717 dp->flags += 1600 << 16;
718 dp->next = vtophys(dp);
720 sc->ch[chan]->rl = dp;
722 for (i = 0; i < (nts + 10); i++) {
724 dp = mn_alloc_desc();
726 MGETHDR(m, MB_WAIT, MT_DATA);
733 if ((m->m_flags & M_EXT) == 0) {
739 dp->data = vtophys(m->m_data);
740 dp->flags = 0x00000000;
741 dp->flags += 1600 << 16;
742 dp->next = vtophys(dp2);
745 sc->m32_mem.cs[chan].rdesc = vtophys(dp);
746 sc->ch[chan]->r1 = dp;
748 /* Initialize this channel */
749 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
754 kprintf("%s: init chan %d stat %08x\n", sc->name, chan, u);
764 ngmn_disconnect(hook_p hook)
769 struct trxd *dp, *dp2;
776 if (sch->state == DOWN)
780 /* Set receiver & transmitter off */
781 sc->m32_mem.cs[chan].flags = 0x80920006;
782 sc->m32_mem.cs[chan].itbs = 0;
784 /* free the timeslots */
785 for (i = 0; i < 32; i++)
786 if (sc->ch[chan]->ts & (1 << i))
787 sc->m32_mem.ts[i] = 0x20002000;
789 /* Initialize this channel */
790 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
795 kprintf("%s: zap chan %d stat %08x\n", sc->name, chan, u);
798 /* Free all receive descriptors and mbufs */
799 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) {
802 sc->ch[chan]->r1 = dp2 = dp->vnext;
806 /* Free all transmit descriptors and mbufs */
807 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) {
809 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len;
812 sc->ch[chan]->x1 = dp2 = dp->vnext;
820 * Create a new channel.
823 mn_create_channel(struct softc *sc, int chan)
827 sch = sc->ch[chan] = (struct schan *)kmalloc(sizeof *sc->ch[chan],
828 M_MN, M_WAITOK | M_ZERO);
832 ksprintf(sch->name, "%s%d", sc->name, chan);
838 * Dump Munich32x state
841 m32_dump(struct softc *sc)
846 kprintf("mn%d: MUNICH32X dump\n", sc->unit);
847 tp4 = (u_int32_t *)sc->m0v;
848 for(j = 0; j < 64; j += 8) {
849 kprintf("%02x", j * sizeof *tp4);
850 for(i = 0; i < 8; i++)
851 kprintf(" %08x", tp4[i+j]);
854 for(j = 0; j < M32_CHAN; j++) {
857 kprintf("CH%d: state %d ts %08x",
858 j, sc->ch[j]->state, sc->ch[j]->ts);
859 kprintf(" %08x %08x %08x %08x %08x %08x\n",
860 sc->m32_mem.cs[j].flags,
861 sc->m32_mem.cs[j].rdesc,
862 sc->m32_mem.cs[j].tdesc,
863 sc->m32_mem.cs[j].itbs,
865 sc->m32_mem.ctxd[j] );
873 f54_dump(struct softc *sc)
878 kprintf("%s: FALC54 dump\n", sc->name);
879 tp1 = (u_int8_t *)sc->m1v;
880 for(j = 0; j < 128; j += 16) {
881 kprintf("%s: %02x |", sc->name, j * sizeof *tp1);
882 for(i = 0; i < 16; i++)
883 kprintf(" %02x", tp1[i+j]);
893 m32_init(struct softc *sc)
896 sc->m32x->conf = 0x00000000;
897 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */
899 sc->m32x->mode2 = 0x00000081;
900 sc->m32x->txpoll = 0xffffffff;
902 sc->m32x->mode2 = 0x00000081;
903 sc->m32x->txpoll = 0xffffffff;
905 sc->m32x->mode2 = 0x00000101;
907 sc->m32x->lconf = 0x6060009B;
908 sc->m32x->imask = 0x00000000;
915 f54_init(struct softc *sc)
917 sc->f54w->ipc = 0x07;
919 sc->f54w->xpm0 = 0xbd;
920 sc->f54w->xpm1 = 0x03;
921 sc->f54w->xpm2 = 0x00;
923 sc->f54w->imr0 = 0x18; /* RMB, CASC */
924 sc->f54w->imr1 = 0x08; /* XMB */
925 sc->f54w->imr2 = 0x00;
926 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */
927 sc->f54w->imr4 = 0x00;
929 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */
930 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */
931 if (sc->framing == E1)
932 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */
933 else if (sc->framing == E1U)
934 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */
936 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */
937 sc->f54w->pcd = 0x0a;
938 sc->f54w->pcr = 0x15;
939 sc->f54w->xsw = 0x9f; /* fmr4 */
940 if (sc->framing == E1)
941 sc->f54w->xsp = 0x1c; /* fmr5 */
942 else if (sc->framing == E1U)
943 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */
944 sc->f54w->xc0 = 0x07;
945 sc->f54w->xc1 = 0x3d;
946 sc->f54w->rc0 = 0x05;
947 sc->f54w->rc1 = 0x00;
948 sc->f54w->cmdr = 0x51;
952 mn_reset(struct softc *sc)
957 sc->m32x->ccba = vtophys(&sc->m32_mem.csa);
958 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb);
960 bzero(sc->tiqb, sizeof sc->tiqb);
961 sc->m32x->tiqba = vtophys(&sc->tiqb);
962 sc->m32x->tiql = NIQB / 16 - 1;
964 bzero(sc->riqb, sizeof sc->riqb);
965 sc->m32x->riqba = vtophys(&sc->riqb);
966 sc->m32x->riql = NIQB / 16 - 1;
968 bzero(sc->ltiqb, sizeof sc->ltiqb);
969 sc->m32x->ltiqba = vtophys(&sc->ltiqb);
970 sc->m32x->ltiql = NIQB / 16 - 1;
972 bzero(sc->lriqb, sizeof sc->lriqb);
973 sc->m32x->lriqba = vtophys(&sc->lriqb);
974 sc->m32x->lriql = NIQB / 16 - 1;
976 bzero(sc->piqb, sizeof sc->piqb);
977 sc->m32x->piqba = vtophys(&sc->piqb);
978 sc->m32x->piql = NIQB / 16 - 1;
985 sc->m32_mem.ccb = 0x4;
991 /* set all timeslots to known state */
992 for (i = 0; i < 32; i++)
993 sc->m32_mem.ts[i] = 0x20002000;
997 "mn%d: WARNING: Controller failed the PCI bus-master test.\n"
998 "mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n",
1006 * FALC54 interrupt handling
1009 f54_intr(struct softc *sc)
1014 u = sc->f54r->isr0 << 24;
1015 u |= sc->f54r->isr1 << 16;
1016 u |= sc->f54r->isr2 << 8;
1017 u |= sc->f54r->isr3;
1019 /* don't chat about the 1 sec heart beat */
1022 kprintf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20"
1023 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
1024 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
1025 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
1026 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
1028 s = sc->f54r->frs0 << 24;
1029 s |= sc->f54r->frs1 << 16;
1030 s |= sc->f54r->rsw << 8;
1034 s &= ~0x01844038; /* undefined or static bits */
1035 s &= ~0x00009fc7; /* bits we don't care about */
1036 s &= ~0x00780000; /* XXX: TS16 related */
1037 s &= ~0x06000000; /* XXX: Multiframe related */
1039 kprintf("%s*: FALC54 Status %b\n", sc->name, s, "\20"
1040 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0"
1041 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO"
1042 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4"
1043 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15");
1045 if (s != sc->framer_state) {
1047 for (i = 0; i < M32_CHAN; i++) {
1050 sp = &sc->ch[i]->ifsppp;
1051 if (!(sp->pp_if.if_flags & IFF_UP))
1054 timeout((timeout_t *)sp->pp_down, sp, 1 * hz);
1056 timeout((timeout_t *)sp->pp_up, sp, 1 * hz);
1059 sc->framer_state = s;
1062 /* Once per second check error counters */
1063 /* XXX: not clear if this is actually ok */
1066 sc->cnt_fec += sc->f54r->fec;
1067 sc->cnt_cvc += sc->f54r->cvc;
1068 sc->cnt_cec1 += sc->f54r->cec1;
1069 sc->cnt_ebc += sc->f54r->ebc;
1070 sc->cnt_cec2 += sc->f54r->cec2;
1071 sc->cnt_cec3 += sc->f54r->cec3;
1072 sc->cnt_rbc += sc->f54r->rbc;
1076 * Transmit interrupt for one channel
1079 mn_tx_intr(struct softc *sc, u_int32_t vector)
1085 chan = vector & 0x1f;
1088 if (sc->ch[chan]->state != UP) {
1089 kprintf("%s: tx_intr when not UP\n", sc->name);
1093 dp = sc->ch[chan]->x1;
1094 if (vtophys(dp) == sc->m32_mem.ctxd[chan])
1099 kprintf("%d = %d - %d (%p)\n",
1100 sc->ch[chan]->tx_pending - m->m_pkthdr.len,
1101 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m);
1103 sc->ch[chan]->tx_pending -= m->m_pkthdr.len;
1106 sc->ch[chan]->last_xmit = time_second;
1107 sc->ch[chan]->x1 = dp->vnext;
1113 * Receive interrupt for one channel
1116 mn_rx_intr(struct softc *sc, u_int32_t vector)
1118 u_int32_t chan, err;
1123 chan = vector & 0x1f;
1127 if (sch->state != UP) {
1128 kprintf("%s: rx_intr when not UP\n", sc->name);
1132 if (vector == 0x30000b00)
1136 if (vtophys(dp) == sc->m32_mem.crxd[chan])
1140 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff;
1141 err = (dp->status >> 8) & 0xff;
1143 ng_queue_data(sch->hook, m, NULL);
1144 sch->last_recv = time_second;
1146 /* we could be down by now... */
1147 if (sch->state != UP)
1149 } else if (err & 0x40) {
1151 } else if (err & 0x10) {
1153 } else if (err & 0x08) {
1154 sch->dribble_error++;
1155 } else if (err & 0x04) {
1157 } else if (err & 0x02) {
1159 } else if (err & 0x01) {
1160 sch->overflow_error++;
1163 sch->last_rxerr = time_second;
1164 sch->prev_error = sch->last_error;
1165 sch->last_error = err;
1168 sc->ch[chan]->r1 = dp->vnext;
1170 /* Replenish desc + mbuf supplies */
1172 MGETHDR(m, MB_DONTWAIT, MT_DATA);
1175 return; /* ENOBUFS */
1177 MCLGET(m, MB_DONTWAIT);
1178 if((m->m_flags & M_EXT) == 0) {
1181 return; /* ENOBUFS */
1185 dp->data = vtophys(m->m_data);
1186 dp->flags = 0x40000000;
1187 dp->flags += 1600 << 16;
1188 dp->next = vtophys(dp);
1190 sc->ch[chan]->rl->next = vtophys(dp);
1191 sc->ch[chan]->rl->vnext = dp;
1192 sc->ch[chan]->rl->flags &= ~0x40000000;
1193 sc->ch[chan]->rl = dp;
1206 u_int32_t stat, lstat, u;
1210 stat = sc->m32x->stat;
1211 lstat = sc->m32x->lstat;
1213 if (!stat && !(lstat & 2))
1217 if (stat & ~0xc200) {
1218 kprintf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat);
1221 if ((stat & 0x200) || (lstat & 2))
1224 for (j = i = 0; i < 64; i ++) {
1229 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00)
1231 u &= ~0x30000400; /* bits we don't care about */
1232 if ((u & ~0x1f) == 0x00000900)
1237 kprintf("%s*: RIQB:", sc->name);
1238 kprintf(" [%d]=%08x", i, u);
1245 for (j = i = 0; i < 64; i ++) {
1250 if ((u & ~0x1f) == 0x20000800)
1252 u &= ~0x20000000; /* bits we don't care about */
1256 kprintf("%s*: TIQB:", sc->name);
1257 kprintf(" [%d]=%08x", i, u);
1263 sc->m32x->stat = stat;
1267 * PCI initialization stuff
1271 mn_probe (device_t self)
1273 u_int id = pci_get_devid(self);
1275 if (sizeof (struct m32xreg) != 256) {
1276 kprintf("MN: sizeof(struct m32xreg) = %zd, should have been 256\n", sizeof (struct m32xreg));
1279 if (sizeof (struct f54rreg) != 128) {
1280 kprintf("MN: sizeof(struct f54rreg) = %zd, should have been 128\n", sizeof (struct f54rreg));
1283 if (sizeof (struct f54wreg) != 128) {
1284 kprintf("MN: sizeof(struct f54wreg) = %zd, should have been 128\n", sizeof (struct f54wreg));
1288 if (id != 0x2101110a)
1291 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller");
1296 mn_attach (device_t self)
1303 struct resource *res;
1306 if (ng_newtype(&mntypestruct))
1307 kprintf("ng_newtype failed\n");
1311 sc = (struct softc *)kmalloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO);
1312 device_set_softc(self, sc);
1315 sc->unit = device_get_unit(self);
1317 ksprintf(sc->name, "mn%d", sc->unit);
1320 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1322 device_printf(self, "Could not map memory\n");
1325 sc->m0v = rman_get_virtual(res);
1326 sc->m0p = rman_get_start(res);
1328 rid = PCIR_MAPS + 4;
1329 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1331 device_printf(self, "Could not map memory\n");
1334 sc->m1v = rman_get_virtual(res);
1335 sc->m1p = rman_get_start(res);
1337 /* Allocate interrupt */
1339 sc->irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
1340 RF_SHAREABLE | RF_ACTIVE);
1342 if (sc->irq == NULL) {
1343 kprintf("couldn't map interrupt\n");
1347 error = bus_setup_intr(self, sc->irq, INTR_MPSAFE, mn_intr, sc,
1348 &sc->intrhand, NULL);
1351 kprintf("couldn't set up irq\n");
1355 u = pci_read_config(self, PCIR_COMMAND, 1);
1357 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1);
1359 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4);
1361 u = pci_read_config(self, PCIR_COMMAND, 1);
1364 ver = pci_get_revid(self);
1366 sc->m32x = (struct m32xreg *) sc->m0v;
1367 sc->f54w = (struct f54wreg *) sc->m1v;
1368 sc->f54r = (struct f54rreg *) sc->m1v;
1370 /* We must reset before poking at FALC54 registers */
1375 kprintf("mn%d: Munich32X", sc->unit);
1378 kprintf(" Rev 2.2");
1381 kprintf(" Rev 0x%x\n", ver);
1383 kprintf(", Falc54");
1384 switch (sc->f54r->vstr) {
1386 kprintf(" Rev < 1.3\n");
1389 kprintf(" Rev 1.3\n");
1392 kprintf(" Rev 1.4\n");
1395 kprintf("-LH Rev 1.1\n");
1398 kprintf("-LH Rev 1.3\n");
1401 kprintf(" Rev 0x%x\n", sc->f54r->vstr);
1404 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) {
1405 kprintf("ng_make_node_common failed\n");
1408 sc->node->private = sc;
1409 ksprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit);
1410 if (ng_name_node(sc->node, sc->nodename)) {
1411 ng_rmnode(sc->node);
1420 static device_method_t mn_methods[] = {
1421 /* Device interface */
1422 DEVMETHOD(device_probe, mn_probe),
1423 DEVMETHOD(device_attach, mn_attach),
1424 DEVMETHOD(device_suspend, bus_generic_suspend),
1425 DEVMETHOD(device_resume, bus_generic_resume),
1426 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1431 static driver_t mn_driver = {
1437 static devclass_t mn_devclass;
1439 DECLARE_DUMMY_MODULE(if_mn);
1440 DRIVER_MODULE(if_mn, pci, mn_driver, mn_devclass, NULL, NULL);