2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pcireg.h,v 1.24.2.5 2002/08/31 10:06:51 gibbs Exp $
27 * $DragonFly: src/sys/bus/pci/pcireg.h,v 1.5 2004/02/21 06:37:05 dillon Exp $
32 * PCIM_xxx: mask to locate subfield in register
33 * PCIR_xxx: config register offset
34 * PCIC_xxx: device class
35 * PCIS_xxx: device subclass
36 * PCIP_xxx: device programming interface
37 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
41 /* some PCI bus constants */
43 #define PCI_BUSMAX 255
44 #define PCI_SLOTMAX 31
46 #define PCI_REGMAX 255
47 #define PCI_MAXHDRTYPE 2
49 /* PCI config header registers for all devices */
51 #define PCIR_DEVVENDOR 0x00
52 #define PCIR_VENDOR 0x00
53 #define PCIR_DEVICE 0x02
54 #define PCIR_COMMAND 0x04
55 #define PCIM_CMD_PORTEN 0x0001
56 #define PCIM_CMD_MEMEN 0x0002
57 #define PCIM_CMD_BUSMASTEREN 0x0004
58 #define PCIM_CMD_MWRICEN 0x0010
59 #define PCIM_CMD_PERRESPEN 0x0040
60 #define PCIM_CMD_SERRESPEN 0x0100
61 #define PCIR_STATUS 0x06
62 #define PCIM_STATUS_CAPPRESENT 0x0010
63 #define PCIM_STATUS_66CAPABLE 0x0020
64 #define PCIM_STATUS_BACKTOBACK 0x0080
65 #define PCIM_STATUS_PERRREPORT 0x0100
66 #define PCIM_STATUS_SEL_FAST 0x0000
67 #define PCIM_STATUS_SEL_MEDIMUM 0x0200
68 #define PCIM_STATUS_SEL_SLOW 0x0400
69 #define PCIM_STATUS_SEL_MASK 0x0600
70 #define PCIM_STATUS_STABORT 0x0800
71 #define PCIM_STATUS_RTABORT 0x1000
72 #define PCIM_STATUS_RMABORT 0x2000
73 #define PCIM_STATUS_SERR 0x4000
74 #define PCIM_STATUS_PERR 0x8000
75 #define PCIR_REVID 0x08
76 #define PCIR_PROGIF 0x09
77 #define PCIR_SUBCLASS 0x0a
78 #define PCIR_CLASS 0x0b
79 #define PCIR_CACHELNSZ 0x0c
80 #define PCIR_LATTIMER 0x0d
81 #define PCIR_HDRTYPE 0x0e
82 #define PCIM_HDRTYPE 0x7f
83 #define PCIM_HDRTYPE_NORMAL 0x00
84 #define PCIM_HDRTYPE_BRIDGE 0x01
85 #define PCIM_HDRTYPE_CARDBUS 0x02
86 #define PCIM_MFDEV 0x80
87 #define PCIR_BIST 0x0f
89 /* Capability Identification Numbers */
90 #define PCIY_PMG 0x01 /* PCI Power Management */
91 #define PCIY_AGP 0x02 /* AGP */
92 #define PCIY_VPD 0x03 /* Vital Product Data */
93 #define PCIY_SLOTID 0x04 /* Slot Identification */
94 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */
95 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */
96 #define PCIY_PCIX 0x07 /* PCI-X */
97 #define PCIY_HT 0x08 /* HyperTransport */
98 #define PCIY_VENDOR 0x09 /* Vendor Unique */
99 #define PCIY_DEBUG 0x0a /* Debug port */
100 #define PCIY_CRES 0x0b /* CompactPCI central resource control */
101 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */
102 #define PCIY_AGP8X 0x0e /* AGP 8x */
103 #define PCIY_SECDEV 0x0f /* Secure Device */
104 #define PCIY_EXPRESS 0x10 /* PCI Express */
105 #define PCIY_MSIX 0x11 /* MSI-X */
107 /* config registers for header type 0 devices */
109 #define PCIR_BARS 0x10
110 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
111 #define PCIR_MAPS PCIR_BARS /* DEPRECATED XXX */
112 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
113 #define PCIR_CARDBUSCIS 0x28
114 #define PCIR_SUBVEND_0 0x2c
115 #define PCIR_SUBDEV_0 0x2e
116 #define PCIR_BIOS 0x30
117 #define PCIM_BIOS_ENABLE 0x01
118 #define PCIR_CAP_PTR 0x34
119 #define PCIR_INTLINE 0x3c
120 #define PCIR_INTPIN 0x3d
121 #define PCIR_MINGNT 0x3e
122 #define PCIR_MAXLAT 0x3f
124 /* config registers for header type 1 devices */
126 #define PCIR_SECSTAT_1 0x1e
128 #define PCIR_PRIBUS_1 0x18
129 #define PCIR_SECBUS_1 0x19
130 #define PCIR_SUBBUS_1 0x1a
131 #define PCIR_SECLAT_1 0x1b
133 #define PCIR_IOBASEL_1 0x1c
134 #define PCIR_IOLIMITL_1 0x1d
135 #define PCIR_IOBASEH_1 0x30
136 #define PCIR_IOLIMITH_1 0x32
137 #define PCIM_BRIO_16 0x0
138 #define PCIM_BRIO_32 0x1
139 #define PCIM_BRIO_MASK 0xf
141 #define PCIR_MEMBASE_1 0x20
142 #define PCIR_MEMLIMIT_1 0x22
144 #define PCIR_PMBASEL_1 0x24
145 #define PCIR_PMLIMITL_1 0x26
146 #define PCIR_PMBASEH_1 0x28
147 #define PCIR_PMLIMITH_1 0x2c
149 #define PCIR_BRIDGECTL_1 0x3e
151 #define PCIR_SUBVEND_1 0x34
152 #define PCIR_SUBDEV_1 0x36
154 /* config registers for header type 2 devices */
156 #define PCIR_SECSTAT_2 0x16
158 #define PCIR_PRIBUS_2 0x18
159 #define PCIR_SECBUS_2 0x19
160 #define PCIR_SUBBUS_2 0x1a
161 #define PCIR_SECLAT_2 0x1b
163 #define PCIR_MEMBASE0_2 0x1c
164 #define PCIR_MEMLIMIT0_2 0x20
165 #define PCIR_MEMBASE1_2 0x24
166 #define PCIR_MEMLIMIT1_2 0x28
167 #define PCIR_IOBASE0_2 0x2c
168 #define PCIR_IOLIMIT0_2 0x30
169 #define PCIR_IOBASE1_2 0x34
170 #define PCIR_IOLIMIT1_2 0x38
172 #define PCIR_BRIDGECTL_2 0x3e
174 #define PCIR_SUBVEND_2 0x40
175 #define PCIR_SUBDEV_2 0x42
177 #define PCIR_PCCARDIF_2 0x44
179 /* PCI device class, subclass and programming interface definitions */
181 #define PCIC_OLD 0x00
182 #define PCIS_OLD_NONVGA 0x00
183 #define PCIS_OLD_VGA 0x01
185 #define PCIC_STORAGE 0x01
186 #define PCIS_STORAGE_SCSI 0x00
187 #define PCIS_STORAGE_IDE 0x01
188 #define PCIP_STORAGE_IDE_MODEPRIM 0x01
189 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02
190 #define PCIP_STORAGE_IDE_MODESEC 0x04
191 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08
192 #define PCIP_STORAGE_IDE_MASTERDEV 0x80
193 #define PCIS_STORAGE_FLOPPY 0x02
194 #define PCIS_STORAGE_IPI 0x03
195 #define PCIS_STORAGE_RAID 0x04
196 #define PCIS_STORAGE_OTHER 0x80
198 #define PCIC_NETWORK 0x02
199 #define PCIS_NETWORK_ETHERNET 0x00
200 #define PCIS_NETWORK_TOKENRING 0x01
201 #define PCIS_NETWORK_FDDI 0x02
202 #define PCIS_NETWORK_ATM 0x03
203 #define PCIS_NETWORK_OTHER 0x80
205 #define PCIC_DISPLAY 0x03
206 #define PCIS_DISPLAY_VGA 0x00
207 #define PCIS_DISPLAY_XGA 0x01
208 #define PCIS_DISPLAY_OTHER 0x80
210 #define PCIC_MULTIMEDIA 0x04
211 #define PCIS_MULTIMEDIA_VIDEO 0x00
212 #define PCIS_MULTIMEDIA_AUDIO 0x01
213 #define PCIS_MULTIMEDIA_OTHER 0x80
215 #define PCIC_MEMORY 0x05
216 #define PCIS_MEMORY_RAM 0x00
217 #define PCIS_MEMORY_FLASH 0x01
218 #define PCIS_MEMORY_OTHER 0x80
220 #define PCIC_BRIDGE 0x06
221 #define PCIS_BRIDGE_HOST 0x00
222 #define PCIS_BRIDGE_ISA 0x01
223 #define PCIS_BRIDGE_EISA 0x02
224 #define PCIS_BRIDGE_MCA 0x03
225 #define PCIS_BRIDGE_PCI 0x04
226 #define PCIS_BRIDGE_PCMCIA 0x05
227 #define PCIS_BRIDGE_NUBUS 0x06
228 #define PCIS_BRIDGE_CARDBUS 0x07
229 #define PCIS_BRIDGE_OTHER 0x80
231 #define PCIC_SIMPLECOMM 0x07
232 #define PCIS_SIMPLECOMM_UART 0x00
233 #define PCIP_SIMPLECOMM_UART_16550A 0x02
234 #define PCIS_SIMPLECOMM_PAR 0x01
235 #define PCIS_SIMPLECOMM_OTHER 0x80
237 #define PCIC_BASEPERIPH 0x08
238 #define PCIS_BASEPERIPH_PIC 0x00
239 #define PCIS_BASEPERIPH_DMA 0x01
240 #define PCIS_BASEPERIPH_TIMER 0x02
241 #define PCIS_BASEPERIPH_RTC 0x03
242 #define PCIS_BASEPERIPH_OTHER 0x80
244 #define PCIC_INPUTDEV 0x09
245 #define PCIS_INPUTDEV_KEYBOARD 0x00
246 #define PCIS_INPUTDEV_DIGITIZER 0x01
247 #define PCIS_INPUTDEV_MOUSE 0x02
248 #define PCIS_INPUTDEV_OTHER 0x80
250 #define PCIC_DOCKING 0x0a
251 #define PCIS_DOCKING_GENERIC 0x00
252 #define PCIS_DOCKING_OTHER 0x80
254 #define PCIC_PROCESSOR 0x0b
255 #define PCIS_PROCESSOR_386 0x00
256 #define PCIS_PROCESSOR_486 0x01
257 #define PCIS_PROCESSOR_PENTIUM 0x02
258 #define PCIS_PROCESSOR_ALPHA 0x10
259 #define PCIS_PROCESSOR_POWERPC 0x20
260 #define PCIS_PROCESSOR_COPROC 0x40
262 #define PCIC_SERIALBUS 0x0c
263 #define PCIS_SERIALBUS_FW 0x00
264 #define PCIS_SERIALBUS_ACCESS 0x01
265 #define PCIS_SERIALBUS_SSA 0x02
266 #define PCIS_SERIALBUS_USB 0x03
267 #define PCIS_SERIALBUS_FC 0x04
268 #define PCIS_SERIALBUS_SMBUS 0x05
270 #define PCIC_OTHER 0xff
272 /* PCI power manangement */
274 #define PCIR_POWER_CAP 0x2
275 #define PCIM_PCAP_SPEC 0x0007
276 #define PCIM_PCAP_PMEREQCLK 0x0008
277 #define PCIM_PCAP_PMEREQPWR 0x0010
278 #define PCIM_PCAP_DEVSPECINIT 0x0020
279 #define PCIM_PCAP_DYNCLOCK 0x0040
280 #define PCIM_PCAP_SECCLOCK 0x00c0
281 #define PCIM_PCAP_CLOCKMASK 0x00c0
282 #define PCIM_PCAP_REQFULLCLOCK 0x0100
283 #define PCIM_PCAP_D1SUPP 0x0200
284 #define PCIM_PCAP_D2SUPP 0x0400
285 #define PCIM_PCAP_D0PME 0x1000
286 #define PCIM_PCAP_D1PME 0x2000
287 #define PCIM_PCAP_D2PME 0x4000
289 #define PCIR_POWER_STATUS 0x4
290 #define PCIM_PSTAT_D0 0x0000
291 #define PCIM_PSTAT_D1 0x0001
292 #define PCIM_PSTAT_D2 0x0002
293 #define PCIM_PSTAT_D3 0x0003
294 #define PCIM_PSTAT_DMASK 0x0003
295 #define PCIM_PSTAT_REPENABLE 0x0010
296 #define PCIM_PSTAT_PMEENABLE 0x0100
297 #define PCIM_PSTAT_D0POWER 0x0000
298 #define PCIM_PSTAT_D1POWER 0x0200
299 #define PCIM_PSTAT_D2POWER 0x0400
300 #define PCIM_PSTAT_D3POWER 0x0600
301 #define PCIM_PSTAT_D0HEAT 0x0800
302 #define PCIM_PSTAT_D1HEAT 0x1000
303 #define PCIM_PSTAT_D2HEAT 0x1200
304 #define PCIM_PSTAT_D3HEAT 0x1400
305 #define PCIM_PSTAT_DATAUNKN 0x0000
306 #define PCIM_PSTAT_DATADIV10 0x2000
307 #define PCIM_PSTAT_DATADIV100 0x4000
308 #define PCIM_PSTAT_DATADIV1000 0x6000
309 #define PCIM_PSTAT_DATADIVMASK 0x6000
310 #define PCIM_PSTAT_PME 0x8000
312 #define PCIR_POWER_PMCSR 0x6
313 #define PCIM_PMCSR_DCLOCK 0x10
314 #define PCIM_PMCSR_B2SUPP 0x20
315 #define PCIM_BMCSR_B3SUPP 0x40
316 #define PCIM_BMCSR_BPCE 0x80
318 #define PCIR_POWER_DATA 0x7
320 /* PCI Message Signalled Interrupts (MSI) */
321 #define PCIR_MSI_CTRL 0x2
322 #define PCIM_MSICTRL_VECTOR 0x0100
323 #define PCIM_MSICTRL_64BIT 0x0080
324 #define PCIM_MSICTRL_MME_MASK 0x0070
325 #define PCIM_MSICTRL_MME_1 0x0000
326 #define PCIM_MSICTRL_MME_2 0x0010
327 #define PCIM_MSICTRL_MME_4 0x0020
328 #define PCIM_MSICTRL_MME_8 0x0030
329 #define PCIM_MSICTRL_MME_16 0x0040
330 #define PCIM_MSICTRL_MME_32 0x0050
331 #define PCIM_MSICTRL_MMC_MASK 0x000E
332 #define PCIM_MSICTRL_MMC_1 0x0000
333 #define PCIM_MSICTRL_MMC_2 0x0002
334 #define PCIM_MSICTRL_MMC_4 0x0004
335 #define PCIM_MSICTRL_MMC_8 0x0006
336 #define PCIM_MSICTRL_MMC_16 0x0008
337 #define PCIM_MSICTRL_MMC_32 0x000A
338 #define PCIM_MSICTRL_MSI_ENABLE 0x0001
339 #define PCIR_MSI_ADDR 0x4
340 #define PCIR_MSI_ADDR_HIGH 0x8
341 #define PCIR_MSI_DATA 0x8
342 #define PCIR_MSI_DATA_64BIT 0xc
343 #define PCIR_MSI_MASK 0x10
344 #define PCIR_MSI_PENDING 0x14
346 /* PCI-X definitions */
347 #define PCIXR_COMMAND 0x96
348 #define PCIXR_DEVADDR 0x98
349 #define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */
350 #define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */
351 #define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */
352 #define PCIXR_STATUS 0x9A
353 #define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */
354 #define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */
355 #define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */
356 #define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */
357 #define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */
358 #define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */
359 #define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */
360 #define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */
361 #define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */
363 /* some PCI vendor definitions (only used to identify ancient devices !!! */
365 #define PCIV_INTEL 0x8086
367 #define PCID_INTEL_SATURN 0x0483
368 #define PCID_INTEL_ORION 0x84c4
370 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */
372 #if defined(_KERNEL) && !defined(KLD_MODULE)
373 #include "opt_compat_oldpci.h"
378 #define PCI_ID_REG 0x00
379 #define PCI_COMMAND_STATUS_REG 0x04
380 #define PCI_COMMAND_IO_ENABLE 0x00000001
381 #define PCI_COMMAND_MEM_ENABLE 0x00000002
382 #define PCI_CLASS_REG 0x08
383 #define PCI_CLASS_MASK 0xff000000
384 #define PCI_SUBCLASS_MASK 0x00ff0000
385 #define PCI_REVISION_MASK 0x000000ff
386 #define PCI_CLASS_PREHISTORIC 0x00000000
387 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000
388 #define PCI_CLASS_MASS_STORAGE 0x01000000
389 #define PCI_CLASS_DISPLAY 0x03000000
390 #define PCI_SUBCLASS_DISPLAY_VGA 0x00000000
391 #define PCI_CLASS_BRIDGE 0x06000000
392 #define PCI_MAP_REG_START 0x10
393 #define PCI_MAP_REG_END 0x28
394 #define PCI_MAP_IO 0x00000001
395 #define PCI_INTERRUPT_REG 0x3c
397 #endif /* COMPAT_OLDPCI */