2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-dma.c,v 1.35.2.31 2003/05/07 16:46:11 jhb Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-dma.c,v 1.27 2005/05/27 21:12:51 swildner Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/mpipe.h>
40 #include <sys/devicestat.h>
43 #include <bus/pci/pcivar.h>
44 #include <machine/bus.h>
49 static void cyrix_timing(struct ata_device *, int, int);
50 static void promise_timing(struct ata_device *, int, int);
51 static void hpt_timing(struct ata_device *, int, int);
52 static int hpt_cable80(struct ata_device *);
55 #define ATAPI_DEVICE(atadev) \
56 ((atadev->unit == ATA_MASTER && \
57 atadev->channel->devices & ATA_ATAPI_MASTER) || \
58 (atadev->unit == ATA_SLAVE && \
59 atadev->channel->devices & ATA_ATAPI_SLAVE))
61 int ata_dma_debug = 0;
64 ata_dmaalloc(struct ata_device *atadev, int flags)
66 struct ata_channel *ch = atadev->channel;
68 if (atadev->dmastate.dmatab != NULL)
71 KKASSERT(ch->dma_mpipe.max_count != 0);
72 if (flags & M_RNOWAIT)
73 atadev->dmastate.dmatab = mpipe_alloc_nowait(&ch->dma_mpipe);
75 atadev->dmastate.dmatab = mpipe_alloc_waitok(&ch->dma_mpipe);
77 if (atadev->dmastate.dmatab != NULL) {
78 KKASSERT(((uintptr_t)atadev->dmastate.dmatab & PAGE_MASK) == 0);
85 ata_dmafree(struct ata_device *atadev)
87 struct ata_channel *ch = atadev->channel;
89 if (atadev->dmastate.dmatab) {
90 mpipe_free(&ch->dma_mpipe, atadev->dmastate.dmatab);
91 atadev->dmastate.dmatab = NULL;
96 ata_dmafreetags(struct ata_channel *ch)
101 ata_dmacreate(struct ata_device *atadev, int apiomode, int mode)
107 ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode)
109 device_t parent = device_get_parent(atadev->channel->dev);
110 int chiptype = atadev->channel->chiptype;
111 int chiprev = pci_get_revid(parent);
112 int channel = atadev->channel->unit;
113 int device = ATA_DEV(atadev->unit);
114 int devno = (channel << 1) + device;
117 /* set our most pessimistic default mode */
118 atadev->mode = ATA_PIO;
120 if (!atadev->channel->r_bmio)
123 /* if simplex controller, only allow DMA on primary channel */
125 ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT,
126 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
127 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
128 if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
129 ATA_BMSTAT_DMA_SIMPLEX) {
130 ata_prtdev(atadev, "simplex device, DMA on primary only\n");
135 /* DMA engine address alignment is usually 1 word (2 bytes) */
136 atadev->channel->alignment = 0x1;
139 if (udmamode > 2 && !atadev->param->hwres_cblid) {
140 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
146 case 0x266f8086: /* Intel ICH6 ATA */
147 case 0x26528086: /* Intel ICH6R/RW SATA */
148 case 0x26518086: /* Intel ICH6/W SATA */
149 case 0x24db8086: /* Intel ICH5 */
150 case 0x24d18086: /* Intel ICH5 SATA */
151 case 0x24ca8086: /* Intel ICH4 mobile */
152 case 0x24cb8086: /* Intel ICH4 */
153 case 0x248a8086: /* Intel ICH3 mobile */
154 case 0x248b8086: /* Intel ICH3 */
155 case 0x244a8086: /* Intel ICH2 mobile */
156 case 0x244b8086: /* Intel ICH2 */
158 int32_t mask48, new48;
161 word54 = pci_read_config(parent, 0x54, 2);
162 if (word54 & (0x10 << devno)) {
163 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
164 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
166 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
167 (error) ? "failed" : "success");
169 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
170 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
171 pci_write_config(parent, 0x48,
172 (pci_read_config(parent, 0x48, 4) &
173 ~mask48) | new48, 4);
174 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
175 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
180 /* make sure eventual ATA100 mode from the BIOS is disabled */
181 pci_write_config(parent, 0x54,
182 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
185 case 0x24118086: /* Intel ICH */
186 case 0x76018086: /* Intel ICH */
188 int32_t mask48, new48;
191 word54 = pci_read_config(parent, 0x54, 2);
192 if (word54 & (0x10 << devno)) {
193 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
194 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
196 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
197 (error) ? "failed" : "success");
199 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
200 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
201 pci_write_config(parent, 0x48,
202 (pci_read_config(parent, 0x48, 4) &
203 ~mask48) | new48, 4);
204 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
205 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
210 /* make sure eventual ATA66 mode from the BIOS is disabled */
211 pci_write_config(parent, 0x54,
212 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
215 case 0x71118086: /* Intel PIIX4 */
216 case 0x84CA8086: /* Intel PIIX4 */
217 case 0x71998086: /* Intel PIIX4e */
218 case 0x24218086: /* Intel ICH0 */
220 int32_t mask48, new48;
222 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
223 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
225 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
226 (error) ? "failed" : "success");
228 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
229 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
230 pci_write_config(parent, 0x48,
231 (pci_read_config(parent, 0x48, 4) &
232 ~mask48) | new48, 4);
233 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
237 /* make sure eventual ATA33 mode from the BIOS is disabled */
238 pci_write_config(parent, 0x48,
239 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
242 case 0x70108086: /* Intel PIIX3 */
243 if (wdmamode >= 2 && apiomode >= 4) {
244 int32_t mask40, new40, mask44, new44;
246 /* if SITRE not set doit for both channels */
247 if (!((pci_read_config(parent,0x40,4)>>(channel<<8))&0x4000)) {
248 new40 = pci_read_config(parent, 0x40, 4);
249 new44 = pci_read_config(parent, 0x44, 4);
250 if (!(new40 & 0x00004000)) {
251 new44 &= ~0x0000000f;
252 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
254 if (!(new40 & 0x40000000)) {
255 new44 &= ~0x000000f0;
256 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
259 pci_write_config(parent, 0x40, new40, 4);
260 pci_write_config(parent, 0x44, new44, 4);
262 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
263 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
265 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
266 (error) ? "failed" : "success");
268 if (device == ATA_MASTER) {
286 pci_write_config(parent, 0x40,
287 (pci_read_config(parent, 0x40, 4) & ~mask40)|
289 pci_write_config(parent, 0x44,
290 (pci_read_config(parent, 0x44, 4) & ~mask44)|
292 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
296 /* we could set PIO mode timings, but we assume the BIOS did that */
299 case 0x12308086: /* Intel PIIX */
300 if (wdmamode >= 2 && apiomode >= 4) {
303 word40 = pci_read_config(parent, 0x40, 4);
304 word40 >>= channel * 16;
306 /* Check for timing config usable for DMA on controller */
307 if (!((word40 & 0x3300) == 0x2300 &&
308 ((word40 >> (device ? 4 : 0)) & 1) == 1))
311 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
312 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
314 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
315 (error) ? "failed" : "success");
317 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
323 case 0x522910b9: /* AcerLabs Aladdin IV/V */
324 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
325 if (chiprev < 0xc2 &&
326 atadev->channel->devices & ATA_ATAPI_MASTER &&
327 atadev->channel->devices & ATA_ATAPI_SLAVE) {
328 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
331 #if !defined(NO_ATANG)
332 pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4);
334 if (udmamode >= 5 && chiprev >= 0xc4) {
335 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
336 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
338 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
339 (error) ? "failed" : "success");
341 int32_t word54 = pci_read_config(parent, 0x54, 4);
343 pci_write_config(parent, 0x4b,
344 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
345 word54 &= ~(0x000f000f << (devno << 2));
346 word54 |= (0x000f0005 << (devno << 2));
347 pci_write_config(parent, 0x54, word54, 4);
348 pci_write_config(parent, 0x53,
349 pci_read_config(parent, 0x53, 1) | 0x03, 1);
350 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
354 if (udmamode >= 4 && chiprev >= 0xc2) {
355 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
356 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
358 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
359 (error) ? "failed" : "success");
361 int32_t word54 = pci_read_config(parent, 0x54, 4);
363 pci_write_config(parent, 0x4b,
364 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
365 word54 &= ~(0x000f000f << (devno << 2));
366 word54 |= (0x00080005 << (devno << 2));
367 pci_write_config(parent, 0x54, word54, 4);
368 pci_write_config(parent, 0x53,
369 pci_read_config(parent, 0x53, 1) | 0x03, 1);
370 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
374 if (udmamode >= 2 && chiprev >= 0x20) {
375 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
376 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
378 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
379 (error) ? "failed" : "success");
381 int32_t word54 = pci_read_config(parent, 0x54, 4);
383 word54 &= ~(0x000f000f << (devno << 2));
384 word54 |= (0x000a0005 << (devno << 2));
385 pci_write_config(parent, 0x54, word54, 4);
386 pci_write_config(parent, 0x53,
387 pci_read_config(parent, 0x53, 1) | 0x03, 1);
388 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
389 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
394 /* make sure eventual UDMA mode from the BIOS is disabled */
395 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
396 ~(0x0008 << (devno << 2)), 2);
398 if (wdmamode >= 2 && apiomode >= 4) {
399 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
400 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
402 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
403 (error) ? "failed" : "success");
405 pci_write_config(parent, 0x53,
406 pci_read_config(parent, 0x53, 1) | 0x03, 1);
407 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
408 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
412 pci_write_config(parent, 0x53,
413 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
414 #if !defined(NO_ATANG)
415 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
417 ATA_C_F_SETXFER, ATA_WAIT_READY);
419 ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n",
420 (error) ? "failed" : "success",
421 (apiomode >= 0) ? apiomode : 0);
423 int32_t word54 = pci_read_config(parent, 0x54, 4);
426 switch(ATA_PIO0 + apiomode) {
427 case ATA_PIO0: timing = 0x006d0003; break;
428 case ATA_PIO1: timing = 0x00580002; break;
429 case ATA_PIO2: timing = 0x00440001; break;
430 case ATA_PIO3: timing = 0x00330001; break;
431 case ATA_PIO4: timing = 0x00310001; break;
432 default: timing = 0x006d0003; break;
434 pci_write_config(parent, 0x58 + (channel << 2), timing, 4);
435 word54 &= ~(0x000f000f << (devno << 2));
436 word54 |= (0x00000004 << (devno << 2));
437 pci_write_config(parent, 0x54, word54, 4);
438 atadev->mode = ATA_PIO0 + apiomode;
444 case 0x31491106: /* VIA 8237 SATA part */
446 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
448 ATA_C_F_SETXFER, ATA_WAIT_READY);
450 ata_prtdev(atadev, "%s setting UDMA%d on VIA chip\n",
451 (error) ? "failed" : "success", udmamode);
453 ata_dmacreate(atadev, apiomode, ATA_UDMA + udmamode);
457 /* we could set PIO mode timings, but we assume the BIOS did that */
460 case 0x01bc10de: /* NVIDIA nForce1 */
461 case 0x006510de: /* NVIDIA nForce2 */
462 case 0x00d510de: /* NVIDIA nForce3 */
463 case 0x00e310de: /* NVIDIA nForce3 PRO S1 */
464 case 0x00e510de: /* NVIDIA nForce3 PRO */
465 case 0x74691022: /* AMD 8111 */
466 case 0x74411022: /* AMD 768 */
467 case 0x74111022: /* AMD 766 */
468 case 0x74091022: /* AMD 756 */
469 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */
471 int via_modes[][7] = {
472 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
473 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
474 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
475 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
476 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/NVIDIA */
481 if (ata_find_dev(parent, 0x31471106, 0) || /* 8233a */
482 ata_find_dev(parent, 0x31771106, 0) || /* 8235 */
483 ata_find_dev(parent, 0x31491106, 0)) { /* 8237 */
484 udmamode = imin(udmamode, 6);
485 reg_val = via_modes[3];
487 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */
488 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */
489 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */
490 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */
491 udmamode = imin(udmamode, 5);
492 reg_val = via_modes[2];
494 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */
495 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
496 udmamode = imin(udmamode, 4);
497 reg_val = via_modes[1];
499 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */
500 udmamode = imin(udmamode, 2);
501 reg_val = via_modes[1];
503 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
504 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
505 udmamode = imin(udmamode, 2);
506 reg_val = via_modes[0];
508 else if (chiptype == 0x74691022 || /* AMD 8111 */
509 chiptype == 0x74411022 || /* AMD 768 */
510 chiptype == 0x74111022) { /* AMD 766 */
511 udmamode = imin(udmamode, 5);
512 reg_val = via_modes[4];
515 else if (chiptype == 0x74091022) { /* AMD 756 */
516 udmamode = imin(udmamode, 4);
517 reg_val = via_modes[4];
520 else if (chiptype == 0x01bc10de) { /* nForce1 */
521 udmamode = imin(udmamode, 5);
522 reg_val = via_modes[4];
523 #if !defined(NO_ATANG)
528 else if (chiptype == 0x006510de || /* nForce2 */
529 chiptype == 0x00d510de || /* nForce3 */
530 chiptype == 0x00e310de || /* nForce3 PRO S1 */
531 chiptype == 0x00e510de) { /* nForce3 PRO */
532 udmamode = imin(udmamode, 6);
533 reg_val = via_modes[4];
534 #if !defined(NO_ATANG)
545 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
546 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
548 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n",
549 (error) ? "failed" : "success", chip);
551 pci_write_config(parent, reg_off, reg_val[6], 1);
552 pci_write_config(parent, reg_off - 8, 0x20, 1);
553 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
558 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
559 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
561 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n",
562 (error) ? "failed" : "success", chip);
564 pci_write_config(parent, reg_off, reg_val[5], 1);
565 pci_write_config(parent, reg_off - 8, 0x20, 1);
566 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
571 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
572 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
574 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n",
575 (error) ? "failed" : "success", chip);
577 pci_write_config(parent, reg_off, reg_val[4], 1);
578 pci_write_config(parent, reg_off - 8, 0x20, 1);
579 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
584 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
585 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
587 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n",
588 (error) ? "failed" : "success", chip);
590 pci_write_config(parent, reg_off, reg_val[2], 1);
591 pci_write_config(parent, reg_off - 8, 0x20, 1);
592 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
596 if (wdmamode >= 2 && apiomode >= 4) {
597 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
598 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
600 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
601 (error) ? "failed" : "success", chip);
603 pci_write_config(parent, reg_off, 0x0b, 1);
604 pci_write_config(parent, reg_off - 8, 0x20, 1);
605 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
609 pci_write_config(parent, reg_off, 0x8b, 1);
612 pci_write_config(parent, reg_off - 8, 0xa8, 1);
615 pci_write_config(parent, reg_off - 8, 0x65, 1);
618 pci_write_config(parent, reg_off - 8, 0x42, 1);
621 pci_write_config(parent, reg_off - 8, 0x22, 1);
624 pci_write_config(parent, reg_off - 8, 0x20, 1);
630 case 0x55131039: /* SiS 5591 */
631 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
632 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */
633 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */
634 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */
635 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */
636 ata_find_dev(parent, 0x06461039, 0) || /* SiS 645DX */
637 ata_find_dev(parent, 0x06481039, 0) || /* SiS 648 */
638 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */
639 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */
640 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */
641 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */
642 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */
643 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */
644 ata_find_dev(parent, 0x07461039, 0) || /* SiS 746 */
645 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */
646 int8_t reg = 0x40 + (devno << 1);
647 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
650 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
651 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
653 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
654 (error) ? "failed" : "success");
656 pci_write_config(parent, reg, val | 0x8000, 2);
657 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
662 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
663 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
665 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
666 (error) ? "failed" : "success");
668 pci_write_config(parent, reg, val | 0x9000, 2);
669 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
674 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
675 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
677 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
678 (error) ? "failed" : "success");
680 pci_write_config(parent, reg, val | 0xb000, 2);
681 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
685 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
686 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
687 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
688 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
689 int8_t reg = 0x40 + (devno << 1);
690 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
693 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
694 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
696 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
697 (error) ? "failed" : "success");
699 pci_write_config(parent, reg, val | 0x9000, 2);
700 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
705 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
706 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
708 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
709 (error) ? "failed" : "success");
711 pci_write_config(parent, reg, val | 0xa000, 2);
712 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
716 } else if (udmamode >= 2 && chiprev > 0xc1) {
717 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
718 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
720 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
721 (error) ? "failed" : "success");
723 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
724 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
728 if (wdmamode >=2 && apiomode >= 4) {
729 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
730 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
732 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
733 (error) ? "failed" : "success");
735 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
736 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
740 /* we could set PIO mode timings, but we assume the BIOS did that */
743 case 0x35121095: /* SiI 3512 SATA controller */
744 /* EXPERIMENTAL! Works with FN85 AMD 64 3200+ motherboard */
746 case 0x31241095: /* SiI 3124 SATA controller */
747 case 0x31141095: /* SiI 3114 SATA controller */
748 case 0x31121095: /* SiI 3112 SATA controller */
749 case 0x06801095: /* SiI 0680 ATA133 controller */
751 u_int8_t ureg = 0xac + (device * 0x02) + (channel * 0x10);
752 u_int8_t uval = pci_read_config(parent, ureg, 1);
753 u_int8_t mreg = channel ? 0x84 : 0x80;
754 u_int8_t mask = device ? 0x30 : 0x03;
755 u_int8_t mode = pci_read_config(parent, mreg, 1);
757 /* enable UDMA mode */
758 pci_write_config(parent, mreg,
759 (mode & ~mask) | (device ? 0x30 : 0x03), 1);
761 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
762 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
764 ata_prtdev(atadev, "%s setting UDMA6 on SiI chip\n",
765 (error) ? "failed" : "success");
767 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x01, 1);
768 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
773 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
774 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
776 ata_prtdev(atadev, "%s setting UDMA5 on SiI chip\n",
777 (error) ? "failed" : "success");
779 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x02, 1);
780 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
785 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
786 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
788 ata_prtdev(atadev, "%s setting UDMA4 on SiI chip\n",
789 (error) ? "failed" : "success");
791 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x03, 1);
792 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
797 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
798 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
800 ata_prtdev(atadev, "%s setting UDMA2 on SiI chip\n",
801 (error) ? "failed" : "success");
803 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x07, 1);
804 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
809 /* disable UDMA mode and enable WDMA mode */
810 pci_write_config(parent, mreg,
811 (mode & ~mask) | (device ? 0x20 : 0x02), 1);
812 if (wdmamode >= 2 && apiomode >= 4) {
813 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
814 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
816 ata_prtdev(atadev, "%s setting WDMA2 on SiI chip\n",
817 (error) ? "failed" : "success");
819 pci_write_config(parent, ureg - 0x4, 0x10c1, 2);
820 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
825 /* restore PIO mode */
826 pci_write_config(parent, mreg, mode, 1);
828 /* we could set PIO mode timings, but we assume the BIOS did that */
831 case 0x06491095: /* CMD 649 ATA100 controller */
835 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
836 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
838 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
839 (error) ? "failed" : "success");
841 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
842 umode &= ~(device ? 0xca : 0x35);
843 umode |= (device ? 0x0a : 0x05);
844 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
845 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
851 case 0x06481095: /* CMD 648 ATA66 controller */
855 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
856 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
858 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
859 (error) ? "failed" : "success");
861 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
862 umode &= ~(device ? 0xca : 0x35);
863 umode |= (device ? 0x4a : 0x15);
864 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
865 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
872 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
873 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
875 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
876 (error) ? "failed" : "success");
878 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
879 umode &= ~(device ? 0xca : 0x35);
880 umode |= (device ? 0x42 : 0x11);
881 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
882 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
886 /* make sure eventual UDMA mode from the BIOS is disabled */
887 pci_write_config(parent, channel ? 0x7b : 0x73,
888 pci_read_config(parent, channel ? 0x7b : 0x73, 1)&
889 #if !defined(NO_ATANG)
890 ~(device ? 0xca : 0x53), 1);
892 ~(device ? 0xca : 0x35), 1);
896 case 0x06461095: /* CMD 646 ATA controller */
897 if (wdmamode >= 2 && apiomode >= 4) {
898 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
899 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
901 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
902 error ? "failed" : "success");
904 int32_t offset = (devno < 3) ? (devno << 1) : 7;
906 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
907 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
911 /* we could set PIO mode timings, but we assume the BIOS did that */
914 case 0xc6931080: /* Cypress 82c693 ATA controller */
915 if (wdmamode >= 2 && apiomode >= 4) {
916 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
917 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
919 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
920 error ? "failed" : "success");
922 pci_write_config(atadev->channel->dev,
923 channel ? 0x4e:0x4c, 0x2020, 2);
924 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
928 /* we could set PIO mode timings, but we assume the BIOS did that */
931 case 0x01021078: /* Cyrix 5530 ATA33 controller */
932 atadev->channel->alignment = 0xf; /* DMA engine requires 16 byte alignment */
934 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
935 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
937 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
938 (error) ? "failed" : "success");
940 cyrix_timing(atadev, devno, ATA_UDMA2);
941 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
945 if (wdmamode >= 2 && apiomode >= 4) {
946 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
947 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
949 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
950 (error) ? "failed" : "success");
952 cyrix_timing(atadev, devno, ATA_WDMA2);
953 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
957 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
958 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
961 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
962 (error) ? "failed" : "success",
963 ata_mode2str(ATA_PIO0 + apiomode));
964 cyrix_timing(atadev, devno, ATA_PIO0 + apiomode);
965 atadev->mode = ATA_PIO0 + apiomode;
968 #if !defined(NO_ATANG)
969 case 0x02131166: /* ServerWorks CSB6 ATA 100 controller (chan 0+1) */
971 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */
972 #if !defined(NO_ATANG)
973 if (udmamode >= 5 && (chiptype == 0x02131166 ||
974 (chiptype == 0x02121166 &&
977 if (udmamode >= 5 && chiprev >= 0x92) {
979 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
980 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
982 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
983 (error) ? "failed" : "success");
987 pci_write_config(parent, 0x54,
988 pci_read_config(parent, 0x54, 1) |
990 reg56 = pci_read_config(parent, 0x56, 2);
991 reg56 &= ~(0xf << (devno * 4));
992 reg56 |= (0x5 << (devno * 4));
993 pci_write_config(parent, 0x56, reg56, 2);
994 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
998 #if !defined(NO_ATANG)
1000 case 0x02171166: /* Server Works CSB6 ATA 66 controller chan 2 */
1002 if (udmamode >= 4) {
1003 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1004 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1006 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
1007 (error) ? "failed" : "success");
1011 pci_write_config(parent, 0x54,
1012 pci_read_config(parent, 0x54, 1) |
1013 (0x01 << devno), 1);
1014 reg56 = pci_read_config(parent, 0x56, 2);
1015 reg56 &= ~(0xf << (devno * 4));
1016 reg56 |= (0x4 << (devno * 4));
1017 pci_write_config(parent, 0x56, reg56, 2);
1018 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1024 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
1025 if (udmamode >= 2) {
1026 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1027 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1029 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
1030 (error) ? "failed" : "success");
1034 pci_write_config(parent, 0x54,
1035 pci_read_config(parent, 0x54, 1) |
1036 (0x01 << devno), 1);
1037 reg56 = pci_read_config(parent, 0x56, 2);
1038 reg56 &= ~(0xf << (devno * 4));
1039 reg56 |= (0x2 << (devno * 4));
1040 pci_write_config(parent, 0x56, reg56, 2);
1041 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1045 if (wdmamode >= 2 && apiomode >= 4) {
1046 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1047 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1049 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
1050 (error) ? "failed" : "success");
1052 int offset = devno ^ 0x01; /* (chan*2) + (dev==ATA_MASTER)*/
1053 int word44 = pci_read_config(parent, 0x44, 4);
1055 pci_write_config(parent, 0x54,
1056 pci_read_config(parent, 0x54, 1) &
1057 ~(0x01 << devno), 1);
1058 word44 &= ~(0xff << (offset << 8));
1059 word44 |= (0x20 << (offset << 8));
1060 pci_write_config(parent, 0x44, 0x20, 4);
1061 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1065 /* we could set PIO mode timings, but we assume the BIOS did that */
1068 case 0x4d69105a: /* Promise TX2 ATA133 controllers */
1069 case 0x5275105a: /* Promise TX2 ATA133 controllers */
1070 case 0x6269105a: /* Promise TX2 ATA133 controllers */
1071 case 0x7275105a: /* Promise TX2 ATA133 controllers */
1072 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1073 if (udmamode >= 6 &&
1074 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1075 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1076 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1078 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
1079 (error) ? "failed" : "success");
1081 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1087 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
1088 case 0x6268105a: /* Promise TX2 ATA100 controllers */
1089 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1090 if (udmamode >= 5 &&
1091 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1092 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1093 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1095 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1096 (error) ? "failed" : "success");
1098 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1102 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1103 if (udmamode >= 4 &&
1104 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1105 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1106 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1108 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1109 (error) ? "failed" : "success");
1111 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1115 if (udmamode >= 2) {
1116 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1117 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1119 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
1120 (error) ? "failed" : "success");
1122 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1126 if (wdmamode >= 2 && apiomode >= 4) {
1127 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1128 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1130 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1131 (error) ? "failed" : "success");
1133 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1139 case 0x0d30105a: /* Promise OEM ATA100 controllers */
1140 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
1141 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 &&
1142 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1143 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1144 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1146 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1147 (error) ? "failed" : "success");
1149 promise_timing(atadev, devno, ATA_UDMA5);
1150 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1156 case 0x0d38105a: /* Promise FastTrak 66 controllers */
1157 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
1158 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 &&
1159 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1160 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1161 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1163 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1164 (error) ? "failed" : "success");
1166 promise_timing(atadev, devno, ATA_UDMA4);
1167 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1173 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
1174 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1175 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1176 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1178 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
1179 (error) ? "failed" : "success");
1181 promise_timing(atadev, devno, ATA_UDMA2);
1182 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1186 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1187 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1188 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1190 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1191 (error) ? "failed" : "success");
1193 promise_timing(atadev, devno, ATA_WDMA2);
1194 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1198 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1199 ATA_PIO0 + apiomode,
1200 ATA_C_F_SETXFER, ATA_WAIT_READY);
1202 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
1203 (error) ? "failed" : "success",
1204 (apiomode >= 0) ? apiomode : 0);
1205 promise_timing(atadev, devno, ATA_PIO0 + apiomode);
1206 atadev->mode = ATA_PIO0 + apiomode;
1209 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
1210 case 0x00051103: /* HighPoint HPT372 controllers */
1211 case 0x00081103: /* HighPoint HPT374 controllers */
1212 if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) &&
1213 ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1214 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1215 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1216 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1217 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1219 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
1220 (error) ? "failed" : "success");
1222 hpt_timing(atadev, devno, ATA_UDMA6);
1223 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1227 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) &&
1228 ((chiptype == 0x00041103 && chiprev >= 0x03) ||
1229 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1230 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1231 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1232 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1234 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
1235 (error) ? "failed" : "success");
1237 hpt_timing(atadev, devno, ATA_UDMA5);
1238 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1242 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) {
1243 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1244 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1246 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
1247 (error) ? "failed" : "success");
1249 hpt_timing(atadev, devno, ATA_UDMA4);
1250 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1254 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1255 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1256 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1258 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
1259 (error) ? "failed" : "success");
1261 hpt_timing(atadev, devno, ATA_UDMA2);
1262 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1266 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1267 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1268 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1270 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
1271 (error) ? "failed" : "success");
1273 hpt_timing(atadev, devno, ATA_WDMA2);
1274 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1278 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1279 ATA_PIO0 + apiomode,
1280 ATA_C_F_SETXFER, ATA_WAIT_READY);
1282 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
1283 (error) ? "failed" : "success",
1284 (apiomode >= 0) ? apiomode : 0);
1285 hpt_timing(atadev, devno, ATA_PIO0 + apiomode);
1286 atadev->mode = ATA_PIO0 + apiomode;
1289 case 0x000116ca: /* Cenatek Rocket Drive controller */
1290 if (wdmamode >= 0 &&
1291 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1292 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER)))
1293 ata_dmacreate(atadev, apiomode, ATA_DMA);
1295 atadev->mode = ATA_PIO;
1298 default: /* unknown controller chip */
1299 /* better not try generic DMA on ATAPI devices it almost never works */
1300 if (ATAPI_DEVICE(atadev))
1303 /* if controller says its setup for DMA take the easy way out */
1304 /* the downside is we dont know what DMA mode we are in */
1305 if ((udmamode >= 0 || wdmamode >= 2) &&
1306 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1307 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) {
1308 ata_dmacreate(atadev, apiomode, ATA_DMA);
1312 /* well, we have no support for this, but try anyways */
1313 if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) {
1314 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1315 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1317 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
1318 (error) ? "failed" : "success");
1320 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1325 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1326 ATA_C_F_SETXFER, ATA_WAIT_READY);
1328 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
1329 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1331 atadev->mode = ATA_PIO0 + apiomode;
1334 ata_prtdev(atadev, "using PIO mode set by BIOS\n");
1335 atadev->mode = ATA_PIO;
1340 ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count)
1342 struct ata_channel *ch = atadev->channel;
1343 struct ata_dmastate *ds = &atadev->dmastate;
1344 u_int32_t dma_count, dma_base;
1347 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
1348 ata_prtdev(atadev, "non aligned DMA transfer attempted\n");
1353 ata_prtdev(atadev, "zero length DMA transfer attempted\n");
1357 dma_base = vtophys(data);
1358 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1363 ds->dmatab[i].base = dma_base;
1364 ds->dmatab[i].count = (dma_count & 0xffff);
1366 if (i >= ATA_DMA_ENTRIES) {
1367 ata_prtdev(atadev, "too many segments in DMA table\n");
1370 dma_base = vtophys(data);
1371 dma_count = imin(count, PAGE_SIZE);
1372 data += imin(count, PAGE_SIZE);
1373 count -= imin(count, PAGE_SIZE);
1375 ds->dmatab[i].base = dma_base;
1376 ds->dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1381 ata_dmastart(struct ata_device *atadev, caddr_t data, int32_t count, int dir)
1383 struct ata_channel *ch = atadev->channel;
1384 struct ata_dmastate *ds = &atadev->dmastate;
1386 ch->flags |= ATA_DMA_ACTIVE;
1387 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(ds->dmatab));
1388 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1389 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1390 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1391 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1392 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1393 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1398 ata_dmadone(struct ata_device *atadev)
1400 struct ata_channel *ch;
1401 struct ata_dmastate *ds;
1404 ch = atadev->channel;
1405 ds = &atadev->dmastate;
1407 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1408 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1409 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1410 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1411 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1412 ch->flags &= ~ATA_DMA_ACTIVE;
1414 return error & ATA_BMSTAT_MASK;
1418 ata_dmastatus(struct ata_channel *ch)
1420 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1424 cyrix_timing(struct ata_device *atadev, int devno, int mode)
1426 u_int32_t reg20 = 0x0000e132;
1427 u_int32_t reg24 = 0x00017771;
1430 case ATA_PIO0: reg20 = 0x0000e132; break;
1431 case ATA_PIO1: reg20 = 0x00018121; break;
1432 case ATA_PIO2: reg20 = 0x00024020; break;
1433 case ATA_PIO3: reg20 = 0x00032010; break;
1434 case ATA_PIO4: reg20 = 0x00040010; break;
1435 case ATA_WDMA2: reg24 = 0x00002020; break;
1436 case ATA_UDMA2: reg24 = 0x00911030; break;
1438 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20);
1439 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24);
1443 promise_timing(struct ata_device *atadev, int devno, int mode)
1445 u_int32_t timing = 0;
1446 /* XXX: Endianess */
1447 struct promise_timing {
1449 u_int8_t prefetch:1;
1460 u_int8_t reserved:8;
1461 } *t = (struct promise_timing*)&timing;
1463 t->iordy = 1; t->iordyp = 1;
1464 if (mode >= ATA_DMA) {
1465 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1468 switch (atadev->channel->chiptype) {
1469 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1472 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1473 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1474 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1475 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1476 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1477 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1478 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1482 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1483 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1484 case 0x0d30105a: /* Promise OEM ATA 100 */
1487 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1488 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1489 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1490 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1491 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1492 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1493 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1494 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1495 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1499 pci_write_config(device_get_parent(atadev->channel->dev),
1500 0x60 + (devno<<2), timing, 4);
1504 hpt_timing(struct ata_device *atadev, int devno, int mode)
1506 device_t parent = device_get_parent(atadev->channel->dev);
1507 u_int32_t chiptype = atadev->channel->chiptype;
1508 int chiprev = pci_get_revid(parent);
1511 if (chiptype == 0x00081103 && chiprev >= 0x07) {
1512 switch (mode) { /* HPT374 */
1513 case ATA_PIO0: timing = 0x0ac1f48a; break;
1514 case ATA_PIO1: timing = 0x0ac1f465; break;
1515 case ATA_PIO2: timing = 0x0a81f454; break;
1516 case ATA_PIO3: timing = 0x0a81f443; break;
1517 case ATA_PIO4: timing = 0x0a81f442; break;
1518 case ATA_WDMA2: timing = 0x22808242; break;
1519 case ATA_UDMA2: timing = 0x120c8242; break;
1520 case ATA_UDMA4: timing = 0x12ac8242; break;
1521 case ATA_UDMA5: timing = 0x12848242; break;
1522 case ATA_UDMA6: timing = 0x12808242; break;
1523 default: timing = 0x0d029d5e;
1526 else if ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1527 (chiptype == 0x00051103 && chiprev >= 0x01)) {
1528 switch (mode) { /* HPT372 */
1529 case ATA_PIO0: timing = 0x0d029d5e; break;
1530 case ATA_PIO1: timing = 0x0d029d26; break;
1531 case ATA_PIO2: timing = 0x0c829ca6; break;
1532 case ATA_PIO3: timing = 0x0c829c84; break;
1533 case ATA_PIO4: timing = 0x0c829c62; break;
1534 case ATA_WDMA2: timing = 0x2c829262; break;
1535 case ATA_UDMA2: timing = 0x1c91dc62; break;
1536 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1537 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1538 case ATA_UDMA6: timing = 0x1c81dc62; break;
1539 default: timing = 0x0d029d5e;
1542 else if (chiptype == 0x00041103 && chiprev >= 0x03) {
1543 switch (mode) { /* HPT370 */
1544 case ATA_PIO0: timing = 0x06914e57; break;
1545 case ATA_PIO1: timing = 0x06914e43; break;
1546 case ATA_PIO2: timing = 0x06514e33; break;
1547 case ATA_PIO3: timing = 0x06514e22; break;
1548 case ATA_PIO4: timing = 0x06514e21; break;
1549 case ATA_WDMA2: timing = 0x26514e21; break;
1550 case ATA_UDMA2: timing = 0x16494e31; break;
1551 case ATA_UDMA4: timing = 0x16454e31; break;
1552 case ATA_UDMA5: timing = 0x16454e31; break;
1553 default: timing = 0x06514e57;
1555 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1557 else { /* HPT36[68] */
1558 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1559 case 0x85: /* 25Mhz */
1561 case ATA_PIO0: timing = 0x40d08585; break;
1562 case ATA_PIO1: timing = 0x40d08572; break;
1563 case ATA_PIO2: timing = 0x40ca8542; break;
1564 case ATA_PIO3: timing = 0x40ca8532; break;
1565 case ATA_PIO4: timing = 0x40ca8521; break;
1566 case ATA_WDMA2: timing = 0x20ca8521; break;
1567 case ATA_UDMA2: timing = 0x10cf8521; break;
1568 case ATA_UDMA4: timing = 0x10c98521; break;
1569 default: timing = 0x01208585;
1573 case 0xa7: /* 33MHz */
1575 case ATA_PIO0: timing = 0x40d0a7aa; break;
1576 case ATA_PIO1: timing = 0x40d0a7a3; break;
1577 case ATA_PIO2: timing = 0x40d0a753; break;
1578 case ATA_PIO3: timing = 0x40c8a742; break;
1579 case ATA_PIO4: timing = 0x40c8a731; break;
1580 case ATA_WDMA2: timing = 0x20c8a731; break;
1581 case ATA_UDMA2: timing = 0x10caa731; break;
1582 case ATA_UDMA4: timing = 0x10c9a731; break;
1583 default: timing = 0x0120a7a7;
1586 case 0xd9: /* 40Mhz */
1588 case ATA_PIO0: timing = 0x4018d9d9; break;
1589 case ATA_PIO1: timing = 0x4010d9c7; break;
1590 case ATA_PIO2: timing = 0x4010d997; break;
1591 case ATA_PIO3: timing = 0x4010d974; break;
1592 case ATA_PIO4: timing = 0x4008d963; break;
1593 case ATA_WDMA2: timing = 0x2008d943; break;
1594 case ATA_UDMA2: timing = 0x100bd943; break;
1595 case ATA_UDMA4: timing = 0x100fd943; break;
1596 default: timing = 0x0120d9d9;
1600 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1604 hpt_cable80(struct ata_device *atadev)
1606 device_t parent = device_get_parent(atadev->channel->dev);
1607 u_int8_t reg, val, res;
1609 if (atadev->channel->chiptype == 0x00081103 && pci_get_function(parent) == 1) {
1610 reg = atadev->channel->unit ? 0x57 : 0x53;
1611 val = pci_read_config(parent, reg, 1);
1612 pci_write_config(parent, reg, val | 0x80, 1);
1616 val = pci_read_config(parent, reg, 1);
1617 pci_write_config(parent, reg, val & 0xfe, 1);
1619 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x01 : 0x02);
1620 pci_write_config(parent, reg, val, 1);