2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $
33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.31 2005/08/03 16:01:11 hmp Exp $
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
79 * The 3c90x series chips use a bus-master DMA interface for transfering
80 * packets to and from the controller chip. Some of the "vortex" cards
81 * (3c59x) also supported a bus master mode, however for those chips
82 * you could only DMA packets to/from a contiguous memory buffer. For
83 * transmission this would mean copying the contents of the queued mbuf
84 * chain into an mbuf cluster and then DMAing the cluster. This extra
85 * copy would sort of defeat the purpose of the bus master support for
86 * any packet that doesn't fit into a single mbuf.
88 * By contrast, the 3c90x cards support a fragment-based bus master
89 * mode where mbuf chains can be encapsulated using TX descriptors.
90 * This is similar to other PCI chips such as the Texas Instruments
91 * ThunderLAN and the Intel 82557/82558.
93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
94 * bus master chips because they maintain the old PIO interface for
95 * backwards compatibility, but starting with the 3c905B and the
96 * "cyclone" chips, the compatibility interface has been dropped.
97 * Since using bus master DMA is a big win, we use this driver to
98 * support the PCI "boomerang" chips even though they work with the
99 * "vortex" driver in order to obtain better performance.
102 #include <sys/param.h>
103 #include <sys/systm.h>
104 #include <sys/sockio.h>
105 #include <sys/endian.h>
106 #include <sys/mbuf.h>
107 #include <sys/kernel.h>
108 #include <sys/socket.h>
109 #include <sys/thread2.h>
112 #include <net/ifq_var.h>
113 #include <net/if_arp.h>
114 #include <net/ethernet.h>
115 #include <net/if_dl.h>
116 #include <net/if_media.h>
117 #include <net/vlan/if_vlan_var.h>
121 #include <machine/bus_memio.h>
122 #include <machine/bus_pio.h>
123 #include <machine/bus.h>
124 #include <machine/resource.h>
126 #include <sys/rman.h>
128 #include "../mii_layer/mii.h"
129 #include "../mii_layer/miivar.h"
131 #include <bus/pci/pcireg.h>
132 #include <bus/pci/pcivar.h>
134 /* "controller miibus0" required. See GENERIC if you get errors here. */
135 #include "miibus_if.h"
137 #include "if_xlreg.h"
139 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
142 * Various supported device vendors/types and their names.
144 static struct xl_type xl_devs[] = {
145 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
146 "3Com 3c900-TPO Etherlink XL" },
147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
148 "3Com 3c900-COMBO Etherlink XL" },
149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
150 "3Com 3c905-TX Fast Etherlink XL" },
151 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
152 "3Com 3c905-T4 Fast Etherlink XL" },
153 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
154 "3Com 3c900B-TPO Etherlink XL" },
155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
156 "3Com 3c900B-COMBO Etherlink XL" },
157 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
158 "3Com 3c900B-TPC Etherlink XL" },
159 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
160 "3Com 3c900B-FL Etherlink XL" },
161 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
162 "3Com 3c905B-TX Fast Etherlink XL" },
163 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
164 "3Com 3c905B-T4 Fast Etherlink XL" },
165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
166 "3Com 3c905B-FX/SC Fast Etherlink XL" },
167 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
168 "3Com 3c905B-COMBO Fast Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
170 "3Com 3c905C-TX Fast Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
172 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
174 "3Com 3c980 Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
176 "3Com 3c980C Fast Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
178 "3Com 3cSOHO100-TX OfficeConnect" },
179 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
180 "3Com 3c450-TX HomeConnect" },
181 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
182 "3Com 3c555 Fast Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
184 "3Com 3c556 Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
186 "3Com 3c556B Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
188 "3Com 3c575TX Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
190 "3Com 3c575B Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
192 "3Com 3c575C Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
194 "3Com 3c656 Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
196 "3Com 3c656B Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
198 "3Com 3c656C Fast Etherlink XL" },
202 static int xl_probe (device_t);
203 static int xl_attach (device_t);
204 static int xl_detach (device_t);
206 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *);
207 static void xl_stats_update (void *);
208 static int xl_encap (struct xl_softc *, struct xl_chain *,
210 static void xl_rxeof (struct xl_softc *);
211 static int xl_rx_resync (struct xl_softc *);
212 static void xl_txeof (struct xl_softc *);
213 static void xl_txeof_90xB (struct xl_softc *);
214 static void xl_txeoc (struct xl_softc *);
215 static void xl_intr (void *);
216 static void xl_start (struct ifnet *);
217 static void xl_start_90xB (struct ifnet *);
218 static int xl_ioctl (struct ifnet *, u_long, caddr_t,
220 static void xl_init (void *);
221 static void xl_stop (struct xl_softc *);
222 static void xl_watchdog (struct ifnet *);
223 static void xl_shutdown (device_t);
224 static int xl_suspend (device_t);
225 static int xl_resume (device_t);
227 static int xl_ifmedia_upd (struct ifnet *);
228 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
230 static int xl_eeprom_wait (struct xl_softc *);
231 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
232 static void xl_mii_sync (struct xl_softc *);
233 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
234 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
235 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
237 static void xl_setcfg (struct xl_softc *);
238 static void xl_setmode (struct xl_softc *, int);
239 static void xl_setmulti (struct xl_softc *);
240 static void xl_setmulti_hash (struct xl_softc *);
241 static void xl_reset (struct xl_softc *);
242 static int xl_list_rx_init (struct xl_softc *);
243 static int xl_list_tx_init (struct xl_softc *);
244 static int xl_list_tx_init_90xB (struct xl_softc *);
245 static void xl_wait (struct xl_softc *);
246 static void xl_mediacheck (struct xl_softc *);
247 static void xl_choose_xcvr (struct xl_softc *, int);
248 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int);
249 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t,
251 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t,
254 static void xl_testpacket (struct xl_softc *);
257 static int xl_miibus_readreg (device_t, int, int);
258 static int xl_miibus_writereg (device_t, int, int, int);
259 static void xl_miibus_statchg (device_t);
260 static void xl_miibus_mediainit (device_t);
262 static device_method_t xl_methods[] = {
263 /* Device interface */
264 DEVMETHOD(device_probe, xl_probe),
265 DEVMETHOD(device_attach, xl_attach),
266 DEVMETHOD(device_detach, xl_detach),
267 DEVMETHOD(device_shutdown, xl_shutdown),
268 DEVMETHOD(device_suspend, xl_suspend),
269 DEVMETHOD(device_resume, xl_resume),
272 DEVMETHOD(bus_print_child, bus_generic_print_child),
273 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
276 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
277 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
278 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
279 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
284 static driver_t xl_driver = {
287 sizeof(struct xl_softc)
290 static devclass_t xl_devclass;
292 DECLARE_DUMMY_MODULE(if_xl);
293 MODULE_DEPEND(if_xl, miibus, 1, 1, 1);
294 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
295 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0);
296 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
299 xl_dma_map_addr(arg, segs, nseg, error)
301 bus_dma_segment_t *segs;
307 *paddr = segs->ds_addr;
311 xl_dma_map_rxbuf(arg, segs, nseg, mapsize, error)
313 bus_dma_segment_t *segs;
322 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
324 *paddr = segs->ds_addr;
328 xl_dma_map_txbuf(arg, segs, nseg, mapsize, error)
330 bus_dma_segment_t *segs;
341 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
345 for (i = 0; i < nseg; i++) {
346 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
347 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
348 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
349 total_len += segs[i].ds_len;
351 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
353 l->xl_status = htole32(total_len);
358 * Murphy's law says that it's possible the chip can wedge and
359 * the 'command in progress' bit may never clear. Hence, we wait
360 * only a finite amount of time to avoid getting caught in an
361 * infinite loop. Normally this delay routine would be a macro,
362 * but it isn't called during normal operation so we can afford
363 * to make it a function.
371 for (i = 0; i < XL_TIMEOUT; i++) {
372 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
377 if_printf(&sc->arpcom.ac_if, "command never completed!");
383 * MII access routines are provided for adapters with external
384 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
385 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
386 * Note: if you don't perform the MDIO operations just right,
387 * it's possible to end up with code that works correctly with
388 * some chips/CPUs/processor speeds/bus speeds/etc but not
392 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
393 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
396 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
397 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
400 * Sync the PHYs by setting data bit and strobing the clock 32 times.
409 MII_SET(XL_MII_DIR|XL_MII_DATA);
411 for (i = 0; i < 32; i++) {
413 MII_SET(XL_MII_DATA);
414 MII_SET(XL_MII_DATA);
416 MII_SET(XL_MII_DATA);
417 MII_SET(XL_MII_DATA);
424 * Clock a series of bits through the MII.
427 xl_mii_send(sc, bits, cnt)
437 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
439 MII_SET(XL_MII_DATA);
441 MII_CLR(XL_MII_DATA);
449 * Read an PHY register through the MII.
452 xl_mii_readreg(sc, frame)
454 struct xl_mii_frame *frame;
462 * Set up frame for RX.
464 frame->mii_stdelim = XL_MII_STARTDELIM;
465 frame->mii_opcode = XL_MII_READOP;
466 frame->mii_turnaround = 0;
470 * Select register window 4.
475 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
484 * Send command/address info.
486 xl_mii_send(sc, frame->mii_stdelim, 2);
487 xl_mii_send(sc, frame->mii_opcode, 2);
488 xl_mii_send(sc, frame->mii_phyaddr, 5);
489 xl_mii_send(sc, frame->mii_regaddr, 5);
492 MII_CLR((XL_MII_CLK|XL_MII_DATA));
500 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
504 * Now try reading data bits. If the ack failed, we still
505 * need to clock through 16 cycles to keep the PHY(s) in sync.
508 for(i = 0; i < 16; i++) {
515 for (i = 0x8000; i; i >>= 1) {
518 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
519 frame->mii_data |= i;
537 * Write to a PHY register through the MII.
540 xl_mii_writereg(sc, frame)
542 struct xl_mii_frame *frame;
548 * Set up frame for TX.
551 frame->mii_stdelim = XL_MII_STARTDELIM;
552 frame->mii_opcode = XL_MII_WRITEOP;
553 frame->mii_turnaround = XL_MII_TURNAROUND;
556 * Select the window 4.
561 * Turn on data output.
567 xl_mii_send(sc, frame->mii_stdelim, 2);
568 xl_mii_send(sc, frame->mii_opcode, 2);
569 xl_mii_send(sc, frame->mii_phyaddr, 5);
570 xl_mii_send(sc, frame->mii_regaddr, 5);
571 xl_mii_send(sc, frame->mii_turnaround, 2);
572 xl_mii_send(sc, frame->mii_data, 16);
589 xl_miibus_readreg(dev, phy, reg)
594 struct xl_mii_frame frame;
596 sc = device_get_softc(dev);
599 * Pretend that PHYs are only available at MII address 24.
600 * This is to guard against problems with certain 3Com ASIC
601 * revisions that incorrectly map the internal transceiver
602 * control registers at all MII addresses. This can cause
603 * the miibus code to attach the same PHY several times over.
605 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
608 bzero((char *)&frame, sizeof(frame));
610 frame.mii_phyaddr = phy;
611 frame.mii_regaddr = reg;
612 xl_mii_readreg(sc, &frame);
614 return(frame.mii_data);
618 xl_miibus_writereg(dev, phy, reg, data)
623 struct xl_mii_frame frame;
625 sc = device_get_softc(dev);
627 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
630 bzero((char *)&frame, sizeof(frame));
632 frame.mii_phyaddr = phy;
633 frame.mii_regaddr = reg;
634 frame.mii_data = data;
636 xl_mii_writereg(sc, &frame);
642 xl_miibus_statchg(dev)
646 struct mii_data *mii;
649 sc = device_get_softc(dev);
650 mii = device_get_softc(sc->xl_miibus);
654 /* Set ASIC's duplex mode to match the PHY. */
656 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
657 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
659 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
660 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
666 * Special support for the 3c905B-COMBO. This card has 10/100 support
667 * plus BNC and AUI ports. This means we will have both an miibus attached
668 * plus some non-MII media settings. In order to allow this, we have to
669 * add the extra media to the miibus's ifmedia struct, but we can't do
670 * that during xl_attach() because the miibus hasn't been attached yet.
671 * So instead, we wait until the miibus probe/attach is done, at which
672 * point we will get a callback telling is that it's safe to add our
676 xl_miibus_mediainit(dev)
680 struct mii_data *mii;
683 sc = device_get_softc(dev);
684 mii = device_get_softc(sc->xl_miibus);
685 ifm = &mii->mii_media;
687 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
689 * Check for a 10baseFL board in disguise.
691 if (sc->xl_type == XL_TYPE_905B &&
692 sc->xl_media == XL_MEDIAOPT_10FL) {
694 device_printf(dev, "found 10baseFL\n");
695 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
696 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
697 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
699 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
702 device_printf(dev, "found AUI\n");
703 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
707 if (sc->xl_media & XL_MEDIAOPT_BNC) {
709 device_printf(dev, "found BNC\n");
710 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
717 * The EEPROM is slow: give it time to come ready after issuing
726 for (i = 0; i < 100; i++) {
727 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
734 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n");
742 * Read a sequence of words from the EEPROM. Note that ethernet address
743 * data is stored in the EEPROM in network byte order.
746 xl_read_eeprom(sc, dest, off, cnt, swap)
754 u_int16_t word = 0, *ptr;
755 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
756 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
758 * It's easy to accidentally overwrite the rom content!
759 * Note: the 3c575 uses 8bit EEPROM offsets.
763 if (xl_eeprom_wait(sc))
766 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
769 for (i = 0; i < cnt; i++) {
770 if (sc->xl_flags & XL_FLAG_8BITROM)
771 CSR_WRITE_2(sc, XL_W0_EE_CMD,
772 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
774 CSR_WRITE_2(sc, XL_W0_EE_CMD,
775 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
776 err = xl_eeprom_wait(sc);
779 word = CSR_READ_2(sc, XL_W0_EE_DATA);
780 ptr = (u_int16_t *)(dest + (i * 2));
791 * NICs older than the 3c905B have only one multicast option, which
792 * is to enable reception of all multicast frames.
799 struct ifmultiaddr *ifma;
803 ifp = &sc->arpcom.ac_if;
806 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
808 if (ifp->if_flags & IFF_ALLMULTI) {
809 rxfilt |= XL_RXFILTER_ALLMULTI;
810 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
814 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
818 rxfilt |= XL_RXFILTER_ALLMULTI;
820 rxfilt &= ~XL_RXFILTER_ALLMULTI;
822 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
828 * 3c905B adapters have a hash filter that we can program.
836 struct ifmultiaddr *ifma;
840 ifp = &sc->arpcom.ac_if;
843 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
845 if (ifp->if_flags & IFF_ALLMULTI) {
846 rxfilt |= XL_RXFILTER_ALLMULTI;
847 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
850 rxfilt &= ~XL_RXFILTER_ALLMULTI;
853 /* first, zot all the existing hash bits */
854 for (i = 0; i < XL_HASHFILT_SIZE; i++)
855 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
857 /* now program new ones */
858 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
859 if (ifma->ifma_addr->sa_family != AF_LINK)
863 * Note: the 3c905B currently only supports a 64-bit
864 * hash table, which means we really only need 6 bits,
865 * but the manual indicates that future chip revisions
866 * will have a 256-bit hash table, hence the routine is
867 * set up to calculate 8 bits of position info in case
868 * we need it some day.
869 * Note II, The Sequel: _CURRENT_ versions of the 3c905B
870 * have a 256 bit hash table. This means we have to use
871 * all 8 bits regardless. On older cards, the upper 2
872 * bits will be ignored. Grrrr....
875 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
876 ETHER_ADDR_LEN) & 0xff;
877 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
882 rxfilt |= XL_RXFILTER_MULTIHASH;
884 rxfilt &= ~XL_RXFILTER_MULTIHASH;
886 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
899 ifp = &sc->arpcom.ac_if;
901 MGETHDR(m, MB_DONTWAIT, MT_DATA);
906 bcopy(&sc->arpcom.ac_enaddr,
907 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
908 bcopy(&sc->arpcom.ac_enaddr,
909 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
910 mtod(m, struct ether_header *)->ether_type = htons(3);
911 mtod(m, unsigned char *)[14] = 0;
912 mtod(m, unsigned char *)[15] = 0;
913 mtod(m, unsigned char *)[16] = 0xE3;
914 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
915 IF_ENQUEUE(&ifp->if_snd, m);
929 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
930 icfg &= ~XL_ICFG_CONNECTOR_MASK;
931 if (sc->xl_media & XL_MEDIAOPT_MII ||
932 sc->xl_media & XL_MEDIAOPT_BT4)
933 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
934 if (sc->xl_media & XL_MEDIAOPT_BTX)
935 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
937 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
938 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
944 xl_setmode(sc, media)
948 struct ifnet *ifp = &sc->arpcom.ac_if;
952 if_printf(ifp, "selecting ");
955 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
957 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
959 if (sc->xl_media & XL_MEDIAOPT_BT) {
960 if (IFM_SUBTYPE(media) == IFM_10_T) {
961 printf("10baseT transceiver, ");
962 sc->xl_xcvr = XL_XCVR_10BT;
963 icfg &= ~XL_ICFG_CONNECTOR_MASK;
964 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
965 mediastat |= XL_MEDIASTAT_LINKBEAT|
966 XL_MEDIASTAT_JABGUARD;
967 mediastat &= ~XL_MEDIASTAT_SQEENB;
971 if (sc->xl_media & XL_MEDIAOPT_BFX) {
972 if (IFM_SUBTYPE(media) == IFM_100_FX) {
973 printf("100baseFX port, ");
974 sc->xl_xcvr = XL_XCVR_100BFX;
975 icfg &= ~XL_ICFG_CONNECTOR_MASK;
976 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
977 mediastat |= XL_MEDIASTAT_LINKBEAT;
978 mediastat &= ~XL_MEDIASTAT_SQEENB;
982 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
983 if (IFM_SUBTYPE(media) == IFM_10_5) {
984 printf("AUI port, ");
985 sc->xl_xcvr = XL_XCVR_AUI;
986 icfg &= ~XL_ICFG_CONNECTOR_MASK;
987 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
988 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
989 XL_MEDIASTAT_JABGUARD);
990 mediastat |= ~XL_MEDIASTAT_SQEENB;
992 if (IFM_SUBTYPE(media) == IFM_10_FL) {
993 printf("10baseFL transceiver, ");
994 sc->xl_xcvr = XL_XCVR_AUI;
995 icfg &= ~XL_ICFG_CONNECTOR_MASK;
996 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
997 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
998 XL_MEDIASTAT_JABGUARD);
999 mediastat |= ~XL_MEDIASTAT_SQEENB;
1003 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1004 if (IFM_SUBTYPE(media) == IFM_10_2) {
1005 printf("BNC port, ");
1006 sc->xl_xcvr = XL_XCVR_COAX;
1007 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1008 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
1009 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1010 XL_MEDIASTAT_JABGUARD|
1011 XL_MEDIASTAT_SQEENB);
1015 if ((media & IFM_GMASK) == IFM_FDX ||
1016 IFM_SUBTYPE(media) == IFM_100_FX) {
1017 printf("full duplex\n");
1019 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
1021 printf("half duplex\n");
1023 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
1024 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
1027 if (IFM_SUBTYPE(media) == IFM_10_2)
1028 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1030 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1031 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1033 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1040 struct xl_softc *sc;
1045 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1046 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1047 XL_RESETOPT_DISADVFD:0));
1050 * If we're using memory mapped register mode, pause briefly
1051 * after issuing the reset command before trying to access any
1052 * other registers. With my 3c575C cardbus card, failing to do
1053 * this results in the system locking up while trying to poll
1054 * the command busy bit in the status register.
1056 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1059 for (i = 0; i < XL_TIMEOUT; i++) {
1061 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1065 if (i == XL_TIMEOUT)
1066 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n");
1068 /* Reset TX and RX. */
1069 /* Note: the RX reset takes an absurd amount of time
1070 * on newer versions of the Tornado chips such as those
1071 * on the 3c905CX and newer 3c908C cards. We wait an
1072 * extra amount of time so that xl_wait() doesn't complain
1073 * and annoy the users.
1075 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1078 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1081 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1082 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1084 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1085 XL_W2_RESET_OPTIONS)
1086 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1087 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1091 /* Wait a little while for the chip to get its brains in order. */
1097 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1098 * IDs against our list and return a device name if we find a match.
1101 xl_probe(device_t dev)
1106 vid = pci_get_vendor(dev);
1107 did = pci_get_device(dev);
1108 for (t = xl_devs; t->xl_name != NULL; t++) {
1109 if (vid == t->xl_vid && did == t->xl_did) {
1110 device_set_desc(dev, t->xl_name);
1118 * This routine is a kludge to work around possible hardware faults
1119 * or manufacturing defects that can cause the media options register
1120 * (or reset options register, as it's called for the first generation
1121 * 3c90x adapters) to return an incorrect result. I have encountered
1122 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1123 * which doesn't have any of the 'mediaopt' bits set. This screws up
1124 * the attach routine pretty badly because it doesn't know what media
1125 * to look for. If we find ourselves in this predicament, this routine
1126 * will try to guess the media options values and warn the user of a
1127 * possible manufacturing defect with his adapter/system/whatever.
1131 struct xl_softc *sc;
1133 struct ifnet *ifp = &sc->arpcom.ac_if;
1136 * If some of the media options bits are set, assume they are
1137 * correct. If not, try to figure it out down below.
1138 * XXX I should check for 10baseFL, but I don't have an adapter
1141 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1143 * Check the XCVR value. If it's not in the normal range
1144 * of values, we need to fake it up here.
1146 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1149 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n",
1152 "choosing new default based on card type\n");
1155 if (sc->xl_type == XL_TYPE_905B &&
1156 sc->xl_media & XL_MEDIAOPT_10FL)
1158 if_printf(ifp, "WARNING: no media options bits set in "
1159 "the media options register!!\n");
1160 if_printf(ifp, "this could be a manufacturing defect in "
1161 "your adapter or system\n");
1162 if_printf(ifp, "attempting to guess media type; you "
1163 "should probably consult your vendor\n");
1166 xl_choose_xcvr(sc, 1);
1170 xl_choose_xcvr(sc, verbose)
1171 struct xl_softc *sc;
1174 struct ifnet *ifp = &sc->arpcom.ac_if;
1178 * Read the device ID from the EEPROM.
1179 * This is what's loaded into the PCI device ID register, so it has
1180 * to be correct otherwise we wouldn't have gotten this far.
1182 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1185 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1186 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1187 sc->xl_media = XL_MEDIAOPT_BT;
1188 sc->xl_xcvr = XL_XCVR_10BT;
1190 if_printf(ifp, "guessing 10BaseT transceiver\n");
1192 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1193 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1194 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1195 sc->xl_xcvr = XL_XCVR_10BT;
1197 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n");
1199 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1200 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1201 sc->xl_xcvr = XL_XCVR_10BT;
1203 if_printf(ifp, "guessing TPC (BNC/TP)\n");
1205 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1206 sc->xl_media = XL_MEDIAOPT_10FL;
1207 sc->xl_xcvr = XL_XCVR_AUI;
1209 if_printf(ifp, "guessing 10baseFL\n");
1211 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1212 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1213 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1214 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1215 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1216 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1217 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1218 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1219 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1220 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1221 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1222 sc->xl_media = XL_MEDIAOPT_MII;
1223 sc->xl_xcvr = XL_XCVR_MII;
1225 if_printf(ifp, "guessing MII\n");
1227 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1228 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1229 sc->xl_media = XL_MEDIAOPT_BT4;
1230 sc->xl_xcvr = XL_XCVR_MII;
1232 if_printf(ifp, "guessing 100BaseT4/MII\n");
1234 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1235 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1236 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1237 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1238 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1239 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1240 sc->xl_media = XL_MEDIAOPT_BTX;
1241 sc->xl_xcvr = XL_XCVR_AUTO;
1243 if_printf(ifp, "guessing 10/100 internal\n");
1245 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1246 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1247 sc->xl_xcvr = XL_XCVR_AUTO;
1249 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n");
1253 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1254 sc->xl_media = XL_MEDIAOPT_BT;
1262 * Attach the interface. Allocate softc structures, do ifmedia
1263 * setup and ethernet/BPF attach.
1269 u_char eaddr[ETHER_ADDR_LEN];
1271 struct xl_softc *sc;
1273 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1274 int error = 0, rid, res;
1276 sc = device_get_softc(dev);
1278 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1281 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555)
1282 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1283 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 ||
1284 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1285 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1286 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1287 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1288 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 ||
1289 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556)
1290 sc->xl_flags |= XL_FLAG_8BITROM;
1291 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1292 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1293 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1294 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1295 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B ||
1296 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1297 sc->xl_flags |= XL_FLAG_FUNCREG;
1298 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A ||
1299 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1300 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1301 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B ||
1302 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1303 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1305 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656)
1306 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1307 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B)
1308 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1309 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C)
1310 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1311 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1312 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1313 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 ||
1314 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B)
1315 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1316 XL_FLAG_INVERT_LED_PWR;
1317 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B)
1318 sc->xl_flags |= XL_FLAG_PHYOK;
1319 #ifndef BURN_BRIDGES
1321 * If this is a 3c905B, we have to check one extra thing.
1322 * The 905B supports power management and may be placed in
1323 * a low-power mode (D3 mode), typically by certain operating
1324 * systems which shall not be named. The PCI BIOS is supposed
1325 * to reset the NIC and bring it out of low-power mode, but
1326 * some do not. Consequently, we have to see if this chip
1327 * supports power management, and if so, make sure it's not
1328 * in low-power mode. If power management is available, the
1329 * capid byte will be 0x01.
1331 * I _think_ that what actually happens is that the chip
1332 * loses its PCI configuration during the transition from
1333 * D3 back to D0; this means that it should be possible for
1334 * us to save the PCI iobase, membase and IRQ, put the chip
1335 * back in the D0 state, then restore the PCI config ourselves.
1338 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1339 u_int32_t iobase, membase, irq;
1341 /* Save important PCI config data. */
1342 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1343 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1344 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1346 /* Reset the power state. */
1347 device_printf(dev, "chip is in D%d power mode "
1348 "-- setting to D0\n", pci_get_powerstate(dev));
1350 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1352 /* Restore PCI config data. */
1353 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1354 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1355 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1359 * Map control/status registers.
1361 pci_enable_busmaster(dev);
1364 res = SYS_RES_MEMORY;
1367 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1370 if (sc->xl_res != NULL) {
1371 sc->xl_flags |= XL_FLAG_USE_MMIO;
1373 device_printf(dev, "using memory mapped I/O\n");
1376 res = SYS_RES_IOPORT;
1377 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1378 if (sc->xl_res == NULL) {
1379 device_printf(dev, "couldn't map ports/memory\n");
1384 device_printf(dev, "using port I/O\n");
1387 sc->xl_btag = rman_get_bustag(sc->xl_res);
1388 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1390 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1391 rid = XL_PCI_FUNCMEM;
1392 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1395 if (sc->xl_fres == NULL) {
1396 device_printf(dev, "couldn't map funcreg memory\n");
1401 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1402 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1405 /* Allocate interrupt */
1407 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1408 RF_SHAREABLE | RF_ACTIVE);
1409 if (sc->xl_irq == NULL) {
1410 device_printf(dev, "couldn't map interrupt\n");
1415 sc->xl_flags |= XL_FLAG_ATTACH_MAPPED;
1417 ifp = &sc->arpcom.ac_if;
1418 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1420 /* Reset the adapter. */
1424 * Get station address from the EEPROM.
1426 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1427 device_printf(dev, "failed to read station address\n");
1432 callout_init(&sc->xl_stat_timer);
1435 * Now allocate a tag for the DMA descriptor lists and a chunk
1436 * of DMA-able memory based on the tag. Also obtain the DMA
1437 * addresses of the RX and TX ring, which we'll need later.
1438 * All of our lists are allocated as a contiguous block
1441 error = bus_dma_tag_create(NULL, 8, 0,
1442 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1443 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0,
1444 &sc->xl_ldata.xl_rx_tag);
1446 device_printf(dev, "failed to allocate rx dma tag\n");
1450 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1451 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT,
1452 &sc->xl_ldata.xl_rx_dmamap);
1454 device_printf(dev, "no memory for rx list buffers!\n");
1455 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1456 sc->xl_ldata.xl_rx_tag = NULL;
1460 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1461 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1462 XL_RX_LIST_SZ, xl_dma_map_addr,
1463 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1465 device_printf(dev, "cannot get dma address of the rx ring!\n");
1466 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1467 sc->xl_ldata.xl_rx_dmamap);
1468 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1469 sc->xl_ldata.xl_rx_tag = NULL;
1473 error = bus_dma_tag_create(NULL, 8, 0,
1474 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1475 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0,
1476 &sc->xl_ldata.xl_tx_tag);
1478 device_printf(dev, "failed to allocate tx dma tag\n");
1482 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1483 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT,
1484 &sc->xl_ldata.xl_tx_dmamap);
1486 device_printf(dev, "no memory for list buffers!\n");
1487 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1488 sc->xl_ldata.xl_tx_tag = NULL;
1492 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1493 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1494 XL_TX_LIST_SZ, xl_dma_map_addr,
1495 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1497 device_printf(dev, "cannot get dma address of the tx ring!\n");
1498 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1499 sc->xl_ldata.xl_tx_dmamap);
1500 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1501 sc->xl_ldata.xl_tx_tag = NULL;
1506 * Allocate a DMA tag for the mapping of mbufs.
1508 error = bus_dma_tag_create(NULL, 1, 0,
1509 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1510 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0,
1513 device_printf(dev, "failed to allocate mbuf dma tag\n");
1517 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
1518 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
1520 /* We need a spare DMA map for the RX ring. */
1521 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1526 * Figure out the card type. 3c905B adapters have the
1527 * 'supportsNoTxLength' bit set in the capabilities
1528 * word in the EEPROM.
1529 * Note: my 3c575C cardbus card lies. It returns a value
1530 * of 0x1578 for its capabilities word, which is somewhat
1531 * nonsensical. Another way to distinguish a 3c90x chip
1532 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1533 * bit. This will only be set for 3c90x boomerage chips.
1535 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1536 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1537 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1538 sc->xl_type = XL_TYPE_905B;
1540 sc->xl_type = XL_TYPE_90X;
1543 ifp->if_mtu = ETHERMTU;
1544 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1545 ifp->if_ioctl = xl_ioctl;
1546 ifp->if_capabilities = 0;
1547 if (sc->xl_type == XL_TYPE_905B) {
1548 ifp->if_start = xl_start_90xB;
1549 ifp->if_capabilities |= IFCAP_HWCSUM;
1551 ifp->if_start = xl_start;
1553 ifp->if_watchdog = xl_watchdog;
1554 ifp->if_init = xl_init;
1555 ifp->if_baudrate = 10000000;
1556 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1557 ifq_set_ready(&ifp->if_snd);
1559 * NOTE: features disabled by default. This seems to corrupt
1560 * tx packet data one out of a million packets or so and then
1561 * generates a good checksum so the receiver doesn't
1562 * know the packet is bad
1564 ifp->if_capenable = 0; /*ifp->if_capabilities;*/
1565 if (ifp->if_capenable & IFCAP_TXCSUM)
1566 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1569 * Now we have to see what sort of media we have.
1570 * This includes probing for an MII interace and a
1574 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1576 if_printf(ifp, "media options word: %x\n", sc->xl_media);
1578 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1579 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1580 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1581 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1585 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1586 || sc->xl_media & XL_MEDIAOPT_BT4) {
1588 if_printf(ifp, "found MII/AUTO\n");
1590 if (mii_phy_probe(dev, &sc->xl_miibus,
1591 xl_ifmedia_upd, xl_ifmedia_sts)) {
1592 if_printf(ifp, "no PHY found!\n");
1601 * Sanity check. If the user has selected "auto" and this isn't
1602 * a 10/100 card of some kind, we need to force the transceiver
1603 * type to something sane.
1605 if (sc->xl_xcvr == XL_XCVR_AUTO)
1606 xl_choose_xcvr(sc, bootverbose);
1611 if (sc->xl_media & XL_MEDIAOPT_BT) {
1613 if_printf(ifp, "found 10baseT\n");
1614 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1615 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1616 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1617 ifmedia_add(&sc->ifmedia,
1618 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1621 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1623 * Check for a 10baseFL board in disguise.
1625 if (sc->xl_type == XL_TYPE_905B &&
1626 sc->xl_media == XL_MEDIAOPT_10FL) {
1628 if_printf(ifp, "found 10baseFL\n");
1629 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1630 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1632 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1633 ifmedia_add(&sc->ifmedia,
1634 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1637 if_printf(ifp, "found AUI\n");
1638 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1642 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1644 if_printf(ifp, "found BNC\n");
1645 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1648 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1650 if_printf(ifp, "found 100baseFX\n");
1651 ifp->if_baudrate = 100000000;
1652 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1655 /* Choose a default media. */
1656 switch(sc->xl_xcvr) {
1658 media = IFM_ETHER|IFM_10_T;
1659 xl_setmode(sc, media);
1662 if (sc->xl_type == XL_TYPE_905B &&
1663 sc->xl_media == XL_MEDIAOPT_10FL) {
1664 media = IFM_ETHER|IFM_10_FL;
1665 xl_setmode(sc, media);
1667 media = IFM_ETHER|IFM_10_5;
1668 xl_setmode(sc, media);
1672 media = IFM_ETHER|IFM_10_2;
1673 xl_setmode(sc, media);
1676 case XL_XCVR_100BTX:
1678 /* Chosen by miibus */
1680 case XL_XCVR_100BFX:
1681 media = IFM_ETHER|IFM_100_FX;
1684 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr);
1686 * This will probably be wrong, but it prevents
1687 * the ifmedia code from panicking.
1689 media = IFM_ETHER|IFM_10_T;
1693 if (sc->xl_miibus == NULL)
1694 ifmedia_set(&sc->ifmedia, media);
1698 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1700 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1704 * Call MI attach routine.
1706 ether_ifattach(ifp, eaddr);
1709 * Tell the upper layer(s) we support long frames.
1711 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1713 /* Hook interrupt last to avoid having to lock softc */
1714 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET,
1715 xl_intr, sc, &sc->xl_intrhand, NULL);
1717 if_printf(ifp, "couldn't set up irq\n");
1718 ether_ifdetach(ifp);
1730 * Shutdown hardware and free up resources. This can be called any
1731 * time after the mutex has been initialized. It is called in both
1732 * the error case in attach and the normal detach case so it needs
1733 * to be careful about only freeing resources that have actually been
1740 struct xl_softc *sc;
1744 sc = device_get_softc(dev);
1745 ifp = &sc->arpcom.ac_if;
1747 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1749 res = SYS_RES_MEMORY;
1752 res = SYS_RES_IOPORT;
1758 * Only try to communicate with the device if we were able to map
1759 * the ports. This flag is set before ether_ifattach() so it also
1760 * governs our call to ether_ifdetach().
1762 if (sc->xl_flags & XL_FLAG_ATTACH_MAPPED) {
1765 ether_ifdetach(ifp);
1769 device_delete_child(dev, sc->xl_miibus);
1770 bus_generic_detach(dev);
1771 ifmedia_removeall(&sc->ifmedia);
1773 if (sc->xl_intrhand)
1774 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1779 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1780 if (sc->xl_fres != NULL)
1781 bus_release_resource(dev, SYS_RES_MEMORY,
1782 XL_PCI_FUNCMEM, sc->xl_fres);
1784 bus_release_resource(dev, res, rid, sc->xl_res);
1787 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1788 bus_dma_tag_destroy(sc->xl_mtag);
1790 if (sc->xl_ldata.xl_rx_tag) {
1791 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1792 sc->xl_ldata.xl_rx_dmamap);
1793 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1794 sc->xl_ldata.xl_rx_dmamap);
1795 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1797 if (sc->xl_ldata.xl_tx_tag) {
1798 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1799 sc->xl_ldata.xl_tx_dmamap);
1800 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1801 sc->xl_ldata.xl_tx_dmamap);
1802 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1809 * Initialize the transmit descriptors.
1813 struct xl_softc *sc;
1815 struct xl_chain_data *cd;
1816 struct xl_list_data *ld;
1821 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1822 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1823 error = bus_dmamap_create(sc->xl_mtag, 0,
1824 &cd->xl_tx_chain[i].xl_map);
1827 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1828 i * sizeof(struct xl_list);
1829 if (i == (XL_TX_LIST_CNT - 1))
1830 cd->xl_tx_chain[i].xl_next = NULL;
1832 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1835 cd->xl_tx_free = &cd->xl_tx_chain[0];
1836 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1838 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1843 * Initialize the transmit descriptors.
1846 xl_list_tx_init_90xB(sc)
1847 struct xl_softc *sc;
1849 struct xl_chain_data *cd;
1850 struct xl_list_data *ld;
1855 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1856 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1857 error = bus_dmamap_create(sc->xl_mtag, 0,
1858 &cd->xl_tx_chain[i].xl_map);
1861 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1862 i * sizeof(struct xl_list);
1863 if (i == (XL_TX_LIST_CNT - 1))
1864 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1866 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1868 cd->xl_tx_chain[i].xl_prev =
1869 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1871 cd->xl_tx_chain[i].xl_prev =
1872 &cd->xl_tx_chain[i - 1];
1875 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1876 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1882 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1887 * Initialize the RX descriptors and allocate mbufs for them. Note that
1888 * we arrange the descriptors in a closed ring, so that the last descriptor
1889 * points back to the first.
1893 struct xl_softc *sc;
1895 struct xl_chain_data *cd;
1896 struct xl_list_data *ld;
1903 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1904 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1905 error = bus_dmamap_create(sc->xl_mtag, 0,
1906 &cd->xl_rx_chain[i].xl_map);
1909 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1912 if (i == (XL_RX_LIST_CNT - 1))
1916 nextptr = ld->xl_rx_dmaaddr +
1917 next * sizeof(struct xl_list_onefrag);
1918 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1919 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1922 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1923 cd->xl_rx_head = &cd->xl_rx_chain[0];
1929 * Initialize an RX descriptor and attach an MBUF cluster.
1930 * If we fail to do so, we need to leave the old mbuf and
1931 * the old DMA map untouched so that it can be reused.
1935 struct xl_softc *sc;
1936 struct xl_chain_onefrag *c;
1938 struct mbuf *m_new = NULL;
1943 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1947 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1949 /* Force longword alignment for packet payload. */
1950 m_adj(m_new, ETHER_ALIGN);
1952 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
1953 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
1956 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n",
1961 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1963 c->xl_map = sc->xl_tmpmap;
1964 sc->xl_tmpmap = map;
1966 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1967 c->xl_ptr->xl_status = 0;
1968 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
1969 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1975 struct xl_softc *sc;
1977 struct xl_chain_onefrag *pos;
1980 pos = sc->xl_cdata.xl_rx_head;
1982 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1983 if (pos->xl_ptr->xl_status)
1988 if (i == XL_RX_LIST_CNT)
1991 sc->xl_cdata.xl_rx_head = pos;
1997 * A frame has been uploaded: pass the resulting mbuf chain up to
1998 * the higher level protocols.
2002 struct xl_softc *sc;
2006 struct xl_chain_onefrag *cur_rx;
2010 ifp = &sc->arpcom.ac_if;
2014 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
2015 BUS_DMASYNC_POSTREAD);
2016 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
2017 cur_rx = sc->xl_cdata.xl_rx_head;
2018 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
2019 total_len = rxstat & XL_RXSTAT_LENMASK;
2022 * Since we have told the chip to allow large frames,
2023 * we need to trap giant frame errors in software. We allow
2024 * a little more than the normal frame size to account for
2025 * frames with VLAN tags.
2027 if (total_len > XL_MAX_FRAMELEN)
2028 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
2031 * If an error occurs, update stats, clear the
2032 * status word and leave the mbuf cluster in place:
2033 * it should simply get re-used next time this descriptor
2034 * comes up in the ring.
2036 if (rxstat & XL_RXSTAT_UP_ERROR) {
2038 cur_rx->xl_ptr->xl_status = 0;
2039 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2040 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2045 * If the error bit was not set, the upload complete
2046 * bit should be set which means we have a valid packet.
2047 * If not, something truly strange has happened.
2049 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2051 "bad receive status -- packet dropped\n");
2053 cur_rx->xl_ptr->xl_status = 0;
2054 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2055 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2059 /* No errors; receive the packet. */
2060 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2061 BUS_DMASYNC_POSTREAD);
2062 m = cur_rx->xl_mbuf;
2065 * Try to conjure up a new mbuf cluster. If that
2066 * fails, it means we have an out of memory condition and
2067 * should leave the buffer in place and continue. This will
2068 * result in a lost packet, but there's little else we
2069 * can do in this situation.
2071 if (xl_newbuf(sc, cur_rx)) {
2073 cur_rx->xl_ptr->xl_status = 0;
2074 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2075 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2078 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2079 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2082 m->m_pkthdr.rcvif = ifp;
2083 m->m_pkthdr.len = m->m_len = total_len;
2085 if (ifp->if_capenable & IFCAP_RXCSUM) {
2086 /* Do IP checksum checking. */
2087 if (rxstat & XL_RXSTAT_IPCKOK)
2088 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2089 if (!(rxstat & XL_RXSTAT_IPCKERR))
2090 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2091 if ((rxstat & XL_RXSTAT_TCPCOK &&
2092 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2093 (rxstat & XL_RXSTAT_UDPCKOK &&
2094 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2095 m->m_pkthdr.csum_flags |=
2096 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2097 m->m_pkthdr.csum_data = 0xffff;
2101 (*ifp->if_input)(ifp, m);
2105 * Handle the 'end of channel' condition. When the upload
2106 * engine hits the end of the RX ring, it will stall. This
2107 * is our cue to flush the RX ring, reload the uplist pointer
2108 * register and unstall the engine.
2109 * XXX This is actually a little goofy. With the ThunderLAN
2110 * chip, you get an interrupt when the receiver hits the end
2111 * of the receive ring, which tells you exactly when you
2112 * you need to reload the ring pointer. Here we have to
2113 * fake it. I'm mad at myself for not being clever enough
2114 * to avoid the use of a goto here.
2116 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2117 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2118 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2120 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2121 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2122 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2130 * A frame was downloaded to the chip. It's safe for us to clean up
2135 struct xl_softc *sc;
2137 struct xl_chain *cur_tx;
2140 ifp = &sc->arpcom.ac_if;
2142 /* Clear the timeout timer. */
2146 * Go through our tx list and free mbufs for those
2147 * frames that have been uploaded. Note: the 3c905B
2148 * sets a special bit in the status word to let us
2149 * know that a frame has been downloaded, but the
2150 * original 3c900/3c905 adapters don't do that.
2151 * Consequently, we have to use a different test if
2152 * xl_type != XL_TYPE_905B.
2154 while(sc->xl_cdata.xl_tx_head != NULL) {
2155 cur_tx = sc->xl_cdata.xl_tx_head;
2157 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2160 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2161 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2162 BUS_DMASYNC_POSTWRITE);
2163 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2164 m_freem(cur_tx->xl_mbuf);
2165 cur_tx->xl_mbuf = NULL;
2168 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2169 sc->xl_cdata.xl_tx_free = cur_tx;
2172 if (sc->xl_cdata.xl_tx_head == NULL) {
2173 ifp->if_flags &= ~IFF_OACTIVE;
2174 sc->xl_cdata.xl_tx_tail = NULL;
2176 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2177 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2178 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2179 sc->xl_cdata.xl_tx_head->xl_phys);
2180 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2189 struct xl_softc *sc;
2191 struct xl_chain *cur_tx = NULL;
2195 ifp = &sc->arpcom.ac_if;
2197 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2198 BUS_DMASYNC_POSTREAD);
2199 idx = sc->xl_cdata.xl_tx_cons;
2200 while(idx != sc->xl_cdata.xl_tx_prod) {
2202 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2204 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2205 XL_TXSTAT_DL_COMPLETE))
2208 if (cur_tx->xl_mbuf != NULL) {
2209 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2210 BUS_DMASYNC_POSTWRITE);
2211 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2212 m_freem(cur_tx->xl_mbuf);
2213 cur_tx->xl_mbuf = NULL;
2218 sc->xl_cdata.xl_tx_cnt--;
2219 XL_INC(idx, XL_TX_LIST_CNT);
2223 sc->xl_cdata.xl_tx_cons = idx;
2226 ifp->if_flags &= ~IFF_OACTIVE;
2232 * TX 'end of channel' interrupt handler. Actually, we should
2233 * only get a 'TX complete' interrupt if there's a transmit error,
2234 * so this is really TX error handler.
2238 struct xl_softc *sc;
2240 struct ifnet *ifp = &sc->arpcom.ac_if;
2243 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2244 if (txstat & XL_TXSTATUS_UNDERRUN ||
2245 txstat & XL_TXSTATUS_JABBER ||
2246 txstat & XL_TXSTATUS_RECLAIM) {
2247 if_printf(ifp, "transmission error: %x\n", txstat);
2248 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2250 if (sc->xl_type == XL_TYPE_905B) {
2251 if (sc->xl_cdata.xl_tx_cnt) {
2254 i = sc->xl_cdata.xl_tx_cons;
2255 c = &sc->xl_cdata.xl_tx_chain[i];
2256 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2258 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2261 if (sc->xl_cdata.xl_tx_head != NULL)
2262 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2263 sc->xl_cdata.xl_tx_head->xl_phys);
2266 * Remember to set this for the
2267 * first generation 3c90X chips.
2269 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2270 if (txstat & XL_TXSTATUS_UNDERRUN &&
2271 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2272 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2273 if_printf(ifp, "tx underrun, increasing tx start"
2274 " threshold to %d bytes\n",
2277 CSR_WRITE_2(sc, XL_COMMAND,
2278 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2279 if (sc->xl_type == XL_TYPE_905B) {
2280 CSR_WRITE_2(sc, XL_COMMAND,
2281 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2283 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2284 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2286 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2287 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2290 * Write an arbitrary byte to the TX_STATUS register
2291 * to clear this interrupt/error and advance to the next.
2293 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2303 struct xl_softc *sc;
2308 ifp = &sc->arpcom.ac_if;
2310 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) {
2312 CSR_WRITE_2(sc, XL_COMMAND,
2313 XL_CMD_INTR_ACK|(status & XL_INTRS));
2315 if (status & XL_STAT_UP_COMPLETE) {
2318 curpkts = ifp->if_ipackets;
2320 if (curpkts == ifp->if_ipackets) {
2321 while (xl_rx_resync(sc))
2326 if (status & XL_STAT_DOWN_COMPLETE) {
2327 if (sc->xl_type == XL_TYPE_905B)
2333 if (status & XL_STAT_TX_COMPLETE) {
2338 if (status & XL_STAT_ADFAIL) {
2343 if (status & XL_STAT_STATSOFLOW) {
2344 sc->xl_stats_no_timeout = 1;
2345 xl_stats_update(sc);
2346 sc->xl_stats_no_timeout = 0;
2350 if (!ifq_is_empty(&ifp->if_snd))
2351 (*ifp->if_start)(ifp);
2357 xl_stats_update(xsc)
2360 struct xl_softc *sc;
2362 struct xl_stats xl_stats;
2365 struct mii_data *mii = NULL;
2367 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2370 ifp = &sc->arpcom.ac_if;
2371 if (sc->xl_miibus != NULL)
2372 mii = device_get_softc(sc->xl_miibus);
2374 p = (u_int8_t *)&xl_stats;
2376 /* Read all the stats registers. */
2379 for (i = 0; i < 16; i++)
2380 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2382 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2384 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2385 xl_stats.xl_tx_single_collision +
2386 xl_stats.xl_tx_late_collision;
2389 * Boomerang and cyclone chips have an extra stats counter
2390 * in window 4 (BadSSD). We have to read this too in order
2391 * to clear out all the stats registers and avoid a statsoflow
2395 CSR_READ_1(sc, XL_W4_BADSSD);
2397 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2402 if (!sc->xl_stats_no_timeout)
2403 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2409 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2410 * pointers to the fragment pointers.
2413 xl_encap(sc, c, m_head)
2414 struct xl_softc *sc;
2416 struct mbuf *m_head;
2422 ifp = &sc->arpcom.ac_if;
2425 * Start packing the mbufs in this chain into
2426 * the fragment pointers. Stop when we run out
2427 * of fragments or hit the end of the mbuf chain.
2429 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2430 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2432 if (error && error != EFBIG) {
2434 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2439 * Handle special case: we used up all 63 fragments,
2440 * but we have more mbufs left in the chain. Copy the
2441 * data into an mbuf cluster. Note that we don't
2442 * bother clearing the values in the other fragment
2443 * pointers/counters; it wouldn't gain us anything,
2444 * and would waste cycles.
2449 m_new = m_defrag(m_head, MB_DONTWAIT);
2450 if (m_new == NULL) {
2457 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2458 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2461 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2466 if (sc->xl_type == XL_TYPE_905B) {
2467 status = XL_TXSTAT_RND_DEFEAT;
2469 if (m_head->m_pkthdr.csum_flags) {
2470 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2471 status |= XL_TXSTAT_IPCKSUM;
2472 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2473 status |= XL_TXSTAT_TCPCKSUM;
2474 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2475 status |= XL_TXSTAT_UDPCKSUM;
2477 c->xl_ptr->xl_status = htole32(status);
2480 c->xl_mbuf = m_head;
2481 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2486 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2487 * to the mbuf data regions directly in the transmit lists. We also save a
2488 * copy of the pointers since the transmit list fragment pointers are
2489 * physical addresses.
2495 struct xl_softc *sc;
2496 struct mbuf *m_head = NULL;
2497 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2498 struct xl_chain *prev_tx;
2504 * Check for an available queue slot. If there are none,
2507 if (sc->xl_cdata.xl_tx_free == NULL) {
2510 if (sc->xl_cdata.xl_tx_free == NULL) {
2511 ifp->if_flags |= IFF_OACTIVE;
2516 start_tx = sc->xl_cdata.xl_tx_free;
2518 while(sc->xl_cdata.xl_tx_free != NULL) {
2519 m_head = ifq_dequeue(&ifp->if_snd);
2523 /* Pick a descriptor off the free list. */
2525 cur_tx = sc->xl_cdata.xl_tx_free;
2527 /* Pack the data into the descriptor. */
2528 error = xl_encap(sc, cur_tx, m_head);
2534 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2535 cur_tx->xl_next = NULL;
2537 /* Chain it together. */
2539 prev->xl_next = cur_tx;
2540 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2544 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2548 * If there are no packets queued, bail.
2550 if (cur_tx == NULL) {
2555 * Place the request for the upload interrupt
2556 * in the last descriptor in the chain. This way, if
2557 * we're chaining several packets at once, we'll only
2558 * get an interupt once for the whole chain rather than
2559 * once for each packet.
2561 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2563 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2564 BUS_DMASYNC_PREWRITE);
2567 * Queue the packets. If the TX channel is clear, update
2568 * the downlist pointer register.
2570 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2573 if (sc->xl_cdata.xl_tx_head != NULL) {
2574 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2575 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2576 htole32(start_tx->xl_phys);
2577 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2578 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2579 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2580 sc->xl_cdata.xl_tx_tail = cur_tx;
2582 sc->xl_cdata.xl_tx_head = start_tx;
2583 sc->xl_cdata.xl_tx_tail = cur_tx;
2585 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2586 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2588 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2593 * Set a timeout in case the chip goes out to lunch.
2598 * XXX Under certain conditions, usually on slower machines
2599 * where interrupts may be dropped, it's possible for the
2600 * adapter to chew up all the buffers in the receive ring
2601 * and stall, without us being able to do anything about it.
2602 * To guard against this, we need to make a pass over the
2603 * RX queue to make sure there aren't any packets pending.
2604 * Doing it here means we can flush the receive ring at the
2605 * same time the chip is DMAing the transmit descriptors we
2608 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2609 * nature of their chips in all their marketing literature;
2610 * we may as well take advantage of it. :)
2621 struct xl_softc *sc;
2622 struct mbuf *m_head = NULL;
2623 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2624 struct xl_chain *prev_tx;
2629 if (ifp->if_flags & IFF_OACTIVE) {
2633 idx = sc->xl_cdata.xl_tx_prod;
2634 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2636 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2638 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2639 ifp->if_flags |= IFF_OACTIVE;
2643 m_head = ifq_dequeue(&ifp->if_snd);
2648 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2650 /* Pack the data into the descriptor. */
2651 error = xl_encap(sc, cur_tx, m_head);
2657 /* Chain it together. */
2659 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2662 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2664 XL_INC(idx, XL_TX_LIST_CNT);
2665 sc->xl_cdata.xl_tx_cnt++;
2669 * If there are no packets queued, bail.
2671 if (cur_tx == NULL) {
2676 * Place the request for the upload interrupt
2677 * in the last descriptor in the chain. This way, if
2678 * we're chaining several packets at once, we'll only
2679 * get an interupt once for the whole chain rather than
2680 * once for each packet.
2682 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2684 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2685 BUS_DMASYNC_PREWRITE);
2687 /* Start transmission */
2688 sc->xl_cdata.xl_tx_prod = idx;
2689 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2692 * Set a timeout in case the chip goes out to lunch.
2703 struct xl_softc *sc = xsc;
2704 struct ifnet *ifp = &sc->arpcom.ac_if;
2706 u_int16_t rxfilt = 0;
2707 struct mii_data *mii = NULL;
2712 * Cancel pending I/O and free all RX/TX buffers.
2716 if (sc->xl_miibus == NULL) {
2717 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2720 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2724 if (sc->xl_miibus != NULL)
2725 mii = device_get_softc(sc->xl_miibus);
2727 /* Init our MAC address */
2729 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2730 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2731 sc->arpcom.ac_enaddr[i]);
2734 /* Clear the station mask. */
2735 for (i = 0; i < 3; i++)
2736 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2738 /* Reset TX and RX. */
2739 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2741 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2744 /* Init circular RX list. */
2745 error = xl_list_rx_init(sc);
2747 if_printf(ifp, "initialization of the rx ring failed (%d)\n",
2754 /* Init TX descriptors. */
2755 if (sc->xl_type == XL_TYPE_905B)
2756 error = xl_list_tx_init_90xB(sc);
2758 error = xl_list_tx_init(sc);
2760 if_printf(ifp, "initialization of the tx ring failed (%d)\n",
2768 * Set the TX freethresh value.
2769 * Note that this has no effect on 3c905B "cyclone"
2770 * cards but is required for 3c900/3c905 "boomerang"
2771 * cards in order to enable the download engine.
2773 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2775 /* Set the TX start threshold for best performance. */
2776 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2777 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2780 * If this is a 3c905B, also set the tx reclaim threshold.
2781 * This helps cut down on the number of tx reclaim errors
2782 * that could happen on a busy network. The chip multiplies
2783 * the register value by 16 to obtain the actual threshold
2784 * in bytes, so we divide by 16 when setting the value here.
2785 * The existing threshold value can be examined by reading
2786 * the register at offset 9 in window 5.
2788 if (sc->xl_type == XL_TYPE_905B) {
2789 CSR_WRITE_2(sc, XL_COMMAND,
2790 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2793 /* Set RX filter bits. */
2795 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2797 /* Set the individual bit to receive frames for this host only. */
2798 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2800 /* If we want promiscuous mode, set the allframes bit. */
2801 if (ifp->if_flags & IFF_PROMISC) {
2802 rxfilt |= XL_RXFILTER_ALLFRAMES;
2803 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2805 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2810 * Set capture broadcast bit to capture broadcast frames.
2812 if (ifp->if_flags & IFF_BROADCAST) {
2813 rxfilt |= XL_RXFILTER_BROADCAST;
2814 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2816 rxfilt &= ~XL_RXFILTER_BROADCAST;
2817 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2821 * Program the multicast filter, if necessary.
2823 if (sc->xl_type == XL_TYPE_905B)
2824 xl_setmulti_hash(sc);
2829 * Load the address of the RX list. We have to
2830 * stall the upload engine before we can manipulate
2831 * the uplist pointer register, then unstall it when
2832 * we're finished. We also have to wait for the
2833 * stall command to complete before proceeding.
2834 * Note that we have to do this after any RX resets
2835 * have completed since the uplist register is cleared
2838 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2840 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2841 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2845 if (sc->xl_type == XL_TYPE_905B) {
2846 /* Set polling interval */
2847 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2848 /* Load the address of the TX list */
2849 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2851 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2852 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2853 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2858 * If the coax transceiver is on, make sure to enable
2859 * the DC-DC converter.
2862 if (sc->xl_xcvr == XL_XCVR_COAX)
2863 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2865 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2868 * increase packet size to allow reception of 802.1q or ISL packets.
2869 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2870 * control register. For 3c90xB/C chips, use the RX packet size
2874 if (sc->xl_type == XL_TYPE_905B)
2875 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2878 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2879 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2880 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2883 /* Clear out the stats counters. */
2884 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2885 sc->xl_stats_no_timeout = 1;
2886 xl_stats_update(sc);
2887 sc->xl_stats_no_timeout = 0;
2889 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2893 * Enable interrupts.
2895 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2896 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2897 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2898 if (sc->xl_flags & XL_FLAG_FUNCREG)
2899 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2901 /* Set the RX early threshold */
2902 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2903 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2905 /* Enable receiver and transmitter. */
2906 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2908 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2914 /* Select window 7 for normal operations. */
2917 ifp->if_flags |= IFF_RUNNING;
2918 ifp->if_flags &= ~IFF_OACTIVE;
2920 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2926 * Set media options.
2932 struct xl_softc *sc;
2933 struct ifmedia *ifm = NULL;
2934 struct mii_data *mii = NULL;
2937 if (sc->xl_miibus != NULL)
2938 mii = device_get_softc(sc->xl_miibus);
2942 ifm = &mii->mii_media;
2944 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2949 xl_setmode(sc, ifm->ifm_media);
2956 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
2957 || sc->xl_media & XL_MEDIAOPT_BT4) {
2960 xl_setmode(sc, ifm->ifm_media);
2967 * Report current media status.
2970 xl_ifmedia_sts(ifp, ifmr)
2972 struct ifmediareq *ifmr;
2974 struct xl_softc *sc;
2976 struct mii_data *mii = NULL;
2979 if (sc->xl_miibus != NULL)
2980 mii = device_get_softc(sc->xl_miibus);
2983 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2984 icfg >>= XL_ICFG_CONNECTOR_BITS;
2986 ifmr->ifm_active = IFM_ETHER;
2990 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2991 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2992 ifmr->ifm_active |= IFM_FDX;
2994 ifmr->ifm_active |= IFM_HDX;
2997 if (sc->xl_type == XL_TYPE_905B &&
2998 sc->xl_media == XL_MEDIAOPT_10FL) {
2999 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3000 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3001 ifmr->ifm_active |= IFM_FDX;
3003 ifmr->ifm_active |= IFM_HDX;
3005 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3008 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3011 * XXX MII and BTX/AUTO should be separate cases.
3014 case XL_XCVR_100BTX:
3019 ifmr->ifm_active = mii->mii_media_active;
3020 ifmr->ifm_status = mii->mii_media_status;
3023 case XL_XCVR_100BFX:
3024 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3027 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3035 xl_ioctl(ifp, command, data, cr)
3041 struct xl_softc *sc = ifp->if_softc;
3042 struct ifreq *ifr = (struct ifreq *) data;
3044 struct mii_data *mii = NULL;
3052 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3053 if (ifp->if_flags & IFF_UP) {
3054 if (ifp->if_flags & IFF_RUNNING &&
3055 ifp->if_flags & IFF_PROMISC &&
3056 !(sc->xl_if_flags & IFF_PROMISC)) {
3057 rxfilt |= XL_RXFILTER_ALLFRAMES;
3058 CSR_WRITE_2(sc, XL_COMMAND,
3059 XL_CMD_RX_SET_FILT|rxfilt);
3061 } else if (ifp->if_flags & IFF_RUNNING &&
3062 !(ifp->if_flags & IFF_PROMISC) &&
3063 sc->xl_if_flags & IFF_PROMISC) {
3064 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3065 CSR_WRITE_2(sc, XL_COMMAND,
3066 XL_CMD_RX_SET_FILT|rxfilt);
3071 if (ifp->if_flags & IFF_RUNNING)
3074 sc->xl_if_flags = ifp->if_flags;
3079 if (sc->xl_type == XL_TYPE_905B)
3080 xl_setmulti_hash(sc);
3087 if (sc->xl_miibus != NULL)
3088 mii = device_get_softc(sc->xl_miibus);
3090 error = ifmedia_ioctl(ifp, ifr,
3091 &sc->ifmedia, command);
3093 error = ifmedia_ioctl(ifp, ifr,
3094 &mii->mii_media, command);
3097 ifp->if_capenable = ifr->ifr_reqcap;
3098 if (ifp->if_capenable & IFCAP_TXCSUM)
3099 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3101 ifp->if_hwassist = 0;
3104 error = ether_ioctl(ifp, command, data);
3117 struct xl_softc *sc;
3118 u_int16_t status = 0;
3124 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3125 if_printf(ifp, "watchdog timeout\n");
3127 if (status & XL_MEDIASTAT_CARRIER)
3128 if_printf(ifp, "no carrier - transceiver cable problem?\n");
3135 if (!ifq_is_empty(&ifp->if_snd))
3136 (*ifp->if_start)(ifp);
3140 * Stop the adapter and free any mbufs allocated to the
3145 struct xl_softc *sc;
3150 ifp = &sc->arpcom.ac_if;
3153 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3154 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3155 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3156 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3158 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3159 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3163 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3169 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3170 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3171 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3172 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3174 /* Stop the stats updater. */
3175 callout_stop(&sc->xl_stat_timer);
3178 * Free data in the RX lists.
3180 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3181 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3182 bus_dmamap_unload(sc->xl_mtag,
3183 sc->xl_cdata.xl_rx_chain[i].xl_map);
3184 bus_dmamap_destroy(sc->xl_mtag,
3185 sc->xl_cdata.xl_rx_chain[i].xl_map);
3186 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3187 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3190 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3192 * Free the TX list buffers.
3194 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3195 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3196 bus_dmamap_unload(sc->xl_mtag,
3197 sc->xl_cdata.xl_tx_chain[i].xl_map);
3198 bus_dmamap_destroy(sc->xl_mtag,
3199 sc->xl_cdata.xl_tx_chain[i].xl_map);
3200 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3201 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3204 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3206 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3212 * Stop all chip I/O so that the kernel's probe routines don't
3213 * get confused by errant DMAs when rebooting.
3219 struct xl_softc *sc;
3221 sc = device_get_softc(dev);
3233 struct xl_softc *sc = device_get_softc(dev);
3248 struct xl_softc *sc;
3251 sc = device_get_softc(dev);
3252 ifp = &sc->arpcom.ac_if;
3257 if (ifp->if_flags & IFF_UP)