sys/dev/drm/radeon/rs400.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "rs400d.h"
  32
  33 /* This files gather functions specifics to : rs400,rs480 */
  34 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  35
  36 void rs400_gart_adjust_size(struct radeon_device *rdev)
  37 {
  38         /* Check gart size */
  39         switch (rdev->mc.gtt_size/(1024*1024)) {
  40         case 32:
  41         case 64:
  42         case 128:
  43         case 256:
  44         case 512:
  45         case 1024:
  46         case 2048:
  47                 break;
  48         default:
  49                 DRM_ERROR("Unable to use IGP GART size %uM\n",
  50                           (unsigned)(rdev->mc.gtt_size >> 20));
  51                 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
  52                 DRM_ERROR("Forcing to 32M GART size\n");
  53                 rdev->mc.gtt_size = 32 * 1024 * 1024;
  54                 return;
  55         }
  56 }
  57
  58 void rs400_gart_tlb_flush(struct radeon_device *rdev)
  59 {
  60         uint32_t tmp;
  61         unsigned int timeout = rdev->usec_timeout;
  62
  63         WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
  64         do {
  65                 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
  66                 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
  67                         break;
  68                 DRM_UDELAY(1);
  69                 timeout--;
  70         } while (timeout > 0);
  71         WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
  72 }
  73
  74 int rs400_gart_init(struct radeon_device *rdev)
  75 {
  76         int r;
  77
  78         if (rdev->gart.ptr) {
  79                 WARN(1, "RS400 GART already initialized\n");
  80                 return 0;
  81         }
  82         /* Check gart size */
  83         switch(rdev->mc.gtt_size / (1024 * 1024)) {
  84         case 32:
  85         case 64:
  86         case 128:
  87         case 256:
  88         case 512:
  89         case 1024:
  90         case 2048:
  91                 break;
  92         default:
  93                 return -EINVAL;
  94         }
  95         /* Initialize common gart structure */
  96         r = radeon_gart_init(rdev);
  97         if (r)
  98                 return r;
  99         if (rs400_debugfs_pcie_gart_info_init(rdev))
 100                 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
 101         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 102         return radeon_gart_table_ram_alloc(rdev);
 103 }
 104
 105 int rs400_gart_enable(struct radeon_device *rdev)
 106 {
 107         uint32_t size_reg;
 108         uint32_t tmp;
 109
 110         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 111         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
 112         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
 113         /* Check gart size */
 114         switch(rdev->mc.gtt_size / (1024 * 1024)) {
 115         case 32:
 116                 size_reg = RS480_VA_SIZE_32MB;
 117                 break;
 118         case 64:
 119                 size_reg = RS480_VA_SIZE_64MB;
 120                 break;
 121         case 128:
 122                 size_reg = RS480_VA_SIZE_128MB;
 123                 break;
 124         case 256:
 125                 size_reg = RS480_VA_SIZE_256MB;
 126                 break;
 127         case 512:
 128                 size_reg = RS480_VA_SIZE_512MB;
 129                 break;
 130         case 1024:
 131                 size_reg = RS480_VA_SIZE_1GB;
 132                 break;
 133         case 2048:
 134                 size_reg = RS480_VA_SIZE_2GB;
 135                 break;
 136         default:
 137                 return -EINVAL;
 138         }
 139         /* It should be fine to program it to max value */
 140         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
 141                 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
 142                 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
 143         } else {
 144                 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
 145                 WREG32(RS480_AGP_BASE_2, 0);
 146         }
 147         tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
 148         tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
 149         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
 150                 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
 151                 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 152                 WREG32(RADEON_BUS_CNTL, tmp);
 153         } else {
 154                 WREG32(RADEON_MC_AGP_LOCATION, tmp);
 155                 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 156                 WREG32(RADEON_BUS_CNTL, tmp);
 157         }
 158         /* Table should be in 32bits address space so ignore bits above. */
 159         tmp = (u32)rdev->gart.table_addr & 0xfffff000;
 160         tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
 161
 162         WREG32_MC(RS480_GART_BASE, tmp);
 163         /* TODO: more tweaking here */
 164         WREG32_MC(RS480_GART_FEATURE_ID,
 165                   (RS480_TLB_ENABLE |
 166                    RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
 167         /* Disable snooping */
 168         WREG32_MC(RS480_AGP_MODE_CNTL,
 169                   (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
 170         /* Disable AGP mode */
 171         /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
 172          * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
 173         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
 174                 tmp = RREG32_MC(RS480_MC_MISC_CNTL);
 175                 tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
 176                 WREG32_MC(RS480_MC_MISC_CNTL, tmp);
 177         } else {
 178                 tmp = RREG32_MC(RS480_MC_MISC_CNTL);
 179                 tmp |= RS480_GART_INDEX_REG_EN;
 180                 WREG32_MC(RS480_MC_MISC_CNTL, tmp);
 181         }
 182         /* Enable gart */
 183         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
 184         rs400_gart_tlb_flush(rdev);
 185         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 186                  (unsigned)(rdev->mc.gtt_size >> 20),
 187                  (unsigned long long)rdev->gart.table_addr);
 188         rdev->gart.ready = true;
 189         return 0;
 190 }
 191
 192 void rs400_gart_disable(struct radeon_device *rdev)
 193 {
 194         uint32_t tmp;
 195
 196         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 197         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
 198         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
 199         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 200 }
 201
 202 void rs400_gart_fini(struct radeon_device *rdev)
 203 {
 204         radeon_gart_fini(rdev);
 205         rs400_gart_disable(rdev);
 206         radeon_gart_table_ram_free(rdev);
 207 }
 208
 209 #define RS400_PTE_UNSNOOPED (1 << 0)
 210 #define RS400_PTE_WRITEABLE (1 << 2)
 211 #define RS400_PTE_READABLE  (1 << 3)
 212
 213 uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags)
 214 {
 215         uint32_t entry;
 216
 217         entry = (lower_32_bits(addr) & LINUX_PAGE_MASK) |
 218                 ((upper_32_bits(addr) & 0xff) << 4);
 219         if (flags & RADEON_GART_PAGE_READ)
 220                 entry |= RS400_PTE_READABLE;
 221         if (flags & RADEON_GART_PAGE_WRITE)
 222                 entry |= RS400_PTE_WRITEABLE;
 223         if (!(flags & RADEON_GART_PAGE_SNOOP))
 224                 entry |= RS400_PTE_UNSNOOPED;
 225         return entry;
 226 }
 227
 228 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
 229                          uint64_t entry)
 230 {
 231         u32 *gtt = rdev->gart.ptr;
 232         gtt[i] = cpu_to_le32(lower_32_bits(entry));
 233 }
 234
 235 int rs400_mc_wait_for_idle(struct radeon_device *rdev)
 236 {
 237         unsigned i;
 238         uint32_t tmp;
 239
 240         for (i = 0; i < rdev->usec_timeout; i++) {
 241                 /* read MC_STATUS */
 242                 tmp = RREG32(RADEON_MC_STATUS);
 243                 if (tmp & RADEON_MC_IDLE) {
 244                         return 0;
 245                 }
 246                 DRM_UDELAY(1);
 247         }
 248         return -1;
 249 }
 250
 251 static void rs400_gpu_init(struct radeon_device *rdev)
 252 {
 253         /* FIXME: is this correct ? */
 254         r420_pipes_init(rdev);
 255         if (rs400_mc_wait_for_idle(rdev)) {
 256                 pr_warn("rs400: Failed to wait MC idle while programming pipes. Bad things might happen. %08x\n",
 257                         RREG32(RADEON_MC_STATUS));
 258         }
 259 }
 260
 261 static void rs400_mc_init(struct radeon_device *rdev)
 262 {
 263         u64 base;
 264
 265         rs400_gart_adjust_size(rdev);
 266         rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
 267         /* DDR for all card after R300 & IGP */
 268         rdev->mc.vram_is_ddr = true;
 269         rdev->mc.vram_width = 128;
 270         r100_vram_init_sizes(rdev);
 271         base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
 272         radeon_vram_location(rdev, &rdev->mc, base);
 273         rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
 274         radeon_gtt_location(rdev, &rdev->mc);
 275         radeon_update_bandwidth_info(rdev);
 276 }
 277
 278 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 279 {
 280         uint32_t r;
 281
 282         lockmgr(&rdev->mc_idx_lock, LK_EXCLUSIVE);
 283         WREG32(RS480_NB_MC_INDEX, reg & 0xff);
 284         r = RREG32(RS480_NB_MC_DATA);
 285         WREG32(RS480_NB_MC_INDEX, 0xff);
 286         lockmgr(&rdev->mc_idx_lock, LK_RELEASE);
 287         return r;
 288 }
 289
 290 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 291 {
 292         lockmgr(&rdev->mc_idx_lock, LK_EXCLUSIVE);
 293         WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
 294         WREG32(RS480_NB_MC_DATA, (v));
 295         WREG32(RS480_NB_MC_INDEX, 0xff);
 296         lockmgr(&rdev->mc_idx_lock, LK_RELEASE);
 297 }
 298
 299 #if defined(CONFIG_DEBUG_FS)
 300 static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
 301 {
 302         struct drm_info_node *node = (struct drm_info_node *) m->private;
 303         struct drm_device *dev = node->minor->dev;
 304         struct radeon_device *rdev = dev->dev_private;
 305         uint32_t tmp;
 306
 307         tmp = RREG32(RADEON_HOST_PATH_CNTL);
 308         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
 309         tmp = RREG32(RADEON_BUS_CNTL);
 310         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
 311         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 312         seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
 313         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
 314                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
 315                 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
 316                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
 317                 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
 318                 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
 319                 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
 320                 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
 321                 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
 322                 tmp = RREG32(RS690_HDP_FB_LOCATION);
 323                 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
 324         } else {
 325                 tmp = RREG32(RADEON_AGP_BASE);
 326                 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
 327                 tmp = RREG32(RS480_AGP_BASE_2);
 328                 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
 329                 tmp = RREG32(RADEON_MC_AGP_LOCATION);
 330                 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
 331         }
 332         tmp = RREG32_MC(RS480_GART_BASE);
 333         seq_printf(m, "GART_BASE 0x%08x\n", tmp);
 334         tmp = RREG32_MC(RS480_GART_FEATURE_ID);
 335         seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
 336         tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
 337         seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
 338         tmp = RREG32_MC(RS480_MC_MISC_CNTL);
 339         seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
 340         tmp = RREG32_MC(0x5F);
 341         seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
 342         tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
 343         seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
 344         tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
 345         seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
 346         tmp = RREG32_MC(0x3B);
 347         seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
 348         tmp = RREG32_MC(0x3C);
 349         seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
 350         tmp = RREG32_MC(0x30);
 351         seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
 352         tmp = RREG32_MC(0x31);
 353         seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
 354         tmp = RREG32_MC(0x32);
 355         seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
 356         tmp = RREG32_MC(0x33);
 357         seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
 358         tmp = RREG32_MC(0x34);
 359         seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
 360         tmp = RREG32_MC(0x35);
 361         seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
 362         tmp = RREG32_MC(0x36);
 363         seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
 364         tmp = RREG32_MC(0x37);
 365         seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
 366         return 0;
 367 }
 368
 369 static struct drm_info_list rs400_gart_info_list[] = {
 370         {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
 371 };
 372 #endif
 373
 374 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 375 {
 376 #if defined(CONFIG_DEBUG_FS)
 377         return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
 378 #else
 379         return 0;
 380 #endif
 381 }
 382
 383 static void rs400_mc_program(struct radeon_device *rdev)
 384 {
 385         struct r100_mc_save save;
 386
 387         /* Stops all mc clients */
 388         r100_mc_stop(rdev, &save);
 389
 390         /* Wait for mc idle */
 391         if (rs400_mc_wait_for_idle(rdev))
 392                 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
 393         WREG32(R_000148_MC_FB_LOCATION,
 394                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
 395                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
 396
 397         r100_mc_resume(rdev, &save);
 398 }
 399
 400 static int rs400_startup(struct radeon_device *rdev)
 401 {
 402         int r;
 403
 404         r100_set_common_regs(rdev);
 405
 406         rs400_mc_program(rdev);
 407         /* Resume clock */
 408         r300_clock_startup(rdev);
 409         /* Initialize GPU configuration (# pipes, ...) */
 410         rs400_gpu_init(rdev);
 411         r100_enable_bm(rdev);
 412         /* Initialize GART (initialize after TTM so we can allocate
 413          * memory through TTM but finalize after TTM) */
 414         r = rs400_gart_enable(rdev);
 415         if (r)
 416                 return r;
 417
 418         /* allocate wb buffer */
 419         r = radeon_wb_init(rdev);
 420         if (r)
 421                 return r;
 422
 423         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 424         if (r) {
 425                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 426                 return r;
 427         }
 428
 429         /* Enable IRQ */
 430         if (!rdev->irq.installed) {
 431                 r = radeon_irq_kms_init(rdev);
 432                 if (r)
 433                         return r;
 434         }
 435
 436         r100_irq_set(rdev);
 437         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 438         /* 1M ring buffer */
 439         r = r100_cp_init(rdev, 1024 * 1024);
 440         if (r) {
 441                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
 442                 return r;
 443         }
 444
 445         r = radeon_ib_pool_init(rdev);
 446         if (r) {
 447                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 448                 return r;
 449         }
 450
 451         return 0;
 452 }
 453
 454 int rs400_resume(struct radeon_device *rdev)
 455 {
 456         int r;
 457
 458         /* Make sur GART are not working */
 459         rs400_gart_disable(rdev);
 460         /* Resume clock before doing reset */
 461         r300_clock_startup(rdev);
 462         /* setup MC before calling post tables */
 463         rs400_mc_program(rdev);
 464         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 465         if (radeon_asic_reset(rdev)) {
 466                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 467                         RREG32(R_000E40_RBBM_STATUS),
 468                         RREG32(R_0007C0_CP_STAT));
 469         }
 470         /* post */
 471         radeon_combios_asic_init(rdev->ddev);
 472         /* Resume clock after posting */
 473         r300_clock_startup(rdev);
 474         /* Initialize surface registers */
 475         radeon_surface_init(rdev);
 476
 477         rdev->accel_working = true;
 478         r = rs400_startup(rdev);
 479         if (r) {
 480                 rdev->accel_working = false;
 481         }
 482         return r;
 483 }
 484
 485 int rs400_suspend(struct radeon_device *rdev)
 486 {
 487         radeon_pm_suspend(rdev);
 488         r100_cp_disable(rdev);
 489         radeon_wb_disable(rdev);
 490         r100_irq_disable(rdev);
 491         rs400_gart_disable(rdev);
 492         return 0;
 493 }
 494
 495 void rs400_fini(struct radeon_device *rdev)
 496 {
 497         radeon_pm_fini(rdev);
 498         r100_cp_fini(rdev);
 499         radeon_wb_fini(rdev);
 500         radeon_ib_pool_fini(rdev);
 501         radeon_gem_fini(rdev);
 502         rs400_gart_fini(rdev);
 503         radeon_irq_kms_fini(rdev);
 504         radeon_fence_driver_fini(rdev);
 505         radeon_bo_fini(rdev);
 506         radeon_atombios_fini(rdev);
 507         kfree(rdev->bios);
 508         rdev->bios = NULL;
 509 }
 510
 511 int rs400_init(struct radeon_device *rdev)
 512 {
 513         int r;
 514
 515         /* Disable VGA */
 516         r100_vga_render_disable(rdev);
 517         /* Initialize scratch registers */
 518         radeon_scratch_init(rdev);
 519         /* Initialize surface registers */
 520         radeon_surface_init(rdev);
 521         /* TODO: disable VGA need to use VGA request */
 522         /* restore some register to sane defaults */
 523         r100_restore_sanity(rdev);
 524         /* BIOS*/
 525         if (!radeon_get_bios(rdev)) {
 526                 if (ASIC_IS_AVIVO(rdev))
 527                         return -EINVAL;
 528         }
 529         if (rdev->is_atom_bios) {
 530                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
 531                 return -EINVAL;
 532         } else {
 533                 r = radeon_combios_init(rdev);
 534                 if (r)
 535                         return r;
 536         }
 537         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 538         if (radeon_asic_reset(rdev)) {
 539                 dev_warn(rdev->dev,
 540                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 541                         RREG32(R_000E40_RBBM_STATUS),
 542                         RREG32(R_0007C0_CP_STAT));
 543         }
 544         /* check if cards are posted or not */
 545         if (radeon_boot_test_post_card(rdev) == false)
 546                 return -EINVAL;
 547
 548         /* Initialize clocks */
 549         radeon_get_clock_info(rdev->ddev);
 550         /* initialize memory controller */
 551         rs400_mc_init(rdev);
 552         /* Fence driver */
 553         r = radeon_fence_driver_init(rdev);
 554         if (r)
 555                 return r;
 556         /* Memory manager */
 557         r = radeon_bo_init(rdev);
 558         if (r)
 559                 return r;
 560         r = rs400_gart_init(rdev);
 561         if (r)
 562                 return r;
 563         r300_set_reg_safe(rdev);
 564
 565         /* Initialize power management */
 566         radeon_pm_init(rdev);
 567
 568         rdev->accel_working = true;
 569         r = rs400_startup(rdev);
 570         if (r) {
 571                 /* Somethings want wront with the accel init stop accel */
 572                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 573                 r100_cp_fini(rdev);
 574                 radeon_wb_fini(rdev);
 575                 radeon_ib_pool_fini(rdev);
 576                 rs400_gart_fini(rdev);
 577                 radeon_irq_kms_fini(rdev);
 578                 rdev->accel_working = false;
 579         }
 580         return 0;
 581 }