sys/dev/netif/sr/if_sr.c

   1 /*
   2  * Copyright (c) 1996 - 2001 John Hay.
   3  * Copyright (c) 1996 SDL Communications, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of the author nor the names of any co-contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/sr/if_sr.c,v 1.48.2.1 2002/06/17 15:10:58 jhay Exp $
  31  * $DragonFly: src/sys/dev/netif/sr/if_sr.c,v 1.8 2004/03/23 22:19:03 hsu Exp $
  32  */
  33
  34 /*
  35  * Programming assumptions and other issues.
  36  *
  37  * Only a 16K window will be used.
  38  *
  39  * The descriptors of a DMA channel will fit in a 16K memory window.
  40  *
  41  * The buffers of a transmit DMA channel will fit in a 16K memory window.
  42  *
  43  * When interface is going up, handshaking is set and it is only cleared
  44  * when the interface is down'ed.
  45  *
  46  * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
  47  * internal/external clock, etc.....
  48  *
  49  */
  50
  51 #include "opt_netgraph.h"
  52 #ifdef NETGRAPH
  53 #include "if_sr.h"
  54 #endif  /* NETGRAPH */
  55
  56 #include <sys/param.h>
  57 #include <sys/systm.h>
  58 #include <sys/kernel.h>
  59 #include <sys/malloc.h>
  60 #include <sys/mbuf.h>
  61 #include <sys/sockio.h>
  62 #include <sys/socket.h>
  63 #include <sys/bus.h>
  64 #include <machine/bus.h>
  65 #include <machine/resource.h>
  66 #include <machine/bus_pio.h>
  67 #include <machine/bus_memio.h>
  68 #include <sys/rman.h>
  69
  70 #include <net/if.h>
  71 #ifdef NETGRAPH
  72 #include <sys/syslog.h>
  73 #else /* NETGRAPH */
  74 #include <net/sppp/if_sppp.h>
  75
  76 #include <net/bpf.h>
  77 #endif  /* NETGRAPH */
  78
  79 #include <machine/md_var.h>
  80
  81 #include "../ic_layer/hd64570.h"
  82 #include "if_srregs.h"
  83
  84 #ifdef NETGRAPH
  85 #include <netgraph/ng_message.h>
  86 #include <netgraph/netgraph.h>
  87 #endif /* NETGRAPH */
  88 /* #define USE_MODEMCK */
  89
  90 #ifndef BUGGY
  91 #define BUGGY           0
  92 #endif
  93
  94 #ifndef NETGRAPH
  95 #define PPP_HEADER_LEN  4
  96 #endif /* NETGRAPH */
  97
  98 static int      next_sc_unit = 0;
  99 #ifndef NETGRAPH
 100 #ifdef USE_MODEMCK
 101 static int      sr_watcher = 0;
 102 #endif
 103 #endif /* NETGRAPH */
 104
 105 /*
 106  * Define the software interface for the card... There is one for
 107  * every channel (port).
 108  */
 109 struct sr_softc {
 110 #ifndef NETGRAPH
 111         struct  sppp ifsppp;    /* PPP service w/in system */
 112 #endif /* NETGRAPH */
 113         struct  sr_hardc *hc;   /* card-level information */
 114
 115         int     unit;           /* With regard to all sr devices */
 116         int     subunit;        /* With regard to this card */
 117
 118         struct  buf_block {
 119                 u_int   txdesc; /* DPRAM offset */
 120                 u_int   txstart;/* DPRAM offset */
 121                 u_int   txend;  /* DPRAM offset */
 122                 u_int   txtail; /* # of 1st free gran */
 123                 u_int   txmax;  /* # of free grans */
 124                 u_int   txeda;  /* err descr addr */
 125         } block[SR_TX_BLOCKS];
 126
 127         char    xmit_busy;      /* Transmitter is busy */
 128         char    txb_inuse;      /* # of tx grans in use */
 129         u_int   txb_new;        /* ndx to new buffer */
 130         u_int   txb_next_tx;    /* ndx to next gran rdy tx */
 131
 132         u_int   rxdesc;         /* DPRAM offset */
 133         u_int   rxstart;        /* DPRAM offset */
 134         u_int   rxend;          /* DPRAM offset */
 135         u_int   rxhind;         /* ndx to the hd of rx bufrs */
 136         u_int   rxmax;          /* # of avail grans */
 137
 138         u_int   clk_cfg;        /* Clock configuration */
 139
 140         int     scachan;        /* channel # on card */
 141 #ifdef NETGRAPH
 142         int     running;        /* something is attached so we are running */
 143         int     dcd;            /* do we have dcd? */
 144         /* ---netgraph bits --- */
 145         char            nodename[NG_NODELEN + 1]; /* store our node name */
 146         int             datahooks;      /* number of data hooks attached */
 147         node_p          node;           /* netgraph node */
 148         hook_p          hook;           /* data hook */
 149         hook_p          debug_hook;
 150         struct ifqueue  xmitq_hipri;    /* hi-priority transmit queue */
 151         struct ifqueue  xmitq;          /* transmit queue */
 152         int             flags;          /* state */
 153 #define SCF_RUNNING     0x01            /* board is active */
 154 #define SCF_OACTIVE     0x02            /* output is active */
 155         int             out_dog;        /* watchdog cycles output count-down */
 156 #if defined(__DragonFly__) || ( __FreeBSD__ >= 3 )
 157         struct callout_handle handle;   /* timeout(9) handle */
 158 #endif
 159         u_long          inbytes, outbytes;      /* stats */
 160         u_long          lastinbytes, lastoutbytes; /* a second ago */
 161         u_long          inrate, outrate;        /* highest rate seen */
 162         u_long          inlast;         /* last input N secs ago */
 163         u_long          out_deficit;    /* output since last input */
 164         u_long          oerrors, ierrors[6];
 165         u_long          opackets, ipackets;
 166 #endif /* NETGRAPH */
 167 };
 168
 169 #ifdef NETGRAPH
 170 #define DOG_HOLDOFF     6       /* dog holds off for 6 secs */
 171 #define QUITE_A_WHILE   300     /* 5 MINUTES */
 172 #define LOTS_OF_PACKETS 100
 173 #endif /* NETGRAPH */
 174
 175 /*
 176  * Baud Rate table for Sync Mode.
 177  * Each entry consists of 3 elements:
 178  * Baud Rate (x100) , TMC, BR
 179  *
 180  * Baud Rate = FCLK / TMC / 2^BR
 181  * Baud table for Crystal freq. of 9.8304 Mhz
 182  */
 183 #ifdef N2_TEST_SPEED
 184 struct rate_line {
 185         int     target;         /* target rate/100 */
 186         int     tmc_reg;        /* TMC register value */
 187         int     br_reg;         /* BR (BaudRateClk) selector */
 188 } n2_rates[] = {
 189         /* Baudx100     TMC             BR */
 190         { 3,            128,            8 },
 191         { 6,            128,            7 },
 192         { 12,           128,            6 },
 193         { 24,           128,            5 },
 194         { 48,           128,            4 },
 195         { 96,           128,            3 },
 196         { 192,          128,            2 },
 197         { 384,          128,            1 },
 198         { 560,          88,             1 },
 199         { 640,          77,             1 },
 200         { 1280,         38,             1 },
 201         { 2560,         19,             1 },
 202         { 5120,         10,             1 },
 203         { 10000,        5,              1 },
 204         { 15000,        3,              1 },
 205         { 25000,        2,              1 },
 206         { 50000,        1,              1 },
 207         { 0,            0,              0 }
 208 };
 209
 210 int     sr_test_speed[] = {
 211         N2_TEST_SPEED,
 212         N2_TEST_SPEED
 213 };
 214
 215 int     etc0vals[] = {
 216         SR_MCR_ETC0,            /* ISA channel 0 */
 217         SR_MCR_ETC1,            /* ISA channel 1 */
 218         SR_FECR_ETC0,           /* PCI channel 0 */
 219         SR_FECR_ETC1            /* PCI channel 1 */
 220 };
 221 #endif
 222
 223 devclass_t sr_devclass;
 224 #ifndef NETGRAPH
 225 DECLARE_DUMMY_MODULE(if_sr);
 226 MODULE_DEPEND(if_sr, sppp, 1, 1, 1);
 227 #else
 228 MODULE_DEPEND(ng_sync_sr, netgraph, 1, 1, 1);
 229 #endif
 230
 231 static void     srintr(void *arg);
 232 static void     sr_xmit(struct sr_softc *sc);
 233 #ifndef NETGRAPH
 234 static void     srstart(struct ifnet *ifp);
 235 static int      srioctl(struct ifnet *ifp, u_long cmd, caddr_t data,
 236                         struct ucred *);
 237 static void     srwatchdog(struct ifnet *ifp);
 238 #else
 239 static void     srstart(struct sr_softc *sc);
 240 static void     srwatchdog(struct sr_softc *sc);
 241 #endif /* NETGRAPH */
 242 static int      sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat);
 243 static void     sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len);
 244 static void     sr_eat_packet(struct sr_softc *sc, int single);
 245 static void     sr_get_packets(struct sr_softc *sc);
 246
 247 static void     sr_up(struct sr_softc *sc);
 248 static void     sr_down(struct sr_softc *sc);
 249 static void     src_init(struct sr_hardc *hc);
 250 static void     sr_init_sca(struct sr_hardc *hc);
 251 static void     sr_init_msci(struct sr_softc *sc);
 252 static void     sr_init_rx_dmac(struct sr_softc *sc);
 253 static void     sr_init_tx_dmac(struct sr_softc *sc);
 254 static void     sr_dmac_intr(struct sr_hardc *hc, u_char isr);
 255 static void     sr_msci_intr(struct sr_hardc *hc, u_char isr);
 256 static void     sr_timer_intr(struct sr_hardc *hc, u_char isr);
 257 #ifndef NETGRAPH
 258 #ifdef USE_MODEMCK
 259 static void     sr_modemck(void *x);
 260 #endif
 261 #else
 262 static void     sr_modemck(struct sr_softc *x);
 263 #endif /* NETGRAPH */
 264
 265 #ifdef NETGRAPH
 266 static  void    ngsr_watchdog_frame(void * arg);
 267 static  void    ngsr_init(void* ignored);
 268
 269 static ng_constructor_t ngsr_constructor;
 270 static ng_rcvmsg_t      ngsr_rcvmsg;
 271 static ng_shutdown_t    ngsr_rmnode;
 272 static ng_newhook_t     ngsr_newhook;
 273 /*static ng_findhook_t  ngsr_findhook; */
 274 static ng_connect_t     ngsr_connect;
 275 static ng_rcvdata_t     ngsr_rcvdata;
 276 static ng_disconnect_t  ngsr_disconnect;
 277
 278 static struct ng_type typestruct = {
 279         NG_VERSION,
 280         NG_SR_NODE_TYPE,
 281         NULL,
 282         ngsr_constructor,
 283         ngsr_rcvmsg,
 284         ngsr_rmnode,
 285         ngsr_newhook,
 286         NULL,
 287         ngsr_connect,
 288         ngsr_rcvdata,
 289         ngsr_rcvdata,
 290         ngsr_disconnect,
 291         NULL
 292 };
 293
 294 static int      ngsr_done_init = 0;
 295 #endif /* NETGRAPH */
 296
 297 /*
 298  * Register the ports on the adapter.
 299  * Fill in the info for each port.
 300 #ifndef NETGRAPH
 301  * Attach each port to sppp and bpf.
 302 #endif
 303  */
 304 int
 305 sr_attach(device_t device)
 306 {
 307         int intf_sw, pndx;
 308         u_int32_t flags;
 309         u_int fecr, *fecrp;
 310         struct sr_hardc *hc;
 311         struct sr_softc *sc;
 312 #ifndef NETGRAPH
 313         struct ifnet *ifp;
 314 #endif /* NETGRAPH */
 315         int unit;               /* index: channel w/in card */
 316
 317         hc = (struct sr_hardc *)device_get_softc(device);
 318         MALLOC(sc, struct sr_softc *,
 319                 hc->numports * sizeof(struct sr_softc),
 320                 M_DEVBUF, M_WAITOK | M_ZERO);
 321         if (sc == NULL)
 322                 goto errexit;
 323         hc->sc = sc;
 324
 325         /*
 326          * Get the TX clock direction and configuration. The default is a
 327          * single external clock which is used by RX and TX.
 328          */
 329         switch(hc->cardtype) {
 330         case SR_CRD_N2:
 331                 flags = device_get_flags(device);
 332 #ifdef N2_TEST_SPEED
 333                 if (sr_test_speed[0] > 0)
 334                         hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
 335                 else
 336 #endif
 337                 if (flags & SR_FLAGS_0_CLK_MSK)
 338                         hc->sc[0].clk_cfg =
 339                             (flags & SR_FLAGS_0_CLK_MSK)
 340                             >> SR_FLAGS_CLK_SHFT;
 341
 342                 if (hc->numports == 2)
 343 #ifdef N2_TEST_SPEED
 344                         if (sr_test_speed[1] > 0)
 345                                 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
 346                         else
 347 #endif
 348                         if (flags & SR_FLAGS_1_CLK_MSK)
 349                                 hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK)
 350                                     >> (SR_FLAGS_CLK_SHFT +
 351                                     SR_FLAGS_CLK_CHAN_SHFT);
 352                 break;
 353         case SR_CRD_N2PCI:
 354                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
 355                 fecr = *fecrp;
 356                 for (pndx = 0; pndx < hc->numports; pndx++, sc++) {
 357                         switch (pndx) {
 358                         case 1:
 359                                 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT;
 360                                 break;
 361                         case 0:
 362                         default:
 363                                 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT;
 364                         }
 365
 366 #ifdef N2_TEST_SPEED
 367                         if (sr_test_speed[pndx] > 0)
 368                                 sc->clk_cfg = SR_FLAGS_INT_CLK;
 369                         else
 370 #endif
 371                                 switch (intf_sw) {
 372                                 default:
 373                                 case SR_FE_ID_RS232:
 374                                 case SR_FE_ID_HSSI:
 375                                 case SR_FE_ID_RS422:
 376                                 case SR_FE_ID_TEST:
 377                                         break;
 378
 379                                 case SR_FE_ID_V35:
 380                                         sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK;
 381                                         break;
 382
 383                                 case SR_FE_ID_X21:
 384                                         sc->clk_cfg = SR_FLAGS_EXT_CLK;
 385                                         break;
 386                                 }
 387                 }
 388                 sc = hc->sc;
 389                 break;
 390         }
 391
 392         /*
 393          * Report Card configuration information before we start configuring
 394          * each channel on the card...
 395          */
 396         printf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n",
 397                hc->cunit, hc->memsize / 1024, hc->mempages,
 398                (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports);
 399
 400         src_init(hc);
 401         sr_init_sca(hc);
 402
 403         if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
 404             INTR_TYPE_NET, srintr, hc, &hc->intr_cookie) != 0)
 405                 goto errexit;
 406
 407         /*
 408          * Now configure each port on the card.
 409          */
 410         for (unit = 0; unit < hc->numports; sc++, unit++) {
 411                 sc->hc = hc;
 412                 sc->subunit = unit;
 413                 sc->unit = next_sc_unit;
 414                 next_sc_unit++;
 415                 sc->scachan = unit % NCHAN;
 416
 417                 sr_init_rx_dmac(sc);
 418                 sr_init_tx_dmac(sc);
 419                 sr_init_msci(sc);
 420
 421                 printf("sr%d: Adapter %d, port %d.\n",
 422                        sc->unit, hc->cunit, sc->subunit);
 423
 424 #ifndef NETGRAPH
 425                 ifp = &sc->ifsppp.pp_if;
 426                 ifp->if_softc = sc;
 427                 if_initname(ifp, "sr", sc->unit);
 428                 ifp->if_mtu = PP_MTU;
 429                 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
 430                 ifp->if_ioctl = srioctl;
 431                 ifp->if_start = srstart;
 432                 ifp->if_watchdog = srwatchdog;
 433
 434                 sc->ifsppp.pp_flags = PP_KEEPALIVE;
 435                 sppp_attach((struct ifnet *)&sc->ifsppp);
 436                 if_attach(ifp);
 437
 438                 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
 439 #else   /* NETGRAPH */
 440                 /*
 441                  * we have found a node, make sure our 'type' is availabe.
 442                  */
 443                 if (ngsr_done_init == 0) ngsr_init(NULL);
 444                 if (ng_make_node_common(&typestruct, &sc->node) != 0)
 445                         goto errexit;
 446                 sc->node->private = sc;
 447                 callout_handle_init(&sc->handle);
 448                 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
 449                 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
 450                 sprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit);
 451                 if (ng_name_node(sc->node, sc->nodename)) {
 452                         ng_rmnode(sc->node);
 453                         ng_unref(sc->node);
 454                         return (0);
 455                 }
 456                 sc->running = 0;
 457 #endif  /* NETGRAPH */
 458         }
 459
 460         if (hc->mempages)
 461                 SRC_SET_OFF(hc->iobase);
 462
 463         return (0);
 464
 465 errexit:
 466         sr_deallocate_resources(device);
 467         return (ENXIO);
 468 }
 469
 470 int
 471 sr_detach(device_t device)
 472 {
 473         device_t parent = device_get_parent(device);
 474         struct sr_hardc *hc = device_get_softc(device);
 475
 476         if (hc->intr_cookie != NULL) {
 477                 if (BUS_TEARDOWN_INTR(parent, device,
 478                         hc->res_irq, hc->intr_cookie) != 0) {
 479                                 printf("intr teardown failed.. continuing\n");
 480                 }
 481                 hc->intr_cookie = NULL;
 482         }
 483
 484         /* XXX Stop the DMA. */
 485
 486         /*
 487          * deallocate any system resources we may have
 488          * allocated on behalf of this driver.
 489          */
 490         FREE(hc->sc, M_DEVBUF);
 491         hc->sc = NULL;
 492         hc->mem_start = NULL;
 493         return (sr_deallocate_resources(device));
 494 }
 495
 496 int
 497 sr_allocate_ioport(device_t device, int rid, u_long size)
 498 {
 499         struct sr_hardc *hc = device_get_softc(device);
 500
 501         hc->rid_ioport = rid;
 502         hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
 503                         &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
 504         if (hc->res_ioport == NULL) {
 505                 goto errexit;
 506         }
 507         return (0);
 508
 509 errexit:
 510         sr_deallocate_resources(device);
 511         return (ENXIO);
 512 }
 513
 514 int
 515 sr_allocate_irq(device_t device, int rid, u_long size)
 516 {
 517         struct sr_hardc *hc = device_get_softc(device);
 518
 519         hc->rid_irq = rid;
 520         hc->res_irq = bus_alloc_resource(device, SYS_RES_IRQ,
 521                         &hc->rid_irq, 0ul, ~0ul, 1, RF_SHAREABLE|RF_ACTIVE);
 522         if (hc->res_irq == NULL) {
 523                 goto errexit;
 524         }
 525         return (0);
 526
 527 errexit:
 528         sr_deallocate_resources(device);
 529         return (ENXIO);
 530 }
 531
 532 int
 533 sr_allocate_memory(device_t device, int rid, u_long size)
 534 {
 535         struct sr_hardc *hc = device_get_softc(device);
 536
 537         hc->rid_memory = rid;
 538         hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
 539                         &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
 540         if (hc->res_memory == NULL) {
 541                 goto errexit;
 542         }
 543         return (0);
 544
 545 errexit:
 546         sr_deallocate_resources(device);
 547         return (ENXIO);
 548 }
 549
 550 int
 551 sr_allocate_plx_memory(device_t device, int rid, u_long size)
 552 {
 553         struct sr_hardc *hc = device_get_softc(device);
 554
 555         hc->rid_plx_memory = rid;
 556         hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
 557                         &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
 558         if (hc->res_plx_memory == NULL) {
 559                 goto errexit;
 560         }
 561         return (0);
 562
 563 errexit:
 564         sr_deallocate_resources(device);
 565         return (ENXIO);
 566 }
 567
 568 int
 569 sr_deallocate_resources(device_t device)
 570 {
 571         struct sr_hardc *hc = device_get_softc(device);
 572
 573         if (hc->res_irq != 0) {
 574                 bus_deactivate_resource(device, SYS_RES_IRQ,
 575                         hc->rid_irq, hc->res_irq);
 576                 bus_release_resource(device, SYS_RES_IRQ,
 577                         hc->rid_irq, hc->res_irq);
 578                 hc->res_irq = 0;
 579         }
 580         if (hc->res_ioport != 0) {
 581                 bus_deactivate_resource(device, SYS_RES_IOPORT,
 582                         hc->rid_ioport, hc->res_ioport);
 583                 bus_release_resource(device, SYS_RES_IOPORT,
 584                         hc->rid_ioport, hc->res_ioport);
 585                 hc->res_ioport = 0;
 586         }
 587         if (hc->res_memory != 0) {
 588                 bus_deactivate_resource(device, SYS_RES_MEMORY,
 589                         hc->rid_memory, hc->res_memory);
 590                 bus_release_resource(device, SYS_RES_MEMORY,
 591                         hc->rid_memory, hc->res_memory);
 592                 hc->res_memory = 0;
 593         }
 594         if (hc->res_plx_memory != 0) {
 595                 bus_deactivate_resource(device, SYS_RES_MEMORY,
 596                         hc->rid_plx_memory, hc->res_plx_memory);
 597                 bus_release_resource(device, SYS_RES_MEMORY,
 598                         hc->rid_plx_memory, hc->res_plx_memory);
 599                 hc->res_plx_memory = 0;
 600         }
 601         return (0);
 602 }
 603
 604 /*
 605  * N2 Interrupt Service Routine
 606  *
 607  * First figure out which SCA gave the interrupt.
 608  * Process it.
 609  * See if there is other interrupts pending.
 610  * Repeat until there no interrupts remain.
 611  */
 612 static void
 613 srintr(void *arg)
 614 {
 615         struct sr_hardc *hc = (struct sr_hardc *)arg;
 616         sca_regs *sca = hc->sca;        /* MSCI register tree */
 617         u_char  isr0, isr1, isr2;       /* interrupt statii captured */
 618
 619 #if BUGGY > 1
 620         printf("sr: srintr_hc(hc=%08x)\n", hc);
 621 #endif
 622
 623         /*
 624          * Since multiple interfaces may share this interrupt, we must loop
 625          * until no interrupts are still pending service.
 626          */
 627         while (1) {
 628                 /*
 629                  * Read all three interrupt status registers from the N2
 630                  * card...
 631                  */
 632                 isr0 = SRC_GET8(hc->sca_base, sca->isr0);
 633                 isr1 = SRC_GET8(hc->sca_base, sca->isr1);
 634                 isr2 = SRC_GET8(hc->sca_base, sca->isr2);
 635
 636                 /*
 637                  * If all three registers returned 0, we've finished
 638                  * processing interrupts from this device, so we can quit
 639                  * this loop...
 640                  */
 641                 if ((isr0 | isr1 | isr2) == 0)
 642                         break;
 643
 644 #if BUGGY > 2
 645                 printf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n",
 646 #ifndef NETGRAPH
 647                         unit, isr0, isr1, isr2);
 648 #else
 649                         hc->cunit, isr0, isr1, isr2);
 650 #endif /* NETGRAPH */
 651 #endif
 652
 653                 /*
 654                  * Now we can dispatch the interrupts. Since we don't expect
 655                  * either MSCI or timer interrupts, we'll test for DMA
 656                  * interrupts first...
 657                  */
 658                 if (isr1)       /* DMA-initiated interrupt */
 659                         sr_dmac_intr(hc, isr1);
 660
 661                 if (isr0)       /* serial part IRQ? */
 662                         sr_msci_intr(hc, isr0);
 663
 664                 if (isr2)       /* timer-initiated interrupt */
 665                         sr_timer_intr(hc, isr2);
 666         }
 667 }
 668
 669 /*
 670  * This will only start the transmitter. It is assumed that the data
 671  * is already there.
 672  * It is normally called from srstart() or sr_dmac_intr().
 673  */
 674 static void
 675 sr_xmit(struct sr_softc *sc)
 676 {
 677         u_short cda_value;      /* starting descriptor */
 678         u_short eda_value;      /* ending descriptor */
 679         struct sr_hardc *hc;
 680 #ifndef NETGRAPH
 681         struct ifnet *ifp;      /* O/S Network Services */
 682 #endif /* NETGRAPH */
 683         dmac_channel *dmac;     /* DMA channel registers */
 684
 685 #if BUGGY > 0
 686         printf("sr: sr_xmit( sc=%08x)\n", sc);
 687 #endif
 688
 689         hc = sc->hc;
 690 #ifndef NETGRAPH
 691         ifp = &sc->ifsppp.pp_if;
 692 #endif /* NETGRAPH */
 693         dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
 694
 695         /*
 696          * Get the starting and ending addresses of the chain to be
 697          * transmitted and pass these on to the DMA engine on-chip.
 698          */
 699         cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart;
 700         cda_value &= 0x00ffff;
 701         eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart;
 702         eda_value &= 0x00ffff;
 703
 704         SRC_PUT16(hc->sca_base, dmac->cda, cda_value);
 705         SRC_PUT16(hc->sca_base, dmac->eda, eda_value);
 706
 707         /*
 708          * Now we'll let the DMA status register know about this change
 709          */
 710         SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
 711
 712         sc->xmit_busy = 1;      /* mark transmitter busy */
 713
 714 #if BUGGY > 2
 715         printf("sr%d: XMIT  cda=%04x, eda=%4x, rcda=%08lx\n",
 716                sc->unit, cda_value, eda_value,
 717                sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart);
 718 #endif
 719
 720         sc->txb_next_tx++;      /* update next transmit seq# */
 721
 722         if (sc->txb_next_tx == SR_TX_BLOCKS)    /* handle wrap... */
 723                 sc->txb_next_tx = 0;
 724
 725 #ifndef NETGRAPH
 726         /*
 727          * Finally, we'll set a timout (which will start srwatchdog())
 728          * within the O/S network services layer...
 729          */
 730         ifp->if_timer = 2;      /* Value in seconds. */
 731 #else
 732         /*
 733          * Don't time out for a while.
 734          */
 735         sc->out_dog = DOG_HOLDOFF;      /* give ourself some breathing space*/
 736 #endif /* NETGRAPH */
 737 }
 738
 739 /*
 740  * This function will be called from the upper level when a user add a
 741  * packet to be send, and from the interrupt handler after a finished
 742  * transmit.
 743  *
 744  * NOTE: it should run at spl_imp().
 745  *
 746  * This function only place the data in the oncard buffers. It does not
 747  * start the transmition. sr_xmit() does that.
 748  *
 749  * Transmitter idle state is indicated by the IFF_OACTIVE flag.
 750  * The function that clears that should ensure that the transmitter
 751  * and its DMA is in a "good" idle state.
 752  */
 753 #ifndef NETGRAPH
 754 static void
 755 srstart(struct ifnet *ifp)
 756 {
 757         struct sr_softc *sc;    /* channel control structure */
 758 #else
 759 static void
 760 srstart(struct sr_softc *sc)
 761 {
 762 #endif /* NETGRAPH */
 763         struct sr_hardc *hc;    /* card control/config block */
 764         int len;                /* total length of a packet */
 765         int pkts;               /* packets placed in DPRAM */
 766         int tlen;               /* working length of pkt */
 767         u_int i;
 768         struct mbuf *mtx;       /* message buffer from O/S */
 769         u_char *txdata;         /* buffer address in DPRAM */
 770         sca_descriptor *txdesc; /* working descriptor pointr */
 771         struct buf_block *blkp;
 772
 773 #ifndef NETGRAPH
 774 #if BUGGY > 0
 775         printf("sr: srstart( ifp=%08x)\n", ifp);
 776 #endif
 777         sc = ifp->if_softc;
 778         if ((ifp->if_flags & IFF_RUNNING) == 0)
 779                 return;
 780 #endif /* NETGRAPH */
 781         hc = sc->hc;
 782         /*
 783          * It is OK to set the memory window outside the loop because all tx
 784          * buffers and descriptors are assumed to be in the same 16K window.
 785          */
 786         if (hc->mempages) {
 787                 SRC_SET_ON(hc->iobase);
 788                 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
 789         }
 790
 791         /*
 792          * Loop to place packets into DPRAM.
 793          *
 794          * We stay in this loop until there is nothing in
 795          * the TX queue left or the tx buffers are full.
 796          */
 797 top_srstart:
 798
 799         /*
 800          * See if we have space for more packets.
 801          */
 802         if (sc->txb_inuse == SR_TX_BLOCKS) {    /* out of space? */
 803 #ifndef NETGRAPH
 804                 ifp->if_flags |= IFF_OACTIVE;   /* yes, mark active */
 805 #else
 806                 /*ifp->if_flags |= IFF_OACTIVE;*/       /* yes, mark active */
 807 #endif /* NETGRAPH */
 808
 809                 if (hc->mempages)
 810                         SRC_SET_OFF(hc->iobase);
 811
 812 #if BUGGY > 9
 813                 printf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n",
 814                        sc->unit, sc->txb_inuse);
 815 #endif
 816                 return;
 817         }
 818         /*
 819          * OK, the card can take more traffic.  Let's see if there's any
 820          * pending from the system...
 821          *
 822          * NOTE:
 823          * The architecture of the networking interface doesn't
 824          * actually call us like 'write()', providing an address.  We get
 825          * started, a lot like a disk strategy routine, and we actually call
 826          * back out to the system to get traffic to send...
 827          *
 828          * NOTE:
 829          * If we were gonna run through another layer, we would use a
 830          * dispatch table to select the service we're getting a packet
 831          * from...
 832          */
 833 #ifndef NETGRAPH
 834         mtx = sppp_dequeue(ifp);
 835 #else /* NETGRAPH */
 836         IF_DEQUEUE(&sc->xmitq_hipri, mtx);
 837         if (mtx == NULL) {
 838                 IF_DEQUEUE(&sc->xmitq, mtx);
 839         }
 840 #endif /* NETGRAPH */
 841         if (!mtx) {
 842                 if (hc->mempages)
 843                         SRC_SET_OFF(hc->iobase);
 844                 return;
 845         }
 846         /*
 847          * OK, we got a packet from the network services of the O/S. Now we
 848          * can move it into the DPRAM (under control of the descriptors) and
 849          * fire it off...
 850          */
 851         pkts = 0;
 852         i = 0;                  /* counts # of granules used */
 853
 854         blkp = &sc->block[sc->txb_new]; /* address of free granule */
 855         txdesc = (sca_descriptor *)
 856             (hc->mem_start + (blkp->txdesc & hc->winmsk));
 857
 858         txdata = (u_char *)(hc->mem_start
 859                             + (blkp->txstart & hc->winmsk));
 860
 861         /*
 862          * Now we'll try to install as many packets as possible into the
 863          * card's DP RAM buffers.
 864          */
 865         for (;;) {              /* perform actual copy of packet */
 866                 len = mtx->m_pkthdr.len;        /* length of message */
 867
 868 #if BUGGY > 1
 869                 printf("sr%d.srstart: mbuf @ %08lx, %d bytes\n",
 870                            sc->unit, mtx, len);
 871 #endif
 872
 873 #ifndef NETGRAPH
 874                 if (ifp->if_bpf)
 875                         bpf_mtap(ifp, mtx);
 876 #else   /* NETGRAPH */
 877                 sc->outbytes += len;
 878 #endif  /* NETGRAPH */
 879
 880                 /*
 881                  * We can perform a straight copy because the tranmit
 882                  * buffers won't wrap.
 883                  */
 884                 m_copydata(mtx, 0, len, txdata);
 885
 886                 /*
 887                  * Now we know how big the message is gonna be.  We must now
 888                  * construct the descriptors to drive this message out...
 889                  */
 890                 tlen = len;
 891                 while (tlen > SR_BUF_SIZ) {     /* loop for full granules */
 892                         txdesc->stat = 0;       /* reset bits */
 893                         txdesc->len = SR_BUF_SIZ;       /* size of granule */
 894                         tlen -= SR_BUF_SIZ;
 895
 896                         txdesc++;       /* move to next dscr */
 897                         txdata += SR_BUF_SIZ;   /* adjust data addr */
 898                         i++;
 899                 }
 900
 901                 /*
 902                  * This section handles the setting of the final piece of a
 903                  * message.
 904                  */
 905                 txdesc->stat = SCA_DESC_EOM;
 906                 txdesc->len = tlen;
 907                 pkts++;
 908
 909                 /*
 910                  * prepare for subsequent packets (if any)
 911                  */
 912                 txdesc++;
 913                 txdata += SR_BUF_SIZ;   /* next mem granule */
 914                 i++;            /* count of granules */
 915
 916                 /*
 917                  * OK, we've now placed the message into the DPRAM where it
 918                  * can be transmitted.  We'll now release the message memory
 919                  * and update the statistics...
 920                  */
 921                 m_freem(mtx);
 922 #ifndef NETGRAPH
 923                 ++sc->ifsppp.pp_if.if_opackets;
 924 #else   /* NETGRAPH */
 925                 sc->opackets++;
 926 #endif /* NETGRAPH */
 927
 928                 /*
 929                  * Check if we have space for another packet. XXX This is
 930                  * hardcoded.  A packet can't be larger than 3 buffers (3 x
 931                  * 512).
 932                  */
 933                 if ((i + 3) >= blkp->txmax) {   /* enough remains? */
 934 #if BUGGY > 9
 935                         printf("sr%d.srstart: i=%d (%d pkts); card full.\n",
 936                                sc->unit, i, pkts);
 937 #endif
 938                         break;
 939                 }
 940                 /*
 941                  * We'll pull the next message to be sent (if any)
 942                  */
 943 #ifndef NETGRAPH
 944                 mtx = sppp_dequeue(ifp);
 945 #else /* NETGRAPH */
 946                 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
 947                 if (mtx == NULL) {
 948                         IF_DEQUEUE(&sc->xmitq, mtx);
 949                 }
 950 #endif /* NETGRAPH */
 951                 if (!mtx) {     /* no message?  We're done! */
 952 #if BUGGY > 9
 953                         printf("sr%d.srstart: pending=0, pkts=%d\n",
 954                                sc->unit, pkts);
 955 #endif
 956                         break;
 957                 }
 958         }
 959
 960         blkp->txtail = i;       /* record next free granule */
 961
 962         /*
 963          * Mark the last descriptor, so that the SCA know where to stop.
 964          */
 965         txdesc--;               /* back up to last descriptor in list */
 966         txdesc->stat |= SCA_DESC_EOT;   /* mark as end of list */
 967
 968         /*
 969          * Now we'll reset the transmit granule's descriptor address so we
 970          * can record this in the structure and fire it off w/ the DMA
 971          * processor of the serial chip...
 972          */
 973         txdesc = (sca_descriptor *)blkp->txdesc;
 974         blkp->txeda = (u_short)((u_int)&txdesc[i]);
 975
 976         sc->txb_inuse++;        /* update inuse status */
 977         sc->txb_new++;          /* new traffic wuz added */
 978
 979         if (sc->txb_new == SR_TX_BLOCKS)
 980                 sc->txb_new = 0;
 981
 982         /*
 983          * If the tranmitter wasn't marked as "busy" we will force it to be
 984          * started...
 985          */
 986         if (sc->xmit_busy == 0) {
 987                 sr_xmit(sc);
 988 #if BUGGY > 9
 989                 printf("sr%d.srstart: called sr_xmit()\n", sc->unit);
 990 #endif
 991         }
 992         goto top_srstart;
 993 }
 994
 995 #ifndef NETGRAPH
 996 /*
 997  * Handle ioctl's at the device level, though we *will* call up
 998  * a layer...
 999  */
1000 #if BUGGY > 2
1001 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0};
1002 #endif
1003
1004 static int
1005 srioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1006 {
1007         int s, error, was_up, should_be_up;
1008         struct sr_softc *sc = ifp->if_softc;
1009
1010 #if BUGGY > 0
1011         printf("%s: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n",
1012                ifp->if_xname, ifp, cmd, data);
1013 #endif
1014
1015         was_up = ifp->if_flags & IFF_RUNNING;
1016
1017         error = sppp_ioctl(ifp, cmd, data);
1018
1019 #if BUGGY > 1
1020         printf("%s: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n",
1021               ifp->if_xname, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);
1022 #endif
1023
1024         if (error)
1025                 return error;
1026
1027         if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) {
1028 #if BUGGY > 2
1029                 if (bug_splats[sc->unit]++ < 2) {
1030                         printf("sr(%d).if_addrlist = %08x\n",
1031                                sc->unit, ifp->if_addrlist);
1032                         printf("sr(%d).if_bpf = %08x\n",
1033                                sc->unit, ifp->if_bpf);
1034                         printf("sr(%d).if_init = %08x\n",
1035                                sc->unit, ifp->if_init);
1036                         printf("sr(%d).if_output = %08x\n",
1037                                sc->unit, ifp->if_output);
1038                         printf("sr(%d).if_start = %08x\n",
1039                                sc->unit, ifp->if_start);
1040                         printf("sr(%d).if_done = %08x\n",
1041                                sc->unit, ifp->if_done);
1042                         printf("sr(%d).if_ioctl = %08x\n",
1043                                sc->unit, ifp->if_ioctl);
1044                         printf("sr(%d).if_reset = %08x\n",
1045                                sc->unit, ifp->if_reset);
1046                         printf("sr(%d).if_watchdog = %08x\n",
1047                                sc->unit, ifp->if_watchdog);
1048                 }
1049 #endif
1050                 return 0;
1051         }
1052
1053         s = splimp();
1054         should_be_up = ifp->if_flags & IFF_RUNNING;
1055
1056         if (!was_up && should_be_up) {
1057                 /*
1058                  * Interface should be up -- start it.
1059                  */
1060                 sr_up(sc);
1061                 srstart(ifp);
1062
1063                 /*
1064                  * XXX Clear the IFF_UP flag so that the link will only go
1065                  * up after sppp lcp and ipcp negotiation.
1066                  */
1067                 /* ifp->if_flags &= ~IFF_UP; */
1068         } else if (was_up && !should_be_up) {
1069                 /*
1070                  * Interface should be down -- stop it.
1071                  */
1072                 sr_down(sc);
1073                 sppp_flush(ifp);
1074         }
1075         splx(s);
1076         return 0;
1077 }
1078 #endif /* NETGRAPH */
1079
1080 /*
1081  * This is to catch lost tx interrupts.
1082  */
1083 static void
1084 #ifndef NETGRAPH
1085 srwatchdog(struct ifnet *ifp)
1086 #else
1087 srwatchdog(struct sr_softc *sc)
1088 #endif /* NETGRAPH */
1089 {
1090         int     got_st0, got_st1, got_st3, got_dsr;
1091 #ifndef NETGRAPH
1092         struct sr_softc *sc = ifp->if_softc;
1093 #endif /* NETGRAPH */
1094         struct sr_hardc *hc = sc->hc;
1095         msci_channel *msci = &hc->sca->msci[sc->scachan];
1096         dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan];
1097
1098 #if BUGGY > 0
1099 #ifndef NETGRAPH
1100         printf("srwatchdog(unit=%d)\n", unit);
1101 #else
1102         printf("srwatchdog(unit=%d)\n", sc->unit);
1103 #endif /* NETGRAPH */
1104 #endif
1105
1106 #ifndef NETGRAPH
1107         if (!(ifp->if_flags & IFF_RUNNING))
1108                 return;
1109
1110         ifp->if_oerrors++;      /* update output error count */
1111 #else   /* NETGRAPH */
1112         sc->oerrors++;  /* update output error count */
1113 #endif /* NETGRAPH */
1114
1115         got_st0 = SRC_GET8(hc->sca_base, msci->st0);
1116         got_st1 = SRC_GET8(hc->sca_base, msci->st1);
1117         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
1118         got_dsr = SRC_GET8(hc->sca_base, dmac->dsr);
1119
1120 #ifndef NETGRAPH
1121 #if     0
1122         if (ifp->if_flags & IFF_DEBUG)
1123 #endif
1124                 printf("sr%d: transmit failed, "
1125 #else   /* NETGRAPH */
1126         printf("sr%d: transmit failed, "
1127 #endif /* NETGRAPH */
1128                        "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n",
1129                        sc->unit,
1130                        got_st0, got_st1, got_st3, got_dsr);
1131
1132         if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) {
1133                 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT);
1134                 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1135                 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN);
1136         }
1137         sc->xmit_busy = 0;
1138 #ifndef NETGRAPH
1139         ifp->if_flags &= ~IFF_OACTIVE;
1140 #else
1141         /*ifp->if_flags &= ~IFF_OACTIVE; */
1142 #endif /* NETGRAPH */
1143
1144         if (sc->txb_inuse && --sc->txb_inuse)
1145                 sr_xmit(sc);
1146
1147 #ifndef NETGRAPH
1148         srstart(ifp);   /* restart transmitter */
1149 #else
1150         srstart(sc);    /* restart transmitter */
1151 #endif /* NETGRAPH */
1152 }
1153
1154 static void
1155 sr_up(struct sr_softc *sc)
1156 {
1157         u_int *fecrp;
1158         struct sr_hardc *hc = sc->hc;
1159         sca_regs *sca = hc->sca;
1160         msci_channel *msci = &sca->msci[sc->scachan];
1161
1162 #if BUGGY > 0
1163         printf("sr_up(sc=%08x)\n", sc);
1164 #endif
1165
1166         /*
1167          * Enable transmitter and receiver. Raise DTR and RTS. Enable
1168          * interrupts.
1169          *
1170          * XXX What about using AUTO mode in msci->md0 ???
1171          */
1172         SRC_PUT8(hc->sca_base, msci->ctl,
1173                  SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS);
1174
1175         if (sc->scachan == 0)
1176                 switch (hc->cardtype) {
1177                 case SR_CRD_N2:
1178                         outb(hc->iobase + SR_MCR,
1179                              (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR0));
1180                         break;
1181                 case SR_CRD_N2PCI:
1182                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1183                         *fecrp &= ~SR_FECR_DTR0;
1184                         break;
1185                 }
1186         else
1187                 switch (hc->cardtype) {
1188                 case SR_CRD_N2:
1189                         outb(hc->iobase + SR_MCR,
1190                              (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR1));
1191                         break;
1192                 case SR_CRD_N2PCI:
1193                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1194                         *fecrp &= ~SR_FECR_DTR1;
1195                         break;
1196                 }
1197
1198         if (sc->scachan == 0) {
1199                 SRC_PUT8(hc->sca_base, sca->ier0,
1200                          SRC_GET8(hc->sca_base, sca->ier0) | 0x000F);
1201                 SRC_PUT8(hc->sca_base, sca->ier1,
1202                          SRC_GET8(hc->sca_base, sca->ier1) | 0x000F);
1203         } else {
1204                 SRC_PUT8(hc->sca_base, sca->ier0,
1205                          SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0);
1206                 SRC_PUT8(hc->sca_base, sca->ier1,
1207                          SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0);
1208         }
1209
1210         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE);
1211         inb(hc->iobase);        /* XXX slow it down a bit. */
1212         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1213
1214 #ifndef NETGRAPH
1215 #ifdef USE_MODEMCK
1216         if (sr_watcher == 0)
1217                 sr_modemck(NULL);
1218 #endif
1219 #else   /* NETGRAPH */
1220         untimeout(ngsr_watchdog_frame, sc, sc->handle);
1221         sc->handle = timeout(ngsr_watchdog_frame, sc, hz);
1222         sc->running = 1;
1223 #endif /* NETGRAPH */
1224 }
1225
1226 static void
1227 sr_down(struct sr_softc *sc)
1228 {
1229         u_int *fecrp;
1230         struct sr_hardc *hc = sc->hc;
1231         sca_regs *sca = hc->sca;
1232         msci_channel *msci = &sca->msci[sc->scachan];
1233
1234 #if BUGGY > 0
1235         printf("sr_down(sc=%08x)\n", sc);
1236 #endif
1237 #ifdef NETGRAPH
1238         untimeout(ngsr_watchdog_frame, sc, sc->handle);
1239         sc->running = 0;
1240 #endif /* NETGRAPH */
1241
1242         /*
1243          * Disable transmitter and receiver. Lower DTR and RTS. Disable
1244          * interrupts.
1245          */
1246         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE);
1247         inb(hc->iobase);        /* XXX slow it down a bit. */
1248         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE);
1249
1250         SRC_PUT8(hc->sca_base, msci->ctl,
1251                  SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS);
1252
1253         if (sc->scachan == 0)
1254                 switch (hc->cardtype) {
1255                 case SR_CRD_N2:
1256                         outb(hc->iobase + SR_MCR,
1257                              (inb(hc->iobase + SR_MCR) | SR_MCR_DTR0));
1258                         break;
1259                 case SR_CRD_N2PCI:
1260                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1261                         *fecrp |= SR_FECR_DTR0;
1262                         break;
1263                 }
1264         else
1265                 switch (hc->cardtype) {
1266                 case SR_CRD_N2:
1267                         outb(hc->iobase + SR_MCR,
1268                              (inb(hc->iobase + SR_MCR) | SR_MCR_DTR1));
1269                         break;
1270                 case SR_CRD_N2PCI:
1271                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1272                         *fecrp |= SR_FECR_DTR1;
1273                         break;
1274                 }
1275
1276         if (sc->scachan == 0) {
1277                 SRC_PUT8(hc->sca_base, sca->ier0,
1278                          SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F);
1279                 SRC_PUT8(hc->sca_base, sca->ier1,
1280                          SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F);
1281         } else {
1282                 SRC_PUT8(hc->sca_base, sca->ier0,
1283                          SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0);
1284                 SRC_PUT8(hc->sca_base, sca->ier1,
1285                          SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0);
1286         }
1287 }
1288
1289 /*
1290  * Initialize the card, allocate memory for the sr_softc structures
1291  * and fill in the pointers.
1292  */
1293 static void
1294 src_init(struct sr_hardc *hc)
1295 {
1296         struct sr_softc *sc = hc->sc;
1297         int x;
1298         u_int chanmem;
1299         u_int bufmem;
1300         u_int next;
1301         u_int descneeded;
1302
1303 #if BUGGY > 0
1304         printf("src_init(hc=%08x)\n", hc);
1305 #endif
1306
1307         chanmem = hc->memsize / hc->numports;
1308         next = 0;
1309
1310         for (x = 0; x < hc->numports; x++, sc++) {
1311                 int blk;
1312
1313                 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1314                         sc->block[blk].txdesc = next;
1315                         bufmem = (16 * 1024) / SR_TX_BLOCKS;
1316                         descneeded = bufmem / SR_BUF_SIZ;
1317
1318                         sc->block[blk].txstart = sc->block[blk].txdesc
1319                             + ((((descneeded * sizeof(sca_descriptor))
1320                                  / SR_BUF_SIZ) + 1)
1321                                * SR_BUF_SIZ);
1322
1323                         sc->block[blk].txend = next + bufmem;
1324                         sc->block[blk].txmax =
1325                             (sc->block[blk].txend - sc->block[blk].txstart)
1326                             / SR_BUF_SIZ;
1327                         next += bufmem;
1328
1329 #if BUGGY > 2
1330                         printf("sr%d: blk %d: txdesc %08x, txstart %08x\n",
1331                                sc->unit, blk,
1332                                sc->block[blk].txdesc, sc->block[blk].txstart);
1333 #endif
1334                 }
1335
1336                 sc->rxdesc = next;
1337                 bufmem = chanmem - (bufmem * SR_TX_BLOCKS);
1338                 descneeded = bufmem / SR_BUF_SIZ;
1339                 sc->rxstart = sc->rxdesc +
1340                     ((((descneeded * sizeof(sca_descriptor)) /
1341                        SR_BUF_SIZ) + 1) * SR_BUF_SIZ);
1342                 sc->rxend = next + bufmem;
1343                 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ;
1344                 next += bufmem;
1345         }
1346 }
1347
1348 /*
1349  * The things done here are channel independent.
1350  *
1351  * Configure the sca waitstates.
1352  * Configure the global interrupt registers.
1353  * Enable master dma enable.
1354  */
1355 static void
1356 sr_init_sca(struct sr_hardc *hc)
1357 {
1358         sca_regs *sca = hc->sca;
1359
1360 #if BUGGY > 0
1361         printf("sr_init_sca(hc=%08x)\n", hc);
1362 #endif
1363
1364         /*
1365          * Do the wait registers. Set everything to 0 wait states.
1366          */
1367         SRC_PUT8(hc->sca_base, sca->pabr0, 0);
1368         SRC_PUT8(hc->sca_base, sca->pabr1, 0);
1369         SRC_PUT8(hc->sca_base, sca->wcrl, 0);
1370         SRC_PUT8(hc->sca_base, sca->wcrm, 0);
1371         SRC_PUT8(hc->sca_base, sca->wcrh, 0);
1372
1373         /*
1374          * Configure the interrupt registers. Most are cleared until the
1375          * interface is configured.
1376          */
1377         SRC_PUT8(hc->sca_base, sca->ier0, 0x00);        /* MSCI interrupts. */
1378         SRC_PUT8(hc->sca_base, sca->ier1, 0x00);        /* DMAC interrupts */
1379         SRC_PUT8(hc->sca_base, sca->ier2, 0x00);        /* TIMER interrupts. */
1380         SRC_PUT8(hc->sca_base, sca->itcr, 0x00);        /* Use ivr and no intr
1381                                                          * ack */
1382         SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */
1383         SRC_PUT8(hc->sca_base, sca->imvr, 0x40);
1384
1385         /*
1386          * Configure the timers. XXX Later
1387          */
1388
1389         /*
1390          * Set the DMA channel priority to rotate between all four channels.
1391          *
1392          * Enable all dma channels.
1393          */
1394         SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2);
1395         SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN);
1396 }
1397
1398 /*
1399  * Configure the msci
1400  *
1401  * NOTE: The serial port configuration is hardcoded at the moment.
1402  */
1403 static void
1404 sr_init_msci(struct sr_softc *sc)
1405 {
1406         int portndx;            /* on-board port number */
1407         u_int mcr_v;            /* contents of modem control */
1408         u_int *fecrp;           /* pointer for PCI's MCR i/o */
1409         struct sr_hardc *hc = sc->hc;
1410         msci_channel *msci = &hc->sca->msci[sc->scachan];
1411 #ifdef N2_TEST_SPEED
1412         int br_v;               /* contents for BR divisor */
1413         int etcndx;             /* index into ETC table */
1414         int fifo_v, gotspeed;   /* final tabled speed found */
1415         int tmc_v;              /* timer control register */
1416         int wanted;             /* speed (bitrate) wanted... */
1417         struct rate_line *rtp;
1418 #endif
1419
1420         portndx = sc->scachan;
1421
1422 #if BUGGY > 0
1423         printf("sr: sr_init_msci( sc=%08x)\n", sc);
1424 #endif
1425
1426         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET);
1427         SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 |
1428                  SCA_MD0_CRC_CCITT |
1429                  SCA_MD0_CRC_ENABLE |
1430                  SCA_MD0_MODE_HDLC);
1431         SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK);
1432         SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ);
1433
1434         /*
1435          * According to the manual I should give a reset after changing the
1436          * mode registers.
1437          */
1438         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET);
1439         SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT |
1440                  SCA_CTL_UDRNC |
1441                  SCA_CTL_RTS);
1442
1443         /*
1444          * XXX Later we will have to support different clock settings.
1445          */
1446         switch (sc->clk_cfg) {
1447         default:
1448 #if BUGGY > 0
1449                 printf("sr%: clk_cfg=%08x, selected default clock.\n",
1450                        portndx, sc->clk_cfg);
1451 #endif
1452                 /* FALLTHROUGH */
1453         case SR_FLAGS_EXT_CLK:
1454                 /*
1455                  * For now all interfaces are programmed to use the RX clock
1456                  * for the TX clock.
1457                  */
1458
1459 #if BUGGY > 0
1460                 printf("sr%d: External Clock Selected.\n", portndx);
1461 #endif
1462
1463                 SRC_PUT8(hc->sca_base, msci->rxs,
1464                          SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1465                 SRC_PUT8(hc->sca_base, msci->txs,
1466                          SCA_TXS_CLK_RX | SCA_TXS_DIV1);
1467                 break;
1468
1469         case SR_FLAGS_EXT_SEP_CLK:
1470 #if BUGGY > 0
1471                 printf("sr%d: Split Clocking Selected.\n", portndx);
1472 #endif
1473
1474                 SRC_PUT8(hc->sca_base, msci->rxs,
1475                          SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1476                 SRC_PUT8(hc->sca_base, msci->txs,
1477                          SCA_TXS_CLK_TXC | SCA_TXS_DIV1);
1478                 break;
1479
1480         case SR_FLAGS_INT_CLK:
1481 #if BUGGY > 0
1482                 printf("sr%d: Internal Clocking selected.\n", portndx);
1483 #endif
1484
1485                 /*
1486                  * XXX I do need some code to set the baud rate here!
1487                  */
1488 #ifdef N2_TEST_SPEED
1489                 switch (hc->cardtype) {
1490                 case SR_CRD_N2PCI:
1491                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1492                         mcr_v = *fecrp;
1493                         etcndx = 2;
1494                         break;
1495                 case SR_CRD_N2:
1496                 default:
1497                         mcr_v = inb(hc->iobase + SR_MCR);
1498                         etcndx = 0;
1499                 }
1500
1501                 fifo_v = 0x10;  /* stolen from Linux version */
1502
1503                 /*
1504                  * search for appropriate speed in table, don't calc it:
1505                  */
1506                 wanted = sr_test_speed[portndx];
1507                 rtp = &n2_rates[0];     /* point to first table item */
1508
1509                 while ((rtp->target > 0)        /* search table for speed */
1510                        &&(rtp->target != wanted))
1511                         rtp++;
1512
1513                 /*
1514                  * We've searched the table for a matching speed.  If we've
1515                  * found the correct rate line, we'll get the pre-calc'd
1516                  * values for the TMC and baud rate divisor for subsequent
1517                  * use...
1518                  */
1519                 if (rtp->target > 0) {  /* use table-provided values */
1520                         gotspeed = wanted;
1521                         tmc_v = rtp->tmc_reg;
1522                         br_v = rtp->br_reg;
1523                 } else {        /* otherwise assume 1MBit comm rate */
1524                         gotspeed = 10000;
1525                         tmc_v = 5;
1526                         br_v = 1;
1527                 }
1528
1529                 /*
1530                  * Now we mask in the enable clock output for the MCR:
1531                  */
1532                 mcr_v |= etc0vals[etcndx + portndx];
1533
1534                 /*
1535                  * Now we'll program the registers with these speed- related
1536                  * contents...
1537                  */
1538                 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v);
1539                 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v);
1540                 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v);
1541                 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v);
1542
1543                 switch (hc->cardtype) {
1544                 case SR_CRD_N2PCI:
1545                         *fecrp = mcr_v;
1546                         break;
1547                 case SR_CRD_N2:
1548                 default:
1549                         outb(hc->iobase + SR_MCR, mcr_v);
1550                 }
1551
1552 #if BUGGY > 0
1553                 if (wanted != gotspeed)
1554                         printf("sr%d: Speed wanted=%d, found=%d\n",
1555                                wanted, gotspeed);
1556
1557                 printf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n",
1558                        portndx, gotspeed, tmc_v, br_v);
1559 #endif
1560 #else
1561                 SRC_PUT8(hc->sca_base, msci->rxs,
1562                          SCA_RXS_CLK_INT | SCA_RXS_DIV1);
1563                 SRC_PUT8(hc->sca_base, msci->txs,
1564                          SCA_TXS_CLK_INT | SCA_TXS_DIV1);
1565
1566                 SRC_PUT8(hc->sca_base, msci->tmc, 5);
1567
1568                 if (portndx == 0)
1569                         switch (hc->cardtype) {
1570                         case SR_CRD_N2PCI:
1571                                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1572                                 *fecrp |= SR_FECR_ETC0;
1573                                 break;
1574                         case SR_CRD_N2:
1575                         default:
1576                                 mcr_v = inb(hc->iobase + SR_MCR);
1577                                 mcr_v |= SR_MCR_ETC0;
1578                                 outb(hc->iobase + SR_MCR, mcr_v);
1579                         }
1580                 else
1581                         switch (hc->cardtype) {
1582                         case SR_CRD_N2:
1583                                 mcr_v = inb(hc->iobase + SR_MCR);
1584                                 mcr_v |= SR_MCR_ETC1;
1585                                 outb(hc->iobase + SR_MCR, mcr_v);
1586                                 break;
1587                         case SR_CRD_N2PCI:
1588                                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1589                                 *fecrp |= SR_FECR_ETC1;
1590                                 break;
1591                         }
1592 #endif
1593         }
1594
1595         /*
1596          * XXX Disable all interrupts for now. I think if you are using the
1597          * dmac you don't use these interrupts.
1598          */
1599         SRC_PUT8(hc->sca_base, msci->ie0, 0);
1600         SRC_PUT8(hc->sca_base, msci->ie1, 0x0C);
1601         SRC_PUT8(hc->sca_base, msci->ie2, 0);
1602         SRC_PUT8(hc->sca_base, msci->fie, 0);
1603
1604         SRC_PUT8(hc->sca_base, msci->sa0, 0);
1605         SRC_PUT8(hc->sca_base, msci->sa1, 0);
1606
1607         SRC_PUT8(hc->sca_base, msci->idl, 0x7E);        /* set flags value */
1608
1609         SRC_PUT8(hc->sca_base, msci->rrc, 0x0E);
1610         SRC_PUT8(hc->sca_base, msci->trc0, 0x10);
1611         SRC_PUT8(hc->sca_base, msci->trc1, 0x1F);
1612 }
1613
1614 /*
1615  * Configure the rx dma controller.
1616  */
1617 static void
1618 sr_init_rx_dmac(struct sr_softc *sc)
1619 {
1620         struct sr_hardc *hc;
1621         dmac_channel *dmac;
1622         sca_descriptor *rxd;
1623         u_int cda_v, sarb_v, rxbuf, rxda, rxda_d;
1624
1625 #if BUGGY > 0
1626         printf("sr_init_rx_dmac(sc=%08x)\n", sc);
1627 #endif
1628
1629         hc = sc->hc;
1630         dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)];
1631
1632         if (hc->mempages)
1633                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1634
1635         /*
1636          * This phase initializes the contents of the descriptor table
1637          * needed to construct a circular buffer...
1638          */
1639         rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk));
1640         rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk);
1641
1642         for (rxbuf = sc->rxstart;
1643              rxbuf < sc->rxend;
1644              rxbuf += SR_BUF_SIZ, rxd++) {
1645                 /*
1646                  * construct the circular chain...
1647                  */
1648                 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart;
1649                 rxd->cp = (u_short)(rxda & 0xffff);
1650
1651                 /*
1652                  * set the on-card buffer address...
1653                  */
1654                 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff);
1655                 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff);
1656
1657                 rxd->len = 0;   /* bytes resident w/in granule */
1658                 rxd->stat = 0xff;       /* The sca write here when finished */
1659         }
1660
1661         /*
1662          * heal the chain so that the last entry points to the first...
1663          */
1664         rxd--;
1665         rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1666
1667         /*
1668          * reset the reception handler's index...
1669          */
1670         sc->rxhind = 0;
1671
1672         /*
1673          * We'll now configure the receiver's DMA logic...
1674          */
1675         SRC_PUT8(hc->sca_base, dmac->dsr, 0);   /* Disable DMA transfer */
1676         SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1677
1678         /* XXX maybe also SCA_DMR_CNTE */
1679         SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1680         SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ);
1681
1682         cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1683         sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff);
1684
1685         SRC_PUT16(hc->sca_base, dmac->cda, cda_v);
1686         SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v);
1687
1688         rxd = (sca_descriptor *)sc->rxstart;
1689
1690         SRC_PUT16(hc->sca_base, dmac->eda,
1691                   (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff));
1692
1693         SRC_PUT8(hc->sca_base, dmac->dir, 0xF0);
1694
1695
1696         SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);  /* Enable DMA */
1697 }
1698
1699 /*
1700  * Configure the TX DMA descriptors.
1701  * Initialize the needed values and chain the descriptors.
1702  */
1703 static void
1704 sr_init_tx_dmac(struct sr_softc *sc)
1705 {
1706         int blk;
1707         u_int txbuf, txda, txda_d;
1708         struct sr_hardc *hc;
1709         sca_descriptor *txd;
1710         dmac_channel *dmac;
1711         struct buf_block *blkp;
1712         u_int x;
1713         u_int sarb_v;
1714
1715 #if BUGGY > 0
1716         printf("sr_init_tx_dmac(sc=%08x)\n", sc);
1717 #endif
1718
1719         hc = sc->hc;
1720         dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
1721
1722         if (hc->mempages)
1723                 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
1724
1725         /*
1726          * Initialize the array of descriptors for transmission
1727          */
1728         for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1729                 blkp = &sc->block[blk];
1730                 txd = (sca_descriptor *)(hc->mem_start
1731                                          + (blkp->txdesc & hc->winmsk));
1732                 txda_d = (u_int) hc->mem_start
1733                     - (blkp->txdesc & ~hc->winmsk);
1734
1735                 x = 0;
1736                 txbuf = blkp->txstart;
1737                 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) {
1738                         txda = (u_int) & txd[1] - txda_d + hc->mem_pstart;
1739                         txd->cp = (u_short)(txda & 0xffff);
1740
1741                         txd->bp = (u_short)((txbuf + hc->mem_pstart)
1742                                             & 0xffff);
1743                         txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16)
1744                                             & 0xff);
1745                         txd->len = 0;
1746                         txd->stat = 0;
1747                         x++;
1748                 }
1749
1750                 txd--;
1751                 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart)
1752                                     & 0xffff);
1753
1754                 blkp->txtail = (u_int)txd - (u_int)hc->mem_start;
1755         }
1756
1757         SRC_PUT8(hc->sca_base, dmac->dsr, 0);   /* Disable DMA */
1758         SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1759         SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1760         SRC_PUT8(hc->sca_base, dmac->dir,
1761                  SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF);
1762
1763         sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16;
1764         sarb_v &= 0x00ff;
1765
1766         SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v);
1767 }
1768
1769 /*
1770  * Look through the descriptors to see if there is a complete packet
1771  * available. Stop if we get to where the sca is busy.
1772  *
1773  * Return the length and status of the packet.
1774  * Return nonzero if there is a packet available.
1775  *
1776  * NOTE:
1777  * It seems that we get the interrupt a bit early. The updateing of
1778  * descriptor values is not always completed when this is called.
1779  */
1780 static int
1781 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat)
1782 {
1783         int granules;   /* count of granules in pkt */
1784         int wki, wko;
1785         struct sr_hardc *hc;
1786         sca_descriptor *rxdesc; /* current descriptor */
1787         sca_descriptor *endp;   /* ending descriptor */
1788         sca_descriptor *cda;    /* starting descriptor */
1789
1790         hc = sc->hc;            /* get card's information */
1791
1792         /*
1793          * set up starting descriptor by pulling that info from the DMA half
1794          * of the HD chip...
1795          */
1796         wki = DMAC_RXCH(sc->scachan);
1797         wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda);
1798
1799         cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk));
1800
1801 #if BUGGY > 1
1802         printf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n",
1803                wki, wko, cda);
1804 #endif
1805
1806         /*
1807          * open the appropriate memory window and set our expectations...
1808          */
1809         if (hc->mempages) {
1810                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1811                 SRC_SET_ON(hc->iobase);
1812         }
1813         rxdesc = (sca_descriptor *)
1814             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1815         endp = rxdesc;
1816         rxdesc = &rxdesc[sc->rxhind];
1817         endp = &endp[sc->rxmax];
1818
1819         *len = 0;               /* reset result total length */
1820         granules = 0;           /* reset count of granules */
1821
1822         /*
1823          * This loop will scan descriptors, but it *will* puke up if we wrap
1824          * around to our starting point...
1825          */
1826         while (rxdesc != cda) {
1827                 *len += rxdesc->len;    /* increment result length */
1828                 granules++;
1829
1830                 /*
1831                  * If we hit a valid packet's completion we'll know we've
1832                  * got a live one, and that we can deliver the packet.
1833                  * Since we're only allowed to report a packet available,
1834                  * somebody else does that...
1835                  */
1836                 if (rxdesc->stat & SCA_DESC_EOM) {      /* End Of Message */
1837                         *rxstat = rxdesc->stat; /* return closing */
1838 #if BUGGY > 0
1839                         printf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n",
1840                                sc->unit, *len, *rxstat, granules);
1841 #endif
1842                         return 1;       /* indicate success */
1843                 }
1844                 /*
1845                  * OK, this packet take up multiple granules.  Move on to
1846                  * the next descriptor so we can consider it...
1847                  */
1848                 rxdesc++;
1849
1850                 if (rxdesc == endp)     /* recognize & act on wrap point */
1851                         rxdesc = (sca_descriptor *)
1852                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1853         }
1854
1855         /*
1856          * Nothing found in the DPRAM.  Let the caller know...
1857          */
1858         *len = 0;
1859         *rxstat = 0;
1860
1861         return 0;
1862 }
1863
1864 /*
1865  * Copy a packet from the on card memory into a provided mbuf.
1866  * Take into account that buffers wrap and that a packet may
1867  * be larger than a buffer.
1868  */
1869 static void
1870 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len)
1871 {
1872         struct sr_hardc *hc;
1873         sca_descriptor *rxdesc;
1874         u_int rxdata;
1875         u_int rxmax;
1876         u_int off = 0;
1877         u_int tlen;
1878
1879 #if BUGGY > 0
1880         printf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n",
1881                m, sc, len);
1882 #endif
1883
1884         hc = sc->hc;
1885
1886         rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ);
1887         rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ);
1888
1889         rxdesc = (sca_descriptor *)
1890             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1891         rxdesc = &rxdesc[sc->rxhind];
1892
1893         /*
1894          * Using the count of bytes in the received packet, we decrement it
1895          * for each granule (controller by an SCA descriptor) to control the
1896          * looping...
1897          */
1898         while (len) {
1899                 /*
1900                  * tlen gets the length of *this* granule... ...which is
1901                  * then copied to the target buffer.
1902                  */
1903                 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ;
1904
1905                 if (hc->mempages)
1906                         SRC_SET_MEM(hc->iobase, rxdata);
1907
1908                 bcopy(hc->mem_start + (rxdata & hc->winmsk),
1909                       mtod(m, caddr_t) +off,
1910                       tlen);
1911
1912                 off += tlen;
1913                 len -= tlen;
1914
1915                 /*
1916                  * now, return to the descriptor's window in DPRAM and reset
1917                  * the descriptor we've just suctioned...
1918                  */
1919                 if (hc->mempages)
1920                         SRC_SET_MEM(hc->iobase, sc->rxdesc);
1921
1922                 rxdesc->len = 0;
1923                 rxdesc->stat = 0xff;
1924
1925                 /*
1926                  * Move on to the next granule.  If we've any remaining
1927                  * bytes to process we'll just continue in our loop...
1928                  */
1929                 rxdata += SR_BUF_SIZ;
1930                 rxdesc++;
1931
1932                 if (rxdata == rxmax) {  /* handle the wrap point */
1933                         rxdata = sc->rxstart;
1934                         rxdesc = (sca_descriptor *)
1935                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1936                 }
1937         }
1938 }
1939
1940 /*
1941  * If single is set, just eat a packet. Otherwise eat everything up to
1942  * where cda points. Update pointers to point to the next packet.
1943  *
1944  * This handles "flushing" of a packet as received...
1945  *
1946  * If the "single" parameter is zero, all pending reeceive traffic will
1947  * be flushed out of existence.  A non-zero value will only drop the
1948  * *next* (currently) pending packet...
1949  */
1950 static void
1951 sr_eat_packet(struct sr_softc *sc, int single)
1952 {
1953         struct sr_hardc *hc;
1954         sca_descriptor *rxdesc; /* current descriptor being eval'd */
1955         sca_descriptor *endp;   /* last descriptor in chain */
1956         sca_descriptor *cda;    /* current start point */
1957         u_int loopcnt = 0;      /* count of packets flushed ??? */
1958         u_char stat;            /* captured status byte from descr */
1959
1960         hc = sc->hc;
1961         cda = (sca_descriptor *)(hc->mem_start +
1962                                  (SRC_GET16(hc->sca_base,
1963                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) &
1964                                   hc->winmsk));
1965
1966         /*
1967          * loop until desc->stat == (0xff || EOM) Clear the status and
1968          * length in the descriptor. Increment the descriptor.
1969          */
1970         if (hc->mempages)
1971                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1972
1973         rxdesc = (sca_descriptor *)
1974             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1975         endp = rxdesc;
1976         rxdesc = &rxdesc[sc->rxhind];
1977         endp = &endp[sc->rxmax];
1978
1979         /*
1980          * allow loop, but abort it if we wrap completely...
1981          */
1982         while (rxdesc != cda) {
1983                 loopcnt++;
1984
1985                 if (loopcnt > sc->rxmax) {
1986                         printf("sr%d: eat pkt %d loop, cda %x, "
1987                                "rxdesc %x, stat %x.\n",
1988                                sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc,
1989                                rxdesc->stat);
1990                         break;
1991                 }
1992                 stat = rxdesc->stat;
1993
1994                 rxdesc->len = 0;
1995                 rxdesc->stat = 0xff;
1996
1997                 rxdesc++;
1998                 sc->rxhind++;
1999
2000                 if (rxdesc == endp) {
2001                         rxdesc = (sca_descriptor *)
2002                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
2003                         sc->rxhind = 0;
2004                 }
2005                 if (single && (stat == SCA_DESC_EOM))
2006                         break;
2007         }
2008
2009         /*
2010          * Update the eda to the previous descriptor.
2011          */
2012         rxdesc = (sca_descriptor *)sc->rxdesc;
2013         rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax];
2014
2015         SRC_PUT16(hc->sca_base,
2016                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2017                   (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff));
2018 }
2019
2020 /*
2021  * While there is packets available in the rx buffer, read them out
2022  * into mbufs and ship them off.
2023  */
2024 static void
2025 sr_get_packets(struct sr_softc *sc)
2026 {
2027         u_char rxstat;          /* acquired status byte */
2028         int i;
2029         int pkts;               /* count of packets found */
2030         int rxndx;              /* rcv buffer index */
2031         int tries;              /* settling time counter */
2032         u_int len;              /* length of pending packet */
2033         struct sr_hardc *hc;    /* card-level information */
2034         sca_descriptor *rxdesc; /* descriptor in memory */
2035 #ifndef NETGRAPH
2036         struct ifnet *ifp;      /* network intf ctl table */
2037 #endif /* NETGRAPH */
2038         struct mbuf *m = NULL;  /* message buffer */
2039
2040 #if BUGGY > 0
2041         printf("sr_get_packets(sc=%08x)\n", sc);
2042 #endif
2043
2044         hc = sc->hc;
2045 #ifndef NETGRAPH
2046         ifp = &sc->ifsppp.pp_if;
2047 #endif /* NETGRAPH */
2048
2049         if (hc->mempages) {
2050                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2051                 SRC_SET_ON(hc->iobase); /* enable shared memory */
2052         }
2053         pkts = 0;               /* reset count of found packets */
2054
2055         /*
2056          * for each complete packet in the receiving pool, process each
2057          * packet...
2058          */
2059         while (sr_packet_avail(sc, &len, &rxstat)) {    /* packet pending? */
2060                 /*
2061                  * I have seen situations where we got the interrupt but the
2062                  * status value wasn't deposited.  This code should allow
2063                  * the status byte's value to settle...
2064                  */
2065
2066                 tries = 5;
2067
2068                 while ((rxstat == 0x00ff)
2069                        && --tries)
2070                         sr_packet_avail(sc, &len, &rxstat);
2071
2072 #if BUGGY > 1
2073                 printf("sr_packet_avail() returned len=%d, rxstat=%02ux\n",
2074                        len, rxstat);
2075 #endif
2076
2077                 pkts++;
2078 #ifdef NETGRAPH
2079                 sc->inbytes += len;
2080                 sc->inlast = 0;
2081 #endif /* NETGRAPH */
2082
2083                 /*
2084                  * OK, we've settled the incoming message status. We can now
2085                  * process it...
2086                  */
2087                 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
2088 #if BUGGY > 1
2089                         printf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n",
2090                                sc->unit, rxstat, len);
2091 #endif
2092
2093                         MGETHDR(m, M_DONTWAIT, MT_DATA);
2094                         if (m == NULL) {
2095                                 /*
2096                                  * eat (flush) packet if get mbuf fail!!
2097                                  */
2098                                 sr_eat_packet(sc, 1);
2099                                 continue;
2100                         }
2101                         /*
2102                          * construct control information for pass-off
2103                          */
2104 #ifndef NETGRAPH
2105                         m->m_pkthdr.rcvif = ifp;
2106 #else
2107                         m->m_pkthdr.rcvif = NULL;
2108 #endif /* NETGRAPH */
2109                         m->m_pkthdr.len = m->m_len = len;
2110                         if (len > MHLEN) {
2111                                 MCLGET(m, M_DONTWAIT);
2112                                 if ((m->m_flags & M_EXT) == 0) {
2113                                         /*
2114                                          * We couldn't get a big enough
2115                                          * message packet, so we'll send the
2116                                          * packet to /dev/null...
2117                                          */
2118                                         m_freem(m);
2119                                         sr_eat_packet(sc, 1);
2120                                         continue;
2121                                 }
2122                         }
2123                         /*
2124                          * OK, we've got a good message buffer.  Now we can
2125                          * copy the received message into it
2126                          */
2127                         sr_copy_rxbuf(m, sc, len);      /* copy from DPRAM */
2128
2129 #ifndef NETGRAPH
2130                         if (ifp->if_bpf)
2131                                 bpf_mtap(ifp, m);
2132
2133 #if BUGGY > 3
2134                         {
2135                                 u_char *bp;
2136
2137                                 bp = (u_char *)m;
2138                                 printf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n",
2139                                        sc->unit,
2140                                        bp[0], bp[1], bp[2],
2141                                        bp[4], bp[5], bp[6]);
2142                         }
2143 #endif
2144                         sppp_input(ifp, m);
2145                         ifp->if_ipackets++;
2146
2147 #else   /* NETGRAPH */
2148 #if BUGGY > 3
2149                         {
2150                                 u_char *bp;
2151
2152                                 bp = mtod(m,u_char *);
2153                                 printf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x",
2154                                        sc->unit,
2155                                        bp[0], bp[1], bp[2],
2156                                        bp[4], bp[5], bp[6]);
2157                                 printf(":%02x:%02x:%02x:%02x:%02x:%02x\n",
2158                                        bp[6], bp[7], bp[8],
2159                                        bp[9], bp[10], bp[11]);
2160                         }
2161 #endif
2162                         ng_queue_data(sc->hook, m, NULL);
2163                         sc->ipackets++;
2164 #endif /* NETGRAPH */
2165                         /*
2166                          * Update the eda to the previous descriptor.
2167                          */
2168                         i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ;
2169                         sc->rxhind = (sc->rxhind + i) % sc->rxmax;
2170
2171                         rxdesc = (sca_descriptor *)sc->rxdesc;
2172                         rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax;
2173                         rxdesc = &rxdesc[rxndx];
2174
2175                         SRC_PUT16(hc->sca_base,
2176                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2177                                   (u_short)((u_int)(rxdesc + hc->mem_pstart)
2178                                              & 0xffff));
2179
2180                 } else {
2181                         int got_st3, got_cda, got_eda;
2182                         int tries = 5;
2183
2184                         while ((rxstat == 0xff) && --tries)
2185                                 sr_packet_avail(sc, &len, &rxstat);
2186
2187                         /*
2188                          * It look like we get an interrupt early
2189                          * sometimes and then the status is not
2190                          * filled in yet.
2191                          */
2192                         if (tries && (tries != 5))
2193                                 continue;
2194
2195                         /*
2196                          * This chunk of code handles the error packets.
2197                          * We'll log them for posterity...
2198                          */
2199                         sr_eat_packet(sc, 1);
2200
2201 #ifndef NETGRAPH
2202                         ifp->if_ierrors++;
2203 #else
2204                         sc->ierrors[0]++;
2205 #endif /* NETGRAPH */
2206
2207                         got_st3 = SRC_GET8(hc->sca_base,
2208                                   hc->sca->msci[sc->scachan].st3);
2209                         got_cda = SRC_GET16(hc->sca_base,
2210                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda);
2211                         got_eda = SRC_GET16(hc->sca_base,
2212                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda);
2213
2214 #if BUGGY > 0
2215                         printf("sr%d: Receive error chan %d, "
2216                                "stat %02x, msci st3 %02x,"
2217                                "rxhind %d, cda %04x, eda %04x.\n",
2218                                sc->unit, sc->scachan, rxstat,
2219                                got_st3, sc->rxhind, got_cda, got_eda);
2220 #endif
2221                 }
2222         }
2223
2224 #if BUGGY > 0
2225         printf("sr%d: sr_get_packets() found %d packet(s)\n",
2226                sc->unit, pkts);
2227 #endif
2228
2229         if (hc->mempages)
2230                 SRC_SET_OFF(hc->iobase);
2231 }
2232
2233 /*
2234  * All DMA interrupts come here.
2235  *
2236  * Each channel has two interrupts.
2237  * Interrupt A for errors and Interrupt B for normal stuff like end
2238  * of transmit or receive dmas.
2239  */
2240 static void
2241 sr_dmac_intr(struct sr_hardc *hc, u_char isr1)
2242 {
2243         u_char dsr;             /* contents of DMA Stat Reg */
2244         u_char dotxstart;       /* enables for tranmit part */
2245         int mch;                /* channel being processed */
2246         struct sr_softc *sc;    /* channel's softc structure */
2247         sca_regs *sca = hc->sca;
2248         dmac_channel *dmac;     /* dma structure of chip */
2249
2250 #if BUGGY > 0
2251         printf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1);
2252 #endif
2253
2254         mch = 0;                /* assume chan0 on card */
2255         dotxstart = isr1;       /* copy for xmitter starts */
2256
2257         /*
2258          * Shortcut if there is no interrupts for dma channel 0 or 1.
2259          * Skip processing for channel 0 if no incoming hit
2260          */
2261         if ((isr1 & 0x0F) == 0) {
2262                 mch = 1;
2263                 isr1 >>= 4;
2264         }
2265         do {
2266                 sc = &hc->sc[mch];
2267
2268                 /*
2269                  * Transmit channel - DMA Status Register Evaluation
2270                  */
2271                 if (isr1 & 0x0C) {
2272                         dmac = &sca->dmac[DMAC_TXCH(mch)];
2273
2274                         /*
2275                          * get the DMA Status Register contents and write
2276                          * back to reset interrupt...
2277                          */
2278                         dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2279                         SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2280
2281                         /*
2282                          * Check for (& process) a Counter overflow
2283                          */
2284                         if (dsr & SCA_DSR_COF) {
2285                                 printf("sr%d: TX DMA Counter overflow, "
2286                                        "txpacket no %lu.\n",
2287 #ifndef NETGRAPH
2288                                        sc->unit, sc->ifsppp.pp_if.if_opackets);
2289                                 sc->ifsppp.pp_if.if_oerrors++;
2290 #else
2291                                        sc->unit, sc->opackets);
2292                                 sc->oerrors++;
2293 #endif /* NETGRAPH */
2294                         }
2295                         /*
2296                          * Check for (& process) a Buffer overflow
2297                          */
2298                         if (dsr & SCA_DSR_BOF) {
2299                                 printf("sr%d: TX DMA Buffer overflow, "
2300                                        "txpacket no %lu, dsr %02x, "
2301                                        "cda %04x, eda %04x.\n",
2302 #ifndef NETGRAPH
2303                                        sc->unit, sc->ifsppp.pp_if.if_opackets,
2304 #else
2305                                        sc->unit, sc->opackets,
2306 #endif /* NETGRAPH */
2307                                        dsr,
2308                                        SRC_GET16(hc->sca_base, dmac->cda),
2309                                        SRC_GET16(hc->sca_base, dmac->eda));
2310 #ifndef NETGRAPH
2311                                 sc->ifsppp.pp_if.if_oerrors++;
2312 #else
2313                                 sc->oerrors++;
2314 #endif /* NETGRAPH */
2315                         }
2316                         /*
2317                          * Check for (& process) an End of Transfer (OK)
2318                          */
2319                         if (dsr & SCA_DSR_EOT) {
2320                                 /*
2321                                  * This should be the most common case.
2322                                  *
2323                                  * Clear the IFF_OACTIVE flag.
2324                                  *
2325                                  * Call srstart to start a new transmit if
2326                                  * there is data to transmit.
2327                                  */
2328 #if BUGGY > 0
2329                                 printf("sr%d: TX Completed OK\n", sc->unit);
2330 #endif
2331                                 sc->xmit_busy = 0;
2332 #ifndef NETGRAPH
2333                                 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
2334                                 sc->ifsppp.pp_if.if_timer = 0;
2335 #else
2336                                 /* XXX may need to mark tx inactive? */
2337                                 sc->out_deficit++;
2338                                 sc->out_dog = DOG_HOLDOFF;
2339 #endif /* NETGRAPH */
2340
2341                                 if (sc->txb_inuse && --sc->txb_inuse)
2342                                         sr_xmit(sc);
2343                         }
2344                 }
2345                 /*
2346                  * Receive channel processing of DMA Status Register
2347                  */
2348                 if (isr1 & 0x03) {
2349                         dmac = &sca->dmac[DMAC_RXCH(mch)];
2350
2351                         dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2352                         SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2353
2354                         /*
2355                          * End of frame processing (MSG OK?)
2356                          */
2357                         if (dsr & SCA_DSR_EOM) {
2358 #if BUGGY > 0
2359                                 int tt, ind;
2360
2361 #ifndef NETGRAPH
2362                                 tt = sc->ifsppp.pp_if.if_ipackets;
2363 #else   /* NETGRAPH */
2364                                 tt = sc->ipackets;
2365 #endif /* NETGRAPH */
2366                                 ind = sc->rxhind;
2367 #endif
2368
2369                                 sr_get_packets(sc);
2370 #if BUGGY > 0
2371 #ifndef NETGRAPH
2372                                 if (tt == sc->ifsppp.pp_if.if_ipackets)
2373 #else   /* NETGRAPH */
2374                                 if (tt == sc->ipackets)
2375 #endif /* NETGRAPH */
2376                                 {
2377                                         sca_descriptor *rxdesc;
2378                                         int i;
2379
2380                                         printf("SR: RXINTR isr1 %x, dsr %x, "
2381                                                "no data %d pkts, orxind %d.\n",
2382                                                dotxstart, dsr, tt, ind);
2383                                         printf("SR: rxdesc %x, rxstart %x, "
2384                                                "rxend %x, rxhind %d, "
2385                                                "rxmax %d.\n",
2386                                                sc->rxdesc, sc->rxstart,
2387                                                sc->rxend, sc->rxhind,
2388                                                sc->rxmax);
2389                                         printf("SR: cda %x, eda %x.\n",
2390                                             SRC_GET16(hc->sca_base, dmac->cda),
2391                                             SRC_GET16(hc->sca_base, dmac->eda));
2392
2393                                         if (hc->mempages) {
2394                                                 SRC_SET_ON(hc->iobase);
2395                                                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2396                                         }
2397                                         rxdesc = (sca_descriptor *)
2398                                                  (hc->mem_start +
2399                                                   (sc->rxdesc & hc->winmsk));
2400                                         rxdesc = &rxdesc[sc->rxhind];
2401
2402                                         for (i = 0; i < 3; i++, rxdesc++)
2403                                                 printf("SR: rxdesc->stat %x, "
2404                                                        "len %d.\n",
2405                                                        rxdesc->stat,
2406                                                        rxdesc->len);
2407
2408                                         if (hc->mempages)
2409                                                 SRC_SET_OFF(hc->iobase);
2410                                 }
2411 #endif /* BUGGY */
2412                         }
2413                         /*
2414                          * Check for Counter overflow
2415                          */
2416                         if (dsr & SCA_DSR_COF) {
2417                                 printf("sr%d: RX DMA Counter overflow, "
2418                                        "rxpkts %lu.\n",
2419 #ifndef NETGRAPH
2420                                        sc->unit, sc->ifsppp.pp_if.if_ipackets);
2421                                 sc->ifsppp.pp_if.if_ierrors++;
2422 #else   /* NETGRAPH */
2423                                        sc->unit, sc->ipackets);
2424                                 sc->ierrors[1]++;
2425 #endif /* NETGRAPH */
2426                         }
2427                         /*
2428                          * Check for Buffer overflow
2429                          */
2430                         if (dsr & SCA_DSR_BOF) {
2431                                 printf("sr%d: RX DMA Buffer overflow, "
2432                                        "rxpkts %lu, rxind %d, "
2433                                        "cda %x, eda %x, dsr %x.\n",
2434 #ifndef NETGRAPH
2435                                        sc->unit, sc->ifsppp.pp_if.if_ipackets,
2436 #else   /* NETGRAPH */
2437                                        sc->unit, sc->ipackets,
2438 #endif /* NETGRAPH */
2439                                        sc->rxhind,
2440                                        SRC_GET16(hc->sca_base, dmac->cda),
2441                                        SRC_GET16(hc->sca_base, dmac->eda),
2442                                        dsr);
2443
2444                                 /*
2445                                  * Make sure we eat as many as possible.
2446                                  * Then get the system running again.
2447                                  */
2448                                 if (hc->mempages)
2449                                         SRC_SET_ON(hc->iobase);
2450
2451                                 sr_eat_packet(sc, 0);
2452 #ifndef NETGRAPH
2453                                 sc->ifsppp.pp_if.if_ierrors++;
2454 #else   /* NETGRAPH */
2455                                 sc->ierrors[2]++;
2456 #endif /* NETGRAPH */
2457
2458                                 SRC_PUT8(hc->sca_base,
2459                                          sca->msci[mch].cmd,
2460                                          SCA_CMD_RXMSGREJ);
2461
2462                                 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
2463
2464 #if BUGGY > 0
2465                                 printf("sr%d: RX DMA Buffer overflow, "
2466                                        "rxpkts %lu, rxind %d, "
2467                                        "cda %x, eda %x, dsr %x. After\n",
2468                                        sc->unit,
2469 #ifndef NETGRAPH
2470                                        sc->ipackets,
2471 #else   /* NETGRAPH */
2472                                        sc->ifsppp.pp_if.if_ipackets,
2473 #endif /* NETGRAPH */
2474                                        sc->rxhind,
2475                                        SRC_GET16(hc->sca_base, dmac->cda),
2476                                        SRC_GET16(hc->sca_base, dmac->eda),
2477                                        SRC_GET8(hc->sca_base, dmac->dsr));
2478 #endif
2479
2480                                 if (hc->mempages)
2481                                         SRC_SET_OFF(hc->iobase);
2482                         }
2483                         /*
2484                          * End of Transfer
2485                          */
2486                         if (dsr & SCA_DSR_EOT) {
2487                                 /*
2488                                  * If this happen, it means that we are
2489                                  * receiving faster than what the processor
2490                                  * can handle.
2491                                  *
2492                                  * XXX We should enable the dma again.
2493                                  */
2494                                 printf("sr%d: RX End of xfer, rxpkts %lu.\n",
2495                                        sc->unit,
2496 #ifndef NETGRAPH
2497                                        sc->ifsppp.pp_if.if_ipackets);
2498                                 sc->ifsppp.pp_if.if_ierrors++;
2499 #else
2500                                        sc->ipackets);
2501                                 sc->ierrors[3]++;
2502 #endif /* NETGRAPH */
2503                         }
2504                 }
2505                 isr1 >>= 4;     /* process next half of ISR */
2506                 mch++;          /* and move to next channel */
2507         } while ((mch < NCHAN) && isr1);        /* loop for each chn */
2508
2509         /*
2510          * Now that we have done all the urgent things, see if we can fill
2511          * the transmit buffers.
2512          */
2513         for (mch = 0; mch < NCHAN; mch++) {
2514                 if (dotxstart & 0x0C) { /* TX initiation enabled? */
2515                         sc = &hc->sc[mch];
2516 #ifndef NETGRAPH
2517                         srstart(&sc->ifsppp.pp_if);
2518 #else
2519                         srstart(sc);
2520 #endif /* NETGRAPH */
2521                 }
2522                 dotxstart >>= 4;/* shift for next channel */
2523         }
2524 }
2525 #ifndef NETGRAPH
2526 #ifdef USE_MODEMCK
2527 /*
2528  * Perform timeout on an FR channel
2529  *
2530  * Establish a periodic check of open N2 ports;  If
2531  * a port is open/active, its DCD state is checked
2532  * and a loss of DCD is recognized (and eventually
2533  * processed).
2534  */
2535 static void
2536 sr_modemck(void *arg)
2537 {
2538         u_int s;
2539         int card;               /* card index in table */
2540         int cards;              /* card list index */
2541         int mch;                /* channel on card */
2542         u_char dcd_v;           /* Data Carrier Detect */
2543         u_char got_st0;         /* contents of ST0 */
2544         u_char got_st1;         /* contents of ST1 */
2545         u_char got_st2;         /* contents of ST2 */
2546         u_char got_st3;         /* contents of ST3 */
2547         struct sr_hardc *hc;    /* card's configuration */
2548         struct sr_hardc *Card[16];/* up to 16 cards in system */
2549         struct sr_softc *sc;    /* channel's softc structure */
2550         struct ifnet *ifp;      /* interface control table */
2551         msci_channel *msci;     /* regs specific to channel */
2552
2553         s = splimp();
2554
2555 #if     0
2556         if (sr_opens == 0) {    /* count of "up" channels */
2557                 sr_watcher = 0; /* indicate no watcher */
2558                 splx(s);
2559                 return;
2560         }
2561 #endif
2562
2563         sr_watcher = 1;         /* mark that we're online */
2564
2565         /*
2566          * Now we'll need a list of cards to process.  Since we can handle
2567          * both ISA and PCI cards (and I didn't think of making this logic
2568          * global YET) we'll generate a single table of card table
2569          * addresses.
2570          */
2571         cards = 0;
2572
2573         for (card = 0; card < NSR; card++) {
2574                 hc = &sr_hardc[card];
2575
2576                 if (hc->sc == (void *)0)
2577                         continue;
2578
2579                 Card[cards++] = hc;
2580         }
2581
2582         hc = sr_hardc_pci;
2583
2584         while (hc) {
2585                 Card[cards++] = hc;
2586                 hc = hc->next;
2587         }
2588
2589         /*
2590          * OK, we've got work we can do.  Let's do it... (Please note that
2591          * this code _only_ deals w/ ISA cards)
2592          */
2593         for (card = 0; card < cards; card++) {
2594                 hc = Card[card];/* get card table */
2595
2596                 for (mch = 0; mch < hc->numports; mch++) {
2597                         sc = &hc->sc[mch];
2598
2599                         ifp = &sc->ifsppp.pp_if;
2600
2601                         /*
2602                          * if this channel isn't "up", skip it
2603                          */
2604                         if ((ifp->if_flags & IFF_UP) == 0)
2605                                 continue;
2606
2607                         /*
2608                          * OK, now we can go looking at this channel's
2609                          * actual register contents...
2610                          */
2611                         msci = &hc->sca->msci[sc->scachan];
2612
2613                         /*
2614                          * OK, now we'll look into the actual status of this
2615                          * channel...
2616                          *
2617                          * I suck in more registers than strictly needed
2618                          */
2619                         got_st0 = SRC_GET8(hc->sca_base, msci->st0);
2620                         got_st1 = SRC_GET8(hc->sca_base, msci->st1);
2621                         got_st2 = SRC_GET8(hc->sca_base, msci->st2);
2622                         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2623
2624                         /*
2625                          * We want to see if the DCD signal is up (DCD is
2626                          * true if zero)
2627                          */
2628                         dcd_v = (got_st3 & SCA_ST3_DCD) == 0;
2629
2630                         if (dcd_v == 0)
2631                                 printf("sr%d: DCD lost\n", sc->unit);
2632                 }
2633         }
2634
2635         /*
2636          * OK, now set up for the next modem signal checking pass...
2637          */
2638         timeout(sr_modemck, NULL, hz);
2639
2640         splx(s);
2641 }
2642 #endif
2643 #else   /* NETGRAPH */
2644 /*
2645  * If a port is open/active, it's DCD state is checked
2646  * and a loss of DCD is recognized (and eventually processed?).
2647  */
2648 static void
2649 sr_modemck(struct sr_softc *sc )
2650 {
2651         u_int s;
2652         u_char got_st3;                 /* contents of ST3 */
2653         struct sr_hardc *hc = sc->hc;   /* card's configuration */
2654         msci_channel *msci;             /* regs specific to channel */
2655
2656         s = splimp();
2657
2658
2659         if (sc->running == 0)
2660                 return;
2661         /*
2662          * OK, now we can go looking at this channel's register contents...
2663          */
2664         msci = &hc->sca->msci[sc->scachan];
2665         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2666
2667         /*
2668          * We want to see if the DCD signal is up (DCD is true if zero)
2669          */
2670         sc->dcd = (got_st3 & SCA_ST3_DCD) == 0;
2671         splx(s);
2672 }
2673
2674 #endif  /* NETGRAPH */
2675 static void
2676 sr_msci_intr(struct sr_hardc *hc, u_char isr0)
2677 {
2678         printf("src%d: SRINTR: MSCI\n", hc->cunit);
2679 }
2680
2681 static void
2682 sr_timer_intr(struct sr_hardc *hc, u_char isr2)
2683 {
2684         printf("src%d: SRINTR: TIMER\n", hc->cunit);
2685 }
2686
2687 #ifdef  NETGRAPH
2688 /*****************************************
2689  * Device timeout/watchdog routine.
2690  * called once per second.
2691  * checks to see that if activity was expected, that it hapenned.
2692  * At present we only look to see if expected output was completed.
2693  */
2694 static void
2695 ngsr_watchdog_frame(void * arg)
2696 {
2697         struct sr_softc * sc = arg;
2698         int s;
2699         int     speed;
2700
2701         if (sc->running == 0)
2702                 return; /* if we are not running let timeouts die */
2703         /*
2704          * calculate the apparent throughputs
2705          *  XXX a real hack
2706          */
2707         s = splimp();
2708         speed = sc->inbytes - sc->lastinbytes;
2709         sc->lastinbytes = sc->inbytes;
2710         if ( sc->inrate < speed )
2711                 sc->inrate = speed;
2712         speed = sc->outbytes - sc->lastoutbytes;
2713         sc->lastoutbytes = sc->outbytes;
2714         if ( sc->outrate < speed )
2715                 sc->outrate = speed;
2716         sc->inlast++;
2717         splx(s);
2718
2719         if ((sc->inlast > QUITE_A_WHILE)
2720         && (sc->out_deficit > LOTS_OF_PACKETS)) {
2721                 log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit);
2722                 s = splimp();
2723                 sr_down(sc);
2724                 sr_up(sc);
2725                 sc->inlast = sc->out_deficit = 0;
2726                 splx(s);
2727         } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2728                 if (sc->out_dog == 0) {
2729                         log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n",
2730                                         sc->unit);
2731                         s = splimp();
2732                         srwatchdog(sc);
2733 #if 0
2734                         sr_down(sc);
2735                         sr_up(sc);
2736 #endif
2737                         splx(s);
2738                         sc->inlast = sc->out_deficit = 0;
2739                 } else {
2740                         sc->out_dog--;
2741                 }
2742         }
2743         sr_modemck(sc);         /* update the DCD status */
2744         sc->handle = timeout(ngsr_watchdog_frame, sc, hz);
2745 }
2746
2747 /***********************************************************************
2748  * This section contains the methods for the Netgraph interface
2749  ***********************************************************************/
2750 /*
2751  * It is not possible or allowable to create a node of this type.
2752  * If the hardware exists, it will already have created it.
2753  */
2754 static  int
2755 ngsr_constructor(node_p *nodep)
2756 {
2757         return (EINVAL);
2758 }
2759
2760 /*
2761  * give our ok for a hook to be added...
2762  * If we are not running this should kick the device into life.
2763  * The hook's private info points to our stash of info about that
2764  * channel.
2765  */
2766 static int
2767 ngsr_newhook(node_p node, hook_p hook, const char *name)
2768 {
2769         struct sr_softc *       sc = node->private;
2770
2771         /*
2772          * check if it's our friend the debug hook
2773          */
2774         if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) {
2775                 hook->private = NULL; /* paranoid */
2776                 sc->debug_hook = hook;
2777                 return (0);
2778         }
2779
2780         /*
2781          * Check for raw mode hook.
2782          */
2783         if (strcmp(name, NG_SR_HOOK_RAW) != 0) {
2784                 return (EINVAL);
2785         }
2786         hook->private = sc;
2787         sc->hook = hook;
2788         sc->datahooks++;
2789         sr_up(sc);
2790         return (0);
2791 }
2792
2793 /*
2794  * incoming messages.
2795  * Just respond to the generic TEXT_STATUS message
2796  */
2797 static  int
2798 ngsr_rcvmsg(node_p node,
2799         struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
2800 {
2801         struct sr_softc *       sc;
2802         int error = 0;
2803
2804         sc = node->private;
2805         switch (msg->header.typecookie) {
2806             case        NG_SR_COOKIE:
2807                 error = EINVAL;
2808                 break;
2809             case        NGM_GENERIC_COOKIE:
2810                 switch(msg->header.cmd) {
2811                     case NGM_TEXT_STATUS: {
2812                             char        *arg;
2813                             int pos = 0;
2814                             int resplen = sizeof(struct ng_mesg) + 512;
2815                             MALLOC(*resp, struct ng_mesg *, resplen,
2816                                         M_NETGRAPH, M_NOWAIT | M_ZERO);
2817                             if (*resp == NULL) {
2818                                 error = ENOMEM;
2819                                 break;
2820                             }
2821                             arg = (*resp)->data;
2822
2823                             /*
2824                              * Put in the throughput information.
2825                              */
2826                             pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2827                             "highest rate seen: %ld B/S in, %ld B/S out\n",
2828                             sc->inbytes, sc->outbytes,
2829                             sc->inrate, sc->outrate);
2830                             pos += sprintf(arg + pos,
2831                                 "%ld output errors\n",
2832                                 sc->oerrors);
2833                             pos += sprintf(arg + pos,
2834                                 "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n",
2835                                 sc->ierrors[0],
2836                                 sc->ierrors[1],
2837                                 sc->ierrors[2],
2838                                 sc->ierrors[3],
2839                                 sc->ierrors[4],
2840                                 sc->ierrors[5]);
2841
2842                             (*resp)->header.version = NG_VERSION;
2843                             (*resp)->header.arglen = strlen(arg) + 1;
2844                             (*resp)->header.token = msg->header.token;
2845                             (*resp)->header.typecookie = NG_SR_COOKIE;
2846                             (*resp)->header.cmd = msg->header.cmd;
2847                             strncpy((*resp)->header.cmdstr, "status",
2848                                         NG_CMDSTRLEN);
2849                         }
2850                         break;
2851                     default:
2852                         error = EINVAL;
2853                         break;
2854                     }
2855                 break;
2856             default:
2857                 error = EINVAL;
2858                 break;
2859         }
2860         free(msg, M_NETGRAPH);
2861         return (error);
2862 }
2863
2864 /*
2865  * get data from another node and transmit it to the correct channel
2866  */
2867 static  int
2868 ngsr_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2869 {
2870         int s;
2871         int error = 0;
2872         struct sr_softc * sc = hook->node->private;
2873         struct ifqueue  *xmitq_p;
2874
2875         /*
2876          * data doesn't come in from just anywhere (e.g control hook)
2877          */
2878         if ( hook->private == NULL) {
2879                 error = ENETDOWN;
2880                 goto bad;
2881         }
2882
2883         /*
2884          * Now queue the data for when it can be sent
2885          */
2886         if (meta && meta->priority > 0) {
2887                 xmitq_p = (&sc->xmitq_hipri);
2888         } else {
2889                 xmitq_p = (&sc->xmitq);
2890         }
2891         s = splimp();
2892         if (IF_QFULL(xmitq_p)) {
2893                 IF_DROP(xmitq_p);
2894                 splx(s);
2895                 error = ENOBUFS;
2896                 goto bad;
2897         }
2898         IF_ENQUEUE(xmitq_p, m);
2899         srstart(sc);
2900         splx(s);
2901         return (0);
2902
2903 bad:
2904         /*
2905          * It was an error case.
2906          * check if we need to free the mbuf, and then return the error
2907          */
2908         NG_FREE_DATA(m, meta);
2909         return (error);
2910 }
2911
2912 /*
2913  * do local shutdown processing..
2914  * this node will refuse to go away, unless the hardware says to..
2915  * don't unref the node, or remove our name. just clear our links up.
2916  */
2917 static  int
2918 ngsr_rmnode(node_p node)
2919 {
2920         struct sr_softc * sc = node->private;
2921
2922         sr_down(sc);
2923         ng_cutlinks(node);
2924         node->flags &= ~NG_INVALID; /* bounce back to life */
2925         return (0);
2926 }
2927
2928 /* already linked */
2929 static  int
2930 ngsr_connect(hook_p hook)
2931 {
2932         /* be really amiable and just say "YUP that's OK by me! " */
2933         return (0);
2934 }
2935
2936 /*
2937  * notify on hook disconnection (destruction)
2938  *
2939  * Invalidate the private data associated with this dlci.
2940  * For this type, removal of the last link resets tries to destroy the node.
2941  * As the device still exists, the shutdown method will not actually
2942  * destroy the node, but reset the device and leave it 'fresh' :)
2943  *
2944  * The node removal code will remove all references except that owned by the
2945  * driver.
2946  */
2947 static  int
2948 ngsr_disconnect(hook_p hook)
2949 {
2950         struct sr_softc * sc = hook->node->private;
2951         int     s;
2952         /*
2953          * If it's the data hook, then free resources etc.
2954          */
2955         if (hook->private) {
2956                 s = splimp();
2957                 sc->datahooks--;
2958                 if (sc->datahooks == 0)
2959                         sr_down(sc);
2960                 splx(s);
2961         } else {
2962                 sc->debug_hook = NULL;
2963         }
2964         return (0);
2965 }
2966
2967 /*
2968  * called during bootup
2969  * or LKM loading to put this type into the list of known modules
2970  */
2971 static void
2972 ngsr_init(void *ignored)
2973 {
2974         if (ng_newtype(&typestruct))
2975                 printf("ngsr install failed\n");
2976         ngsr_done_init = 1;
2977 }
2978 #endif /* NETGRAPH */
2979
2980 /*
2981  ********************************* END ************************************
2982  */