sys/dev/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *
  28  * $FreeBSD: head/sys/dev/drm2/radeon/r600.c 254885 2013-08-25 19:37:15Z dumbbell $
  29  */
  30
  31 #include <drm/drmP.h>
  32 #include <uapi_drm/radeon_drm.h>
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "radeon_mode.h"
  36 #include "r600d.h"
  37 #include "atom.h"
  38 #include "avivod.h"
  39
  40 #define PFP_UCODE_SIZE 576
  41 #define PM4_UCODE_SIZE 1792
  42 #define RLC_UCODE_SIZE 768
  43 #define R700_PFP_UCODE_SIZE 848
  44 #define R700_PM4_UCODE_SIZE 1360
  45 #define R700_RLC_UCODE_SIZE 1024
  46 #define EVERGREEN_PFP_UCODE_SIZE 1120
  47 #define EVERGREEN_PM4_UCODE_SIZE 1376
  48 #define EVERGREEN_RLC_UCODE_SIZE 768
  49 #define CAYMAN_RLC_UCODE_SIZE 1024
  50 #define ARUBA_RLC_UCODE_SIZE 1536
  51
  52 #ifdef DUMBBELL_WIP
  53 /* Firmware Names */
  54 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  55 MODULE_FIRMWARE("radeon/R600_me.bin");
  56 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV610_me.bin");
  58 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV630_me.bin");
  60 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV620_me.bin");
  62 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV635_me.bin");
  64 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RV670_me.bin");
  66 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RS780_me.bin");
  68 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  69 MODULE_FIRMWARE("radeon/RV770_me.bin");
  70 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  71 MODULE_FIRMWARE("radeon/RV730_me.bin");
  72 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  73 MODULE_FIRMWARE("radeon/RV710_me.bin");
  74 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  75 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  77 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  78 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  80 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  81 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  83 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  84 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  86 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  87 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  88 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  89 MODULE_FIRMWARE("radeon/PALM_me.bin");
  90 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  91 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
  92 MODULE_FIRMWARE("radeon/SUMO_me.bin");
  93 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
  94 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
  95 MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
  96 MODULE_FIRMWARE("radeon/OLAND_me.bin");
  97 MODULE_FIRMWARE("radeon/OLAND_ce.bin");
  98 MODULE_FIRMWARE("radeon/OLAND_mc.bin");
  99 MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
 100 #endif /* DUMBBELL_WIP */
 101
 102 static const u32 crtc_offsets[2] =
 103 {
 104         0,
 105         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
 106 };
 107
 108 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
 109
 110 /* r600,rv610,rv630,rv620,rv635,rv670 */
 111 static void r600_gpu_init(struct radeon_device *rdev);
 112 void r600_irq_disable(struct radeon_device *rdev);
 113 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 114
 115 /**
 116  * r600_get_xclk - get the xclk
 117  *
 118  * @rdev: radeon_device pointer
 119  *
 120  * Returns the reference clock used by the gfx engine
 121  * (r6xx, IGPs, APUs).
 122  */
 123 u32 r600_get_xclk(struct radeon_device *rdev)
 124 {
 125         return rdev->clock.spll.reference_freq;
 126 }
 127
 128 /* get temperature in millidegrees */
 129 int rv6xx_get_temp(struct radeon_device *rdev)
 130 {
 131         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 132                 ASIC_T_SHIFT;
 133         int actual_temp = temp & 0xff;
 134
 135         if (temp & 0x100)
 136                 actual_temp -= 256;
 137
 138         return actual_temp * 1000;
 139 }
 140
 141 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 142 {
 143         int i;
 144
 145         rdev->pm.dynpm_can_upclock = true;
 146         rdev->pm.dynpm_can_downclock = true;
 147
 148         /* power state array is low to high, default is first */
 149         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 150                 int min_power_state_index = 0;
 151
 152                 if (rdev->pm.num_power_states > 2)
 153                         min_power_state_index = 1;
 154
 155                 switch (rdev->pm.dynpm_planned_action) {
 156                 case DYNPM_ACTION_MINIMUM:
 157                         rdev->pm.requested_power_state_index = min_power_state_index;
 158                         rdev->pm.requested_clock_mode_index = 0;
 159                         rdev->pm.dynpm_can_downclock = false;
 160                         break;
 161                 case DYNPM_ACTION_DOWNCLOCK:
 162                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 163                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 164                                 rdev->pm.dynpm_can_downclock = false;
 165                         } else {
 166                                 if (rdev->pm.active_crtc_count > 1) {
 167                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 168                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 169                                                         continue;
 170                                                 else if (i >= rdev->pm.current_power_state_index) {
 171                                                         rdev->pm.requested_power_state_index =
 172                                                                 rdev->pm.current_power_state_index;
 173                                                         break;
 174                                                 } else {
 175                                                         rdev->pm.requested_power_state_index = i;
 176                                                         break;
 177                                                 }
 178                                         }
 179                                 } else {
 180                                         if (rdev->pm.current_power_state_index == 0)
 181                                                 rdev->pm.requested_power_state_index =
 182                                                         rdev->pm.num_power_states - 1;
 183                                         else
 184                                                 rdev->pm.requested_power_state_index =
 185                                                         rdev->pm.current_power_state_index - 1;
 186                                 }
 187                         }
 188                         rdev->pm.requested_clock_mode_index = 0;
 189                         /* don't use the power state if crtcs are active and no display flag is set */
 190                         if ((rdev->pm.active_crtc_count > 0) &&
 191                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 192                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 193                              RADEON_PM_MODE_NO_DISPLAY)) {
 194                                 rdev->pm.requested_power_state_index++;
 195                         }
 196                         break;
 197                 case DYNPM_ACTION_UPCLOCK:
 198                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 199                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 200                                 rdev->pm.dynpm_can_upclock = false;
 201                         } else {
 202                                 if (rdev->pm.active_crtc_count > 1) {
 203                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 204                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 205                                                         continue;
 206                                                 else if (i <= rdev->pm.current_power_state_index) {
 207                                                         rdev->pm.requested_power_state_index =
 208                                                                 rdev->pm.current_power_state_index;
 209                                                         break;
 210                                                 } else {
 211                                                         rdev->pm.requested_power_state_index = i;
 212                                                         break;
 213                                                 }
 214                                         }
 215                                 } else
 216                                         rdev->pm.requested_power_state_index =
 217                                                 rdev->pm.current_power_state_index + 1;
 218                         }
 219                         rdev->pm.requested_clock_mode_index = 0;
 220                         break;
 221                 case DYNPM_ACTION_DEFAULT:
 222                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 223                         rdev->pm.requested_clock_mode_index = 0;
 224                         rdev->pm.dynpm_can_upclock = false;
 225                         break;
 226                 case DYNPM_ACTION_NONE:
 227                 default:
 228                         DRM_ERROR("Requested mode for not defined action\n");
 229                         return;
 230                 }
 231         } else {
 232                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 233                 /* for now just select the first power state and switch between clock modes */
 234                 /* power state array is low to high, default is first (0) */
 235                 if (rdev->pm.active_crtc_count > 1) {
 236                         rdev->pm.requested_power_state_index = -1;
 237                         /* start at 1 as we don't want the default mode */
 238                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 239                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 240                                         continue;
 241                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 242                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 243                                         rdev->pm.requested_power_state_index = i;
 244                                         break;
 245                                 }
 246                         }
 247                         /* if nothing selected, grab the default state. */
 248                         if (rdev->pm.requested_power_state_index == -1)
 249                                 rdev->pm.requested_power_state_index = 0;
 250                 } else
 251                         rdev->pm.requested_power_state_index = 1;
 252
 253                 switch (rdev->pm.dynpm_planned_action) {
 254                 case DYNPM_ACTION_MINIMUM:
 255                         rdev->pm.requested_clock_mode_index = 0;
 256                         rdev->pm.dynpm_can_downclock = false;
 257                         break;
 258                 case DYNPM_ACTION_DOWNCLOCK:
 259                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 260                                 if (rdev->pm.current_clock_mode_index == 0) {
 261                                         rdev->pm.requested_clock_mode_index = 0;
 262                                         rdev->pm.dynpm_can_downclock = false;
 263                                 } else
 264                                         rdev->pm.requested_clock_mode_index =
 265                                                 rdev->pm.current_clock_mode_index - 1;
 266                         } else {
 267                                 rdev->pm.requested_clock_mode_index = 0;
 268                                 rdev->pm.dynpm_can_downclock = false;
 269                         }
 270                         /* don't use the power state if crtcs are active and no display flag is set */
 271                         if ((rdev->pm.active_crtc_count > 0) &&
 272                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 273                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 274                              RADEON_PM_MODE_NO_DISPLAY)) {
 275                                 rdev->pm.requested_clock_mode_index++;
 276                         }
 277                         break;
 278                 case DYNPM_ACTION_UPCLOCK:
 279                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 280                                 if (rdev->pm.current_clock_mode_index ==
 281                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 282                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 283                                         rdev->pm.dynpm_can_upclock = false;
 284                                 } else
 285                                         rdev->pm.requested_clock_mode_index =
 286                                                 rdev->pm.current_clock_mode_index + 1;
 287                         } else {
 288                                 rdev->pm.requested_clock_mode_index =
 289                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 290                                 rdev->pm.dynpm_can_upclock = false;
 291                         }
 292                         break;
 293                 case DYNPM_ACTION_DEFAULT:
 294                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 295                         rdev->pm.requested_clock_mode_index = 0;
 296                         rdev->pm.dynpm_can_upclock = false;
 297                         break;
 298                 case DYNPM_ACTION_NONE:
 299                 default:
 300                         DRM_ERROR("Requested mode for not defined action\n");
 301                         return;
 302                 }
 303         }
 304
 305         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 306                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 307                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 308                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 309                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 310                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 311                   pcie_lanes);
 312 }
 313
 314 void rs780_pm_init_profile(struct radeon_device *rdev)
 315 {
 316         if (rdev->pm.num_power_states == 2) {
 317                 /* default */
 318                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 319                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 320                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 321                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 322                 /* low sh */
 323                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 324                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 325                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 326                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 327                 /* mid sh */
 328                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 329                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 330                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 331                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 332                 /* high sh */
 333                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 334                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 335                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 336                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 337                 /* low mh */
 338                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 339                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 340                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 341                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 342                 /* mid mh */
 343                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 344                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 345                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 346                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 347                 /* high mh */
 348                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 349                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 350                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 351                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 352         } else if (rdev->pm.num_power_states == 3) {
 353                 /* default */
 354                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 355                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 356                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 357                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 358                 /* low sh */
 359                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 360                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 361                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 362                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 363                 /* mid sh */
 364                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 365                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 366                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 367                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 368                 /* high sh */
 369                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 370                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 371                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 372                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 373                 /* low mh */
 374                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 375                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 376                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 377                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 378                 /* mid mh */
 379                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 380                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 381                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 382                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 383                 /* high mh */
 384                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 385                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 386                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 387                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 388         } else {
 389                 /* default */
 390                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 391                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 392                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 393                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 394                 /* low sh */
 395                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 396                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 397                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 398                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 399                 /* mid sh */
 400                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 401                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 402                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 403                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 404                 /* high sh */
 405                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 406                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 407                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 408                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 409                 /* low mh */
 410                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 411                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 412                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 413                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 414                 /* mid mh */
 415                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 416                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 417                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 418                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 419                 /* high mh */
 420                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 421                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 422                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 423                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 424         }
 425 }
 426
 427 void r600_pm_init_profile(struct radeon_device *rdev)
 428 {
 429         int idx;
 430
 431         if (rdev->family == CHIP_R600) {
 432                 /* XXX */
 433                 /* default */
 434                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 435                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 436                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 437                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 438                 /* low sh */
 439                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 440                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 441                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 442                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 443                 /* mid sh */
 444                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 445                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 446                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 447                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 448                 /* high sh */
 449                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 450                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 451                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 452                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 453                 /* low mh */
 454                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 455                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 456                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 457                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 458                 /* mid mh */
 459                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 460                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 461                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 462                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 463                 /* high mh */
 464                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 465                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 466                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 467                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 468         } else {
 469                 if (rdev->pm.num_power_states < 4) {
 470                         /* default */
 471                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 472                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 473                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 474                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 475                         /* low sh */
 476                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 477                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 478                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 479                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 480                         /* mid sh */
 481                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 482                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 483                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 484                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 485                         /* high sh */
 486                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 487                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 488                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 489                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 490                         /* low mh */
 491                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 492                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 493                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 494                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 495                         /* low mh */
 496                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 497                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 498                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 499                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 500                         /* high mh */
 501                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 502                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 503                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 504                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 505                 } else {
 506                         /* default */
 507                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 508                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 509                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 510                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 511                         /* low sh */
 512                         if (rdev->flags & RADEON_IS_MOBILITY)
 513                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 514                         else
 515                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 516                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 517                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 518                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 519                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 520                         /* mid sh */
 521                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 522                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 523                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 524                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 525                         /* high sh */
 526                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 527                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 528                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 529                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 530                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 531                         /* low mh */
 532                         if (rdev->flags & RADEON_IS_MOBILITY)
 533                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 534                         else
 535                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 536                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 537                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 538                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 539                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 540                         /* mid mh */
 541                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 542                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 543                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 544                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 545                         /* high mh */
 546                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 547                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 548                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 549                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 550                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 551                 }
 552         }
 553 }
 554
 555 void r600_pm_misc(struct radeon_device *rdev)
 556 {
 557         int req_ps_idx = rdev->pm.requested_power_state_index;
 558         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 559         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 560         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 561
 562         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 563                 /* 0xff01 is a flag rather then an actual voltage */
 564                 if (voltage->voltage == 0xff01)
 565                         return;
 566                 if (voltage->voltage != rdev->pm.current_vddc) {
 567                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 568                         rdev->pm.current_vddc = voltage->voltage;
 569                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 570                 }
 571         }
 572 }
 573
 574 bool r600_gui_idle(struct radeon_device *rdev)
 575 {
 576         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 577                 return false;
 578         else
 579                 return true;
 580 }
 581
 582 /* hpd for digital panel detect/disconnect */
 583 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 584 {
 585         bool connected = false;
 586
 587         if (ASIC_IS_DCE3(rdev)) {
 588                 switch (hpd) {
 589                 case RADEON_HPD_1:
 590                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 591                                 connected = true;
 592                         break;
 593                 case RADEON_HPD_2:
 594                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 595                                 connected = true;
 596                         break;
 597                 case RADEON_HPD_3:
 598                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 599                                 connected = true;
 600                         break;
 601                 case RADEON_HPD_4:
 602                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 603                                 connected = true;
 604                         break;
 605                         /* DCE 3.2 */
 606                 case RADEON_HPD_5:
 607                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 608                                 connected = true;
 609                         break;
 610                 case RADEON_HPD_6:
 611                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 612                                 connected = true;
 613                         break;
 614                 default:
 615                         break;
 616                 }
 617         } else {
 618                 switch (hpd) {
 619                 case RADEON_HPD_1:
 620                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 621                                 connected = true;
 622                         break;
 623                 case RADEON_HPD_2:
 624                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 625                                 connected = true;
 626                         break;
 627                 case RADEON_HPD_3:
 628                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 629                                 connected = true;
 630                         break;
 631                 default:
 632                         break;
 633                 }
 634         }
 635         return connected;
 636 }
 637
 638 void r600_hpd_set_polarity(struct radeon_device *rdev,
 639                            enum radeon_hpd_id hpd)
 640 {
 641         u32 tmp;
 642         bool connected = r600_hpd_sense(rdev, hpd);
 643
 644         if (ASIC_IS_DCE3(rdev)) {
 645                 switch (hpd) {
 646                 case RADEON_HPD_1:
 647                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 648                         if (connected)
 649                                 tmp &= ~DC_HPDx_INT_POLARITY;
 650                         else
 651                                 tmp |= DC_HPDx_INT_POLARITY;
 652                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 653                         break;
 654                 case RADEON_HPD_2:
 655                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 656                         if (connected)
 657                                 tmp &= ~DC_HPDx_INT_POLARITY;
 658                         else
 659                                 tmp |= DC_HPDx_INT_POLARITY;
 660                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 661                         break;
 662                 case RADEON_HPD_3:
 663                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 664                         if (connected)
 665                                 tmp &= ~DC_HPDx_INT_POLARITY;
 666                         else
 667                                 tmp |= DC_HPDx_INT_POLARITY;
 668                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 669                         break;
 670                 case RADEON_HPD_4:
 671                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 672                         if (connected)
 673                                 tmp &= ~DC_HPDx_INT_POLARITY;
 674                         else
 675                                 tmp |= DC_HPDx_INT_POLARITY;
 676                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 677                         break;
 678                 case RADEON_HPD_5:
 679                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 680                         if (connected)
 681                                 tmp &= ~DC_HPDx_INT_POLARITY;
 682                         else
 683                                 tmp |= DC_HPDx_INT_POLARITY;
 684                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 685                         break;
 686                         /* DCE 3.2 */
 687                 case RADEON_HPD_6:
 688                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 689                         if (connected)
 690                                 tmp &= ~DC_HPDx_INT_POLARITY;
 691                         else
 692                                 tmp |= DC_HPDx_INT_POLARITY;
 693                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 694                         break;
 695                 default:
 696                         break;
 697                 }
 698         } else {
 699                 switch (hpd) {
 700                 case RADEON_HPD_1:
 701                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 702                         if (connected)
 703                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 704                         else
 705                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 706                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 707                         break;
 708                 case RADEON_HPD_2:
 709                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 710                         if (connected)
 711                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 712                         else
 713                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 714                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 715                         break;
 716                 case RADEON_HPD_3:
 717                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 718                         if (connected)
 719                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 720                         else
 721                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 722                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 723                         break;
 724                 default:
 725                         break;
 726                 }
 727         }
 728 }
 729
 730 void r600_hpd_init(struct radeon_device *rdev)
 731 {
 732         struct drm_device *dev = rdev->ddev;
 733         struct drm_connector *connector;
 734         unsigned enable = 0;
 735
 736         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 737                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 738
 739                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 740                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 741                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 742                          * aux dp channel on imac and help (but not completely fix)
 743                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 744                          */
 745                         continue;
 746                 }
 747                 if (ASIC_IS_DCE3(rdev)) {
 748                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 749                         if (ASIC_IS_DCE32(rdev))
 750                                 tmp |= DC_HPDx_EN;
 751
 752                         switch (radeon_connector->hpd.hpd) {
 753                         case RADEON_HPD_1:
 754                                 WREG32(DC_HPD1_CONTROL, tmp);
 755                                 break;
 756                         case RADEON_HPD_2:
 757                                 WREG32(DC_HPD2_CONTROL, tmp);
 758                                 break;
 759                         case RADEON_HPD_3:
 760                                 WREG32(DC_HPD3_CONTROL, tmp);
 761                                 break;
 762                         case RADEON_HPD_4:
 763                                 WREG32(DC_HPD4_CONTROL, tmp);
 764                                 break;
 765                                 /* DCE 3.2 */
 766                         case RADEON_HPD_5:
 767                                 WREG32(DC_HPD5_CONTROL, tmp);
 768                                 break;
 769                         case RADEON_HPD_6:
 770                                 WREG32(DC_HPD6_CONTROL, tmp);
 771                                 break;
 772                         default:
 773                                 break;
 774                         }
 775                 } else {
 776                         switch (radeon_connector->hpd.hpd) {
 777                         case RADEON_HPD_1:
 778                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 779                                 break;
 780                         case RADEON_HPD_2:
 781                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 782                                 break;
 783                         case RADEON_HPD_3:
 784                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 785                                 break;
 786                         default:
 787                                 break;
 788                         }
 789                 }
 790                 enable |= 1 << radeon_connector->hpd.hpd;
 791                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 792         }
 793         radeon_irq_kms_enable_hpd(rdev, enable);
 794 }
 795
 796 void r600_hpd_fini(struct radeon_device *rdev)
 797 {
 798         struct drm_device *dev = rdev->ddev;
 799         struct drm_connector *connector;
 800         unsigned disable = 0;
 801
 802         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 803                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 804                 if (ASIC_IS_DCE3(rdev)) {
 805                         switch (radeon_connector->hpd.hpd) {
 806                         case RADEON_HPD_1:
 807                                 WREG32(DC_HPD1_CONTROL, 0);
 808                                 break;
 809                         case RADEON_HPD_2:
 810                                 WREG32(DC_HPD2_CONTROL, 0);
 811                                 break;
 812                         case RADEON_HPD_3:
 813                                 WREG32(DC_HPD3_CONTROL, 0);
 814                                 break;
 815                         case RADEON_HPD_4:
 816                                 WREG32(DC_HPD4_CONTROL, 0);
 817                                 break;
 818                                 /* DCE 3.2 */
 819                         case RADEON_HPD_5:
 820                                 WREG32(DC_HPD5_CONTROL, 0);
 821                                 break;
 822                         case RADEON_HPD_6:
 823                                 WREG32(DC_HPD6_CONTROL, 0);
 824                                 break;
 825                         default:
 826                                 break;
 827                         }
 828                 } else {
 829                         switch (radeon_connector->hpd.hpd) {
 830                         case RADEON_HPD_1:
 831                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 832                                 break;
 833                         case RADEON_HPD_2:
 834                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 835                                 break;
 836                         case RADEON_HPD_3:
 837                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 838                                 break;
 839                         default:
 840                                 break;
 841                         }
 842                 }
 843                 disable |= 1 << radeon_connector->hpd.hpd;
 844         }
 845         radeon_irq_kms_disable_hpd(rdev, disable);
 846 }
 847
 848 /*
 849  * R600 PCIE GART
 850  */
 851 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 852 {
 853         unsigned i;
 854         u32 tmp;
 855
 856         /* flush hdp cache so updates hit vram */
 857         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 858             !(rdev->flags & RADEON_IS_AGP)) {
 859                 volatile uint32_t *ptr = rdev->gart.ptr;
 860                 u32 tmp;
 861
 862                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 863                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 864                  * This seems to cause problems on some AGP cards. Just use the old
 865                  * method for them.
 866                  */
 867                 WREG32(HDP_DEBUG1, 0);
 868                 tmp = *ptr;
 869         } else
 870                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 871
 872         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 873         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 874         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 875         for (i = 0; i < rdev->usec_timeout; i++) {
 876                 /* read MC_STATUS */
 877                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 878                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 879                 if (tmp == 2) {
 880                         DRM_ERROR("[drm] r600 flush TLB failed\n");
 881                         return;
 882                 }
 883                 if (tmp) {
 884                         return;
 885                 }
 886                 DRM_UDELAY(1);
 887         }
 888 }
 889
 890 int r600_pcie_gart_init(struct radeon_device *rdev)
 891 {
 892         int r;
 893
 894         if (rdev->gart.robj) {
 895                 DRM_ERROR("R600 PCIE GART already initialized\n");
 896                 return 0;
 897         }
 898         /* Initialize common gart structure */
 899         r = radeon_gart_init(rdev);
 900         if (r)
 901                 return r;
 902         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 903         return radeon_gart_table_vram_alloc(rdev);
 904 }
 905
 906 static int r600_pcie_gart_enable(struct radeon_device *rdev)
 907 {
 908         u32 tmp;
 909         int r, i;
 910
 911         if (rdev->gart.robj == NULL) {
 912                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 913                 return -EINVAL;
 914         }
 915         r = radeon_gart_table_vram_pin(rdev);
 916         if (r)
 917                 return r;
 918         radeon_gart_restore(rdev);
 919
 920         /* Setup L2 cache */
 921         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 922                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 923                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 924         WREG32(VM_L2_CNTL2, 0);
 925         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 926         /* Setup TLB control */
 927         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 928                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 929                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 930                 ENABLE_WAIT_L2_QUERY;
 931         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 932         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 933         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 934         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 935         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 936         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 937         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 938         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 939         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 940         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 941         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 942         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 943         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 944         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 945         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 946         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 947         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 948         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 949                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 950         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 951                         (u32)(rdev->dummy_page.addr >> 12));
 952         for (i = 1; i < 7; i++)
 953                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 954
 955         r600_pcie_gart_tlb_flush(rdev);
 956         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 957                  (unsigned)(rdev->mc.gtt_size >> 20),
 958                  (unsigned long long)rdev->gart.table_addr);
 959         rdev->gart.ready = true;
 960         return 0;
 961 }
 962
 963 static void r600_pcie_gart_disable(struct radeon_device *rdev)
 964 {
 965         u32 tmp;
 966         int i;
 967
 968         /* Disable all tables */
 969         for (i = 0; i < 7; i++)
 970                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 971
 972         /* Disable L2 cache */
 973         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 974                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 975         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 976         /* Setup L1 TLB control */
 977         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 978                 ENABLE_WAIT_L2_QUERY;
 979         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 980         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 981         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 982         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 983         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 984         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 985         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 986         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 987         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 988         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 989         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 990         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 991         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 992         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 993         radeon_gart_table_vram_unpin(rdev);
 994 }
 995
 996 static void r600_pcie_gart_fini(struct radeon_device *rdev)
 997 {
 998         radeon_gart_fini(rdev);
 999         r600_pcie_gart_disable(rdev);
1000         radeon_gart_table_vram_free(rdev);
1001 }
1002
1003 static void r600_agp_enable(struct radeon_device *rdev)
1004 {
1005         u32 tmp;
1006         int i;
1007
1008         /* Setup L2 cache */
1009         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1010                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1011                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1012         WREG32(VM_L2_CNTL2, 0);
1013         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1014         /* Setup TLB control */
1015         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1016                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1017                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1018                 ENABLE_WAIT_L2_QUERY;
1019         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1020         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1021         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1022         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1023         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1024         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1025         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1026         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1027         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1028         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1029         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1030         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1031         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1032         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1033         for (i = 0; i < 7; i++)
1034                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1035 }
1036
1037 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1038 {
1039         unsigned i;
1040         u32 tmp;
1041
1042         for (i = 0; i < rdev->usec_timeout; i++) {
1043                 /* read MC_STATUS */
1044                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1045                 if (!tmp)
1046                         return 0;
1047                 DRM_UDELAY(1);
1048         }
1049         return -1;
1050 }
1051
1052 static void r600_mc_program(struct radeon_device *rdev)
1053 {
1054         struct rv515_mc_save save;
1055         u32 tmp;
1056         int i, j;
1057
1058         /* Initialize HDP */
1059         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1060                 WREG32((0x2c14 + j), 0x00000000);
1061                 WREG32((0x2c18 + j), 0x00000000);
1062                 WREG32((0x2c1c + j), 0x00000000);
1063                 WREG32((0x2c20 + j), 0x00000000);
1064                 WREG32((0x2c24 + j), 0x00000000);
1065         }
1066         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1067
1068         rv515_mc_stop(rdev, &save);
1069         if (r600_mc_wait_for_idle(rdev)) {
1070                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1071         }
1072         /* Lockout access through VGA aperture (doesn't exist before R600) */
1073         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1074         /* Update configuration */
1075         if (rdev->flags & RADEON_IS_AGP) {
1076                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1077                         /* VRAM before AGP */
1078                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1079                                 rdev->mc.vram_start >> 12);
1080                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1081                                 rdev->mc.gtt_end >> 12);
1082                 } else {
1083                         /* VRAM after AGP */
1084                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1085                                 rdev->mc.gtt_start >> 12);
1086                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1087                                 rdev->mc.vram_end >> 12);
1088                 }
1089         } else {
1090                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1091                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1092         }
1093         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1094         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1095         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1096         WREG32(MC_VM_FB_LOCATION, tmp);
1097         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1098         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1099         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1100         if (rdev->flags & RADEON_IS_AGP) {
1101                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1102                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1103                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1104         } else {
1105                 WREG32(MC_VM_AGP_BASE, 0);
1106                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1107                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1108         }
1109         if (r600_mc_wait_for_idle(rdev)) {
1110                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1111         }
1112         rv515_mc_resume(rdev, &save);
1113         /* we need to own VRAM, so turn off the VGA renderer here
1114          * to stop it overwriting our objects */
1115         rv515_vga_render_disable(rdev);
1116 }
1117
1118 /**
1119  * r600_vram_gtt_location - try to find VRAM & GTT location
1120  * @rdev: radeon device structure holding all necessary informations
1121  * @mc: memory controller structure holding memory informations
1122  *
1123  * Function will place try to place VRAM at same place as in CPU (PCI)
1124  * address space as some GPU seems to have issue when we reprogram at
1125  * different address space.
1126  *
1127  * If there is not enough space to fit the unvisible VRAM after the
1128  * aperture then we limit the VRAM size to the aperture.
1129  *
1130  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1131  * them to be in one from GPU point of view so that we can program GPU to
1132  * catch access outside them (weird GPU policy see ??).
1133  *
1134  * This function will never fails, worst case are limiting VRAM or GTT.
1135  *
1136  * Note: GTT start, end, size should be initialized before calling this
1137  * function on AGP platform.
1138  */
1139 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1140 {
1141         u64 size_bf, size_af;
1142
1143         if (mc->mc_vram_size > 0xE0000000) {
1144                 /* leave room for at least 512M GTT */
1145                 dev_warn(rdev->dev, "limiting VRAM\n");
1146                 mc->real_vram_size = 0xE0000000;
1147                 mc->mc_vram_size = 0xE0000000;
1148         }
1149         if (rdev->flags & RADEON_IS_AGP) {
1150                 size_bf = mc->gtt_start;
1151                 size_af = 0xFFFFFFFF - mc->gtt_end;
1152                 if (size_bf > size_af) {
1153                         if (mc->mc_vram_size > size_bf) {
1154                                 dev_warn(rdev->dev, "limiting VRAM\n");
1155                                 mc->real_vram_size = size_bf;
1156                                 mc->mc_vram_size = size_bf;
1157                         }
1158                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1159                 } else {
1160                         if (mc->mc_vram_size > size_af) {
1161                                 dev_warn(rdev->dev, "limiting VRAM\n");
1162                                 mc->real_vram_size = size_af;
1163                                 mc->mc_vram_size = size_af;
1164                         }
1165                         mc->vram_start = mc->gtt_end + 1;
1166                 }
1167                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1168                 dev_info(rdev->dev, "VRAM: %juM 0x%08jX - 0x%08jX (%juM used)\n",
1169                                 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
1170                                 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20);
1171         } else {
1172                 u64 base = 0;
1173                 if (rdev->flags & RADEON_IS_IGP) {
1174                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1175                         base <<= 24;
1176                 }
1177                 radeon_vram_location(rdev, &rdev->mc, base);
1178                 rdev->mc.gtt_base_align = 0;
1179                 radeon_gtt_location(rdev, mc);
1180         }
1181 }
1182
1183 static int r600_mc_init(struct radeon_device *rdev)
1184 {
1185         u32 tmp;
1186         int chansize, numchan;
1187
1188         /* Get VRAM informations */
1189         rdev->mc.vram_is_ddr = true;
1190         tmp = RREG32(RAMCFG);
1191         if (tmp & CHANSIZE_OVERRIDE) {
1192                 chansize = 16;
1193         } else if (tmp & CHANSIZE_MASK) {
1194                 chansize = 64;
1195         } else {
1196                 chansize = 32;
1197         }
1198         tmp = RREG32(CHMAP);
1199         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1200         case 0:
1201         default:
1202                 numchan = 1;
1203                 break;
1204         case 1:
1205                 numchan = 2;
1206                 break;
1207         case 2:
1208                 numchan = 4;
1209                 break;
1210         case 3:
1211                 numchan = 8;
1212                 break;
1213         }
1214         rdev->mc.vram_width = numchan * chansize;
1215         /* Could aper size report 0 ? */
1216         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1217         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1218         /* Setup GPU memory space */
1219         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1220         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1221         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1222         r600_vram_gtt_location(rdev, &rdev->mc);
1223
1224         if (rdev->flags & RADEON_IS_IGP) {
1225                 rs690_pm_info(rdev);
1226                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1227         }
1228         radeon_update_bandwidth_info(rdev);
1229         return 0;
1230 }
1231
1232 int r600_vram_scratch_init(struct radeon_device *rdev)
1233 {
1234         int r;
1235         void *vram_scratch_ptr_ptr;
1236
1237         if (rdev->vram_scratch.robj == NULL) {
1238                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1239                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1240                                      NULL, &rdev->vram_scratch.robj);
1241                 if (r) {
1242                         return r;
1243                 }
1244         }
1245
1246         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1247         if (unlikely(r != 0)) {
1248                 radeon_bo_unref(&rdev->vram_scratch.robj);
1249                 return r;
1250         }
1251         r = radeon_bo_pin(rdev->vram_scratch.robj,
1252                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1253         if (r) {
1254                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1255                 radeon_bo_unref(&rdev->vram_scratch.robj);
1256                 return r;
1257         }
1258         vram_scratch_ptr_ptr = &rdev->vram_scratch.ptr;
1259         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1260                                 vram_scratch_ptr_ptr);
1261         if (r)
1262                 radeon_bo_unpin(rdev->vram_scratch.robj);
1263         radeon_bo_unreserve(rdev->vram_scratch.robj);
1264         if (r)
1265                 radeon_bo_unref(&rdev->vram_scratch.robj);
1266
1267         return r;
1268 }
1269
1270 void r600_vram_scratch_fini(struct radeon_device *rdev)
1271 {
1272         int r;
1273
1274         if (rdev->vram_scratch.robj == NULL) {
1275                 return;
1276         }
1277         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1278         if (likely(r == 0)) {
1279                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1280                 radeon_bo_unpin(rdev->vram_scratch.robj);
1281                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1282         }
1283         radeon_bo_unref(&rdev->vram_scratch.robj);
1284 }
1285
1286 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1287 {
1288         u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1289
1290         if (hung)
1291                 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1292         else
1293                 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1294
1295         WREG32(R600_BIOS_3_SCRATCH, tmp);
1296 }
1297
1298 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1299 {
1300         dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
1301                  RREG32(R_008010_GRBM_STATUS));
1302         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
1303                  RREG32(R_008014_GRBM_STATUS2));
1304         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
1305                  RREG32(R_000E50_SRBM_STATUS));
1306         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1307                  RREG32(CP_STALLED_STAT1));
1308         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1309                  RREG32(CP_STALLED_STAT2));
1310         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1311                  RREG32(CP_BUSY_STAT));
1312         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1313                  RREG32(CP_STAT));
1314         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1315                 RREG32(DMA_STATUS_REG));
1316 }
1317
1318 static bool r600_is_display_hung(struct radeon_device *rdev)
1319 {
1320         u32 crtc_hung = 0;
1321         u32 crtc_status[2];
1322         u32 i, j, tmp;
1323
1324         for (i = 0; i < rdev->num_crtc; i++) {
1325                 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1326                         crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1327                         crtc_hung |= (1 << i);
1328                 }
1329         }
1330
1331         for (j = 0; j < 10; j++) {
1332                 for (i = 0; i < rdev->num_crtc; i++) {
1333                         if (crtc_hung & (1 << i)) {
1334                                 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1335                                 if (tmp != crtc_status[i])
1336                                         crtc_hung &= ~(1 << i);
1337                         }
1338                 }
1339                 if (crtc_hung == 0)
1340                         return false;
1341                 DRM_UDELAY(100);
1342         }
1343
1344         return true;
1345 }
1346
1347 static u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1348 {
1349         u32 reset_mask = 0;
1350         u32 tmp;
1351
1352         /* GRBM_STATUS */
1353         tmp = RREG32(R_008010_GRBM_STATUS);
1354         if (rdev->family >= CHIP_RV770) {
1355                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1356                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1357                     G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1358                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1359                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1360                         reset_mask |= RADEON_RESET_GFX;
1361         } else {
1362                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1363                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1364                     G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1365                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1366                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1367                         reset_mask |= RADEON_RESET_GFX;
1368         }
1369
1370         if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1371             G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1372                 reset_mask |= RADEON_RESET_CP;
1373
1374         if (G_008010_GRBM_EE_BUSY(tmp))
1375                 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1376
1377         /* DMA_STATUS_REG */
1378         tmp = RREG32(DMA_STATUS_REG);
1379         if (!(tmp & DMA_IDLE))
1380                 reset_mask |= RADEON_RESET_DMA;
1381
1382         /* SRBM_STATUS */
1383         tmp = RREG32(R_000E50_SRBM_STATUS);
1384         if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1385                 reset_mask |= RADEON_RESET_RLC;
1386
1387         if (G_000E50_IH_BUSY(tmp))
1388                 reset_mask |= RADEON_RESET_IH;
1389
1390         if (G_000E50_SEM_BUSY(tmp))
1391                 reset_mask |= RADEON_RESET_SEM;
1392
1393         if (G_000E50_GRBM_RQ_PENDING(tmp))
1394                 reset_mask |= RADEON_RESET_GRBM;
1395
1396         if (G_000E50_VMC_BUSY(tmp))
1397                 reset_mask |= RADEON_RESET_VMC;
1398
1399         if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1400             G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1401             G_000E50_MCDW_BUSY(tmp))
1402                 reset_mask |= RADEON_RESET_MC;
1403
1404         if (r600_is_display_hung(rdev))
1405                 reset_mask |= RADEON_RESET_DISPLAY;
1406
1407         /* Skip MC reset as it's mostly likely not hung, just busy */
1408         if (reset_mask & RADEON_RESET_MC) {
1409                 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1410                 reset_mask &= ~RADEON_RESET_MC;
1411         }
1412
1413         return reset_mask;
1414 }
1415
1416 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1417 {
1418         struct rv515_mc_save save;
1419         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1420         u32 tmp;
1421
1422         if (reset_mask == 0)
1423                 return;
1424
1425         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1426
1427         r600_print_gpu_status_regs(rdev);
1428
1429         /* Disable CP parsing/prefetching */
1430         if (rdev->family >= CHIP_RV770)
1431                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1432         else
1433                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1434
1435         /* disable the RLC */
1436         WREG32(RLC_CNTL, 0);
1437
1438         if (reset_mask & RADEON_RESET_DMA) {
1439                 /* Disable DMA */
1440                 tmp = RREG32(DMA_RB_CNTL);
1441                 tmp &= ~DMA_RB_ENABLE;
1442                 WREG32(DMA_RB_CNTL, tmp);
1443         }
1444
1445         DRM_MDELAY(50);
1446
1447         rv515_mc_stop(rdev, &save);
1448         if (r600_mc_wait_for_idle(rdev)) {
1449                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1450         }
1451
1452         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1453                 if (rdev->family >= CHIP_RV770)
1454                         grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1455                                 S_008020_SOFT_RESET_CB(1) |
1456                                 S_008020_SOFT_RESET_PA(1) |
1457                                 S_008020_SOFT_RESET_SC(1) |
1458                                 S_008020_SOFT_RESET_SPI(1) |
1459                                 S_008020_SOFT_RESET_SX(1) |
1460                                 S_008020_SOFT_RESET_SH(1) |
1461                                 S_008020_SOFT_RESET_TC(1) |
1462                                 S_008020_SOFT_RESET_TA(1) |
1463                                 S_008020_SOFT_RESET_VC(1) |
1464                                 S_008020_SOFT_RESET_VGT(1);
1465                 else
1466                         grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1467                                 S_008020_SOFT_RESET_DB(1) |
1468                                 S_008020_SOFT_RESET_CB(1) |
1469                                 S_008020_SOFT_RESET_PA(1) |
1470                                 S_008020_SOFT_RESET_SC(1) |
1471                                 S_008020_SOFT_RESET_SMX(1) |
1472                                 S_008020_SOFT_RESET_SPI(1) |
1473                                 S_008020_SOFT_RESET_SX(1) |
1474                                 S_008020_SOFT_RESET_SH(1) |
1475                                 S_008020_SOFT_RESET_TC(1) |
1476                                 S_008020_SOFT_RESET_TA(1) |
1477                                 S_008020_SOFT_RESET_VC(1) |
1478                                 S_008020_SOFT_RESET_VGT(1);
1479         }
1480
1481         if (reset_mask & RADEON_RESET_CP) {
1482                 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1483                         S_008020_SOFT_RESET_VGT(1);
1484
1485                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1486         }
1487
1488         if (reset_mask & RADEON_RESET_DMA) {
1489                 if (rdev->family >= CHIP_RV770)
1490                         srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1491                 else
1492                         srbm_soft_reset |= SOFT_RESET_DMA;
1493         }
1494
1495         if (reset_mask & RADEON_RESET_RLC)
1496                 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1497
1498         if (reset_mask & RADEON_RESET_SEM)
1499                 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1500
1501         if (reset_mask & RADEON_RESET_IH)
1502                 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1503
1504         if (reset_mask & RADEON_RESET_GRBM)
1505                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1506
1507         if (!(rdev->flags & RADEON_IS_IGP)) {
1508                 if (reset_mask & RADEON_RESET_MC)
1509                         srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1510         }
1511
1512         if (reset_mask & RADEON_RESET_VMC)
1513                 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1514
1515         if (grbm_soft_reset) {
1516                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1517                 tmp |= grbm_soft_reset;
1518                 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1519                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1520                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1521
1522                 DRM_UDELAY(50);
1523
1524                 tmp &= ~grbm_soft_reset;
1525                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1526                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1527         }
1528
1529         if (srbm_soft_reset) {
1530                 tmp = RREG32(SRBM_SOFT_RESET);
1531                 tmp |= srbm_soft_reset;
1532                 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1533                 WREG32(SRBM_SOFT_RESET, tmp);
1534                 tmp = RREG32(SRBM_SOFT_RESET);
1535
1536                 DRM_UDELAY(50);
1537
1538                 tmp &= ~srbm_soft_reset;
1539                 WREG32(SRBM_SOFT_RESET, tmp);
1540                 tmp = RREG32(SRBM_SOFT_RESET);
1541         }
1542
1543         /* Wait a little for things to settle down */
1544         DRM_MDELAY(1);
1545
1546         rv515_mc_resume(rdev, &save);
1547         DRM_UDELAY(50);
1548
1549         r600_print_gpu_status_regs(rdev);
1550 }
1551
1552 int r600_asic_reset(struct radeon_device *rdev)
1553 {
1554         u32 reset_mask;
1555
1556         reset_mask = r600_gpu_check_soft_reset(rdev);
1557
1558         if (reset_mask)
1559                 r600_set_bios_scratch_engine_hung(rdev, true);
1560
1561         r600_gpu_soft_reset(rdev, reset_mask);
1562
1563         reset_mask = r600_gpu_check_soft_reset(rdev);
1564
1565         if (!reset_mask)
1566                 r600_set_bios_scratch_engine_hung(rdev, false);
1567
1568         return 0;
1569 }
1570
1571 /**
1572  * r600_gfx_is_lockup - Check if the GFX engine is locked up
1573  *
1574  * @rdev: radeon_device pointer
1575  * @ring: radeon_ring structure holding ring information
1576  *
1577  * Check if the GFX engine is locked up.
1578  * Returns true if the engine appears to be locked up, false if not.
1579  */
1580 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1581 {
1582         u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1583
1584         if (!(reset_mask & (RADEON_RESET_GFX |
1585                             RADEON_RESET_COMPUTE |
1586                             RADEON_RESET_CP))) {
1587                 radeon_ring_lockup_update(ring);
1588                 return false;
1589         }
1590         /* force CP activities */
1591         radeon_ring_force_activity(rdev, ring);
1592         return radeon_ring_test_lockup(rdev, ring);
1593 }
1594
1595 /**
1596  * r600_dma_is_lockup - Check if the DMA engine is locked up
1597  *
1598  * @rdev: radeon_device pointer
1599  * @ring: radeon_ring structure holding ring information
1600  *
1601  * Check if the async DMA engine is locked up.
1602  * Returns true if the engine appears to be locked up, false if not.
1603  */
1604 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1605 {
1606         u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1607
1608         if (!(reset_mask & RADEON_RESET_DMA)) {
1609                 radeon_ring_lockup_update(ring);
1610                 return false;
1611         }
1612         /* force ring activities */
1613         radeon_ring_force_activity(rdev, ring);
1614         return radeon_ring_test_lockup(rdev, ring);
1615 }
1616
1617 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1618                               u32 tiling_pipe_num,
1619                               u32 max_rb_num,
1620                               u32 total_max_rb_num,
1621                               u32 disabled_rb_mask)
1622 {
1623         u32 rendering_pipe_num, rb_num_width, req_rb_num;
1624         u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1625         u32 data = 0, mask = 1 << (max_rb_num - 1);
1626         unsigned i, j;
1627
1628         /* mask out the RBs that don't exist on that asic */
1629         tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1630         /* make sure at least one RB is available */
1631         if ((tmp & 0xff) != 0xff)
1632                 disabled_rb_mask = tmp;
1633
1634         rendering_pipe_num = 1 << tiling_pipe_num;
1635         req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1636         KASSERT(rendering_pipe_num >= req_rb_num, ("rendering_pipe_num < req_rb_num"));
1637
1638         pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1639         pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1640
1641         if (rdev->family <= CHIP_RV740) {
1642                 /* r6xx/r7xx */
1643                 rb_num_width = 2;
1644         } else {
1645                 /* eg+ */
1646                 rb_num_width = 4;
1647         }
1648
1649         for (i = 0; i < max_rb_num; i++) {
1650                 if (!(mask & disabled_rb_mask)) {
1651                         for (j = 0; j < pipe_rb_ratio; j++) {
1652                                 data <<= rb_num_width;
1653                                 data |= max_rb_num - i - 1;
1654                         }
1655                         if (pipe_rb_remain) {
1656                                 data <<= rb_num_width;
1657                                 data |= max_rb_num - i - 1;
1658                                 pipe_rb_remain--;
1659                         }
1660                 }
1661                 mask >>= 1;
1662         }
1663
1664         return data;
1665 }
1666
1667 int r600_count_pipe_bits(uint32_t val)
1668 {
1669         return hweight32(val);
1670 }
1671
1672 static void r600_gpu_init(struct radeon_device *rdev)
1673 {
1674         u32 tiling_config;
1675         u32 ramcfg;
1676         u32 cc_rb_backend_disable;
1677         u32 cc_gc_shader_pipe_config;
1678         u32 tmp;
1679         int i, j;
1680         u32 sq_config;
1681         u32 sq_gpr_resource_mgmt_1 = 0;
1682         u32 sq_gpr_resource_mgmt_2 = 0;
1683         u32 sq_thread_resource_mgmt = 0;
1684         u32 sq_stack_resource_mgmt_1 = 0;
1685         u32 sq_stack_resource_mgmt_2 = 0;
1686         u32 disabled_rb_mask;
1687
1688         rdev->config.r600.tiling_group_size = 256;
1689         switch (rdev->family) {
1690         case CHIP_R600:
1691                 rdev->config.r600.max_pipes = 4;
1692                 rdev->config.r600.max_tile_pipes = 8;
1693                 rdev->config.r600.max_simds = 4;
1694                 rdev->config.r600.max_backends = 4;
1695                 rdev->config.r600.max_gprs = 256;
1696                 rdev->config.r600.max_threads = 192;
1697                 rdev->config.r600.max_stack_entries = 256;
1698                 rdev->config.r600.max_hw_contexts = 8;
1699                 rdev->config.r600.max_gs_threads = 16;
1700                 rdev->config.r600.sx_max_export_size = 128;
1701                 rdev->config.r600.sx_max_export_pos_size = 16;
1702                 rdev->config.r600.sx_max_export_smx_size = 128;
1703                 rdev->config.r600.sq_num_cf_insts = 2;
1704                 break;
1705         case CHIP_RV630:
1706         case CHIP_RV635:
1707                 rdev->config.r600.max_pipes = 2;
1708                 rdev->config.r600.max_tile_pipes = 2;
1709                 rdev->config.r600.max_simds = 3;
1710                 rdev->config.r600.max_backends = 1;
1711                 rdev->config.r600.max_gprs = 128;
1712                 rdev->config.r600.max_threads = 192;
1713                 rdev->config.r600.max_stack_entries = 128;
1714                 rdev->config.r600.max_hw_contexts = 8;
1715                 rdev->config.r600.max_gs_threads = 4;
1716                 rdev->config.r600.sx_max_export_size = 128;
1717                 rdev->config.r600.sx_max_export_pos_size = 16;
1718                 rdev->config.r600.sx_max_export_smx_size = 128;
1719                 rdev->config.r600.sq_num_cf_insts = 2;
1720                 break;
1721         case CHIP_RV610:
1722         case CHIP_RV620:
1723         case CHIP_RS780:
1724         case CHIP_RS880:
1725                 rdev->config.r600.max_pipes = 1;
1726                 rdev->config.r600.max_tile_pipes = 1;
1727                 rdev->config.r600.max_simds = 2;
1728                 rdev->config.r600.max_backends = 1;
1729                 rdev->config.r600.max_gprs = 128;
1730                 rdev->config.r600.max_threads = 192;
1731                 rdev->config.r600.max_stack_entries = 128;
1732                 rdev->config.r600.max_hw_contexts = 4;
1733                 rdev->config.r600.max_gs_threads = 4;
1734                 rdev->config.r600.sx_max_export_size = 128;
1735                 rdev->config.r600.sx_max_export_pos_size = 16;
1736                 rdev->config.r600.sx_max_export_smx_size = 128;
1737                 rdev->config.r600.sq_num_cf_insts = 1;
1738                 break;
1739         case CHIP_RV670:
1740                 rdev->config.r600.max_pipes = 4;
1741                 rdev->config.r600.max_tile_pipes = 4;
1742                 rdev->config.r600.max_simds = 4;
1743                 rdev->config.r600.max_backends = 4;
1744                 rdev->config.r600.max_gprs = 192;
1745                 rdev->config.r600.max_threads = 192;
1746                 rdev->config.r600.max_stack_entries = 256;
1747                 rdev->config.r600.max_hw_contexts = 8;
1748                 rdev->config.r600.max_gs_threads = 16;
1749                 rdev->config.r600.sx_max_export_size = 128;
1750                 rdev->config.r600.sx_max_export_pos_size = 16;
1751                 rdev->config.r600.sx_max_export_smx_size = 128;
1752                 rdev->config.r600.sq_num_cf_insts = 2;
1753                 break;
1754         default:
1755                 break;
1756         }
1757
1758         /* Initialize HDP */
1759         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1760                 WREG32((0x2c14 + j), 0x00000000);
1761                 WREG32((0x2c18 + j), 0x00000000);
1762                 WREG32((0x2c1c + j), 0x00000000);
1763                 WREG32((0x2c20 + j), 0x00000000);
1764                 WREG32((0x2c24 + j), 0x00000000);
1765         }
1766
1767         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1768
1769         /* Setup tiling */
1770         tiling_config = 0;
1771         ramcfg = RREG32(RAMCFG);
1772         switch (rdev->config.r600.max_tile_pipes) {
1773         case 1:
1774                 tiling_config |= PIPE_TILING(0);
1775                 break;
1776         case 2:
1777                 tiling_config |= PIPE_TILING(1);
1778                 break;
1779         case 4:
1780                 tiling_config |= PIPE_TILING(2);
1781                 break;
1782         case 8:
1783                 tiling_config |= PIPE_TILING(3);
1784                 break;
1785         default:
1786                 break;
1787         }
1788         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1789         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1790         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1791         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1792
1793         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1794         if (tmp > 3) {
1795                 tiling_config |= ROW_TILING(3);
1796                 tiling_config |= SAMPLE_SPLIT(3);
1797         } else {
1798                 tiling_config |= ROW_TILING(tmp);
1799                 tiling_config |= SAMPLE_SPLIT(tmp);
1800         }
1801         tiling_config |= BANK_SWAPS(1);
1802
1803         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1804         tmp = R6XX_MAX_BACKENDS -
1805                 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1806         if (tmp < rdev->config.r600.max_backends) {
1807                 rdev->config.r600.max_backends = tmp;
1808         }
1809
1810         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1811         tmp = R6XX_MAX_PIPES -
1812                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1813         if (tmp < rdev->config.r600.max_pipes) {
1814                 rdev->config.r600.max_pipes = tmp;
1815         }
1816         tmp = R6XX_MAX_SIMDS -
1817                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1818         if (tmp < rdev->config.r600.max_simds) {
1819                 rdev->config.r600.max_simds = tmp;
1820         }
1821
1822         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1823         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1824         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1825                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
1826         tiling_config |= tmp << 16;
1827         rdev->config.r600.backend_map = tmp;
1828
1829         rdev->config.r600.tile_config = tiling_config;
1830         WREG32(GB_TILING_CONFIG, tiling_config);
1831         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1832         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1833         WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
1834
1835         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1836         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1837         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1838
1839         /* Setup some CP states */
1840         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1841         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1842
1843         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1844                              SYNC_WALKER | SYNC_ALIGNER));
1845         /* Setup various GPU states */
1846         if (rdev->family == CHIP_RV670)
1847                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1848
1849         tmp = RREG32(SX_DEBUG_1);
1850         tmp |= SMX_EVENT_RELEASE;
1851         if ((rdev->family > CHIP_R600))
1852                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1853         WREG32(SX_DEBUG_1, tmp);
1854
1855         if (((rdev->family) == CHIP_R600) ||
1856             ((rdev->family) == CHIP_RV630) ||
1857             ((rdev->family) == CHIP_RV610) ||
1858             ((rdev->family) == CHIP_RV620) ||
1859             ((rdev->family) == CHIP_RS780) ||
1860             ((rdev->family) == CHIP_RS880)) {
1861                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1862         } else {
1863                 WREG32(DB_DEBUG, 0);
1864         }
1865         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1866                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1867
1868         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1869         WREG32(VGT_NUM_INSTANCES, 0);
1870
1871         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1872         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1873
1874         tmp = RREG32(SQ_MS_FIFO_SIZES);
1875         if (((rdev->family) == CHIP_RV610) ||
1876             ((rdev->family) == CHIP_RV620) ||
1877             ((rdev->family) == CHIP_RS780) ||
1878             ((rdev->family) == CHIP_RS880)) {
1879                 tmp = (CACHE_FIFO_SIZE(0xa) |
1880                        FETCH_FIFO_HIWATER(0xa) |
1881                        DONE_FIFO_HIWATER(0xe0) |
1882                        ALU_UPDATE_FIFO_HIWATER(0x8));
1883         } else if (((rdev->family) == CHIP_R600) ||
1884                    ((rdev->family) == CHIP_RV630)) {
1885                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1886                 tmp |= DONE_FIFO_HIWATER(0x4);
1887         }
1888         WREG32(SQ_MS_FIFO_SIZES, tmp);
1889
1890         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1891          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1892          */
1893         sq_config = RREG32(SQ_CONFIG);
1894         sq_config &= ~(PS_PRIO(3) |
1895                        VS_PRIO(3) |
1896                        GS_PRIO(3) |
1897                        ES_PRIO(3));
1898         sq_config |= (DX9_CONSTS |
1899                       VC_ENABLE |
1900                       PS_PRIO(0) |
1901                       VS_PRIO(1) |
1902                       GS_PRIO(2) |
1903                       ES_PRIO(3));
1904
1905         if ((rdev->family) == CHIP_R600) {
1906                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1907                                           NUM_VS_GPRS(124) |
1908                                           NUM_CLAUSE_TEMP_GPRS(4));
1909                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1910                                           NUM_ES_GPRS(0));
1911                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1912                                            NUM_VS_THREADS(48) |
1913                                            NUM_GS_THREADS(4) |
1914                                            NUM_ES_THREADS(4));
1915                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1916                                             NUM_VS_STACK_ENTRIES(128));
1917                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1918                                             NUM_ES_STACK_ENTRIES(0));
1919         } else if (((rdev->family) == CHIP_RV610) ||
1920                    ((rdev->family) == CHIP_RV620) ||
1921                    ((rdev->family) == CHIP_RS780) ||
1922                    ((rdev->family) == CHIP_RS880)) {
1923                 /* no vertex cache */
1924                 sq_config &= ~VC_ENABLE;
1925
1926                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1927                                           NUM_VS_GPRS(44) |
1928                                           NUM_CLAUSE_TEMP_GPRS(2));
1929                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1930                                           NUM_ES_GPRS(17));
1931                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1932                                            NUM_VS_THREADS(78) |
1933                                            NUM_GS_THREADS(4) |
1934                                            NUM_ES_THREADS(31));
1935                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1936                                             NUM_VS_STACK_ENTRIES(40));
1937                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1938                                             NUM_ES_STACK_ENTRIES(16));
1939         } else if (((rdev->family) == CHIP_RV630) ||
1940                    ((rdev->family) == CHIP_RV635)) {
1941                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1942                                           NUM_VS_GPRS(44) |
1943                                           NUM_CLAUSE_TEMP_GPRS(2));
1944                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1945                                           NUM_ES_GPRS(18));
1946                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1947                                            NUM_VS_THREADS(78) |
1948                                            NUM_GS_THREADS(4) |
1949                                            NUM_ES_THREADS(31));
1950                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1951                                             NUM_VS_STACK_ENTRIES(40));
1952                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1953                                             NUM_ES_STACK_ENTRIES(16));
1954         } else if ((rdev->family) == CHIP_RV670) {
1955                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1956                                           NUM_VS_GPRS(44) |
1957                                           NUM_CLAUSE_TEMP_GPRS(2));
1958                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1959                                           NUM_ES_GPRS(17));
1960                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1961                                            NUM_VS_THREADS(78) |
1962                                            NUM_GS_THREADS(4) |
1963                                            NUM_ES_THREADS(31));
1964                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1965                                             NUM_VS_STACK_ENTRIES(64));
1966                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1967                                             NUM_ES_STACK_ENTRIES(64));
1968         }
1969
1970         WREG32(SQ_CONFIG, sq_config);
1971         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1972         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1973         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1974         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1975         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1976
1977         if (((rdev->family) == CHIP_RV610) ||
1978             ((rdev->family) == CHIP_RV620) ||
1979             ((rdev->family) == CHIP_RS780) ||
1980             ((rdev->family) == CHIP_RS880)) {
1981                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1982         } else {
1983                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1984         }
1985
1986         /* More default values. 2D/3D driver should adjust as needed */
1987         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1988                                          S1_X(0x4) | S1_Y(0xc)));
1989         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1990                                          S1_X(0x2) | S1_Y(0x2) |
1991                                          S2_X(0xa) | S2_Y(0x6) |
1992                                          S3_X(0x6) | S3_Y(0xa)));
1993         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1994                                              S1_X(0x4) | S1_Y(0xc) |
1995                                              S2_X(0x1) | S2_Y(0x6) |
1996                                              S3_X(0xa) | S3_Y(0xe)));
1997         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1998                                              S5_X(0x0) | S5_Y(0x0) |
1999                                              S6_X(0xb) | S6_Y(0x4) |
2000                                              S7_X(0x7) | S7_Y(0x8)));
2001
2002         WREG32(VGT_STRMOUT_EN, 0);
2003         tmp = rdev->config.r600.max_pipes * 16;
2004         switch (rdev->family) {
2005         case CHIP_RV610:
2006         case CHIP_RV620:
2007         case CHIP_RS780:
2008         case CHIP_RS880:
2009                 tmp += 32;
2010                 break;
2011         case CHIP_RV670:
2012                 tmp += 128;
2013                 break;
2014         default:
2015                 break;
2016         }
2017         if (tmp > 256) {
2018                 tmp = 256;
2019         }
2020         WREG32(VGT_ES_PER_GS, 128);
2021         WREG32(VGT_GS_PER_ES, tmp);
2022         WREG32(VGT_GS_PER_VS, 2);
2023         WREG32(VGT_GS_VERTEX_REUSE, 16);
2024
2025         /* more default values. 2D/3D driver should adjust as needed */
2026         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2027         WREG32(VGT_STRMOUT_EN, 0);
2028         WREG32(SX_MISC, 0);
2029         WREG32(PA_SC_MODE_CNTL, 0);
2030         WREG32(PA_SC_AA_CONFIG, 0);
2031         WREG32(PA_SC_LINE_STIPPLE, 0);
2032         WREG32(SPI_INPUT_Z, 0);
2033         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2034         WREG32(CB_COLOR7_FRAG, 0);
2035
2036         /* Clear render buffer base addresses */
2037         WREG32(CB_COLOR0_BASE, 0);
2038         WREG32(CB_COLOR1_BASE, 0);
2039         WREG32(CB_COLOR2_BASE, 0);
2040         WREG32(CB_COLOR3_BASE, 0);
2041         WREG32(CB_COLOR4_BASE, 0);
2042         WREG32(CB_COLOR5_BASE, 0);
2043         WREG32(CB_COLOR6_BASE, 0);
2044         WREG32(CB_COLOR7_BASE, 0);
2045         WREG32(CB_COLOR7_FRAG, 0);
2046
2047         switch (rdev->family) {
2048         case CHIP_RV610:
2049         case CHIP_RV620:
2050         case CHIP_RS780:
2051         case CHIP_RS880:
2052                 tmp = TC_L2_SIZE(8);
2053                 break;
2054         case CHIP_RV630:
2055         case CHIP_RV635:
2056                 tmp = TC_L2_SIZE(4);
2057                 break;
2058         case CHIP_R600:
2059                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2060                 break;
2061         default:
2062                 tmp = TC_L2_SIZE(0);
2063                 break;
2064         }
2065         WREG32(TC_CNTL, tmp);
2066
2067         tmp = RREG32(HDP_HOST_PATH_CNTL);
2068         WREG32(HDP_HOST_PATH_CNTL, tmp);
2069
2070         tmp = RREG32(ARB_POP);
2071         tmp |= ENABLE_TC128;
2072         WREG32(ARB_POP, tmp);
2073
2074         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2075         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2076                                NUM_CLIP_SEQ(3)));
2077         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2078         WREG32(VC_ENHANCE, 0);
2079 }
2080
2081
2082 /*
2083  * Indirect registers accessor
2084  */
2085 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2086 {
2087         u32 r;
2088
2089         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2090         (void)RREG32(PCIE_PORT_INDEX);
2091         r = RREG32(PCIE_PORT_DATA);
2092         return r;
2093 }
2094
2095 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2096 {
2097         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2098         (void)RREG32(PCIE_PORT_INDEX);
2099         WREG32(PCIE_PORT_DATA, (v));
2100         (void)RREG32(PCIE_PORT_DATA);
2101 }
2102
2103 /*
2104  * CP & Ring
2105  */
2106 void r600_cp_stop(struct radeon_device *rdev)
2107 {
2108         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2109         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2110         WREG32(SCRATCH_UMSK, 0);
2111         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2112 }
2113
2114 int r600_init_microcode(struct radeon_device *rdev)
2115 {
2116         const char *chip_name;
2117         const char *rlc_chip_name;
2118         size_t pfp_req_size, me_req_size, rlc_req_size;
2119         char fw_name[30];
2120         int err;
2121
2122         DRM_DEBUG("\n");
2123
2124         switch (rdev->family) {
2125         case CHIP_R600:
2126                 chip_name = "R600";
2127                 rlc_chip_name = "R600";
2128                 break;
2129         case CHIP_RV610:
2130                 chip_name = "RV610";
2131                 rlc_chip_name = "R600";
2132                 break;
2133         case CHIP_RV630:
2134                 chip_name = "RV630";
2135                 rlc_chip_name = "R600";
2136                 break;
2137         case CHIP_RV620:
2138                 chip_name = "RV620";
2139                 rlc_chip_name = "R600";
2140                 break;
2141         case CHIP_RV635:
2142                 chip_name = "RV635";
2143                 rlc_chip_name = "R600";
2144                 break;
2145         case CHIP_RV670:
2146                 chip_name = "RV670";
2147                 rlc_chip_name = "R600";
2148                 break;
2149         case CHIP_RS780:
2150         case CHIP_RS880:
2151                 chip_name = "RS780";
2152                 rlc_chip_name = "R600";
2153                 break;
2154         case CHIP_RV770:
2155                 chip_name = "RV770";
2156                 rlc_chip_name = "R700";
2157                 break;
2158         case CHIP_RV730:
2159         case CHIP_RV740:
2160                 chip_name = "RV730";
2161                 rlc_chip_name = "R700";
2162                 break;
2163         case CHIP_RV710:
2164                 chip_name = "RV710";
2165                 rlc_chip_name = "R700";
2166                 break;
2167         case CHIP_CEDAR:
2168                 chip_name = "CEDAR";
2169                 rlc_chip_name = "CEDAR";
2170                 break;
2171         case CHIP_REDWOOD:
2172                 chip_name = "REDWOOD";
2173                 rlc_chip_name = "REDWOOD";
2174                 break;
2175         case CHIP_JUNIPER:
2176                 chip_name = "JUNIPER";
2177                 rlc_chip_name = "JUNIPER";
2178                 break;
2179         case CHIP_CYPRESS:
2180         case CHIP_HEMLOCK:
2181                 chip_name = "CYPRESS";
2182                 rlc_chip_name = "CYPRESS";
2183                 break;
2184         case CHIP_PALM:
2185                 chip_name = "PALM";
2186                 rlc_chip_name = "SUMO";
2187                 break;
2188         case CHIP_SUMO:
2189                 chip_name = "SUMO";
2190                 rlc_chip_name = "SUMO";
2191                 break;
2192         case CHIP_SUMO2:
2193                 chip_name = "SUMO2";
2194                 rlc_chip_name = "SUMO";
2195                 break;
2196         default: panic("%s: Unsupported family %d", __func__, rdev->family);
2197         }
2198
2199         if (rdev->family >= CHIP_CEDAR) {
2200                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2201                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2202                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2203         } else if (rdev->family >= CHIP_RV770) {
2204                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2205                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2206                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2207         } else {
2208                 pfp_req_size = PFP_UCODE_SIZE * 4;
2209                 me_req_size = PM4_UCODE_SIZE * 12;
2210                 rlc_req_size = RLC_UCODE_SIZE * 4;
2211         }
2212
2213         DRM_INFO("Loading %s Microcode\n", chip_name);
2214         err = 0;
2215
2216         ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name);
2217         rdev->pfp_fw = firmware_get(fw_name);
2218         if (rdev->pfp_fw == NULL) {
2219                 err = -ENOENT;
2220                 goto out;
2221         }
2222         if (rdev->pfp_fw->datasize != pfp_req_size) {
2223                 DRM_ERROR(
2224                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2225                        rdev->pfp_fw->datasize, fw_name);
2226                 err = -EINVAL;
2227                 goto out;
2228         }
2229
2230         ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name);
2231         rdev->me_fw = firmware_get(fw_name);
2232         if (rdev->me_fw == NULL) {
2233                 err = -ENOENT;
2234                 goto out;
2235         }
2236         if (rdev->me_fw->datasize != me_req_size) {
2237                 DRM_ERROR(
2238                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2239                        rdev->me_fw->datasize, fw_name);
2240                 err = -EINVAL;
2241         }
2242
2243         ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc",
2244                   rlc_chip_name);
2245         rdev->rlc_fw = firmware_get(fw_name);
2246         if (rdev->rlc_fw == NULL) {
2247                 err = -ENOENT;
2248                 goto out;
2249         }
2250         if (rdev->rlc_fw->datasize != rlc_req_size) {
2251                 DRM_ERROR(
2252                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2253                        rdev->rlc_fw->datasize, fw_name);
2254                 err = -EINVAL;
2255         }
2256
2257 out:
2258         if (err) {
2259                 if (err != -EINVAL)
2260                         DRM_ERROR(
2261                                "r600_cp: Failed to load firmware \"%s\"\n",
2262                                fw_name);
2263                 if (rdev->pfp_fw != NULL) {
2264                         firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD);
2265                         rdev->pfp_fw = NULL;
2266                 }
2267                 if (rdev->me_fw != NULL) {
2268                         firmware_put(rdev->me_fw, FIRMWARE_UNLOAD);
2269                         rdev->me_fw = NULL;
2270                 }
2271                 if (rdev->rlc_fw != NULL) {
2272                         firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD);
2273                         rdev->rlc_fw = NULL;
2274                 }
2275         }
2276         return err;
2277 }
2278
2279 /**
2280  * r600_fini_microcode - drop the firmwares image references
2281  *
2282  * @rdev: radeon_device pointer
2283  *
2284  * Drop the pfp, me and rlc firmwares image references.
2285  * Called at driver shutdown.
2286  */
2287 void r600_fini_microcode(struct radeon_device *rdev)
2288 {
2289
2290         if (rdev->pfp_fw != NULL) {
2291                 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD);
2292                 rdev->pfp_fw = NULL;
2293         }
2294
2295         if (rdev->me_fw != NULL) {
2296                 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD);
2297                 rdev->me_fw = NULL;
2298         }
2299
2300         if (rdev->rlc_fw != NULL) {
2301                 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD);
2302                 rdev->rlc_fw = NULL;
2303         }
2304 }
2305
2306 static int r600_cp_load_microcode(struct radeon_device *rdev)
2307 {
2308         const __be32 *fw_data;
2309         int i;
2310
2311         if (!rdev->me_fw || !rdev->pfp_fw)
2312                 return -EINVAL;
2313
2314         r600_cp_stop(rdev);
2315
2316         WREG32(CP_RB_CNTL,
2317 #ifdef __BIG_ENDIAN
2318                BUF_SWAP_32BIT |
2319 #endif
2320                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2321
2322         /* Reset cp */
2323         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2324         RREG32(GRBM_SOFT_RESET);
2325         DRM_MDELAY(15);
2326         WREG32(GRBM_SOFT_RESET, 0);
2327
2328         WREG32(CP_ME_RAM_WADDR, 0);
2329
2330         fw_data = (const __be32 *)rdev->me_fw->data;
2331         WREG32(CP_ME_RAM_WADDR, 0);
2332         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2333                 WREG32(CP_ME_RAM_DATA,
2334                        be32_to_cpup(fw_data++));
2335
2336         fw_data = (const __be32 *)rdev->pfp_fw->data;
2337         WREG32(CP_PFP_UCODE_ADDR, 0);
2338         for (i = 0; i < PFP_UCODE_SIZE; i++)
2339                 WREG32(CP_PFP_UCODE_DATA,
2340                        be32_to_cpup(fw_data++));
2341
2342         WREG32(CP_PFP_UCODE_ADDR, 0);
2343         WREG32(CP_ME_RAM_WADDR, 0);
2344         WREG32(CP_ME_RAM_RADDR, 0);
2345         return 0;
2346 }
2347
2348 int r600_cp_start(struct radeon_device *rdev)
2349 {
2350         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2351         int r;
2352         uint32_t cp_me;
2353
2354         r = radeon_ring_lock(rdev, ring, 7);
2355         if (r) {
2356                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2357                 return r;
2358         }
2359         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2360         radeon_ring_write(ring, 0x1);
2361         if (rdev->family >= CHIP_RV770) {
2362                 radeon_ring_write(ring, 0x0);
2363                 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2364         } else {
2365                 radeon_ring_write(ring, 0x3);
2366                 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2367         }
2368         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2369         radeon_ring_write(ring, 0);
2370         radeon_ring_write(ring, 0);
2371         radeon_ring_unlock_commit(rdev, ring);
2372
2373         cp_me = 0xff;
2374         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2375         return 0;
2376 }
2377
2378 int r600_cp_resume(struct radeon_device *rdev)
2379 {
2380         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2381         u32 tmp;
2382         u32 rb_bufsz;
2383         int r;
2384
2385         /* Reset cp */
2386         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2387         RREG32(GRBM_SOFT_RESET);
2388         DRM_MDELAY(15);
2389         WREG32(GRBM_SOFT_RESET, 0);
2390
2391         /* Set ring buffer size */
2392         rb_bufsz = drm_order(ring->ring_size / 8);
2393         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2394 #ifdef __BIG_ENDIAN
2395         tmp |= BUF_SWAP_32BIT;
2396 #endif
2397         WREG32(CP_RB_CNTL, tmp);
2398         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2399
2400         /* Set the write pointer delay */
2401         WREG32(CP_RB_WPTR_DELAY, 0);
2402
2403         /* Initialize the ring buffer's read and write pointers */
2404         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2405         WREG32(CP_RB_RPTR_WR, 0);
2406         ring->wptr = 0;
2407         WREG32(CP_RB_WPTR, ring->wptr);
2408
2409         /* set the wb address whether it's enabled or not */
2410         WREG32(CP_RB_RPTR_ADDR,
2411                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2412         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2413         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2414
2415         if (rdev->wb.enabled)
2416                 WREG32(SCRATCH_UMSK, 0xff);
2417         else {
2418                 tmp |= RB_NO_UPDATE;
2419                 WREG32(SCRATCH_UMSK, 0);
2420         }
2421
2422         DRM_MDELAY(1);
2423         WREG32(CP_RB_CNTL, tmp);
2424
2425         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2426         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2427
2428         ring->rptr = RREG32(CP_RB_RPTR);
2429
2430         r600_cp_start(rdev);
2431         ring->ready = true;
2432         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2433         if (r) {
2434                 ring->ready = false;
2435                 return r;
2436         }
2437         return 0;
2438 }
2439
2440 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2441 {
2442         u32 rb_bufsz;
2443         int r;
2444
2445         /* Align ring size */
2446         rb_bufsz = drm_order(ring_size / 8);
2447         ring_size = (1 << (rb_bufsz + 1)) * 4;
2448         ring->ring_size = ring_size;
2449         ring->align_mask = 16 - 1;
2450
2451         if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2452                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2453                 if (r) {
2454                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2455                         ring->rptr_save_reg = 0;
2456                 }
2457         }
2458 }
2459
2460 void r600_cp_fini(struct radeon_device *rdev)
2461 {
2462         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2463         r600_cp_stop(rdev);
2464         radeon_ring_fini(rdev, ring);
2465         radeon_scratch_free(rdev, ring->rptr_save_reg);
2466 }
2467
2468 /*
2469  * DMA
2470  * Starting with R600, the GPU has an asynchronous
2471  * DMA engine.  The programming model is very similar
2472  * to the 3D engine (ring buffer, IBs, etc.), but the
2473  * DMA controller has it's own packet format that is
2474  * different form the PM4 format used by the 3D engine.
2475  * It supports copying data, writing embedded data,
2476  * solid fills, and a number of other things.  It also
2477  * has support for tiling/detiling of buffers.
2478  */
2479 /**
2480  * r600_dma_stop - stop the async dma engine
2481  *
2482  * @rdev: radeon_device pointer
2483  *
2484  * Stop the async dma engine (r6xx-evergreen).
2485  */
2486 void r600_dma_stop(struct radeon_device *rdev)
2487 {
2488         u32 rb_cntl = RREG32(DMA_RB_CNTL);
2489
2490         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2491
2492         rb_cntl &= ~DMA_RB_ENABLE;
2493         WREG32(DMA_RB_CNTL, rb_cntl);
2494
2495         rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2496 }
2497
2498 /**
2499  * r600_dma_resume - setup and start the async dma engine
2500  *
2501  * @rdev: radeon_device pointer
2502  *
2503  * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2504  * Returns 0 for success, error for failure.
2505  */
2506 int r600_dma_resume(struct radeon_device *rdev)
2507 {
2508         struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2509         u32 rb_cntl, dma_cntl, ib_cntl;
2510         u32 rb_bufsz;
2511         int r;
2512
2513         /* Reset dma */
2514         if (rdev->family >= CHIP_RV770)
2515                 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
2516         else
2517                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2518         RREG32(SRBM_SOFT_RESET);
2519         DRM_UDELAY(50);
2520         WREG32(SRBM_SOFT_RESET, 0);
2521
2522         WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
2523         WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
2524
2525         /* Set ring buffer size in dwords */
2526         rb_bufsz = drm_order(ring->ring_size / 4);
2527         rb_cntl = rb_bufsz << 1;
2528 #ifdef __BIG_ENDIAN
2529         rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
2530 #endif
2531         WREG32(DMA_RB_CNTL, rb_cntl);
2532
2533         /* Initialize the ring buffer's read and write pointers */
2534         WREG32(DMA_RB_RPTR, 0);
2535         WREG32(DMA_RB_WPTR, 0);
2536
2537         /* set the wb address whether it's enabled or not */
2538         WREG32(DMA_RB_RPTR_ADDR_HI,
2539                upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2540         WREG32(DMA_RB_RPTR_ADDR_LO,
2541                ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2542
2543         if (rdev->wb.enabled)
2544                 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
2545
2546         WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2547
2548         /* enable DMA IBs */
2549         ib_cntl = DMA_IB_ENABLE;
2550 #ifdef __BIG_ENDIAN
2551         ib_cntl |= DMA_IB_SWAP_ENABLE;
2552 #endif
2553         WREG32(DMA_IB_CNTL, ib_cntl);
2554
2555         dma_cntl = RREG32(DMA_CNTL);
2556         dma_cntl &= ~CTXEMPTY_INT_ENABLE;
2557         WREG32(DMA_CNTL, dma_cntl);
2558
2559         if (rdev->family >= CHIP_RV770)
2560                 WREG32(DMA_MODE, 1);
2561
2562         ring->wptr = 0;
2563         WREG32(DMA_RB_WPTR, ring->wptr << 2);
2564
2565         ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2566
2567         WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
2568
2569         ring->ready = true;
2570
2571         r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2572         if (r) {
2573                 ring->ready = false;
2574                 return r;
2575         }
2576
2577         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2578
2579         return 0;
2580 }
2581
2582 /**
2583  * r600_dma_fini - tear down the async dma engine
2584  *
2585  * @rdev: radeon_device pointer
2586  *
2587  * Stop the async dma engine and free the ring (r6xx-evergreen).
2588  */
2589 void r600_dma_fini(struct radeon_device *rdev)
2590 {
2591         r600_dma_stop(rdev);
2592         radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2593 }
2594
2595 /*
2596  * GPU scratch registers helpers function.
2597  */
2598 void r600_scratch_init(struct radeon_device *rdev)
2599 {
2600         int i;
2601
2602         rdev->scratch.num_reg = 7;
2603         rdev->scratch.reg_base = SCRATCH_REG0;
2604         for (i = 0; i < rdev->scratch.num_reg; i++) {
2605                 rdev->scratch.free[i] = true;
2606                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2607         }
2608 }
2609
2610 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2611 {
2612         uint32_t scratch;
2613         uint32_t tmp = 0;
2614         unsigned i;
2615         int r;
2616
2617         r = radeon_scratch_get(rdev, &scratch);
2618         if (r) {
2619                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2620                 return r;
2621         }
2622         WREG32(scratch, 0xCAFEDEAD);
2623         r = radeon_ring_lock(rdev, ring, 3);
2624         if (r) {
2625                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2626                 radeon_scratch_free(rdev, scratch);
2627                 return r;
2628         }
2629         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2630         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2631         radeon_ring_write(ring, 0xDEADBEEF);
2632         radeon_ring_unlock_commit(rdev, ring);
2633         for (i = 0; i < rdev->usec_timeout; i++) {
2634                 tmp = RREG32(scratch);
2635                 if (tmp == 0xDEADBEEF)
2636                         break;
2637                 DRM_UDELAY(1);
2638         }
2639         if (i < rdev->usec_timeout) {
2640                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2641         } else {
2642                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2643                           ring->idx, scratch, tmp);
2644                 r = -EINVAL;
2645         }
2646         radeon_scratch_free(rdev, scratch);
2647         return r;
2648 }
2649
2650 /**
2651  * r600_dma_ring_test - simple async dma engine test
2652  *
2653  * @rdev: radeon_device pointer
2654  * @ring: radeon_ring structure holding ring information
2655  *
2656  * Test the DMA engine by writing using it to write an
2657  * value to memory. (r6xx-SI).
2658  * Returns 0 for success, error for failure.
2659  */
2660 int r600_dma_ring_test(struct radeon_device *rdev,
2661                        struct radeon_ring *ring)
2662 {
2663         unsigned i;
2664         int r;
2665         volatile uint32_t *ptr = rdev->vram_scratch.ptr;
2666         u32 tmp;
2667
2668         if (!ptr) {
2669                 DRM_ERROR("invalid vram scratch pointer\n");
2670                 return -EINVAL;
2671         }
2672
2673         tmp = 0xCAFEDEAD;
2674         *ptr = tmp;
2675
2676         r = radeon_ring_lock(rdev, ring, 4);
2677         if (r) {
2678                 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2679                 return r;
2680         }
2681         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2682         radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2683         radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2684         radeon_ring_write(ring, 0xDEADBEEF);
2685         radeon_ring_unlock_commit(rdev, ring);
2686
2687         for (i = 0; i < rdev->usec_timeout; i++) {
2688                 tmp = *ptr;
2689                 if (tmp == 0xDEADBEEF)
2690                         break;
2691                 DRM_UDELAY(1);
2692         }
2693
2694         if (i < rdev->usec_timeout) {
2695                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2696         } else {
2697                 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2698                           ring->idx, tmp);
2699                 r = -EINVAL;
2700         }
2701         return r;
2702 }
2703
2704 /*
2705  * CP fences/semaphores
2706  */
2707
2708 void r600_fence_ring_emit(struct radeon_device *rdev,
2709                           struct radeon_fence *fence)
2710 {
2711         struct radeon_ring *ring = &rdev->ring[fence->ring];
2712
2713         if (rdev->wb.use_event) {
2714                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2715                 /* flush read cache over gart */
2716                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2717                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2718                                         PACKET3_VC_ACTION_ENA |
2719                                         PACKET3_SH_ACTION_ENA);
2720                 radeon_ring_write(ring, 0xFFFFFFFF);
2721                 radeon_ring_write(ring, 0);
2722                 radeon_ring_write(ring, 10); /* poll interval */
2723                 /* EVENT_WRITE_EOP - flush caches, send int */
2724                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2725                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2726                 radeon_ring_write(ring, addr & 0xffffffff);
2727                 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2728                 radeon_ring_write(ring, fence->seq);
2729                 radeon_ring_write(ring, 0);
2730         } else {
2731                 /* flush read cache over gart */
2732                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2733                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2734                                         PACKET3_VC_ACTION_ENA |
2735                                         PACKET3_SH_ACTION_ENA);
2736                 radeon_ring_write(ring, 0xFFFFFFFF);
2737                 radeon_ring_write(ring, 0);
2738                 radeon_ring_write(ring, 10); /* poll interval */
2739                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2740                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2741                 /* wait for 3D idle clean */
2742                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2743                 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2744                 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2745                 /* Emit fence sequence & fire IRQ */
2746                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2747                 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2748                 radeon_ring_write(ring, fence->seq);
2749                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2750                 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2751                 radeon_ring_write(ring, RB_INT_STAT);
2752         }
2753 }
2754
2755 void r600_semaphore_ring_emit(struct radeon_device *rdev,
2756                               struct radeon_ring *ring,
2757                               struct radeon_semaphore *semaphore,
2758                               bool emit_wait)
2759 {
2760         uint64_t addr = semaphore->gpu_addr;
2761         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2762
2763         if (rdev->family < CHIP_CAYMAN)
2764                 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2765
2766         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2767         radeon_ring_write(ring, addr & 0xffffffff);
2768         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2769 }
2770
2771 /*
2772  * DMA fences/semaphores
2773  */
2774
2775 /**
2776  * r600_dma_fence_ring_emit - emit a fence on the DMA ring
2777  *
2778  * @rdev: radeon_device pointer
2779  * @fence: radeon fence object
2780  *
2781  * Add a DMA fence packet to the ring to write
2782  * the fence seq number and DMA trap packet to generate
2783  * an interrupt if needed (r6xx-r7xx).
2784  */
2785 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
2786                               struct radeon_fence *fence)
2787 {
2788         struct radeon_ring *ring = &rdev->ring[fence->ring];
2789         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2790
2791         /* write the fence */
2792         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
2793         radeon_ring_write(ring, addr & 0xfffffffc);
2794         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
2795         radeon_ring_write(ring, lower_32_bits(fence->seq));
2796         /* generate an interrupt */
2797         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
2798 }
2799
2800 /**
2801  * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
2802  *
2803  * @rdev: radeon_device pointer
2804  * @ring: radeon_ring structure holding ring information
2805  * @semaphore: radeon semaphore object
2806  * @emit_wait: wait or signal semaphore
2807  *
2808  * Add a DMA semaphore packet to the ring wait on or signal
2809  * other rings (r6xx-SI).
2810  */
2811 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
2812                                   struct radeon_ring *ring,
2813                                   struct radeon_semaphore *semaphore,
2814                                   bool emit_wait)
2815 {
2816         u64 addr = semaphore->gpu_addr;
2817         u32 s = emit_wait ? 0 : 1;
2818
2819         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
2820         radeon_ring_write(ring, addr & 0xfffffffc);
2821         radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2822 }
2823
2824 int r600_copy_blit(struct radeon_device *rdev,
2825                    uint64_t src_offset,
2826                    uint64_t dst_offset,
2827                    unsigned num_gpu_pages,
2828                    struct radeon_fence **fence)
2829 {
2830         struct radeon_semaphore *sem = NULL;
2831         struct radeon_sa_bo *vb = NULL;
2832         int r;
2833
2834         r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
2835         if (r) {
2836                 return r;
2837         }
2838         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
2839         r600_blit_done_copy(rdev, fence, vb, sem);
2840         return 0;
2841 }
2842
2843 /**
2844  * r600_copy_dma - copy pages using the DMA engine
2845  *
2846  * @rdev: radeon_device pointer
2847  * @src_offset: src GPU address
2848  * @dst_offset: dst GPU address
2849  * @num_gpu_pages: number of GPU pages to xfer
2850  * @fence: radeon fence object
2851  *
2852  * Copy GPU paging using the DMA engine (r6xx).
2853  * Used by the radeon ttm implementation to move pages if
2854  * registered as the asic copy callback.
2855  */
2856 int r600_copy_dma(struct radeon_device *rdev,
2857                   uint64_t src_offset, uint64_t dst_offset,
2858                   unsigned num_gpu_pages,
2859                   struct radeon_fence **fence)
2860 {
2861         struct radeon_semaphore *sem = NULL;
2862         int ring_index = rdev->asic->copy.dma_ring_index;
2863         struct radeon_ring *ring = &rdev->ring[ring_index];
2864         u32 size_in_dw, cur_size_in_dw;
2865         int i, num_loops;
2866         int r = 0;
2867
2868         r = radeon_semaphore_create(rdev, &sem);
2869         if (r) {
2870                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2871                 return r;
2872         }
2873
2874         size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
2875         num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
2876         r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
2877         if (r) {
2878                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2879                 radeon_semaphore_free(rdev, &sem, NULL);
2880                 return r;
2881         }
2882
2883         if (radeon_fence_need_sync(*fence, ring->idx)) {
2884                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2885                                             ring->idx);
2886                 radeon_fence_note_sync(*fence, ring->idx);
2887         } else {
2888                 radeon_semaphore_free(rdev, &sem, NULL);
2889         }
2890
2891         for (i = 0; i < num_loops; i++) {
2892                 cur_size_in_dw = size_in_dw;
2893                 if (cur_size_in_dw > 0xFFFE)
2894                         cur_size_in_dw = 0xFFFE;
2895                 size_in_dw -= cur_size_in_dw;
2896                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
2897                 radeon_ring_write(ring, dst_offset & 0xfffffffc);
2898                 radeon_ring_write(ring, src_offset & 0xfffffffc);
2899                 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
2900                                          (upper_32_bits(src_offset) & 0xff)));
2901                 src_offset += cur_size_in_dw * 4;
2902                 dst_offset += cur_size_in_dw * 4;
2903         }
2904
2905         r = radeon_fence_emit(rdev, fence, ring->idx);
2906         if (r) {
2907                 radeon_ring_unlock_undo(rdev, ring);
2908                 return r;
2909         }
2910
2911         radeon_ring_unlock_commit(rdev, ring);
2912         radeon_semaphore_free(rdev, &sem, *fence);
2913
2914         return r;
2915 }
2916
2917 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2918                          uint32_t tiling_flags, uint32_t pitch,
2919                          uint32_t offset, uint32_t obj_size)
2920 {
2921         /* FIXME: implement */
2922         return 0;
2923 }
2924
2925 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2926 {
2927         /* FIXME: implement */
2928 }
2929
2930 static int r600_startup(struct radeon_device *rdev)
2931 {
2932         struct radeon_ring *ring;
2933         int r;
2934
2935         /* enable pcie gen2 link */
2936         r600_pcie_gen2_enable(rdev);
2937
2938         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2939                 r = r600_init_microcode(rdev);
2940                 if (r) {
2941                         DRM_ERROR("Failed to load firmware!\n");
2942                         return r;
2943                 }
2944         }
2945
2946         r = r600_vram_scratch_init(rdev);
2947         if (r)
2948                 return r;
2949
2950         r600_mc_program(rdev);
2951         if (rdev->flags & RADEON_IS_AGP) {
2952                 r600_agp_enable(rdev);
2953         } else {
2954                 r = r600_pcie_gart_enable(rdev);
2955                 if (r)
2956                         return r;
2957         }
2958         r600_gpu_init(rdev);
2959         r = r600_blit_init(rdev);
2960         if (r) {
2961                 r600_blit_fini(rdev);
2962                 rdev->asic->copy.copy = NULL;
2963                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2964         }
2965
2966         /* allocate wb buffer */
2967         r = radeon_wb_init(rdev);
2968         if (r)
2969                 return r;
2970
2971         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2972         if (r) {
2973                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2974                 return r;
2975         }
2976
2977         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2978         if (r) {
2979                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2980                 return r;
2981         }
2982
2983         /* Enable IRQ */
2984         r = r600_irq_init(rdev);
2985         if (r) {
2986                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2987                 radeon_irq_kms_fini(rdev);
2988                 return r;
2989         }
2990         r600_irq_set(rdev);
2991
2992         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2993         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2994                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2995                              0, 0xfffff, RADEON_CP_PACKET2);
2996         if (r)
2997                 return r;
2998
2999         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3000         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3001                              DMA_RB_RPTR, DMA_RB_WPTR,
3002                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3003         if (r)
3004                 return r;
3005
3006         r = r600_cp_load_microcode(rdev);
3007         if (r)
3008                 return r;
3009         r = r600_cp_resume(rdev);
3010         if (r)
3011                 return r;
3012
3013         r = r600_dma_resume(rdev);
3014         if (r)
3015                 return r;
3016
3017         r = radeon_ib_pool_init(rdev);
3018         if (r) {
3019                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3020                 return r;
3021         }
3022
3023         r = r600_audio_init(rdev);
3024         if (r) {
3025                 DRM_ERROR("radeon: audio init failed\n");
3026                 return r;
3027         }
3028
3029         return 0;
3030 }
3031
3032 void r600_vga_set_state(struct radeon_device *rdev, bool state)
3033 {
3034         uint32_t temp;
3035
3036         temp = RREG32(CONFIG_CNTL);
3037         if (state == false) {
3038                 temp &= ~(1<<0);
3039                 temp |= (1<<1);
3040         } else {
3041                 temp &= ~(1<<1);
3042         }
3043         WREG32(CONFIG_CNTL, temp);
3044 }
3045
3046 int r600_resume(struct radeon_device *rdev)
3047 {
3048         int r;
3049
3050         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3051          * posting will perform necessary task to bring back GPU into good
3052          * shape.
3053          */
3054         /* post card */
3055         atom_asic_init(rdev->mode_info.atom_context);
3056
3057         rdev->accel_working = true;
3058         r = r600_startup(rdev);
3059         if (r) {
3060                 DRM_ERROR("r600 startup failed on resume\n");
3061                 rdev->accel_working = false;
3062                 return r;
3063         }
3064
3065         return r;
3066 }
3067
3068 int r600_suspend(struct radeon_device *rdev)
3069 {
3070         r600_audio_fini(rdev);
3071         r600_cp_stop(rdev);
3072         r600_dma_stop(rdev);
3073         r600_irq_suspend(rdev);
3074         radeon_wb_disable(rdev);
3075         r600_pcie_gart_disable(rdev);
3076
3077         return 0;
3078 }
3079
3080 /* Plan is to move initialization in that function and use
3081  * helper function so that radeon_device_init pretty much
3082  * do nothing more than calling asic specific function. This
3083  * should also allow to remove a bunch of callback function
3084  * like vram_info.
3085  */
3086 int r600_init(struct radeon_device *rdev)
3087 {
3088         int r;
3089
3090         if (r600_debugfs_mc_info_init(rdev)) {
3091                 DRM_ERROR("Failed to register debugfs file for mc !\n");
3092         }
3093         /* Read BIOS */
3094         if (!radeon_get_bios(rdev)) {
3095                 if (ASIC_IS_AVIVO(rdev))
3096                         return -EINVAL;
3097         }
3098         /* Must be an ATOMBIOS */
3099         if (!rdev->is_atom_bios) {
3100                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3101                 return -EINVAL;
3102         }
3103         r = radeon_atombios_init(rdev);
3104         if (r)
3105                 return r;
3106         /* Post card if necessary */
3107         if (!radeon_card_posted(rdev)) {
3108                 if (!rdev->bios) {
3109                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3110                         return -EINVAL;
3111                 }
3112                 DRM_INFO("GPU not posted. posting now...\n");
3113                 atom_asic_init(rdev->mode_info.atom_context);
3114         }
3115         /* Initialize scratch registers */
3116         r600_scratch_init(rdev);
3117         /* Initialize surface registers */
3118         radeon_surface_init(rdev);
3119         /* Initialize clocks */
3120         radeon_get_clock_info(rdev->ddev);
3121         /* Fence driver */
3122         r = radeon_fence_driver_init(rdev);
3123         if (r)
3124                 return r;
3125         if (rdev->flags & RADEON_IS_AGP) {
3126                 r = radeon_agp_init(rdev);
3127                 if (r)
3128                         radeon_agp_disable(rdev);
3129         }
3130         r = r600_mc_init(rdev);
3131         if (r)
3132                 return r;
3133         /* Memory manager */
3134         r = radeon_bo_init(rdev);
3135         if (r)
3136                 return r;
3137
3138         r = radeon_irq_kms_init(rdev);
3139         if (r)
3140                 return r;
3141
3142         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3143         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3144
3145         rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3146         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3147
3148         rdev->ih.ring_obj = NULL;
3149         r600_ih_ring_init(rdev, 64 * 1024);
3150
3151         r = r600_pcie_gart_init(rdev);
3152         if (r)
3153                 return r;
3154
3155         rdev->accel_working = true;
3156         r = r600_startup(rdev);
3157         if (r) {
3158                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3159                 r600_cp_fini(rdev);
3160                 r600_dma_fini(rdev);
3161                 r600_irq_fini(rdev);
3162                 radeon_wb_fini(rdev);
3163                 radeon_ib_pool_fini(rdev);
3164                 radeon_irq_kms_fini(rdev);
3165                 r600_pcie_gart_fini(rdev);
3166                 rdev->accel_working = false;
3167         }
3168
3169         return 0;
3170 }
3171
3172 void r600_fini(struct radeon_device *rdev)
3173 {
3174         r600_audio_fini(rdev);
3175         r600_blit_fini(rdev);
3176         r600_cp_fini(rdev);
3177         r600_dma_fini(rdev);
3178         r600_irq_fini(rdev);
3179         radeon_wb_fini(rdev);
3180         radeon_ib_pool_fini(rdev);
3181         radeon_irq_kms_fini(rdev);
3182         r600_pcie_gart_fini(rdev);
3183         r600_vram_scratch_fini(rdev);
3184         radeon_agp_fini(rdev);
3185         radeon_gem_fini(rdev);
3186         radeon_fence_driver_fini(rdev);
3187         radeon_bo_fini(rdev);
3188         radeon_atombios_fini(rdev);
3189         r600_fini_microcode(rdev);
3190         drm_free(rdev->bios, M_DRM);
3191         rdev->bios = NULL;
3192 }
3193
3194
3195 /*
3196  * CS stuff
3197  */
3198 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3199 {
3200         struct radeon_ring *ring = &rdev->ring[ib->ring];
3201         u32 next_rptr;
3202
3203         if (ring->rptr_save_reg) {
3204                 next_rptr = ring->wptr + 3 + 4;
3205                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3206                 radeon_ring_write(ring, ((ring->rptr_save_reg -
3207                                          PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3208                 radeon_ring_write(ring, next_rptr);
3209         } else if (rdev->wb.enabled) {
3210                 next_rptr = ring->wptr + 5 + 4;
3211                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3212                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3213                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3214                 radeon_ring_write(ring, next_rptr);
3215                 radeon_ring_write(ring, 0);
3216         }
3217
3218         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3219         radeon_ring_write(ring,
3220 #ifdef __BIG_ENDIAN
3221                           (2 << 0) |
3222 #endif
3223                           (ib->gpu_addr & 0xFFFFFFFC));
3224         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3225         radeon_ring_write(ring, ib->length_dw);
3226 }
3227
3228 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3229 {
3230         struct radeon_ib ib;
3231         uint32_t scratch;
3232         uint32_t tmp = 0;
3233         unsigned i;
3234         int r;
3235
3236         r = radeon_scratch_get(rdev, &scratch);
3237         if (r) {
3238                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3239                 return r;
3240         }
3241         WREG32(scratch, 0xCAFEDEAD);
3242         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3243         if (r) {
3244                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3245                 goto free_scratch;
3246         }
3247         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3248         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3249         ib.ptr[2] = 0xDEADBEEF;
3250         ib.length_dw = 3;
3251         r = radeon_ib_schedule(rdev, &ib, NULL);
3252         if (r) {
3253                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3254                 goto free_ib;
3255         }
3256         r = radeon_fence_wait(ib.fence, false);
3257         if (r) {
3258                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3259                 goto free_ib;
3260         }
3261         for (i = 0; i < rdev->usec_timeout; i++) {
3262                 tmp = RREG32(scratch);
3263                 if (tmp == 0xDEADBEEF)
3264                         break;
3265                 DRM_UDELAY(1);
3266         }
3267         if (i < rdev->usec_timeout) {
3268                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3269         } else {
3270                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3271                           scratch, tmp);
3272                 r = -EINVAL;
3273         }
3274 free_ib:
3275         radeon_ib_free(rdev, &ib);
3276 free_scratch:
3277         radeon_scratch_free(rdev, scratch);
3278         return r;
3279 }
3280
3281 /**
3282  * r600_dma_ib_test - test an IB on the DMA engine
3283  *
3284  * @rdev: radeon_device pointer
3285  * @ring: radeon_ring structure holding ring information
3286  *
3287  * Test a simple IB in the DMA ring (r6xx-SI).
3288  * Returns 0 on success, error on failure.
3289  */
3290 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3291 {
3292         struct radeon_ib ib;
3293         unsigned i;
3294         int r;
3295         volatile uint32_t *ptr = rdev->vram_scratch.ptr;
3296         u32 tmp = 0;
3297
3298         if (!ptr) {
3299                 DRM_ERROR("invalid vram scratch pointer\n");
3300                 return -EINVAL;
3301         }
3302
3303         tmp = 0xCAFEDEAD;
3304         *ptr = tmp;
3305
3306         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3307         if (r) {
3308                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3309                 return r;
3310         }
3311
3312         ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
3313         ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3314         ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3315         ib.ptr[3] = 0xDEADBEEF;
3316         ib.length_dw = 4;
3317
3318         r = radeon_ib_schedule(rdev, &ib, NULL);
3319         if (r) {
3320                 radeon_ib_free(rdev, &ib);
3321                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3322                 return r;
3323         }
3324         r = radeon_fence_wait(ib.fence, false);
3325         if (r) {
3326                 radeon_ib_free(rdev, &ib);
3327                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3328                 return r;
3329         }
3330         for (i = 0; i < rdev->usec_timeout; i++) {
3331                 tmp = *ptr;
3332                 if (tmp == 0xDEADBEEF)
3333                         break;
3334                 DRM_UDELAY(1);
3335         }
3336         if (i < rdev->usec_timeout) {
3337                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3338         } else {
3339                 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
3340                 r = -EINVAL;
3341         }
3342         radeon_ib_free(rdev, &ib);
3343         return r;
3344 }
3345
3346 /**
3347  * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3348  *
3349  * @rdev: radeon_device pointer
3350  * @ib: IB object to schedule
3351  *
3352  * Schedule an IB in the DMA ring (r6xx-r7xx).
3353  */
3354 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3355 {
3356         struct radeon_ring *ring = &rdev->ring[ib->ring];
3357
3358         if (rdev->wb.enabled) {
3359                 u32 next_rptr = ring->wptr + 4;
3360                 while ((next_rptr & 7) != 5)
3361                         next_rptr++;
3362                 next_rptr += 3;
3363                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3364                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3365                 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3366                 radeon_ring_write(ring, next_rptr);
3367         }
3368
3369         /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3370          * Pad as necessary with NOPs.
3371          */
3372         while ((ring->wptr & 7) != 5)
3373                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3374         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3375         radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3376         radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3377
3378 }
3379
3380 /*
3381  * Interrupts
3382  *
3383  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
3384  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
3385  * writing to the ring and the GPU consuming, the GPU writes to the ring
3386  * and host consumes.  As the host irq handler processes interrupts, it
3387  * increments the rptr.  When the rptr catches up with the wptr, all the
3388  * current interrupts have been processed.
3389  */
3390
3391 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3392 {
3393         u32 rb_bufsz;
3394
3395         /* Align ring size */
3396         rb_bufsz = drm_order(ring_size / 4);
3397         ring_size = (1 << rb_bufsz) * 4;
3398         rdev->ih.ring_size = ring_size;
3399         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3400         rdev->ih.rptr = 0;
3401 }
3402
3403 int r600_ih_ring_alloc(struct radeon_device *rdev)
3404 {
3405         int r;
3406         void *ring_ptr;
3407
3408         /* Allocate ring buffer */
3409         if (rdev->ih.ring_obj == NULL) {
3410                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3411                                      PAGE_SIZE, true,
3412                                      RADEON_GEM_DOMAIN_GTT,
3413                                      NULL, &rdev->ih.ring_obj);
3414                 if (r) {
3415                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3416                         return r;
3417                 }
3418                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3419                 if (unlikely(r != 0)) {
3420                         radeon_bo_unref(&rdev->ih.ring_obj);
3421                         return r;
3422                 }
3423                 r = radeon_bo_pin(rdev->ih.ring_obj,
3424                                   RADEON_GEM_DOMAIN_GTT,
3425                                   &rdev->ih.gpu_addr);
3426                 if (r) {
3427                         radeon_bo_unreserve(rdev->ih.ring_obj);
3428                         radeon_bo_unref(&rdev->ih.ring_obj);
3429                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3430                         return r;
3431                 }
3432                 ring_ptr = &rdev->ih.ring;
3433                 r = radeon_bo_kmap(rdev->ih.ring_obj,
3434                                    ring_ptr);
3435                 if (r)
3436                         radeon_bo_unpin(rdev->ih.ring_obj);
3437                 radeon_bo_unreserve(rdev->ih.ring_obj);
3438                 if (r) {
3439                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3440                         radeon_bo_unref(&rdev->ih.ring_obj);
3441                         return r;
3442                 }
3443         }
3444         return 0;
3445 }
3446
3447 void r600_ih_ring_fini(struct radeon_device *rdev)
3448 {
3449         int r;
3450         if (rdev->ih.ring_obj) {
3451                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3452                 if (likely(r == 0)) {
3453                         radeon_bo_kunmap(rdev->ih.ring_obj);
3454                         radeon_bo_unpin(rdev->ih.ring_obj);
3455                         radeon_bo_unreserve(rdev->ih.ring_obj);
3456                 }
3457                 radeon_bo_unref(&rdev->ih.ring_obj);
3458                 rdev->ih.ring = NULL;
3459                 rdev->ih.ring_obj = NULL;
3460         }
3461 }
3462
3463 void r600_rlc_stop(struct radeon_device *rdev)
3464 {
3465
3466         if ((rdev->family >= CHIP_RV770) &&
3467             (rdev->family <= CHIP_RV740)) {
3468                 /* r7xx asics need to soft reset RLC before halting */
3469                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3470                 RREG32(SRBM_SOFT_RESET);
3471                 DRM_MDELAY(15);
3472                 WREG32(SRBM_SOFT_RESET, 0);
3473                 RREG32(SRBM_SOFT_RESET);
3474         }
3475
3476         WREG32(RLC_CNTL, 0);
3477 }
3478
3479 static void r600_rlc_start(struct radeon_device *rdev)
3480 {
3481         WREG32(RLC_CNTL, RLC_ENABLE);
3482 }
3483
3484 static int r600_rlc_init(struct radeon_device *rdev)
3485 {
3486         u32 i;
3487         const __be32 *fw_data;
3488
3489         if (!rdev->rlc_fw)
3490                 return -EINVAL;
3491
3492         r600_rlc_stop(rdev);
3493
3494         WREG32(RLC_HB_CNTL, 0);
3495
3496         if (rdev->family == CHIP_ARUBA) {
3497                 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3498                 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3499         }
3500         if (rdev->family <= CHIP_CAYMAN) {
3501                 WREG32(RLC_HB_BASE, 0);
3502                 WREG32(RLC_HB_RPTR, 0);
3503                 WREG32(RLC_HB_WPTR, 0);
3504         }
3505         if (rdev->family <= CHIP_CAICOS) {
3506                 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3507                 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3508         }
3509         WREG32(RLC_MC_CNTL, 0);
3510         WREG32(RLC_UCODE_CNTL, 0);
3511
3512         fw_data = (const __be32 *)rdev->rlc_fw->data;
3513         if (rdev->family >= CHIP_ARUBA) {
3514                 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
3515                         WREG32(RLC_UCODE_ADDR, i);
3516                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3517                 }
3518         } else if (rdev->family >= CHIP_CAYMAN) {
3519                 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
3520                         WREG32(RLC_UCODE_ADDR, i);
3521                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3522                 }
3523         } else if (rdev->family >= CHIP_CEDAR) {
3524                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
3525                         WREG32(RLC_UCODE_ADDR, i);
3526                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3527                 }
3528         } else if (rdev->family >= CHIP_RV770) {
3529                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3530                         WREG32(RLC_UCODE_ADDR, i);
3531                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3532                 }
3533         } else {
3534                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
3535                         WREG32(RLC_UCODE_ADDR, i);
3536                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3537                 }
3538         }
3539         WREG32(RLC_UCODE_ADDR, 0);
3540
3541         r600_rlc_start(rdev);
3542
3543         return 0;
3544 }
3545
3546 static void r600_enable_interrupts(struct radeon_device *rdev)
3547 {
3548         u32 ih_cntl = RREG32(IH_CNTL);
3549         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3550
3551         ih_cntl |= ENABLE_INTR;
3552         ih_rb_cntl |= IH_RB_ENABLE;
3553         WREG32(IH_CNTL, ih_cntl);
3554         WREG32(IH_RB_CNTL, ih_rb_cntl);
3555         rdev->ih.enabled = true;
3556 }
3557
3558 void r600_disable_interrupts(struct radeon_device *rdev)
3559 {
3560         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3561         u32 ih_cntl = RREG32(IH_CNTL);
3562
3563         ih_rb_cntl &= ~IH_RB_ENABLE;
3564         ih_cntl &= ~ENABLE_INTR;
3565         WREG32(IH_RB_CNTL, ih_rb_cntl);
3566         WREG32(IH_CNTL, ih_cntl);
3567         /* set rptr, wptr to 0 */
3568         WREG32(IH_RB_RPTR, 0);
3569         WREG32(IH_RB_WPTR, 0);
3570         rdev->ih.enabled = false;
3571         rdev->ih.rptr = 0;
3572 }
3573
3574 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3575 {
3576         u32 tmp;
3577
3578         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3579         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3580         WREG32(DMA_CNTL, tmp);
3581         WREG32(GRBM_INT_CNTL, 0);
3582         WREG32(DxMODE_INT_MASK, 0);
3583         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3584         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3585         if (ASIC_IS_DCE3(rdev)) {
3586                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3587                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3588                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3589                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3590                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3591                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3592                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3593                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3594                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3595                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3596                 if (ASIC_IS_DCE32(rdev)) {
3597                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3598                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3599                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3600                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3601                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3602                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3603                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3604                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3605                 } else {
3606                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3607                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3608                         tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3609                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3610                 }
3611         } else {
3612                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3613                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3614                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3615                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3616                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3617                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3618                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3619                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3620                 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3621                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3622                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3623                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3624         }
3625 }
3626
3627 int r600_irq_init(struct radeon_device *rdev)
3628 {
3629         int ret = 0;
3630         int rb_bufsz;
3631         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3632
3633         /* allocate ring */
3634         ret = r600_ih_ring_alloc(rdev);
3635         if (ret)
3636                 return ret;
3637
3638         /* disable irqs */
3639         r600_disable_interrupts(rdev);
3640
3641         /* init rlc */
3642         ret = r600_rlc_init(rdev);
3643         if (ret) {
3644                 r600_ih_ring_fini(rdev);
3645                 return ret;
3646         }
3647
3648         /* setup interrupt control */
3649         /* set dummy read address to ring address */
3650         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3651         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3652         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3653          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3654          */
3655         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3656         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3657         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3658         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3659
3660         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3661         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3662
3663         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3664                       IH_WPTR_OVERFLOW_CLEAR |
3665                       (rb_bufsz << 1));
3666
3667         if (rdev->wb.enabled)
3668                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3669
3670         /* set the writeback address whether it's enabled or not */
3671         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3672         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3673
3674         WREG32(IH_RB_CNTL, ih_rb_cntl);
3675
3676         /* set rptr, wptr to 0 */
3677         WREG32(IH_RB_RPTR, 0);
3678         WREG32(IH_RB_WPTR, 0);
3679
3680         /* Default settings for IH_CNTL (disabled at first) */
3681         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3682         /* RPTR_REARM only works if msi's are enabled */
3683         if (rdev->msi_enabled)
3684                 ih_cntl |= RPTR_REARM;
3685         WREG32(IH_CNTL, ih_cntl);
3686
3687         /* force the active interrupt state to all disabled */
3688         if (rdev->family >= CHIP_CEDAR)
3689                 evergreen_disable_interrupt_state(rdev);
3690         else
3691                 r600_disable_interrupt_state(rdev);
3692
3693         /* at this point everything should be setup correctly to enable master */
3694         pci_enable_busmaster(rdev->dev);
3695
3696         /* enable irqs */
3697         r600_enable_interrupts(rdev);
3698
3699         return ret;
3700 }
3701
3702 void r600_irq_suspend(struct radeon_device *rdev)
3703 {
3704         r600_irq_disable(rdev);
3705         r600_rlc_stop(rdev);
3706 }
3707
3708 void r600_irq_fini(struct radeon_device *rdev)
3709 {
3710         r600_irq_suspend(rdev);
3711         r600_ih_ring_fini(rdev);
3712 }
3713
3714 int r600_irq_set(struct radeon_device *rdev)
3715 {
3716         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3717         u32 mode_int = 0;
3718         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3719         u32 grbm_int_cntl = 0;
3720         u32 hdmi0, hdmi1;
3721         u32 d1grph = 0, d2grph = 0;
3722         u32 dma_cntl;
3723
3724         if (!rdev->irq.installed) {
3725                 DRM_ERROR("Can't enable IRQ/MSI because no handler is installed\n");
3726                 return -EINVAL;
3727         }
3728         /* don't enable anything if the ih is disabled */
3729         if (!rdev->ih.enabled) {
3730                 r600_disable_interrupts(rdev);
3731                 /* force the active interrupt state to all disabled */
3732                 r600_disable_interrupt_state(rdev);
3733                 return 0;
3734         }
3735
3736         if (ASIC_IS_DCE3(rdev)) {
3737                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3738                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3739                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3740                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3741                 if (ASIC_IS_DCE32(rdev)) {
3742                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3743                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3744                         hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3745                         hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3746                 } else {
3747                         hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3748                         hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3749                 }
3750         } else {
3751                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3752                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3753                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3754                 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3755                 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3756         }
3757         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3758
3759         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3760                 DRM_DEBUG("r600_irq_set: sw int\n");
3761                 cp_int_cntl |= RB_INT_ENABLE;
3762                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3763         }
3764
3765         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3766                 DRM_DEBUG("r600_irq_set: sw int dma\n");
3767                 dma_cntl |= TRAP_ENABLE;
3768         }
3769
3770         if (rdev->irq.crtc_vblank_int[0] ||
3771             atomic_read(&rdev->irq.pflip[0])) {
3772                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3773                 mode_int |= D1MODE_VBLANK_INT_MASK;
3774         }
3775         if (rdev->irq.crtc_vblank_int[1] ||
3776             atomic_read(&rdev->irq.pflip[1])) {
3777                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3778                 mode_int |= D2MODE_VBLANK_INT_MASK;
3779         }
3780         if (rdev->irq.hpd[0]) {
3781                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3782                 hpd1 |= DC_HPDx_INT_EN;
3783         }
3784         if (rdev->irq.hpd[1]) {
3785                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3786                 hpd2 |= DC_HPDx_INT_EN;
3787         }
3788         if (rdev->irq.hpd[2]) {
3789                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3790                 hpd3 |= DC_HPDx_INT_EN;
3791         }
3792         if (rdev->irq.hpd[3]) {
3793                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3794                 hpd4 |= DC_HPDx_INT_EN;
3795         }
3796         if (rdev->irq.hpd[4]) {
3797                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3798                 hpd5 |= DC_HPDx_INT_EN;
3799         }
3800         if (rdev->irq.hpd[5]) {
3801                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3802                 hpd6 |= DC_HPDx_INT_EN;
3803         }
3804         if (rdev->irq.afmt[0]) {
3805                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3806                 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3807         }
3808         if (rdev->irq.afmt[1]) {
3809                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3810                 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3811         }
3812
3813         WREG32(CP_INT_CNTL, cp_int_cntl);
3814         WREG32(DMA_CNTL, dma_cntl);
3815         WREG32(DxMODE_INT_MASK, mode_int);
3816         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3817         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3818         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3819         if (ASIC_IS_DCE3(rdev)) {
3820                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3821                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3822                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3823                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3824                 if (ASIC_IS_DCE32(rdev)) {
3825                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3826                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3827                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3828                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3829                 } else {
3830                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3831                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3832                 }
3833         } else {
3834                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3835                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3836                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3837                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3838                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3839         }
3840
3841         return 0;
3842 }
3843
3844 static void r600_irq_ack(struct radeon_device *rdev)
3845 {
3846         u32 tmp;
3847
3848         if (ASIC_IS_DCE3(rdev)) {
3849                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3850                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3851                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3852                 if (ASIC_IS_DCE32(rdev)) {
3853                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3854                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3855                 } else {
3856                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3857                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3858                 }
3859         } else {
3860                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3861                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3862                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3863                 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3864                 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3865         }
3866         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3867         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3868
3869         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3870                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3871         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3872                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3873         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3874                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3875         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3876                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3877         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3878                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3879         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3880                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3881         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3882                 if (ASIC_IS_DCE3(rdev)) {
3883                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3884                         tmp |= DC_HPDx_INT_ACK;
3885                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3886                 } else {
3887                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3888                         tmp |= DC_HPDx_INT_ACK;
3889                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3890                 }
3891         }
3892         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3893                 if (ASIC_IS_DCE3(rdev)) {
3894                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3895                         tmp |= DC_HPDx_INT_ACK;
3896                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3897                 } else {
3898                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3899                         tmp |= DC_HPDx_INT_ACK;
3900                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3901                 }
3902         }
3903         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3904                 if (ASIC_IS_DCE3(rdev)) {
3905                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3906                         tmp |= DC_HPDx_INT_ACK;
3907                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3908                 } else {
3909                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3910                         tmp |= DC_HPDx_INT_ACK;
3911                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3912                 }
3913         }
3914         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3915                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3916                 tmp |= DC_HPDx_INT_ACK;
3917                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3918         }
3919         if (ASIC_IS_DCE32(rdev)) {
3920                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3921                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3922                         tmp |= DC_HPDx_INT_ACK;
3923                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3924                 }
3925                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3926                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3927                         tmp |= DC_HPDx_INT_ACK;
3928                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3929                 }
3930                 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3931                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3932                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3933                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3934                 }
3935                 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3936                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3937                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3938                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3939                 }
3940         } else {
3941                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3942                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3943                         tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3944                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3945                 }
3946                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3947                         if (ASIC_IS_DCE3(rdev)) {
3948                                 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3949                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3950                                 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3951                         } else {
3952                                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3953                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3954                                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3955                         }
3956                 }
3957         }
3958 }
3959
3960 void r600_irq_disable(struct radeon_device *rdev)
3961 {
3962         r600_disable_interrupts(rdev);
3963         /* Wait and acknowledge irq */
3964         DRM_MDELAY(1);
3965         r600_irq_ack(rdev);
3966         r600_disable_interrupt_state(rdev);
3967 }
3968
3969 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3970 {
3971         u32 wptr, tmp;
3972
3973         if (rdev->wb.enabled)
3974                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3975         else
3976                 wptr = RREG32(IH_RB_WPTR);
3977
3978         if (wptr & RB_OVERFLOW) {
3979                 /* When a ring buffer overflow happen start parsing interrupt
3980                  * from the last not overwritten vector (wptr + 16). Hopefully
3981                  * this should allow us to catchup.
3982                  */
3983                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3984                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3985                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3986                 tmp = RREG32(IH_RB_CNTL);
3987                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3988                 WREG32(IH_RB_CNTL, tmp);
3989         }
3990         return (wptr & rdev->ih.ptr_mask);
3991 }
3992
3993 /*        r600 IV Ring
3994  * Each IV ring entry is 128 bits:
3995  * [7:0]    - interrupt source id
3996  * [31:8]   - reserved
3997  * [59:32]  - interrupt source data
3998  * [127:60]  - reserved
3999  *
4000  * The basic interrupt vector entries
4001  * are decoded as follows:
4002  * src_id  src_data  description
4003  *      1         0  D1 Vblank
4004  *      1         1  D1 Vline
4005  *      5         0  D2 Vblank
4006  *      5         1  D2 Vline
4007  *     19         0  FP Hot plug detection A
4008  *     19         1  FP Hot plug detection B
4009  *     19         2  DAC A auto-detection
4010  *     19         3  DAC B auto-detection
4011  *     21         4  HDMI block A
4012  *     21         5  HDMI block B
4013  *    176         -  CP_INT RB
4014  *    177         -  CP_INT IB1
4015  *    178         -  CP_INT IB2
4016  *    181         -  EOP Interrupt
4017  *    233         -  GUI Idle
4018  *
4019  * Note, these are based on r600 and may need to be
4020  * adjusted or added to on newer asics
4021  */
4022
4023 irqreturn_t r600_irq_process(struct radeon_device *rdev)
4024 {
4025         u32 wptr;
4026         u32 rptr;
4027         u32 src_id, src_data;
4028         u32 ring_index;
4029         bool queue_hotplug = false;
4030         bool queue_hdmi = false;
4031
4032         if (!rdev->ih.enabled || rdev->shutdown)
4033                 return IRQ_NONE;
4034
4035         /* No MSIs, need a dummy read to flush PCI DMAs */
4036         if (!rdev->msi_enabled)
4037                 RREG32(IH_RB_WPTR);
4038
4039         wptr = r600_get_ih_wptr(rdev);
4040
4041 restart_ih:
4042         /* is somebody else already processing irqs? */
4043         if (atomic_xchg(&rdev->ih.lock, 1))
4044                 return IRQ_NONE;
4045
4046         rptr = rdev->ih.rptr;
4047         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
4048
4049         /* Order reading of wptr vs. reading of IH ring data */
4050         cpu_lfence();
4051
4052         /* display interrupts */
4053         r600_irq_ack(rdev);
4054
4055         while (rptr != wptr) {
4056                 /* wptr/rptr are in bytes! */
4057                 ring_index = rptr / 4;
4058                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4059                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4060
4061                 switch (src_id) {
4062                 case 1: /* D1 vblank/vline */
4063                         switch (src_data) {
4064                         case 0: /* D1 vblank */
4065                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
4066                                         if (rdev->irq.crtc_vblank_int[0]) {
4067                                                 drm_handle_vblank(rdev->ddev, 0);
4068                                                 rdev->pm.vblank_sync = true;
4069                                                 DRM_WAKEUP(&rdev->irq.vblank_queue);
4070                                         }
4071                                         if (atomic_read(&rdev->irq.pflip[0]))
4072                                                 radeon_crtc_handle_flip(rdev, 0);
4073                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4074                                         DRM_DEBUG("IH: D1 vblank\n");
4075                                 }
4076                                 break;
4077                         case 1: /* D1 vline */
4078                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
4079                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4080                                         DRM_DEBUG("IH: D1 vline\n");
4081                                 }
4082                                 break;
4083                         default:
4084                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4085                                 break;
4086                         }
4087                         break;
4088                 case 5: /* D2 vblank/vline */
4089                         switch (src_data) {
4090                         case 0: /* D2 vblank */
4091                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
4092                                         if (rdev->irq.crtc_vblank_int[1]) {
4093                                                 drm_handle_vblank(rdev->ddev, 1);
4094                                                 rdev->pm.vblank_sync = true;
4095                                                 DRM_WAKEUP(&rdev->irq.vblank_queue);
4096                                         }
4097                                         if (atomic_read(&rdev->irq.pflip[1]))
4098                                                 radeon_crtc_handle_flip(rdev, 1);
4099                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4100                                         DRM_DEBUG("IH: D2 vblank\n");
4101                                 }
4102                                 break;
4103                         case 1: /* D1 vline */
4104                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
4105                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4106                                         DRM_DEBUG("IH: D2 vline\n");
4107                                 }
4108                                 break;
4109                         default:
4110                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4111                                 break;
4112                         }
4113                         break;
4114                 case 19: /* HPD/DAC hotplug */
4115                         switch (src_data) {
4116                         case 0:
4117                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
4118                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4119                                         queue_hotplug = true;
4120                                         DRM_DEBUG("IH: HPD1\n");
4121                                 }
4122                                 break;
4123                         case 1:
4124                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
4125                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4126                                         queue_hotplug = true;
4127                                         DRM_DEBUG("IH: HPD2\n");
4128                                 }
4129                                 break;
4130                         case 4:
4131                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
4132                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4133                                         queue_hotplug = true;
4134                                         DRM_DEBUG("IH: HPD3\n");
4135                                 }
4136                                 break;
4137                         case 5:
4138                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
4139                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4140                                         queue_hotplug = true;
4141                                         DRM_DEBUG("IH: HPD4\n");
4142                                 }
4143                                 break;
4144                         case 10:
4145                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
4146                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4147                                         queue_hotplug = true;
4148                                         DRM_DEBUG("IH: HPD5\n");
4149                                 }
4150                                 break;
4151                         case 12:
4152                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4153                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4154                                         queue_hotplug = true;
4155                                         DRM_DEBUG("IH: HPD6\n");
4156                                 }
4157                                 break;
4158                         default:
4159                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4160                                 break;
4161                         }
4162                         break;
4163                 case 21: /* hdmi */
4164                         switch (src_data) {
4165                         case 4:
4166                                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4167                                         rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4168                                         queue_hdmi = true;
4169                                         DRM_DEBUG("IH: HDMI0\n");
4170                                 }
4171                                 break;
4172                         case 5:
4173                                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4174                                         rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4175                                         queue_hdmi = true;
4176                                         DRM_DEBUG("IH: HDMI1\n");
4177                                 }
4178                                 break;
4179                         default:
4180                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4181                                 break;
4182                         }
4183                         break;
4184                 case 176: /* CP_INT in ring buffer */
4185                 case 177: /* CP_INT in IB1 */
4186                 case 178: /* CP_INT in IB2 */
4187                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
4188                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4189                         break;
4190                 case 181: /* CP EOP event */
4191                         DRM_DEBUG("IH: CP EOP\n");
4192                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4193                         break;
4194                 case 224: /* DMA trap event */
4195                         DRM_DEBUG("IH: DMA trap\n");
4196                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4197                         break;
4198                 case 233: /* GUI IDLE */
4199                         DRM_DEBUG("IH: GUI idle\n");
4200                         break;
4201                 default:
4202                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4203                         break;
4204                 }
4205
4206                 /* wptr/rptr are in bytes! */
4207                 rptr += 16;
4208                 rptr &= rdev->ih.ptr_mask;
4209         }
4210         if (queue_hotplug)
4211                 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work);
4212         if (queue_hdmi)
4213                 taskqueue_enqueue(rdev->tq, &rdev->audio_work);
4214         rdev->ih.rptr = rptr;
4215         WREG32(IH_RB_RPTR, rdev->ih.rptr);
4216         atomic_set(&rdev->ih.lock, 0);
4217
4218         /* make sure wptr hasn't changed while processing */
4219         wptr = r600_get_ih_wptr(rdev);
4220         if (wptr != rptr)
4221                 goto restart_ih;
4222
4223         return IRQ_HANDLED;
4224 }
4225
4226 /*
4227  * Debugfs info
4228  */
4229 #if defined(CONFIG_DEBUG_FS)
4230
4231 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4232 {
4233         struct drm_info_node *node = (struct drm_info_node *) m->private;
4234         struct drm_device *dev = node->minor->dev;
4235         struct radeon_device *rdev = dev->dev_private;
4236
4237         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4238         DREG32_SYS(m, rdev, VM_L2_STATUS);
4239         return 0;
4240 }
4241
4242 static struct drm_info_list r600_mc_info_list[] = {
4243         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4244 };
4245 #endif
4246
4247 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4248 {
4249 #if defined(CONFIG_DEBUG_FS)
4250         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4251 #else
4252         return 0;
4253 #endif
4254 }
4255
4256 /**
4257  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4258  * rdev: radeon device structure
4259  * bo: buffer object struct which userspace is waiting for idle
4260  *
4261  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4262  * through ring buffer, this leads to corruption in rendering, see
4263  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4264  * directly perform HDP flush by writing register through MMIO.
4265  */
4266 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4267 {
4268         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
4269          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4270          * This seems to cause problems on some AGP cards. Just use the old
4271          * method for them.
4272          */
4273         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4274             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4275                 volatile uint32_t *ptr = rdev->vram_scratch.ptr;
4276                 u32 tmp;
4277
4278                 WREG32(HDP_DEBUG1, 0);
4279                 tmp = *ptr;
4280         } else
4281                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4282 }
4283
4284 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4285 {
4286         u32 link_width_cntl, mask, target_reg;
4287
4288         if (rdev->flags & RADEON_IS_IGP)
4289                 return;
4290
4291         if (!(rdev->flags & RADEON_IS_PCIE))
4292                 return;
4293
4294         /* x2 cards have a special sequence */
4295         if (ASIC_IS_X2(rdev))
4296                 return;
4297
4298         /* FIXME wait for idle */
4299
4300         switch (lanes) {
4301         case 0:
4302                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4303                 break;
4304         case 1:
4305                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4306                 break;
4307         case 2:
4308                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4309                 break;
4310         case 4:
4311                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4312                 break;
4313         case 8:
4314                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4315                 break;
4316         case 12:
4317                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4318                 break;
4319         case 16:
4320         default:
4321                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4322                 break;
4323         }
4324
4325         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4326
4327         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
4328             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
4329                 return;
4330
4331         if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
4332                 return;
4333
4334         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
4335                              RADEON_PCIE_LC_RECONFIG_NOW |
4336                              R600_PCIE_LC_RENEGOTIATE_EN |
4337                              R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4338         link_width_cntl |= mask;
4339
4340         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4341
4342         /* some northbridges can renegotiate the link rather than requiring
4343          * a complete re-config.
4344          * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
4345          */
4346         if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
4347                 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
4348         else
4349                 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
4350
4351         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
4352                                                        RADEON_PCIE_LC_RECONFIG_NOW));
4353
4354         if (rdev->family >= CHIP_RV770)
4355                 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
4356         else
4357                 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
4358
4359         /* wait for lane set to complete */
4360         link_width_cntl = RREG32(target_reg);
4361         while (link_width_cntl == 0xffffffff)
4362                 link_width_cntl = RREG32(target_reg);
4363
4364 }
4365
4366 int r600_get_pcie_lanes(struct radeon_device *rdev)
4367 {
4368         u32 link_width_cntl;
4369
4370         if (rdev->flags & RADEON_IS_IGP)
4371                 return 0;
4372
4373         if (!(rdev->flags & RADEON_IS_PCIE))
4374                 return 0;
4375
4376         /* x2 cards have a special sequence */
4377         if (ASIC_IS_X2(rdev))
4378                 return 0;
4379
4380         /* FIXME wait for idle */
4381
4382         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4383
4384         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4385         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4386                 return 0;
4387         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4388                 return 1;
4389         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4390                 return 2;
4391         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4392                 return 4;
4393         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4394                 return 8;
4395         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4396         default:
4397                 return 16;
4398         }
4399 }
4400
4401 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4402 {
4403         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4404         u16 link_cntl2;
4405         u32 mask;
4406         int ret;
4407
4408         if (radeon_pcie_gen2 == 0)
4409                 return;
4410
4411         if (rdev->flags & RADEON_IS_IGP)
4412                 return;
4413
4414         if (!(rdev->flags & RADEON_IS_PCIE))
4415                 return;
4416
4417         /* x2 cards have a special sequence */
4418         if (ASIC_IS_X2(rdev))
4419                 return;
4420
4421         /* only RV6xx+ chips are supported */
4422         if (rdev->family <= CHIP_R600)
4423                 return;
4424
4425         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
4426         if (ret != 0)
4427                 return;
4428
4429         if (!(mask & DRM_PCIE_SPEED_50))
4430                 return;
4431
4432         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4433         if (speed_cntl & LC_CURRENT_DATA_RATE) {
4434                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4435                 return;
4436         }
4437
4438         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4439
4440         /* 55 nm r6xx asics */
4441         if ((rdev->family == CHIP_RV670) ||
4442             (rdev->family == CHIP_RV620) ||
4443             (rdev->family == CHIP_RV635)) {
4444                 /* advertise upconfig capability */
4445                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4446                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4447                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4448                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4449                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4450                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4451                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4452                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
4453                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4454                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4455                 } else {
4456                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4457                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4458                 }
4459         }
4460
4461         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4462         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4463             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4464
4465                 /* 55 nm r6xx asics */
4466                 if ((rdev->family == CHIP_RV670) ||
4467                     (rdev->family == CHIP_RV620) ||
4468                     (rdev->family == CHIP_RV635)) {
4469                         WREG32(MM_CFGREGS_CNTL, 0x8);
4470                         link_cntl2 = RREG32(0x4088);
4471                         WREG32(MM_CFGREGS_CNTL, 0);
4472                         /* not supported yet */
4473                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4474                                 return;
4475                 }
4476
4477                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4478                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4479                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4480                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4481                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4482                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4483
4484                 tmp = RREG32(0x541c);
4485                 WREG32(0x541c, tmp | 0x8);
4486                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4487                 link_cntl2 = RREG16(0x4088);
4488                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4489                 link_cntl2 |= 0x2;
4490                 WREG16(0x4088, link_cntl2);
4491                 WREG32(MM_CFGREGS_CNTL, 0);
4492
4493                 if ((rdev->family == CHIP_RV670) ||
4494                     (rdev->family == CHIP_RV620) ||
4495                     (rdev->family == CHIP_RV635)) {
4496                         training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
4497                         training_cntl &= ~LC_POINT_7_PLUS_EN;
4498                         WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
4499                 } else {
4500                         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4501                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4502                         WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4503                 }
4504
4505                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4506                 speed_cntl |= LC_GEN2_EN_STRAP;
4507                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4508
4509         } else {
4510                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4511                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4512                 if (1)
4513                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4514                 else
4515                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4516                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4517         }
4518 }
4519
4520 /**
4521  * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4522  *
4523  * @rdev: radeon_device pointer
4524  *
4525  * Fetches a GPU clock counter snapshot (R6xx-cayman).
4526  * Returns the 64 bit clock counter snapshot.
4527  */
4528 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4529 {
4530         uint64_t clock;
4531
4532         spin_lock(&rdev->gpu_clock_mutex);
4533         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4534         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4535                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4536         spin_unlock(&rdev->gpu_clock_mutex);
4537         return clock;
4538 }