1 /* $FreeBSD: src/sys/dev/snc/dp83932subr.c,v 1.2.2.2 2003/06/01 04:24:50 nyan Exp $ */
2 /* $DragonFly: src/sys/dev/netif/snc/Attic/dp83932subr.c,v 1.4 2003/08/27 09:38:32 rob Exp $ */
3 /* $NecBSD: dp83932subr.c,v 1.5.6.2 1999/10/09 05:47:23 kmatsuda Exp $ */
7 * Copyright (c) 1997, 1998, 1999
8 * Kouichi Matsuda. All rights reserved.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Kouichi Matsuda for
22 * 4. The name of the author may not be used to endorse or promote products
23 * derived from this software without specific prior written permission
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Routines of NEC PC-9801-83, 84, 103, 104, PC-9801N-25 and PC-9801N-J02, J02R
38 * Ethernet interface for NetBSD/pc98, ported by Kouichi Matsuda.
40 * These cards use National Semiconductor DP83934AVQB as Ethernet Controller
41 * and National Semiconductor NS46C46 as (64 * 16 bits) Microwire Serial EEPROM.
45 * Modified for FreeBSD(98) 4.0 from NetBSD/pc98 1.4.2 by Motomichi Matsuzaki.
48 #include <sys/param.h>
49 #include <sys/systm.h>
51 #include <sys/protosw.h>
52 #include <sys/socket.h>
53 #include <sys/syslog.h>
54 #include <sys/errno.h>
56 #include <net/ethernet.h>
58 #include <net/if_arp.h>
59 #include <net/if_dl.h>
60 #include <net/if_types.h>
61 #include <net/if_media.h>
64 #include <netinet/in.h>
65 #include <netinet/in_systm.h>
66 #include <netinet/in_var.h>
67 #include <netinet/ip.h>
68 #include <netinet/if_inarp.h>
74 #include <machine/clock.h>
75 #include <machine/cpu.h>
76 #include <machine/bus_pio.h>
77 #include <machine/bus_memio.h>
78 #include <machine/bus.h>
80 #include "dp83932reg.h"
81 #include "dp83932var.h"
82 #include "if_sncreg.h"
83 #include "dp83932subr.h"
85 integrate u_int16_t snc_nec16_select_bank
86 (struct snc_softc *, u_int32_t, u_int32_t);
89 * Interface exists: make available by filling in network interface
90 * record. System will initialize the interface when it is ready
103 * Put the pup in reset mode (sncinit() will fix it later),
104 * stop the timer, disable all interrupts and clear any interrupts.
106 NIC_PUT(sc, SNCR_CR, CR_STP);
108 NIC_PUT(sc, SNCR_CR, CR_RST);
110 NIC_PUT(sc, SNCR_IMR, 0);
112 NIC_PUT(sc, SNCR_ISR, ISR_ALL);
116 * because the SONIC is basically 16bit device it 'concatenates'
117 * a higher buffer address to a 16 bit offset--this will cause wrap
118 * around problems near the end of 64k !!
122 for (i = 0; i < NRRA; i++) {
123 sc->v_rra[i] = SONIC_GETDMA(p);
124 p += RXRSRC_SIZE(sc);
126 sc->v_rea = SONIC_GETDMA(p);
130 sc->v_cda = SONIC_GETDMA(p);
135 for (i = 0; i < NTDA; i++) {
136 struct mtd *mtdp = &sc->mtda[i];
137 mtdp->mtd_vtxp = SONIC_GETDMA(p);
143 if ((p - pp) > NBPG) {
144 device_printf (sc->sc_dev, "sizeof RRA (%ld) + CDA (%ld) +"
145 "TDA (%ld) > NBPG (%d). Punt!\n",
146 (ulong)sc->v_cda - (ulong)sc->v_rra[0],
147 (ulong)sc->mtda[0].mtd_vtxp - (ulong)sc->v_cda,
148 (ulong)p - (ulong)sc->mtda[0].mtd_vtxp,
156 sc->sc_nrda = NBPG / RXPKT_SIZE(sc);
157 sc->v_rda = SONIC_GETDMA(p);
161 for (i = 0; i < NRBA; i++) {
168 for (i = 0; i < NTDA; i++) {
169 struct mtd *mtdp = &sc->mtda[i];
171 mtdp->mtd_vbuf = SONIC_GETDMA(p);
186 * miscellaneous NEC/SONIC detect functions.
190 * check if a specified irq is acceptable.
193 snc_nec16_validate_irq(irq)
196 const u_int8_t encoded_irq[16] = {
197 -1, -1, -1, 0, -1, 1, 2, -1, -1, 3, 4, -1, 5, 6, -1, -1
200 return encoded_irq[irq];
204 * specify irq to board.
207 snc_nec16_register_irq(sc, irq)
208 struct snc_softc *sc;
211 bus_space_tag_t iot = sc->sc_iot;
212 bus_space_handle_t ioh = sc->sc_ioh;
213 u_int8_t encoded_irq;
215 encoded_irq = snc_nec16_validate_irq(irq);
216 if (encoded_irq == (u_int8_t) -1) {
217 printf("snc_nec16_register_irq: unsupported irq (%d)\n", irq);
221 /* select SNECR_IRQSEL register */
222 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_IRQSEL);
223 /* write encoded irq value */
224 bus_space_write_1(iot, ioh, SNEC_CTRLB, encoded_irq);
230 * check if a specified memory base address is acceptable.
233 snc_nec16_validate_mem(maddr)
237 /* Check on Normal mode with max range, only */
238 if ((maddr & ~0x1E000) != 0xC0000) {
239 printf("snc_nec16_validate_mem: "
240 "unsupported window base (0x%x)\n", maddr);
248 * specify memory base address to board and map to first bank.
251 snc_nec16_register_mem(sc, maddr)
252 struct snc_softc *sc;
255 bus_space_tag_t iot = sc->sc_iot;
256 bus_space_handle_t ioh = sc->sc_ioh;
258 if (snc_nec16_validate_mem(maddr) == 0)
261 /* select SNECR_MEMSEL register */
262 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMSEL);
263 /* write encoded memory base select value */
264 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_MEMSEL_PHYS2EN(maddr));
267 * set current bank to 0 (bottom) and map
269 /* select SNECR_MEMBS register */
270 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
271 /* select new bank */
272 bus_space_write_1(iot, ioh, SNEC_CTRLB,
273 SNECR_MEMBS_B2EB(0) | SNECR_MEMBS_BSEN);
274 /* set current bank to 0 */
281 snc_nec16_check_memory(iot, ioh, memt, memh)
283 bus_space_handle_t ioh;
284 bus_space_tag_t memt;
285 bus_space_handle_t memh;
291 for (i = 0; i < SNEC_NBANK; i++) {
292 /* select new bank */
293 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
294 bus_space_write_1(iot, ioh, SNEC_CTRLB,
295 SNECR_MEMBS_B2EB(i) | SNECR_MEMBS_BSEN);
297 /* write test pattern */
298 for (j = 0; j < SNEC_NMEMS / 2; j++) {
299 bus_space_write_2(memt, memh, j * 2, val + j);
305 for (i = 0; i < SNEC_NBANK; i++) {
306 /* select new bank */
307 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
308 bus_space_write_1(iot, ioh, SNEC_CTRLB,
309 SNECR_MEMBS_B2EB(i) | SNECR_MEMBS_BSEN);
311 /* read test pattern */
312 for (j = 0; j < SNEC_NMEMS / 2; j++) {
313 if (bus_space_read_2(memt, memh, j * 2) != val + j)
317 if (j < SNEC_NMEMS / 2) {
318 printf("snc_nec16_check_memory: "
319 "memory check failed at 0x%04x%04x"
320 "val 0x%04x != expected 0x%04x\n", i, j,
321 bus_space_read_2(memt, memh, j * 2),
329 for (i = 0; i < SNEC_NBANK; i++) {
330 /* select new bank */
331 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
332 bus_space_write_1(iot, ioh, SNEC_CTRLB,
333 SNECR_MEMBS_B2EB(i) | SNECR_MEMBS_BSEN);
335 bus_space_set_region_4(memt, memh, 0, 0, SNEC_NMEMS >> 2);
338 /* again read test if these are 0 */
339 for (i = 0; i < SNEC_NBANK; i++) {
340 /* select new bank */
341 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
342 bus_space_write_1(iot, ioh, SNEC_CTRLB,
343 SNECR_MEMBS_B2EB(i) | SNECR_MEMBS_BSEN);
345 /* check if cleared */
346 for (j = 0; j < SNEC_NMEMS; j += 2) {
347 if (bus_space_read_2(memt, memh, j) != 0)
351 if (j != SNEC_NMEMS) {
352 printf("snc_nec16_check_memory: "
353 "memory zero clear failed at 0x%04x%04x\n", i, j);
362 snc_nec16_detectsubr(iot, ioh, memt, memh, irq, maddr, type)
364 bus_space_handle_t ioh;
365 bus_space_tag_t memt;
366 bus_space_handle_t memh;
375 if (snc_nec16_validate_irq(irq) == (u_int8_t) -1)
377 /* XXX: maddr already checked */
378 if (snc_nec16_validate_mem(maddr) == 0)
381 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_IDENT);
382 ident = bus_space_read_1(iot, ioh, SNEC_CTRLB);
383 if (ident == 0xff || ident == 0x00) {
389 case SNEC_TYPE_LEGACY:
390 rv = (ident == SNECR_IDENT_LEGACY_CBUS);
393 rv = ((ident == SNECR_IDENT_PNP_CBUS) ||
394 (ident == SNECR_IDENT_PNP_PCMCIABUS));
401 printf("snc_nec16_detectsubr: parent bus mismatch\n");
405 /* select SONIC register SNCR_CR */
406 bus_space_write_1(iot, ioh, SNEC_ADDR, SNCR_CR);
407 bus_space_write_2(iot, ioh, SNEC_CTRL, CR_RXDIS | CR_STP | CR_RST);
410 cr = bus_space_read_2(iot, ioh, SNEC_CTRL);
411 if (cr != (CR_RXDIS | CR_STP | CR_RST)) {
413 printf("snc_nec16_detectsubr: card reset failed, cr = 0x%04x\n",
419 if (snc_nec16_check_memory(iot, ioh, memt, memh) == 0)
426 #define SNC_VENDOR_NEC 0x00004c
427 #define SNC_NEC_SERIES_LEGACY_CBUS 0xa5
428 #define SNC_NEC_SERIES_PNP_PCMCIA 0xd5
429 #define SNC_NEC_SERIES_PNP_PCMCIA2 0x6d /* XXX */
430 #define SNC_NEC_SERIES_PNP_CBUS 0x0d
431 #define SNC_NEC_SERIES_PNP_CBUS2 0x3d
434 snc_nec16_detect_type(myea)
437 u_int32_t vendor = (myea[0] << 16) | (myea[1] << 8) | myea[2];
438 u_int8_t series = myea[3];
439 u_int8_t type = myea[4] & 0x80;
445 case SNC_NEC_SERIES_LEGACY_CBUS:
447 typestr = "NEC PC-9801-84";
449 typestr = "NEC PC-9801-83";
451 case SNC_NEC_SERIES_PNP_CBUS:
452 case SNC_NEC_SERIES_PNP_CBUS2:
454 typestr = "NEC PC-9801-104";
456 typestr = "NEC PC-9801-103";
458 case SNC_NEC_SERIES_PNP_PCMCIA:
459 case SNC_NEC_SERIES_PNP_PCMCIA2:
462 typestr = "NEC PC-9801N-J02R";
464 typestr = "NEC PC-9801N-J02";
467 typestr = "NEC unknown (PC-9801N-25?)";
472 typestr = "unknown (3rd vendor?)";
480 snc_nec16_get_enaddr(iot, ioh, myea)
482 bus_space_handle_t ioh;
485 u_int8_t eeprom[SNEC_EEPROM_SIZE];
486 u_int8_t rom_sum, sum = 0x00;
489 snc_nec16_read_eeprom(iot, ioh, eeprom);
491 for (i = SNEC_EEPROM_KEY0; i < SNEC_EEPROM_CKSUM; i++) {
492 sum = sum ^ eeprom[i];
495 rom_sum = eeprom[SNEC_EEPROM_CKSUM];
497 if (sum != rom_sum) {
498 printf("snc_nec16_get_enaddr: "
499 "checksum mismatch; calculated %02x != read %02x",
504 for (i = 0; i < ETHER_ADDR_LEN; i++)
505 myea[i] = eeprom[SNEC_EEPROM_SA0 + i];
511 * read from NEC/SONIC NIC register.
514 snc_nec16_nic_get(sc, reg)
515 struct snc_softc *sc;
520 /* select SONIC register */
521 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SNEC_ADDR, reg);
522 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, SNEC_CTRL);
528 * write to NEC/SONIC NIC register.
531 snc_nec16_nic_put(sc, reg, val)
532 struct snc_softc *sc;
537 /* select SONIC register */
538 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SNEC_ADDR, reg);
539 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SNEC_CTRL, val);
544 * select memory bank and map
545 * where exists specified (internal buffer memory) offset.
548 snc_nec16_select_bank(sc, base, offset)
549 struct snc_softc *sc;
553 bus_space_tag_t iot = sc->sc_iot;
554 bus_space_handle_t ioh = sc->sc_ioh;
558 /* bitmode is fixed to 16 bit. */
559 bank = (base + offset * 2) >> 13;
560 noffset = (base + offset * 2) & (SNEC_NMEMS - 1);
564 device_printf(sc->sc_dev, "noffset is odd (0x%04x)\n",
567 #endif /* SNCDEBUG */
569 if (sc->curbank != bank) {
570 /* select SNECR_MEMBS register */
571 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
572 /* select new bank */
573 bus_space_write_1(iot, ioh, SNEC_CTRLB,
574 SNECR_MEMBS_B2EB(bank) | SNECR_MEMBS_BSEN);
575 /* update current bank */
583 * write to SONIC descriptors.
586 snc_nec16_writetodesc(sc, base, offset, val)
587 struct snc_softc *sc;
592 bus_space_tag_t memt = sc->sc_memt;
593 bus_space_handle_t memh = sc->sc_memh;
596 noffset = snc_nec16_select_bank(sc, base, offset);
598 bus_space_write_2(memt, memh, noffset, val);
602 * read from SONIC descriptors.
605 snc_nec16_readfromdesc(sc, base, offset)
606 struct snc_softc *sc;
610 bus_space_tag_t memt = sc->sc_memt;
611 bus_space_handle_t memh = sc->sc_memh;
614 noffset = snc_nec16_select_bank(sc, base, offset);
616 return bus_space_read_2(memt, memh, noffset);
620 * read from SONIC data buffer.
623 snc_nec16_copyfrombuf(sc, dst, offset, size)
624 struct snc_softc *sc;
629 bus_space_tag_t memt = sc->sc_memt;
630 bus_space_handle_t memh = sc->sc_memh;
632 u_int8_t* bptr = dst;
634 noffset = snc_nec16_select_bank(sc, offset, 0);
636 /* XXX: should check if offset + size < 0x2000. */
638 bus_space_barrier(memt, memh, noffset, size,
639 BUS_SPACE_BARRIER_READ);
643 size_t asize = 4 - (noffset & 3);
645 bus_space_read_region_1(memt, memh, noffset,
651 bus_space_read_region_4(memt, memh, noffset,
652 (u_int32_t *) bptr, size >> 2);
654 noffset += size & ~3;
658 bus_space_read_region_1(memt, memh, noffset, bptr, size);
662 * write to SONIC data buffer.
665 snc_nec16_copytobuf(sc, src, offset, size)
666 struct snc_softc *sc;
671 bus_space_tag_t memt = sc->sc_memt;
672 bus_space_handle_t memh = sc->sc_memh;
673 u_int16_t noffset, onoffset;
675 u_int8_t* bptr = src;
677 noffset = snc_nec16_select_bank(sc, offset, 0);
680 /* XXX: should check if offset + size < 0x2000. */
684 size_t asize = 4 - (noffset & 3);
686 bus_space_write_region_1(memt, memh, noffset,
692 bus_space_write_region_4(memt, memh, noffset,
693 (u_int32_t *)bptr, size >> 2);
695 noffset += size & ~3;
699 bus_space_write_region_1(memt, memh, noffset, bptr, size);
701 bus_space_barrier(memt, memh, onoffset, osize,
702 BUS_SPACE_BARRIER_WRITE);
706 * write (fill) 0 to SONIC data buffer.
709 snc_nec16_zerobuf(sc, offset, size)
710 struct snc_softc *sc;
714 bus_space_tag_t memt = sc->sc_memt;
715 bus_space_handle_t memh = sc->sc_memh;
716 u_int16_t noffset, onoffset;
719 noffset = snc_nec16_select_bank(sc, offset, 0);
722 /* XXX: should check if offset + size < 0x2000. */
726 size_t asize = 4 - (noffset & 3);
728 bus_space_set_region_1(memt, memh, noffset, 0, asize);
732 bus_space_set_region_4(memt, memh, noffset, 0, size >> 2);
733 noffset += size & ~3;
737 bus_space_set_region_1(memt, memh, noffset, 0, size);
739 bus_space_barrier(memt, memh, onoffset, osize,
740 BUS_SPACE_BARRIER_WRITE);
745 * Routines to read bytes sequentially from EEPROM through NEC PC-9801-83,
746 * 84, 103, 104, PC-9801N-25 and PC-9801N-J02, J02R for NetBSD/pc98.
747 * Ported by Kouichi Matsuda.
749 * This algorism is generic to read data sequentially from 4-Wire
750 * Microwire Serial EEPROM.
753 #define SNEC_EEP_DELAY 1000
756 snc_nec16_read_eeprom(iot, ioh, data)
758 bus_space_handle_t ioh;
761 u_int8_t n, val, bit;
763 /* Read bytes from EEPROM; two bytes per an iteration. */
764 for (n = 0; n < SNEC_EEPROM_SIZE / 2; n++) {
765 /* select SNECR_EEP */
766 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_EEP);
768 bus_space_write_1(iot, ioh, SNEC_CTRLB, 0x00);
769 delay(SNEC_EEP_DELAY);
771 /* Start EEPROM access. */
772 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
773 delay(SNEC_EEP_DELAY);
775 bus_space_write_1(iot, ioh, SNEC_CTRLB,
776 SNECR_EEP_CS | SNECR_EEP_SK);
777 delay(SNEC_EEP_DELAY);
779 bus_space_write_1(iot, ioh, SNEC_CTRLB,
780 SNECR_EEP_CS | SNECR_EEP_DI);
781 delay(SNEC_EEP_DELAY);
783 bus_space_write_1(iot, ioh, SNEC_CTRLB,
784 SNECR_EEP_CS | SNECR_EEP_SK | SNECR_EEP_DI);
785 delay(SNEC_EEP_DELAY);
787 bus_space_write_1(iot, ioh, SNEC_CTRLB,
788 SNECR_EEP_CS | SNECR_EEP_DI);
789 delay(SNEC_EEP_DELAY);
791 bus_space_write_1(iot, ioh, SNEC_CTRLB,
792 SNECR_EEP_CS | SNECR_EEP_SK | SNECR_EEP_DI);
793 delay(SNEC_EEP_DELAY);
795 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
796 delay(SNEC_EEP_DELAY);
798 bus_space_write_1(iot, ioh, SNEC_CTRLB,
799 SNECR_EEP_CS | SNECR_EEP_SK);
800 delay(SNEC_EEP_DELAY);
802 /* Pass the iteration count to the chip. */
803 for (bit = 0x20; bit != 0x00; bit >>= 1) {
804 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS |
805 ((n & bit) ? SNECR_EEP_DI : 0x00));
806 delay(SNEC_EEP_DELAY);
808 bus_space_write_1(iot, ioh, SNEC_CTRLB,
809 SNECR_EEP_CS | SNECR_EEP_SK |
810 ((n & bit) ? SNECR_EEP_DI : 0x00));
811 delay(SNEC_EEP_DELAY);
814 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
815 (void) bus_space_read_1(iot, ioh, SNEC_CTRLB); /* ACK */
816 delay(SNEC_EEP_DELAY);
820 for (bit = 0x80; bit != 0x00; bit >>= 1) {
821 bus_space_write_1(iot, ioh, SNEC_CTRLB,
822 SNECR_EEP_CS | SNECR_EEP_SK);
823 delay(SNEC_EEP_DELAY);
825 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
827 if (bus_space_read_1(iot, ioh, SNEC_CTRLB) & SNECR_EEP_DO)
832 /* Read one more byte. */
834 for (bit = 0x80; bit != 0x00; bit >>= 1) {
835 bus_space_write_1(iot, ioh, SNEC_CTRLB,
836 SNECR_EEP_CS | SNECR_EEP_SK);
837 delay(SNEC_EEP_DELAY);
839 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
841 if (bus_space_read_1(iot, ioh, SNEC_CTRLB) & SNECR_EEP_DO)
846 bus_space_write_1(iot, ioh, SNEC_CTRLB, 0x00);
847 delay(SNEC_EEP_DELAY);
851 /* Report what we got. */
852 data -= SNEC_EEPROM_SIZE;
853 log(LOG_INFO, "%s: EEPROM:"
854 " %02x%02x%02x%02x %02x%02x%02x%02x -"
855 " %02x%02x%02x%02x %02x%02x%02x%02x -"
856 " %02x%02x%02x%02x %02x%02x%02x%02x -"
857 " %02x%02x%02x%02x %02x%02x%02x%02x\n",
858 "snc_nec16_read_eeprom",
859 data[ 0], data[ 1], data[ 2], data[ 3],
860 data[ 4], data[ 5], data[ 6], data[ 7],
861 data[ 8], data[ 9], data[10], data[11],
862 data[12], data[13], data[14], data[15],
863 data[16], data[17], data[18], data[19],
864 data[20], data[21], data[22], data[23],
865 data[24], data[25], data[26], data[27],
866 data[28], data[29], data[30], data[31]);
872 snc_nec16_dump_reg(iot, ioh)
874 bus_space_handle_t ioh;
879 printf("SONIC registers (word):");
880 for (n = 0; n < SNC_NREGS; n++) {
881 /* select required SONIC register */
882 bus_space_write_1(iot, ioh, SNEC_ADDR, n);
884 val = bus_space_read_2(iot, ioh, SNEC_CTRL);
886 printf("\n%04x ", val);
888 printf("%04x ", val);
892 printf("NEC/SONIC registers (byte):\n");
893 for (n = SNECR_MEMBS; n <= SNECR_IDENT; n += 2) {
894 /* select required SONIC register */
895 bus_space_write_1(iot, ioh, SNEC_ADDR, n);
897 val = (u_int16_t) bus_space_read_1(iot, ioh, SNEC_CTRLB);
898 printf("%04x ", val);
903 #endif /* SNCDEBUG */