2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $
33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.5 2003/08/27 09:38:32 rob Exp $
35 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/sockio.h>
42 #include <sys/malloc.h>
43 #include <sys/kernel.h>
44 #include <sys/socket.h>
47 #include <net/if_arp.h>
48 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51 #include <net/vlan/if_vlan_var.h>
55 #include <vm/vm.h> /* for vtophys */
56 #include <vm/pmap.h> /* for vtophys */
57 #include <machine/clock.h> /* for DELAY */
58 #include <machine/bus_memio.h>
59 #include <machine/bus_pio.h>
60 #include <machine/bus.h>
61 #include <machine/resource.h>
65 #include "../mii_layer/mii.h"
66 #include "../mii_layer/miivar.h"
68 #include <bus/pci/pcireg.h>
69 #include <bus/pci/pcivar.h>
71 /* "controller miibus0" required. See GENERIC if you get errors here. */
72 #include "miibus_if.h"
74 #define STE_USEIOSPACE
76 #include "if_stereg.h"
79 * Various supported device vendors/types and their names.
81 static struct ste_type ste_devs[] = {
82 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" },
83 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" },
87 static int ste_probe (device_t);
88 static int ste_attach (device_t);
89 static int ste_detach (device_t);
90 static void ste_init (void *);
91 static void ste_intr (void *);
92 static void ste_rxeof (struct ste_softc *);
93 static void ste_txeoc (struct ste_softc *);
94 static void ste_txeof (struct ste_softc *);
95 static void ste_stats_update (void *);
96 static void ste_stop (struct ste_softc *);
97 static void ste_reset (struct ste_softc *);
98 static int ste_ioctl (struct ifnet *, u_long, caddr_t);
99 static int ste_encap (struct ste_softc *, struct ste_chain *,
101 static void ste_start (struct ifnet *);
102 static void ste_watchdog (struct ifnet *);
103 static void ste_shutdown (device_t);
104 static int ste_newbuf (struct ste_softc *,
105 struct ste_chain_onefrag *,
107 static int ste_ifmedia_upd (struct ifnet *);
108 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *);
110 static void ste_mii_sync (struct ste_softc *);
111 static void ste_mii_send (struct ste_softc *, u_int32_t, int);
112 static int ste_mii_readreg (struct ste_softc *,
113 struct ste_mii_frame *);
114 static int ste_mii_writereg (struct ste_softc *,
115 struct ste_mii_frame *);
116 static int ste_miibus_readreg (device_t, int, int);
117 static int ste_miibus_writereg (device_t, int, int, int);
118 static void ste_miibus_statchg (device_t);
120 static int ste_eeprom_wait (struct ste_softc *);
121 static int ste_read_eeprom (struct ste_softc *, caddr_t, int,
123 static void ste_wait (struct ste_softc *);
124 static u_int8_t ste_calchash (caddr_t);
125 static void ste_setmulti (struct ste_softc *);
126 static int ste_init_rx_list (struct ste_softc *);
127 static void ste_init_tx_list (struct ste_softc *);
129 #ifdef STE_USEIOSPACE
130 #define STE_RES SYS_RES_IOPORT
131 #define STE_RID STE_PCI_LOIO
133 #define STE_RES SYS_RES_MEMORY
134 #define STE_RID STE_PCI_LOMEM
137 static device_method_t ste_methods[] = {
138 /* Device interface */
139 DEVMETHOD(device_probe, ste_probe),
140 DEVMETHOD(device_attach, ste_attach),
141 DEVMETHOD(device_detach, ste_detach),
142 DEVMETHOD(device_shutdown, ste_shutdown),
145 DEVMETHOD(bus_print_child, bus_generic_print_child),
146 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
149 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
150 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
151 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
156 static driver_t ste_driver = {
159 sizeof(struct ste_softc)
162 static devclass_t ste_devclass;
164 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0);
165 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
167 #define STE_SETBIT4(sc, reg, x) \
168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
170 #define STE_CLRBIT4(sc, reg, x) \
171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
173 #define STE_SETBIT2(sc, reg, x) \
174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
176 #define STE_CLRBIT2(sc, reg, x) \
177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
179 #define STE_SETBIT1(sc, reg, x) \
180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
182 #define STE_CLRBIT1(sc, reg, x) \
183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
186 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
187 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
190 * Sync the PHYs by setting data bit and strobing the clock 32 times.
192 static void ste_mii_sync(sc)
193 struct ste_softc *sc;
197 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
199 for (i = 0; i < 32; i++) {
200 MII_SET(STE_PHYCTL_MCLK);
202 MII_CLR(STE_PHYCTL_MCLK);
210 * Clock a series of bits through the MII.
212 static void ste_mii_send(sc, bits, cnt)
213 struct ste_softc *sc;
219 MII_CLR(STE_PHYCTL_MCLK);
221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
223 MII_SET(STE_PHYCTL_MDATA);
225 MII_CLR(STE_PHYCTL_MDATA);
228 MII_CLR(STE_PHYCTL_MCLK);
230 MII_SET(STE_PHYCTL_MCLK);
235 * Read an PHY register through the MII.
237 static int ste_mii_readreg(sc, frame)
238 struct ste_softc *sc;
239 struct ste_mii_frame *frame;
247 * Set up frame for RX.
249 frame->mii_stdelim = STE_MII_STARTDELIM;
250 frame->mii_opcode = STE_MII_READOP;
251 frame->mii_turnaround = 0;
254 CSR_WRITE_2(sc, STE_PHYCTL, 0);
258 MII_SET(STE_PHYCTL_MDIR);
263 * Send command/address info.
265 ste_mii_send(sc, frame->mii_stdelim, 2);
266 ste_mii_send(sc, frame->mii_opcode, 2);
267 ste_mii_send(sc, frame->mii_phyaddr, 5);
268 ste_mii_send(sc, frame->mii_regaddr, 5);
271 MII_CLR(STE_PHYCTL_MDIR);
274 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
276 MII_SET(STE_PHYCTL_MCLK);
280 MII_CLR(STE_PHYCTL_MCLK);
282 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
283 MII_SET(STE_PHYCTL_MCLK);
287 * Now try reading data bits. If the ack failed, we still
288 * need to clock through 16 cycles to keep the PHY(s) in sync.
291 for(i = 0; i < 16; i++) {
292 MII_CLR(STE_PHYCTL_MCLK);
294 MII_SET(STE_PHYCTL_MCLK);
300 for (i = 0x8000; i; i >>= 1) {
301 MII_CLR(STE_PHYCTL_MCLK);
304 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
305 frame->mii_data |= i;
308 MII_SET(STE_PHYCTL_MCLK);
314 MII_CLR(STE_PHYCTL_MCLK);
316 MII_SET(STE_PHYCTL_MCLK);
327 * Write to a PHY register through the MII.
329 static int ste_mii_writereg(sc, frame)
330 struct ste_softc *sc;
331 struct ste_mii_frame *frame;
338 * Set up frame for TX.
341 frame->mii_stdelim = STE_MII_STARTDELIM;
342 frame->mii_opcode = STE_MII_WRITEOP;
343 frame->mii_turnaround = STE_MII_TURNAROUND;
346 * Turn on data output.
348 MII_SET(STE_PHYCTL_MDIR);
352 ste_mii_send(sc, frame->mii_stdelim, 2);
353 ste_mii_send(sc, frame->mii_opcode, 2);
354 ste_mii_send(sc, frame->mii_phyaddr, 5);
355 ste_mii_send(sc, frame->mii_regaddr, 5);
356 ste_mii_send(sc, frame->mii_turnaround, 2);
357 ste_mii_send(sc, frame->mii_data, 16);
360 MII_SET(STE_PHYCTL_MCLK);
362 MII_CLR(STE_PHYCTL_MCLK);
368 MII_CLR(STE_PHYCTL_MDIR);
375 static int ste_miibus_readreg(dev, phy, reg)
379 struct ste_softc *sc;
380 struct ste_mii_frame frame;
382 sc = device_get_softc(dev);
384 if ( sc->ste_one_phy && phy != 0 )
387 bzero((char *)&frame, sizeof(frame));
389 frame.mii_phyaddr = phy;
390 frame.mii_regaddr = reg;
391 ste_mii_readreg(sc, &frame);
393 return(frame.mii_data);
396 static int ste_miibus_writereg(dev, phy, reg, data)
400 struct ste_softc *sc;
401 struct ste_mii_frame frame;
403 sc = device_get_softc(dev);
404 bzero((char *)&frame, sizeof(frame));
406 frame.mii_phyaddr = phy;
407 frame.mii_regaddr = reg;
408 frame.mii_data = data;
410 ste_mii_writereg(sc, &frame);
415 static void ste_miibus_statchg(dev)
418 struct ste_softc *sc;
419 struct mii_data *mii;
422 sc = device_get_softc(dev);
423 mii = device_get_softc(sc->ste_miibus);
425 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
426 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
428 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
431 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET |
432 STE_ASICCTL_TX_RESET);
433 for (i = 0; i < STE_TIMEOUT; i++) {
434 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
437 if (i == STE_TIMEOUT)
438 printf("ste%d: rx reset never completed\n", sc->ste_unit);
443 static int ste_ifmedia_upd(ifp)
446 struct ste_softc *sc;
447 struct mii_data *mii;
450 mii = device_get_softc(sc->ste_miibus);
452 if (mii->mii_instance) {
453 struct mii_softc *miisc;
454 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
455 miisc = LIST_NEXT(miisc, mii_list))
456 mii_phy_reset(miisc);
463 static void ste_ifmedia_sts(ifp, ifmr)
465 struct ifmediareq *ifmr;
467 struct ste_softc *sc;
468 struct mii_data *mii;
471 mii = device_get_softc(sc->ste_miibus);
474 ifmr->ifm_active = mii->mii_media_active;
475 ifmr->ifm_status = mii->mii_media_status;
480 static void ste_wait(sc)
481 struct ste_softc *sc;
485 for (i = 0; i < STE_TIMEOUT; i++) {
486 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
490 if (i == STE_TIMEOUT)
491 printf("ste%d: command never completed!\n", sc->ste_unit);
497 * The EEPROM is slow: give it time to come ready after issuing
500 static int ste_eeprom_wait(sc)
501 struct ste_softc *sc;
507 for (i = 0; i < 100; i++) {
508 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
515 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit);
523 * Read a sequence of words from the EEPROM. Note that ethernet address
524 * data is stored in the EEPROM in network byte order.
526 static int ste_read_eeprom(sc, dest, off, cnt, swap)
527 struct ste_softc *sc;
534 u_int16_t word = 0, *ptr;
536 if (ste_eeprom_wait(sc))
539 for (i = 0; i < cnt; i++) {
540 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
541 err = ste_eeprom_wait(sc);
544 word = CSR_READ_2(sc, STE_EEPROM_DATA);
545 ptr = (u_int16_t *)(dest + (i * 2));
555 static u_int8_t ste_calchash(addr)
559 u_int32_t crc, carry;
563 /* Compute CRC for the address value. */
564 crc = 0xFFFFFFFF; /* initial value */
566 for (i = 0; i < 6; i++) {
568 for (j = 0; j < 8; j++) {
569 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
573 crc = (crc ^ 0x04c11db6) | carry;
577 /* return the filter bit position */
578 return(crc & 0x0000003F);
581 static void ste_setmulti(sc)
582 struct ste_softc *sc;
586 u_int32_t hashes[2] = { 0, 0 };
587 struct ifmultiaddr *ifma;
589 ifp = &sc->arpcom.ac_if;
590 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
591 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
592 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
596 /* first, zot all the existing hash bits */
597 CSR_WRITE_2(sc, STE_MAR0, 0);
598 CSR_WRITE_2(sc, STE_MAR1, 0);
599 CSR_WRITE_2(sc, STE_MAR2, 0);
600 CSR_WRITE_2(sc, STE_MAR3, 0);
602 /* now program new ones */
603 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
604 ifma = ifma->ifma_link.le_next) {
605 if (ifma->ifma_addr->sa_family != AF_LINK)
607 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
609 hashes[0] |= (1 << h);
611 hashes[1] |= (1 << (h - 32));
614 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
615 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
616 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
617 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
618 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
619 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
624 static void ste_intr(xsc)
627 struct ste_softc *sc;
632 ifp = &sc->arpcom.ac_if;
634 /* See if this is really our interrupt. */
635 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH))
639 status = CSR_READ_2(sc, STE_ISR_ACK);
641 if (!(status & STE_INTRS))
644 if (status & STE_ISR_RX_DMADONE)
647 if (status & STE_ISR_TX_DMADONE)
650 if (status & STE_ISR_TX_DONE)
653 if (status & STE_ISR_STATS_OFLOW) {
654 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
655 ste_stats_update(sc);
658 if (status & STE_ISR_LINKEVENT)
659 mii_pollstat(device_get_softc(sc->ste_miibus));
661 if (status & STE_ISR_HOSTERR) {
667 /* Re-enable interrupts */
668 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
670 if (ifp->if_snd.ifq_head != NULL)
677 * A frame has been uploaded: pass the resulting mbuf chain up to
678 * the higher level protocols.
680 static void ste_rxeof(sc)
681 struct ste_softc *sc;
683 struct ether_header *eh;
686 struct ste_chain_onefrag *cur_rx;
687 int total_len = 0, count=0;
690 ifp = &sc->arpcom.ac_if;
692 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)
693 & STE_RXSTAT_DMADONE) {
694 if ((STE_RX_LIST_CNT - count) < 3) {
698 cur_rx = sc->ste_cdata.ste_rx_head;
699 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
702 * If an error occurs, update stats, clear the
703 * status word and leave the mbuf cluster in place:
704 * it should simply get re-used next time this descriptor
705 * comes up in the ring.
707 if (rxstat & STE_RXSTAT_FRAME_ERR) {
709 cur_rx->ste_ptr->ste_status = 0;
714 * If there error bit was not set, the upload complete
715 * bit should be set which means we have a valid packet.
716 * If not, something truly strange has happened.
718 if (!(rxstat & STE_RXSTAT_DMADONE)) {
719 printf("ste%d: bad receive status -- packet dropped",
722 cur_rx->ste_ptr->ste_status = 0;
726 /* No errors; receive the packet. */
727 m = cur_rx->ste_mbuf;
728 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
731 * Try to conjure up a new mbuf cluster. If that
732 * fails, it means we have an out of memory condition and
733 * should leave the buffer in place and continue. This will
734 * result in a lost packet, but there's little else we
735 * can do in this situation.
737 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
739 cur_rx->ste_ptr->ste_status = 0;
744 eh = mtod(m, struct ether_header *);
745 m->m_pkthdr.rcvif = ifp;
746 m->m_pkthdr.len = m->m_len = total_len;
748 /* Remove header from mbuf and pass it on. */
749 m_adj(m, sizeof(struct ether_header));
750 ether_input(ifp, eh, m);
752 cur_rx->ste_ptr->ste_status = 0;
759 static void ste_txeoc(sc)
760 struct ste_softc *sc;
765 ifp = &sc->arpcom.ac_if;
767 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
768 STE_TXSTATUS_TXDONE) {
769 if (txstat & STE_TXSTATUS_UNDERRUN ||
770 txstat & STE_TXSTATUS_EXCESSCOLLS ||
771 txstat & STE_TXSTATUS_RECLAIMERR) {
773 printf("ste%d: transmission error: %x\n",
774 sc->ste_unit, txstat);
779 if (txstat & STE_TXSTATUS_UNDERRUN &&
780 sc->ste_tx_thresh < STE_PACKET_SIZE) {
781 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
782 printf("ste%d: tx underrun, increasing tx"
783 " start threshold to %d bytes\n",
784 sc->ste_unit, sc->ste_tx_thresh);
786 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
787 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
788 (STE_PACKET_SIZE >> 4));
791 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
797 static void ste_txeof(sc)
798 struct ste_softc *sc;
800 struct ste_chain *cur_tx = NULL;
804 ifp = &sc->arpcom.ac_if;
806 idx = sc->ste_cdata.ste_tx_cons;
807 while(idx != sc->ste_cdata.ste_tx_prod) {
808 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
810 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
813 if (cur_tx->ste_mbuf != NULL) {
814 m_freem(cur_tx->ste_mbuf);
815 cur_tx->ste_mbuf = NULL;
820 sc->ste_cdata.ste_tx_cnt--;
821 STE_INC(idx, STE_TX_LIST_CNT);
825 sc->ste_cdata.ste_tx_cons = idx;
828 ifp->if_flags &= ~IFF_OACTIVE;
833 static void ste_stats_update(xsc)
836 struct ste_softc *sc;
838 struct mii_data *mii;
844 ifp = &sc->arpcom.ac_if;
845 mii = device_get_softc(sc->ste_miibus);
847 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
848 + CSR_READ_1(sc, STE_MULTI_COLLS)
849 + CSR_READ_1(sc, STE_SINGLE_COLLS);
853 if (mii->mii_media_status & IFM_ACTIVE &&
854 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
857 * we don't get a call-back on re-init so do it
858 * otherwise we get stuck in the wrong link state
860 ste_miibus_statchg(sc->ste_dev);
861 if (ifp->if_snd.ifq_head != NULL)
866 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
874 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
875 * IDs against our list and return a device name if we find a match.
877 static int ste_probe(dev)
884 while(t->ste_name != NULL) {
885 if ((pci_get_vendor(dev) == t->ste_vid) &&
886 (pci_get_device(dev) == t->ste_did)) {
887 device_set_desc(dev, t->ste_name);
897 * Attach the interface. Allocate softc structures, do ifmedia
898 * setup and ethernet/BPF attach.
900 static int ste_attach(dev)
905 struct ste_softc *sc;
907 int unit, error = 0, rid;
911 sc = device_get_softc(dev);
912 unit = device_get_unit(dev);
913 bzero(sc, sizeof(struct ste_softc));
917 * Only use one PHY since this chip reports multiple
918 * Note on the DFE-550 the PHY is at 1 on the DFE-580
919 * it is at 0 & 1. It is rev 0x12.
921 if (pci_get_vendor(dev) == DL_VENDORID &&
922 pci_get_device(dev) == DL_DEVICEID_550TX &&
923 pci_get_revid(dev) == 0x12 )
927 * Handle power management nonsense.
929 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF;
930 if (command == 0x01) {
932 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4);
933 if (command & STE_PSTATE_MASK) {
934 u_int32_t iobase, membase, irq;
936 /* Save important PCI config data. */
937 iobase = pci_read_config(dev, STE_PCI_LOIO, 4);
938 membase = pci_read_config(dev, STE_PCI_LOMEM, 4);
939 irq = pci_read_config(dev, STE_PCI_INTLINE, 4);
941 /* Reset the power state. */
942 printf("ste%d: chip is in D%d power mode "
943 "-- setting to D0\n", unit, command & STE_PSTATE_MASK);
944 command &= 0xFFFFFFFC;
945 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4);
947 /* Restore PCI config data. */
948 pci_write_config(dev, STE_PCI_LOIO, iobase, 4);
949 pci_write_config(dev, STE_PCI_LOMEM, membase, 4);
950 pci_write_config(dev, STE_PCI_INTLINE, irq, 4);
955 * Map control/status registers.
957 command = pci_read_config(dev, PCIR_COMMAND, 4);
958 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
959 pci_write_config(dev, PCIR_COMMAND, command, 4);
960 command = pci_read_config(dev, PCIR_COMMAND, 4);
962 #ifdef STE_USEIOSPACE
963 if (!(command & PCIM_CMD_PORTEN)) {
964 printf("ste%d: failed to enable I/O ports!\n", unit);
969 if (!(command & PCIM_CMD_MEMEN)) {
970 printf("ste%d: failed to enable memory mapping!\n", unit);
977 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid,
978 0, ~0, 1, RF_ACTIVE);
980 if (sc->ste_res == NULL) {
981 printf ("ste%d: couldn't map ports/memory\n", unit);
986 sc->ste_btag = rman_get_bustag(sc->ste_res);
987 sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
990 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
991 RF_SHAREABLE | RF_ACTIVE);
993 if (sc->ste_irq == NULL) {
994 printf("ste%d: couldn't map interrupt\n", unit);
995 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1000 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET,
1001 ste_intr, sc, &sc->ste_intrhand);
1004 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1005 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1006 printf("ste%d: couldn't set up irq\n", unit);
1010 callout_handle_init(&sc->ste_stat_ch);
1012 /* Reset the adapter. */
1016 * Get station address from the EEPROM.
1018 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1019 STE_EEADDR_NODE0, 3, 0)) {
1020 printf("ste%d: failed to read station address\n", unit);
1021 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1022 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1023 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1029 * A Sundance chip was detected. Inform the world.
1031 printf("ste%d: Ethernet address: %6D\n", unit,
1032 sc->arpcom.ac_enaddr, ":");
1034 sc->ste_unit = unit;
1036 /* Allocate the descriptor queues. */
1037 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
1038 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1040 if (sc->ste_ldata == NULL) {
1041 printf("ste%d: no memory for list buffers!\n", unit);
1042 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1043 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1044 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1049 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1052 if (mii_phy_probe(dev, &sc->ste_miibus,
1053 ste_ifmedia_upd, ste_ifmedia_sts)) {
1054 printf("ste%d: MII without any phy!\n", sc->ste_unit);
1055 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1056 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1057 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1058 contigfree(sc->ste_ldata,
1059 sizeof(struct ste_list_data), M_DEVBUF);
1064 ifp = &sc->arpcom.ac_if;
1066 ifp->if_unit = unit;
1067 ifp->if_name = "ste";
1068 ifp->if_mtu = ETHERMTU;
1069 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1070 ifp->if_ioctl = ste_ioctl;
1071 ifp->if_output = ether_output;
1072 ifp->if_start = ste_start;
1073 ifp->if_watchdog = ste_watchdog;
1074 ifp->if_init = ste_init;
1075 ifp->if_baudrate = 10000000;
1076 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1;
1078 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1081 * Call MI attach routine.
1083 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1086 * Tell the upper layer(s) we support long frames.
1088 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1095 static int ste_detach(dev)
1098 struct ste_softc *sc;
1104 sc = device_get_softc(dev);
1105 ifp = &sc->arpcom.ac_if;
1108 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1110 bus_generic_detach(dev);
1111 device_delete_child(dev, sc->ste_miibus);
1113 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1114 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1115 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1117 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF);
1124 static int ste_newbuf(sc, c, m)
1125 struct ste_softc *sc;
1126 struct ste_chain_onefrag *c;
1129 struct mbuf *m_new = NULL;
1132 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1135 MCLGET(m_new, M_DONTWAIT);
1136 if (!(m_new->m_flags & M_EXT)) {
1140 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1143 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1144 m_new->m_data = m_new->m_ext.ext_buf;
1147 m_adj(m_new, ETHER_ALIGN);
1149 c->ste_mbuf = m_new;
1150 c->ste_ptr->ste_status = 0;
1151 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
1152 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST;
1157 static int ste_init_rx_list(sc)
1158 struct ste_softc *sc;
1160 struct ste_chain_data *cd;
1161 struct ste_list_data *ld;
1164 cd = &sc->ste_cdata;
1167 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1168 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1169 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
1171 if (i == (STE_RX_LIST_CNT - 1)) {
1172 cd->ste_rx_chain[i].ste_next =
1173 &cd->ste_rx_chain[0];
1174 ld->ste_rx_list[i].ste_next =
1175 vtophys(&ld->ste_rx_list[0]);
1177 cd->ste_rx_chain[i].ste_next =
1178 &cd->ste_rx_chain[i + 1];
1179 ld->ste_rx_list[i].ste_next =
1180 vtophys(&ld->ste_rx_list[i + 1]);
1182 ld->ste_rx_list[i].ste_status = 0;
1185 cd->ste_rx_head = &cd->ste_rx_chain[0];
1190 static void ste_init_tx_list(sc)
1191 struct ste_softc *sc;
1193 struct ste_chain_data *cd;
1194 struct ste_list_data *ld;
1197 cd = &sc->ste_cdata;
1199 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1200 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1201 cd->ste_tx_chain[i].ste_ptr->ste_next = 0;
1202 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0;
1203 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
1204 if (i == (STE_TX_LIST_CNT - 1))
1205 cd->ste_tx_chain[i].ste_next =
1206 &cd->ste_tx_chain[0];
1208 cd->ste_tx_chain[i].ste_next =
1209 &cd->ste_tx_chain[i + 1];
1211 cd->ste_tx_chain[i].ste_prev =
1212 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1];
1214 cd->ste_tx_chain[i].ste_prev =
1215 &cd->ste_tx_chain[i - 1];
1218 cd->ste_tx_prod = 0;
1219 cd->ste_tx_cons = 0;
1225 static void ste_init(xsc)
1228 struct ste_softc *sc;
1231 struct mii_data *mii;
1236 ifp = &sc->arpcom.ac_if;
1237 mii = device_get_softc(sc->ste_miibus);
1241 /* Init our MAC address */
1242 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1243 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1247 if (ste_init_rx_list(sc) == ENOBUFS) {
1248 printf("ste%d: initialization failed: no "
1249 "memory for RX buffers\n", sc->ste_unit);
1255 /* Set RX polling interval */
1256 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1);
1258 /* Init TX descriptors */
1259 ste_init_tx_list(sc);
1261 /* Set the TX freethresh value */
1262 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1264 /* Set the TX start threshold for best performance. */
1265 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1267 /* Set the TX reclaim threshold. */
1268 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1270 /* Set up the RX filter. */
1271 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
1273 /* If we want promiscuous mode, set the allframes bit. */
1274 if (ifp->if_flags & IFF_PROMISC) {
1275 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1277 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1280 /* Set capture broadcast bit to accept broadcast frames. */
1281 if (ifp->if_flags & IFF_BROADCAST) {
1282 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1284 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1289 /* Load the address of the RX list. */
1290 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1292 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1293 vtophys(&sc->ste_ldata->ste_rx_list[0]));
1294 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1295 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1297 /* Set TX polling interval (defer until we TX first packet */
1298 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1300 /* Load address of the TX list */
1301 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1303 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1304 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1305 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1307 sc->ste_tx_prev_idx=-1;
1309 /* Enable receiver and transmitter */
1310 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1311 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1312 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1313 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1315 /* Enable stats counters. */
1316 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1318 /* Enable interrupts. */
1319 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1320 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1322 /* Accept VLAN length packets */
1323 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN);
1325 ste_ifmedia_upd(ifp);
1327 ifp->if_flags |= IFF_RUNNING;
1328 ifp->if_flags &= ~IFF_OACTIVE;
1332 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
1337 static void ste_stop(sc)
1338 struct ste_softc *sc;
1343 ifp = &sc->arpcom.ac_if;
1345 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
1347 CSR_WRITE_2(sc, STE_IMR, 0);
1348 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
1349 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
1350 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
1351 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1352 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1355 * Try really hard to stop the RX engine or under heavy RX
1356 * data chip will write into de-allocated memory.
1362 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1363 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
1364 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
1365 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
1369 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1370 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
1371 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
1372 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
1376 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1378 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1383 static void ste_reset(sc)
1384 struct ste_softc *sc;
1388 STE_SETBIT4(sc, STE_ASICCTL,
1389 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
1390 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
1391 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
1392 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
1393 STE_ASICCTL_EXTRESET_RESET);
1397 for (i = 0; i < STE_TIMEOUT; i++) {
1398 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1402 if (i == STE_TIMEOUT)
1403 printf("ste%d: global reset never completed\n", sc->ste_unit);
1408 static int ste_ioctl(ifp, command, data)
1413 struct ste_softc *sc;
1415 struct mii_data *mii;
1421 ifr = (struct ifreq *)data;
1427 error = ether_ioctl(ifp, command, data);
1430 if (ifp->if_flags & IFF_UP) {
1431 if (ifp->if_flags & IFF_RUNNING &&
1432 ifp->if_flags & IFF_PROMISC &&
1433 !(sc->ste_if_flags & IFF_PROMISC)) {
1434 STE_SETBIT1(sc, STE_RX_MODE,
1435 STE_RXMODE_PROMISC);
1436 } else if (ifp->if_flags & IFF_RUNNING &&
1437 !(ifp->if_flags & IFF_PROMISC) &&
1438 sc->ste_if_flags & IFF_PROMISC) {
1439 STE_CLRBIT1(sc, STE_RX_MODE,
1440 STE_RXMODE_PROMISC);
1442 if (!(ifp->if_flags & IFF_RUNNING)) {
1443 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1447 if (ifp->if_flags & IFF_RUNNING)
1450 sc->ste_if_flags = ifp->if_flags;
1460 mii = device_get_softc(sc->ste_miibus);
1461 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1473 static int ste_encap(sc, c, m_head)
1474 struct ste_softc *sc;
1475 struct ste_chain *c;
1476 struct mbuf *m_head;
1479 struct ste_frag *f = NULL;
1488 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1489 if (m->m_len != 0) {
1490 if (frag == STE_MAXFRAGS)
1492 total_len += m->m_len;
1493 f = &d->ste_frags[frag];
1494 f->ste_addr = vtophys(mtod(m, vm_offset_t));
1495 f->ste_len = m->m_len;
1504 * We ran out of segments. We have to recopy this
1505 * mbuf chain first. Bail out if we can't get the
1506 * new buffers. Code borrowed from if_fxp.c.
1508 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1513 if (m_head->m_pkthdr.len > MHLEN) {
1514 MCLGET(mn, M_DONTWAIT);
1515 if ((mn->m_flags & M_EXT) == 0) {
1521 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1523 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len;
1529 c->ste_mbuf = m_head;
1530 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
1536 static void ste_start(ifp)
1539 struct ste_softc *sc;
1540 struct mbuf *m_head = NULL;
1541 struct ste_chain *cur_tx = NULL;
1549 if (ifp->if_flags & IFF_OACTIVE)
1552 idx = sc->ste_cdata.ste_tx_prod;
1554 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
1556 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) {
1557 ifp->if_flags |= IFF_OACTIVE;
1561 IF_DEQUEUE(&ifp->if_snd, m_head);
1565 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
1567 if (ste_encap(sc, cur_tx, m_head) != 0)
1570 cur_tx->ste_ptr->ste_next = 0;
1572 if(sc->ste_tx_prev_idx < 0){
1573 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1574 /* Load address of the TX list */
1575 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1578 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1579 vtophys(&sc->ste_ldata->ste_tx_list[0]));
1581 /* Set TX polling interval to start TX engine */
1582 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1584 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1587 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1588 sc->ste_cdata.ste_tx_chain[
1589 sc->ste_tx_prev_idx].ste_ptr->ste_next
1593 sc->ste_tx_prev_idx=idx;
1596 * If there's a BPF listener, bounce a copy of this frame
1600 bpf_mtap(ifp, cur_tx->ste_mbuf);
1602 STE_INC(idx, STE_TX_LIST_CNT);
1603 sc->ste_cdata.ste_tx_cnt++;
1605 sc->ste_cdata.ste_tx_prod = idx;
1611 static void ste_watchdog(ifp)
1614 struct ste_softc *sc;
1619 printf("ste%d: watchdog timeout\n", sc->ste_unit);
1627 if (ifp->if_snd.ifq_head != NULL)
1633 static void ste_shutdown(dev)
1636 struct ste_softc *sc;
1638 sc = device_get_softc(dev);