1 ;; GCC machine description for i386 synchronization instructions.
2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_mode_iterator IMODE [QI HI SI (DI "TARGET_64BIT")])
22 (define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
23 (define_mode_attr modeconstraint [(QI "q") (HI "r") (SI "r") (DI "r")])
24 (define_mode_attr immconstraint [(QI "i") (HI "i") (SI "i") (DI "e")])
26 (define_mode_iterator CASMODE [QI HI SI (DI "TARGET_64BIT || TARGET_CMPXCHG8B")
27 (TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
28 (define_mode_iterator DCASMODE
29 [(DI "!TARGET_64BIT && TARGET_CMPXCHG8B && !flag_pic")
30 (TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
31 (define_mode_attr doublemodesuffix [(DI "8") (TI "16")])
32 (define_mode_attr DCASHMODE [(DI "SI") (TI "DI")])
34 (define_expand "memory_barrier"
36 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
39 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
40 MEM_VOLATILE_P (operands[0]) = 1;
42 if (!(TARGET_64BIT || TARGET_SSE2))
44 emit_insn (gen_memory_barrier_nosse (operands[0]));
49 (define_insn "memory_barrier_nosse"
50 [(set (match_operand:BLK 0 "" "")
51 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))
52 (clobber (reg:CC FLAGS_REG))]
53 "!(TARGET_64BIT || TARGET_SSE2)"
54 "lock{%;} or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}"
55 [(set_attr "memory" "unknown")])
57 ;; ??? It would be possible to use cmpxchg8b on pentium for DImode
58 ;; changes. It's complicated because the insn uses ecx:ebx as the
59 ;; new value; note that the registers are reversed from the order
60 ;; that they'd be in with (reg:DI 2 ecx). Similarly for TImode
61 ;; data in 64-bit mode.
63 (define_expand "sync_compare_and_swap<mode>"
65 [(set (match_operand:CASMODE 0 "register_operand" "")
66 (match_operand:CASMODE 1 "memory_operand" ""))
68 (unspec_volatile:CASMODE
70 (match_operand:CASMODE 2 "register_operand" "")
71 (match_operand:CASMODE 3 "register_operand" "")]
73 (clobber (reg:CC FLAGS_REG))])]
76 if ((<MODE>mode == DImode && !TARGET_64BIT) || <MODE>mode == TImode)
78 enum machine_mode hmode = <MODE>mode == DImode ? SImode : DImode;
79 rtx low = simplify_gen_subreg (hmode, operands[3], <MODE>mode, 0);
80 rtx high = simplify_gen_subreg (hmode, operands[3], <MODE>mode,
81 GET_MODE_SIZE (hmode));
82 low = force_reg (hmode, low);
83 high = force_reg (hmode, high);
84 if (<MODE>mode == DImode)
86 if (flag_pic && !cmpxchg8b_pic_memory_operand (operands[1], DImode))
87 operands[1] = replace_equiv_address (operands[1],
91 emit_insn (gen_sync_double_compare_and_swapdi
92 (operands[0], operands[1], operands[2], low, high));
94 else if (<MODE>mode == TImode)
95 emit_insn (gen_sync_double_compare_and_swapti
96 (operands[0], operands[1], operands[2], low, high));
103 (define_insn "*sync_compare_and_swap<mode>"
104 [(set (match_operand:IMODE 0 "register_operand" "=a")
105 (match_operand:IMODE 1 "memory_operand" "+m"))
107 (unspec_volatile:IMODE
109 (match_operand:IMODE 2 "register_operand" "a")
110 (match_operand:IMODE 3 "register_operand" "<modeconstraint>")]
112 (clobber (reg:CC FLAGS_REG))]
114 "lock{%;} cmpxchg{<modesuffix>}\t{%3, %1|%1, %3}")
116 (define_insn "sync_double_compare_and_swap<mode>"
117 [(set (match_operand:DCASMODE 0 "register_operand" "=A")
118 (match_operand:DCASMODE 1 "memory_operand" "+m"))
120 (unspec_volatile:DCASMODE
122 (match_operand:DCASMODE 2 "register_operand" "A")
123 (match_operand:<DCASHMODE> 3 "register_operand" "b")
124 (match_operand:<DCASHMODE> 4 "register_operand" "c")]
126 (clobber (reg:CC FLAGS_REG))]
128 "lock{%;} cmpxchg<doublemodesuffix>b\t%1")
130 ;; Theoretically we'd like to use constraint "r" (any reg) for operand
131 ;; 3, but that includes ecx. If operand 3 and 4 are the same (like when
132 ;; the input is -1LL) GCC might chose to allocate operand 3 to ecx, like
133 ;; operand 4. This breaks, as the xchg will move the PIC register contents
134 ;; to %ecx then --> boom. Operands 3 and 4 really need to be different
135 ;; registers, which in this case means operand 3 must not be ecx.
136 ;; Instead of playing tricks with fake early clobbers or the like we
137 ;; just enumerate all regs possible here, which (as this is !TARGET_64BIT)
138 ;; are just esi and edi.
139 (define_insn "*sync_double_compare_and_swapdi_pic"
140 [(set (match_operand:DI 0 "register_operand" "=A")
141 (match_operand:DI 1 "cmpxchg8b_pic_memory_operand" "+m"))
145 (match_operand:DI 2 "register_operand" "A")
146 (match_operand:SI 3 "register_operand" "SD")
147 (match_operand:SI 4 "register_operand" "c")]
149 (clobber (reg:CC FLAGS_REG))]
150 "!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
151 "xchg{l}\t%%ebx, %3\;lock{%;} cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
153 (define_expand "sync_compare_and_swap_cc<mode>"
155 [(set (match_operand:CASMODE 0 "register_operand" "")
156 (match_operand:CASMODE 1 "memory_operand" ""))
158 (unspec_volatile:CASMODE
160 (match_operand:CASMODE 2 "register_operand" "")
161 (match_operand:CASMODE 3 "register_operand" "")]
165 (unspec_volatile:CASMODE
166 [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG)
170 operands[4] = gen_rtx_REG (CCZmode, FLAGS_REG);
171 ix86_compare_op0 = operands[3];
172 ix86_compare_op1 = NULL;
173 ix86_compare_emitted = operands[4];
174 if ((<MODE>mode == DImode && !TARGET_64BIT) || <MODE>mode == TImode)
176 enum machine_mode hmode = <MODE>mode == DImode ? SImode : DImode;
177 rtx low = simplify_gen_subreg (hmode, operands[3], <MODE>mode, 0);
178 rtx high = simplify_gen_subreg (hmode, operands[3], <MODE>mode,
179 GET_MODE_SIZE (hmode));
180 low = force_reg (hmode, low);
181 high = force_reg (hmode, high);
182 if (<MODE>mode == DImode)
184 if (flag_pic && !cmpxchg8b_pic_memory_operand (operands[1], DImode))
185 operands[1] = replace_equiv_address (operands[1],
189 emit_insn (gen_sync_double_compare_and_swap_ccdi
190 (operands[0], operands[1], operands[2], low, high));
192 else if (<MODE>mode == TImode)
193 emit_insn (gen_sync_double_compare_and_swap_ccti
194 (operands[0], operands[1], operands[2], low, high));
201 (define_insn "*sync_compare_and_swap_cc<mode>"
202 [(set (match_operand:IMODE 0 "register_operand" "=a")
203 (match_operand:IMODE 1 "memory_operand" "+m"))
205 (unspec_volatile:IMODE
207 (match_operand:IMODE 2 "register_operand" "a")
208 (match_operand:IMODE 3 "register_operand" "<modeconstraint>")]
210 (set (reg:CCZ FLAGS_REG)
212 (unspec_volatile:IMODE
213 [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG)
216 "lock{%;} cmpxchg{<modesuffix>}\t{%3, %1|%1, %3}")
218 (define_insn "sync_double_compare_and_swap_cc<mode>"
219 [(set (match_operand:DCASMODE 0 "register_operand" "=A")
220 (match_operand:DCASMODE 1 "memory_operand" "+m"))
222 (unspec_volatile:DCASMODE
224 (match_operand:DCASMODE 2 "register_operand" "A")
225 (match_operand:<DCASHMODE> 3 "register_operand" "b")
226 (match_operand:<DCASHMODE> 4 "register_operand" "c")]
228 (set (reg:CCZ FLAGS_REG)
230 (unspec_volatile:DCASMODE
231 [(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
235 "lock{%;} cmpxchg<doublemodesuffix>b\t%1")
237 ;; See above for the explanation of using the constraint "SD" for
239 (define_insn "*sync_double_compare_and_swap_ccdi_pic"
240 [(set (match_operand:DI 0 "register_operand" "=A")
241 (match_operand:DI 1 "cmpxchg8b_pic_memory_operand" "+m"))
245 (match_operand:DI 2 "register_operand" "A")
246 (match_operand:SI 3 "register_operand" "SD")
247 (match_operand:SI 4 "register_operand" "c")]
249 (set (reg:CCZ FLAGS_REG)
252 [(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
255 "!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
256 "xchg{l}\t%%ebx, %3\;lock{%;} cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
258 (define_insn "sync_old_add<mode>"
259 [(set (match_operand:IMODE 0 "register_operand" "=<modeconstraint>")
260 (unspec_volatile:IMODE
261 [(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
263 (plus:IMODE (match_dup 1)
264 (match_operand:IMODE 2 "register_operand" "0")))
265 (clobber (reg:CC FLAGS_REG))]
267 "lock{%;} xadd{<modesuffix>}\t{%0, %1|%1, %0}")
269 ;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space.
270 (define_insn "sync_lock_test_and_set<mode>"
271 [(set (match_operand:IMODE 0 "register_operand" "=<modeconstraint>")
272 (unspec_volatile:IMODE
273 [(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
275 (match_operand:IMODE 2 "register_operand" "0"))]
277 "xchg{<modesuffix>}\t{%1, %0|%0, %1}")
279 (define_insn "sync_add<mode>"
280 [(set (match_operand:IMODE 0 "memory_operand" "+m")
281 (unspec_volatile:IMODE
282 [(plus:IMODE (match_dup 0)
283 (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
285 (clobber (reg:CC FLAGS_REG))]
288 if (TARGET_USE_INCDEC)
290 if (operands[1] == const1_rtx)
291 return "lock{%;} inc{<modesuffix>}\t%0";
292 if (operands[1] == constm1_rtx)
293 return "lock{%;} dec{<modesuffix>}\t%0";
296 return "lock{%;} add{<modesuffix>}\t{%1, %0|%0, %1}";
299 (define_insn "sync_sub<mode>"
300 [(set (match_operand:IMODE 0 "memory_operand" "+m")
301 (unspec_volatile:IMODE
302 [(minus:IMODE (match_dup 0)
303 (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
305 (clobber (reg:CC FLAGS_REG))]
308 if (TARGET_USE_INCDEC)
310 if (operands[1] == const1_rtx)
311 return "lock{%;} dec{<modesuffix>}\t%0";
312 if (operands[1] == constm1_rtx)
313 return "lock{%;} inc{<modesuffix>}\t%0";
316 return "lock{%;} sub{<modesuffix>}\t{%1, %0|%0, %1}";
319 (define_insn "sync_ior<mode>"
320 [(set (match_operand:IMODE 0 "memory_operand" "+m")
321 (unspec_volatile:IMODE
322 [(ior:IMODE (match_dup 0)
323 (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
325 (clobber (reg:CC FLAGS_REG))]
327 "lock{%;} or{<modesuffix>}\t{%1, %0|%0, %1}")
329 (define_insn "sync_and<mode>"
330 [(set (match_operand:IMODE 0 "memory_operand" "+m")
331 (unspec_volatile:IMODE
332 [(and:IMODE (match_dup 0)
333 (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
335 (clobber (reg:CC FLAGS_REG))]
337 "lock{%;} and{<modesuffix>}\t{%1, %0|%0, %1}")
339 (define_insn "sync_xor<mode>"
340 [(set (match_operand:IMODE 0 "memory_operand" "+m")
341 (unspec_volatile:IMODE
342 [(xor:IMODE (match_dup 0)
343 (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
345 (clobber (reg:CC FLAGS_REG))]
347 "lock{%;} xor{<modesuffix>}\t{%1, %0|%0, %1}")