2 * Copyright (c) 2004, 2005 David Young. All rights reserved.
4 * Programmed for NetBSD by David Young.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of David Young may not be used to endorse or promote
15 * products derived from this software without specific prior
18 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
20 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
21 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
22 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
23 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
24 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
31 * $NetBSD: rtwphy.c,v 1.9 2006/03/08 00:24:06 dyoung Exp $
32 * $DragonFly: src/sys/dev/netif/rtw/rtwphy.c,v 1.4 2007/10/14 04:15:17 sephe Exp $
36 * Control the Philips SA2400 RF front-end and the baseband processor
37 * built into the Realtek RTL8180.
40 #include <sys/param.h>
41 #include <sys/bitops.h>
43 #include <sys/socket.h>
46 #include <net/if_arp.h>
47 #include <net/if_media.h>
49 #include <netproto/802_11/ieee80211_var.h>
50 #include <netproto/802_11/ieee80211_radiotap.h>
52 #include <dev/netif/rtw/rtwreg.h>
53 #include <dev/netif/rtw/max2820reg.h>
54 #include <dev/netif/rtw/sa2400reg.h>
55 #include <dev/netif/rtw/rtwvar.h>
56 #include <dev/netif/rtw/rtwphyio.h>
57 #include <dev/netif/rtw/rtwphy.h>
59 static int rtw_max2820_pwrstate(struct rtw_rf *, enum rtw_pwrstate);
60 static int rtw_sa2400_pwrstate(struct rtw_rf *, enum rtw_pwrstate);
62 #define GCT_WRITE(__gr, __addr, __val, __label) \
64 if (rtw_rfbus_write(&(__gr)->gr_bus, RTW_RFCHIPID_GCT, \
65 (__addr), (__val)) == -1) \
70 rtw_bbp_preinit(struct rtw_regs *regs, u_int antatten0, int dflantb, u_int freq)
72 u_int antatten = antatten0;
75 antatten |= RTW_BBP_ANTATTEN_DFLANTB;
76 if (freq == 2484) /* channel 14 */
77 antatten |= RTW_BBP_ANTATTEN_CHAN14;
78 return rtw_bbp_write(regs, RTW_BBP_ANTATTEN, antatten);
82 rtw_bbp_init(struct rtw_regs *regs, struct rtw_bbpset *bb, int antdiv,
83 int dflantb, uint8_t cs_threshold, u_int freq)
90 sys2 |= RTW_BBP_SYS2_ANTDIV;
92 __SHIFTIN(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK);
94 #define RTW_BBP_WRITE_OR_RETURN(reg, val) \
95 if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \
98 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS1, bb->bb_sys1);
99 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TXAGC, bb->bb_txagc);
100 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_LNADET, bb->bb_lnadet);
101 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCINI, bb->bb_ifagcini);
102 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCLIMIT, bb->bb_ifagclimit);
103 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCDET, bb->bb_ifagcdet);
105 if ((rc = rtw_bbp_preinit(regs, bb->bb_antatten, dflantb, freq)) != 0)
108 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TRL, bb->bb_trl);
109 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS2, sys2);
110 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS3, sys3);
111 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHESTLIM, bb->bb_chestlim);
112 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHSQLIM, bb->bb_chsqlim);
117 rtw_sa2400_txpower(struct rtw_rf *rf, uint8_t opaque_txpower)
119 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
120 struct rtw_rfbus *bus = &sa->sa_bus;
122 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_TX,
126 /* make sure we're using the same settings as the reference driver */
128 verify_syna(u_int freq, uint32_t val)
130 uint32_t expected_val = ~val;
134 expected_val = 0x0000096c; /* ch 1 */
137 expected_val = 0x00080970; /* ch 2 */
140 expected_val = 0x00100974; /* ch 3 */
143 expected_val = 0x00180978; /* ch 4 */
146 expected_val = 0x00000980; /* ch 5 */
149 expected_val = 0x00080984; /* ch 6 */
152 expected_val = 0x00100988; /* ch 7 */
155 expected_val = 0x0018098c; /* ch 8 */
158 expected_val = 0x00000994; /* ch 9 */
161 expected_val = 0x00080998; /* ch 10 */
164 expected_val = 0x0010099c; /* ch 11 */
167 expected_val = 0x001809a0; /* ch 12 */
170 expected_val = 0x000009a8; /* ch 13 */
173 expected_val = 0x000009b4; /* ch 14 */
176 KKASSERT(val == expected_val);
181 rtw_sa2400_tune(struct rtw_rf *rf, u_int freq)
183 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
184 struct rtw_rfbus *bus = &sa->sa_bus;
186 uint32_t syna, synb, sync;
190 * XO = 44MHz, R = 11, hence N is in units of XO / R = 4MHz.
192 * The channel spacing (5MHz) is not divisible by 4MHz, so
193 * we set the fractional part of N to compensate.
198 syna = __SHIFTIN(nf, SA2400_SYNA_NF_MASK) |
199 __SHIFTIN(n, SA2400_SYNA_N_MASK);
200 verify_syna(freq, syna);
203 * Divide the 44MHz crystal down to 4MHz. Set the fractional
204 * compensation charge pump value to agree with the fractional
207 synb = __SHIFTIN(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL |
208 SA2400_SYNB_ON | SA2400_SYNB_ONE |
209 __SHIFTIN(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */
211 sync = SA2400_SYNC_CP_NORMAL;
213 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNA, syna);
217 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNB, synb);
221 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNC, sync);
225 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYND, 0x0);
229 rtw_sa2400_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power)
231 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
232 struct rtw_rfbus *bus = &sa->sa_bus;
235 opmode = SA2400_OPMODE_DEFAULTS;
238 opmode |= SA2400_OPMODE_MODE_TXRX;
241 opmode |= SA2400_OPMODE_MODE_WAIT;
244 opmode |= SA2400_OPMODE_MODE_SLEEP;
249 opmode |= SA2400_OPMODE_DIGIN;
251 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
256 rtw_sa2400_manrx_init(struct rtw_sa2400 *sa)
261 * XXX we are not supposed to be in RXMGC mode when we do this?
263 manrx = SA2400_MANRX_AHSN;
264 manrx |= SA2400_MANRX_TEN;
265 manrx |= __SHIFTIN(1023, SA2400_MANRX_RXGAIN_MASK);
267 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_MANRX,
272 rtw_sa2400_vcocal_start(struct rtw_sa2400 *sa, int start)
276 opmode = SA2400_OPMODE_DEFAULTS;
278 opmode |= SA2400_OPMODE_MODE_VCOCALIB;
280 opmode |= SA2400_OPMODE_MODE_SLEEP;
283 opmode |= SA2400_OPMODE_DIGIN;
285 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
290 rtw_sa2400_vco_calibration(struct rtw_sa2400 *sa)
295 if ((rc = rtw_sa2400_vcocal_start(sa, 1)) != 0)
297 DELAY(2200); /* 2.2 milliseconds */
298 /* XXX superfluous: SA2400 automatically entered SLEEP mode. */
299 return rtw_sa2400_vcocal_start(sa, 0);
303 rtw_sa2400_filter_calibration(struct rtw_sa2400 *sa)
307 opmode = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_FCALIB;
309 opmode |= SA2400_OPMODE_DIGIN;
311 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
316 rtw_sa2400_dc_calibration(struct rtw_sa2400 *sa)
318 struct rtw_rf *rf = &sa->sa_rf;
322 rf->rf_continuous_tx_cb(rf->rf_continuous_tx_arg, 1);
324 dccal = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_TXRX;
326 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
332 * DCALIB after being in Tx mode for 5 microseconds
336 dccal &= ~SA2400_OPMODE_MODE_MASK;
337 dccal |= SA2400_OPMODE_MODE_DCALIB;
339 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
344 DELAY(20); /* calibration takes at most 20 microseconds */
346 rf->rf_continuous_tx_cb(rf->rf_continuous_tx_arg, 0);
351 rtw_sa2400_agc_init(struct rtw_sa2400 *sa)
355 agc = __SHIFTIN(25, SA2400_AGC_MAXGAIN_MASK);
356 agc |= __SHIFTIN(7, SA2400_AGC_BBPDELAY_MASK);
357 agc |= __SHIFTIN(15, SA2400_AGC_LNADELAY_MASK);
358 agc |= __SHIFTIN(27, SA2400_AGC_RXONDELAY_MASK);
360 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_AGC,
365 rtw_sa2400_destroy(struct rtw_rf *rf)
367 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
369 memset(sa, 0, sizeof(*sa));
374 rtw_sa2400_calibrate(struct rtw_rf *rf, u_int freq)
376 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
379 /* XXX reference driver calibrates VCO twice. Is it a bug? */
380 for (i = 0; i < 2; i++) {
381 if ((rc = rtw_sa2400_vco_calibration(sa)) != 0)
384 /* VCO calibration erases synthesizer registers, so re-tune */
385 if ((rc = rtw_sa2400_tune(rf, freq)) != 0)
387 if ((rc = rtw_sa2400_filter_calibration(sa)) != 0)
389 /* analog PHY needs DC calibration */
391 return rtw_sa2400_dc_calibration(sa);
396 rtw_sa2400_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower,
397 enum rtw_pwrstate power)
399 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
402 if ((rc = rtw_sa2400_txpower(rf, opaque_txpower)) != 0)
405 /* skip configuration if it's time to sleep or to power-down. */
406 if (power == RTW_SLEEP || power == RTW_OFF)
407 return rtw_sa2400_pwrstate(rf, power);
409 /* go to sleep for configuration */
410 if ((rc = rtw_sa2400_pwrstate(rf, RTW_SLEEP)) != 0)
413 if ((rc = rtw_sa2400_tune(rf, freq)) != 0)
415 if ((rc = rtw_sa2400_agc_init(sa)) != 0)
417 if ((rc = rtw_sa2400_manrx_init(sa)) != 0)
419 if ((rc = rtw_sa2400_calibrate(rf, freq)) != 0)
422 /* enter Tx/Rx mode */
423 return rtw_sa2400_pwrstate(rf, power);
427 rtw_sa2400_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int digphy)
429 struct rtw_sa2400 *sa;
430 struct rtw_rfbus *bus;
432 struct rtw_bbpset *bb;
434 sa = kmalloc(sizeof(*sa), M_DEVBUF, M_WAITOK | M_ZERO);
436 sa->sa_digphy = digphy;
441 rf->rf_init = rtw_sa2400_init;
442 rf->rf_destroy = rtw_sa2400_destroy;
443 rf->rf_txpower = rtw_sa2400_txpower;
444 rf->rf_tune = rtw_sa2400_tune;
445 rf->rf_pwrstate = rtw_sa2400_pwrstate;
449 bb->bb_antatten = RTW_BBP_ANTATTEN_PHILIPS_MAGIC;
450 bb->bb_chestlim = 0x00;
451 bb->bb_chsqlim = 0xa0;
452 bb->bb_ifagcdet = 0x64;
453 bb->bb_ifagcini = 0x90;
454 bb->bb_ifagclimit = 0x1a;
455 bb->bb_lnadet = 0xe0;
463 bus->b_write = rf_write;
469 rtw_grf5101_txpower(struct rtw_rf *rf, uint8_t opaque_txpower)
471 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
473 GCT_WRITE(gr, 0x15, 0, err);
474 GCT_WRITE(gr, 0x06, opaque_txpower, err);
475 GCT_WRITE(gr, 0x15, 0x10, err);
476 GCT_WRITE(gr, 0x15, 0x00, err);
483 rtw_grf5101_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power)
485 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
490 GCT_WRITE(gr, 0x07, 0x0000, err);
491 GCT_WRITE(gr, 0x1f, 0x0045, err);
492 GCT_WRITE(gr, 0x1f, 0x0005, err);
493 GCT_WRITE(gr, 0x00, 0x08e4, err);
497 GCT_WRITE(gr, 0x1f, 0x0001, err);
499 GCT_WRITE(gr, 0x1f, 0x0001, err);
501 GCT_WRITE(gr, 0x1f, 0x0041, err);
503 GCT_WRITE(gr, 0x1f, 0x0061, err);
505 GCT_WRITE(gr, 0x00, 0x0ae4, err);
507 GCT_WRITE(gr, 0x07, 0x1000, err);
518 rtw_grf5101_tune(struct rtw_rf *rf, u_int freq)
521 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
525 } else if ((channel = (freq - 2412) / 5 + 1) < 1 || channel > 13) {
526 RTW_DPRINTF(RTW_DEBUG_PHY,
527 ("%s: invalid channel %d (freq %d)\n", __func__, channel,
532 GCT_WRITE(gr, 0x07, 0, err);
533 GCT_WRITE(gr, 0x0b, channel - 1, err);
534 GCT_WRITE(gr, 0x07, 0x1000, err);
541 rtw_grf5101_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower,
542 enum rtw_pwrstate power)
545 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
548 * These values have been derived from the rtl8180-sa2400
549 * Linux driver. It is unknown what they all do, GCT refuse
550 * to release any documentation so these are more than
551 * likely sub optimal settings
554 GCT_WRITE(gr, 0x01, 0x1a23, err);
555 GCT_WRITE(gr, 0x02, 0x4971, err);
556 GCT_WRITE(gr, 0x03, 0x41de, err);
557 GCT_WRITE(gr, 0x04, 0x2d80, err);
559 GCT_WRITE(gr, 0x05, 0x61ff, err);
561 GCT_WRITE(gr, 0x06, 0x0, err);
563 GCT_WRITE(gr, 0x08, 0x7533, err);
564 GCT_WRITE(gr, 0x09, 0xc401, err);
565 GCT_WRITE(gr, 0x0a, 0x0, err);
566 GCT_WRITE(gr, 0x0c, 0x1c7, err);
567 GCT_WRITE(gr, 0x0d, 0x29d3, err);
568 GCT_WRITE(gr, 0x0e, 0x2e8, err);
569 GCT_WRITE(gr, 0x10, 0x192, err);
570 GCT_WRITE(gr, 0x11, 0x248, err);
571 GCT_WRITE(gr, 0x12, 0x0, err);
572 GCT_WRITE(gr, 0x13, 0x20c4, err);
573 GCT_WRITE(gr, 0x14, 0xf4fc, err);
574 GCT_WRITE(gr, 0x15, 0x0, err);
575 GCT_WRITE(gr, 0x16, 0x1500, err);
577 if ((rc = rtw_grf5101_txpower(rf, opaque_txpower)) != 0)
580 if ((rc = rtw_grf5101_tune(rf, freq)) != 0)
589 rtw_grf5101_destroy(struct rtw_rf *rf)
591 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
593 memset(gr, 0, sizeof(*gr));
598 rtw_grf5101_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int digphy)
600 struct rtw_grf5101 *gr;
601 struct rtw_rfbus *bus;
603 struct rtw_bbpset *bb;
605 gr = kmalloc(sizeof(*gr), M_DEVBUF, M_WAITOK | M_ZERO);
610 rf->rf_init = rtw_grf5101_init;
611 rf->rf_destroy = rtw_grf5101_destroy;
612 rf->rf_txpower = rtw_grf5101_txpower;
613 rf->rf_tune = rtw_grf5101_tune;
614 rf->rf_pwrstate = rtw_grf5101_pwrstate;
618 bb->bb_antatten = RTW_BBP_ANTATTEN_GCT_MAGIC;
619 bb->bb_chestlim = 0x00;
620 bb->bb_chsqlim = 0xa0;
621 bb->bb_ifagcdet = 0x64;
622 bb->bb_ifagcini = 0x90;
623 bb->bb_ifagclimit = 0x1e;
624 bb->bb_lnadet = 0xc0;
632 bus->b_write = rf_write;
639 rtw_max2820_tune(struct rtw_rf *rf, u_int freq)
641 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf;
642 struct rtw_rfbus *bus = &mx->mx_bus;
644 if (freq < 2400 || freq > 2499)
647 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_CHANNEL,
648 __SHIFTIN(freq - 2400, MAX2820_CHANNEL_CF_MASK));
652 rtw_max2820_destroy(struct rtw_rf *rf)
654 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf;
656 memset(mx, 0, sizeof(*mx));
661 rtw_max2820_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower,
662 enum rtw_pwrstate power)
664 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf;
665 struct rtw_rfbus *bus = &mx->mx_bus;
668 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TEST,
669 MAX2820_TEST_DEFAULT);
673 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE,
674 MAX2820_ENABLE_DEFAULT);
678 /* skip configuration if it's time to sleep or to power-down. */
679 if ((rc = rtw_max2820_pwrstate(rf, power)) != 0)
681 else if (power == RTW_OFF || power == RTW_SLEEP)
684 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_SYNTH,
685 MAX2820_SYNTH_R_44MHZ);
689 if ((rc = rtw_max2820_tune(rf, freq)) != 0)
693 * XXX The MAX2820 datasheet indicates that 1C and 2C should not
694 * be changed from 7, however, the reference driver sets them
695 * to 4 and 1, respectively.
697 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_RECEIVE,
698 MAX2820_RECEIVE_DL_DEFAULT |
699 __SHIFTIN(4, MAX2820A_RECEIVE_1C_MASK) |
700 __SHIFTIN(1, MAX2820A_RECEIVE_2C_MASK));
704 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TRANSMIT,
705 MAX2820_TRANSMIT_PA_DEFAULT);
709 rtw_max2820_txpower(struct rtw_rf *rf, uint8_t opaque_txpower)
716 rtw_max2820_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power)
719 struct rtw_max2820 *mx;
720 struct rtw_rfbus *bus;
722 mx = (struct rtw_max2820 *)rf;
732 enable = MAX2820_ENABLE_DEFAULT;
735 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, enable);
739 rtw_max2820_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int is_a)
741 struct rtw_max2820 *mx;
742 struct rtw_rfbus *bus;
744 struct rtw_bbpset *bb;
746 mx = kmalloc(sizeof(*mx), M_DEVBUF, M_WAITOK | M_ZERO);
753 rf->rf_init = rtw_max2820_init;
754 rf->rf_destroy = rtw_max2820_destroy;
755 rf->rf_txpower = rtw_max2820_txpower;
756 rf->rf_tune = rtw_max2820_tune;
757 rf->rf_pwrstate = rtw_max2820_pwrstate;
761 bb->bb_antatten = RTW_BBP_ANTATTEN_MAXIM_MAGIC;
763 bb->bb_chsqlim = 159;
764 bb->bb_ifagcdet = 100;
765 bb->bb_ifagcini = 144;
766 bb->bb_ifagclimit = 26;
775 bus->b_write = rf_write;
782 rtw_phy_init(struct rtw_regs *regs, struct rtw_rf *rf, uint8_t opaque_txpower,
783 uint8_t cs_threshold, u_int freq, int antdiv, int dflantb,
784 enum rtw_pwrstate power)
787 RTW_DPRINTF(RTW_DEBUG_PHY,
788 ("%s: txpower %u csthresh %u freq %u antdiv %u dflantb %u "
789 "pwrstate %s\n", __func__, opaque_txpower, cs_threshold, freq,
790 antdiv, dflantb, rtw_pwrstate_string(power)));
792 /* XXX is this really necessary? */
793 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0)
796 rc = rtw_bbp_preinit(regs, rf->rf_bbpset.bb_antatten, dflantb, freq);
800 if ((rc = rtw_rf_tune(rf, freq)) != 0)
804 if ((rc = rtw_rf_init(rf, freq, opaque_txpower, power)) != 0)
806 #if 0 /* what is this redundant tx power setting here for? */
807 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0)
810 return rtw_bbp_init(regs, &rf->rf_bbpset, antdiv, dflantb, cs_threshold, freq);