2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.30 2006/10/25 20:55:56 dillon Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
45 #include <sys/thread2.h>
48 #include <net/ifq_var.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
56 #include <net/if_types.h>
57 #include <net/vlan/if_vlan_var.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/in.h>
61 #include <netinet/ip.h>
63 #include <bus/pci/pcireg.h>
64 #include <bus/pci/pcivar.h>
65 #include <bus/pci/pcidevs.h>
67 #include <dev/netif/mii_layer/mii.h>
68 #include <dev/netif/mii_layer/miivar.h>
70 #include "if_bfereg.h"
72 MODULE_DEPEND(bfe, pci, 1, 1, 1);
73 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
75 /* "controller miibus0" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
80 static struct bfe_type bfe_devs[] = {
81 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
82 "Broadcom BCM4401 Fast Ethernet" },
83 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0,
84 "Broadcom BCM4401-B0 Fast Ethernet" },
88 static int bfe_probe(device_t);
89 static int bfe_attach(device_t);
90 static int bfe_detach(device_t);
91 static void bfe_intr(void *);
92 static void bfe_start(struct ifnet *);
93 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
94 static void bfe_init(void *);
95 static void bfe_stop(struct bfe_softc *);
96 static void bfe_watchdog(struct ifnet *);
97 static void bfe_shutdown(device_t);
98 static void bfe_tick(void *);
99 static void bfe_txeof(struct bfe_softc *);
100 static void bfe_rxeof(struct bfe_softc *);
101 static void bfe_set_rx_mode(struct bfe_softc *);
102 static int bfe_list_rx_init(struct bfe_softc *);
103 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*);
104 static void bfe_rx_ring_free(struct bfe_softc *);
106 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
107 static int bfe_ifmedia_upd(struct ifnet *);
108 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
109 static int bfe_miibus_readreg(device_t, int, int);
110 static int bfe_miibus_writereg(device_t, int, int, int);
111 static void bfe_miibus_statchg(device_t);
112 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
114 static void bfe_get_config(struct bfe_softc *sc);
115 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
116 static void bfe_stats_update(struct bfe_softc *);
117 static void bfe_clear_stats (struct bfe_softc *);
118 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
119 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
120 static int bfe_resetphy(struct bfe_softc *);
121 static int bfe_setupphy(struct bfe_softc *);
122 static void bfe_chip_reset(struct bfe_softc *);
123 static void bfe_chip_halt(struct bfe_softc *);
124 static void bfe_core_reset(struct bfe_softc *);
125 static void bfe_core_disable(struct bfe_softc *);
126 static int bfe_dma_alloc(device_t);
127 static void bfe_dma_free(struct bfe_softc *);
128 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int);
129 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
130 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
132 static device_method_t bfe_methods[] = {
133 /* Device interface */
134 DEVMETHOD(device_probe, bfe_probe),
135 DEVMETHOD(device_attach, bfe_attach),
136 DEVMETHOD(device_detach, bfe_detach),
137 DEVMETHOD(device_shutdown, bfe_shutdown),
140 DEVMETHOD(bus_print_child, bus_generic_print_child),
141 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
146 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
151 static driver_t bfe_driver = {
154 sizeof(struct bfe_softc)
157 static devclass_t bfe_devclass;
159 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
160 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
163 * Probe for a Broadcom 4401 chip.
166 bfe_probe(device_t dev)
169 uint16_t vendor, product;
171 vendor = pci_get_vendor(dev);
172 product = pci_get_device(dev);
174 for (t = bfe_devs; t->bfe_name != NULL; t++) {
175 if (vendor == t->bfe_vid && product == t->bfe_did) {
176 device_set_desc(dev, t->bfe_name);
185 bfe_dma_alloc(device_t dev)
187 struct bfe_softc *sc;
188 int error, i, tx_pos, rx_pos;
190 sc = device_get_softc(dev);
193 error = bus_dma_tag_create(NULL, /* parent */
194 PAGE_SIZE, 0, /* alignment, boundary */
195 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
196 BUS_SPACE_MAXADDR, /* highaddr */
197 NULL, NULL, /* filter, filterarg */
198 MAXBSIZE, /* maxsize */
199 BUS_SPACE_UNRESTRICTED, /* num of segments */
200 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
201 BUS_DMA_ALLOCNOW, /* flags */
202 &sc->bfe_parent_tag);
205 device_printf(dev, "could not allocate parent dma tag\n");
209 /* tag for TX ring */
210 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE,
211 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
212 NULL, NULL, BFE_TX_LIST_SIZE, 1,
213 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag);
216 device_printf(dev, "could not allocate dma tag for TX list\n");
220 /* tag for RX ring */
221 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE,
222 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
223 NULL, NULL, BFE_RX_LIST_SIZE, 1,
224 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag);
227 device_printf(dev, "could not allocate dma tag for RX list\n");
232 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
233 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
234 1, BUS_SPACE_MAXSIZE_32BIT, 0,
238 device_printf(dev, "could not allocate dma tag for mbufs\n");
244 /* pre allocate dmamaps for RX list */
245 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
246 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map);
249 device_printf(dev, "cannot create DMA map for RX\n");
253 rx_pos = BFE_RX_LIST_CNT;
255 /* pre allocate dmamaps for TX list */
256 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
257 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map);
260 device_printf(dev, "cannot create DMA map for TX\n");
265 /* Alloc dma for rx ring */
266 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
267 BUS_DMA_WAITOK, &sc->bfe_rx_map);
270 device_printf(dev, "cannot allocate DMA mem for RX\n");
274 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
275 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
276 sc->bfe_rx_list, sizeof(struct bfe_desc),
277 bfe_dma_map, &sc->bfe_rx_dma, 0);
280 device_printf(dev, "cannot load DMA map for RX\n");
284 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
286 /* Alloc dma for tx ring */
287 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
288 BUS_DMA_WAITOK, &sc->bfe_tx_map);
290 device_printf(dev, "cannot allocate DMA mem for TX\n");
294 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
295 sc->bfe_tx_list, sizeof(struct bfe_desc),
296 bfe_dma_map, &sc->bfe_tx_dma, 0);
298 device_printf(dev, "cannot load DMA map for TX\n");
302 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
303 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
308 for (i = 0; i < rx_pos; ++i)
309 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_rx_ring[i].bfe_map);
310 for (i = 0; i < tx_pos; ++i)
311 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map);
313 bus_dma_tag_destroy(sc->bfe_tag);
319 bfe_attach(device_t dev)
322 struct bfe_softc *sc;
325 sc = device_get_softc(dev);
328 callout_init(&sc->bfe_stat_timer);
331 * Handle power management nonsense.
333 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
334 uint32_t membase, irq;
336 /* Save important PCI config data. */
337 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
338 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
340 /* Reset the power state. */
341 device_printf(dev, "chip is in D%d power mode"
342 " -- setting to D0\n", pci_get_powerstate(dev));
344 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
346 /* Restore PCI config data. */
347 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
348 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
352 * Map control/status registers.
354 pci_enable_busmaster(dev);
357 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
359 if (sc->bfe_res == NULL) {
360 device_printf(dev, "couldn't map memory\n");
364 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
365 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
367 /* Allocate interrupt */
370 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
371 RF_SHAREABLE | RF_ACTIVE);
372 if (sc->bfe_irq == NULL) {
373 device_printf(dev, "couldn't map interrupt\n");
378 error = bfe_dma_alloc(dev);
380 device_printf(dev, "failed to allocate DMA resources\n");
384 /* Set up ifnet structure */
385 ifp = &sc->arpcom.ac_if;
387 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
388 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
389 ifp->if_ioctl = bfe_ioctl;
390 ifp->if_start = bfe_start;
391 ifp->if_watchdog = bfe_watchdog;
392 ifp->if_init = bfe_init;
393 ifp->if_mtu = ETHERMTU;
394 ifp->if_baudrate = 100000000;
395 ifp->if_capabilities |= IFCAP_VLAN_MTU;
396 ifp->if_capenable |= IFCAP_VLAN_MTU;
397 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
398 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
399 ifq_set_ready(&ifp->if_snd);
403 /* Reset the chip and turn on the PHY */
406 if (mii_phy_probe(dev, &sc->bfe_miibus,
407 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
408 device_printf(dev, "MII without any PHY!\n");
413 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
416 * Hook interrupt last to avoid having to lock softc
418 error = bus_setup_intr(dev, sc->bfe_irq, INTR_NETSAFE,
419 bfe_intr, sc, &sc->bfe_intrhand,
420 sc->arpcom.ac_if.if_serializer);
424 device_printf(dev, "couldn't set up irq\n");
434 bfe_detach(device_t dev)
436 struct bfe_softc *sc = device_get_softc(dev);
437 struct ifnet *ifp = &sc->arpcom.ac_if;
439 if (device_is_attached(dev)) {
440 lwkt_serialize_enter(ifp->if_serializer);
443 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
444 lwkt_serialize_exit(ifp->if_serializer);
448 if (sc->bfe_miibus != NULL)
449 device_delete_child(dev, sc->bfe_miibus);
450 bus_generic_detach(dev);
452 if (sc->bfe_irq != NULL)
453 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
455 if (sc->bfe_res != NULL) {
456 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO,
465 * Stop all chip I/O so that the kernel's probe routines don't
466 * get confused by errant DMAs when rebooting.
469 bfe_shutdown(device_t dev)
471 struct bfe_softc *sc = device_get_softc(dev);
472 struct ifnet *ifp = &sc->arpcom.ac_if;
474 lwkt_serialize_enter(ifp->if_serializer);
476 lwkt_serialize_exit(ifp->if_serializer);
480 bfe_miibus_readreg(device_t dev, int phy, int reg)
482 struct bfe_softc *sc;
485 sc = device_get_softc(dev);
486 if (phy != sc->bfe_phyaddr)
488 bfe_readphy(sc, reg, &ret);
494 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
496 struct bfe_softc *sc;
498 sc = device_get_softc(dev);
499 if (phy != sc->bfe_phyaddr)
501 bfe_writephy(sc, reg, val);
507 bfe_miibus_statchg(device_t dev)
513 bfe_tx_ring_free(struct bfe_softc *sc)
517 for (i = 0; i < BFE_TX_LIST_CNT; i++)
518 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
519 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
520 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
521 bus_dmamap_unload(sc->bfe_tag,
522 sc->bfe_tx_ring[i].bfe_map);
524 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
525 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
529 bfe_rx_ring_free(struct bfe_softc *sc)
533 for (i = 0; i < BFE_RX_LIST_CNT; i++)
534 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
535 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
536 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
537 bus_dmamap_unload(sc->bfe_tag,
538 sc->bfe_rx_ring[i].bfe_map);
540 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
541 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
546 bfe_list_rx_init(struct bfe_softc *sc)
550 for (i = 0; i < BFE_RX_LIST_CNT; i++)
551 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
554 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
555 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
563 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
565 struct bfe_rxheader *rx_header;
570 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
574 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
577 m->m_len = m->m_pkthdr.len = MCLBYTES;
580 m->m_data = m->m_ext.ext_buf;
582 rx_header = mtod(m, struct bfe_rxheader *);
584 rx_header->flags = 0;
586 /* Map the mbuf into DMA */
588 d = &sc->bfe_rx_list[c];
589 r = &sc->bfe_rx_ring[c];
590 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
591 MCLBYTES, bfe_dma_map_desc, d, 0);
592 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
594 ctrl = ETHER_MAX_LEN + 32;
596 if(c == BFE_RX_LIST_CNT - 1)
597 ctrl |= BFE_DESC_EOT;
601 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
606 bfe_get_config(struct bfe_softc *sc)
610 bfe_read_eeprom(sc, eeprom);
612 sc->arpcom.ac_enaddr[0] = eeprom[79];
613 sc->arpcom.ac_enaddr[1] = eeprom[78];
614 sc->arpcom.ac_enaddr[2] = eeprom[81];
615 sc->arpcom.ac_enaddr[3] = eeprom[80];
616 sc->arpcom.ac_enaddr[4] = eeprom[83];
617 sc->arpcom.ac_enaddr[5] = eeprom[82];
619 sc->bfe_phyaddr = eeprom[90] & 0x1f;
620 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
622 sc->bfe_core_unit = 0;
623 sc->bfe_dma_offset = BFE_PCI_DMA;
627 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
629 uint32_t bar_orig, pci_rev, val;
631 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
632 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
633 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
635 val = CSR_READ_4(sc, BFE_SBINTVEC);
637 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
639 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
640 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
641 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
643 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
647 bfe_clear_stats(struct bfe_softc *sc)
651 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
652 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
654 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
659 bfe_resetphy(struct bfe_softc *sc)
663 bfe_writephy(sc, 0, BMCR_RESET);
665 bfe_readphy(sc, 0, &val);
666 if (val & BMCR_RESET) {
667 if_printf(&sc->arpcom.ac_if,
668 "PHY Reset would not complete.\n");
675 bfe_chip_halt(struct bfe_softc *sc)
677 /* disable interrupts - not that it actually does..*/
678 CSR_WRITE_4(sc, BFE_IMASK, 0);
679 CSR_READ_4(sc, BFE_IMASK);
681 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
682 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
684 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
685 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
690 bfe_chip_reset(struct bfe_softc *sc)
694 /* Set the interrupt vector for the enet core */
695 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
698 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
699 if (val == BFE_CLOCK) {
700 /* It is, so shut it down */
701 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
702 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
703 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
704 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
705 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
706 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
707 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
708 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
709 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
716 * We want the phy registers to be accessible even when
717 * the driver is "downed" so initialize MDC preamble, frequency,
718 * and whether internal or external phy here.
721 /* 4402 has 62.5Mhz SB clock and internal phy */
722 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
724 /* Internal or external PHY? */
725 val = CSR_READ_4(sc, BFE_DEVCTRL);
726 if (!(val & BFE_IPP))
727 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
728 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
729 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
733 /* Enable CRC32 generation and set proper LED modes */
734 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
736 /* Reset or clear powerdown control bit */
737 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
739 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
743 * We don't want lazy interrupts, so just send them at the end of a
746 BFE_OR(sc, BFE_RCV_LAZY, 0);
748 /* Set max lengths, accounting for VLAN tags */
749 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
750 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
752 /* Set watermark XXX - magic */
753 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
756 * Initialise DMA channels - not forgetting dma addresses need to be
757 * added to BFE_PCI_DMA
759 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
760 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
762 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
764 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
771 bfe_core_disable(struct bfe_softc *sc)
773 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
777 * Set reject, wait for it set, then wait for the core to stop being busy
778 * Then set reset and reject and enable the clocks
780 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
781 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
782 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
783 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
785 CSR_READ_4(sc, BFE_SBTMSLOW);
787 /* Leave reset and reject set */
788 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
793 bfe_core_reset(struct bfe_softc *sc)
797 /* Disable the core */
798 bfe_core_disable(sc);
800 /* and bring it back up */
801 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
802 CSR_READ_4(sc, BFE_SBTMSLOW);
805 /* Chip bug, clear SERR, IB and TO if they are set. */
806 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
807 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
808 val = CSR_READ_4(sc, BFE_SBIMSTATE);
809 if (val & (BFE_IBE | BFE_TO))
810 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
812 /* Clear reset and allow it to move through the core */
813 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
814 CSR_READ_4(sc, BFE_SBTMSLOW);
817 /* Leave the clock set */
818 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
819 CSR_READ_4(sc, BFE_SBTMSLOW);
824 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
828 val = ((uint32_t) data[2]) << 24;
829 val |= ((uint32_t) data[3]) << 16;
830 val |= ((uint32_t) data[4]) << 8;
831 val |= ((uint32_t) data[5]);
832 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
833 val = (BFE_CAM_HI_VALID |
834 (((uint32_t) data[0]) << 8) |
835 (((uint32_t) data[1])));
836 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
837 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
838 ((uint32_t)index << BFE_CAM_INDEX_SHIFT)));
839 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
843 bfe_set_rx_mode(struct bfe_softc *sc)
845 struct ifnet *ifp = &sc->arpcom.ac_if;
846 struct ifmultiaddr *ifma;
850 val = CSR_READ_4(sc, BFE_RXCONF);
852 if (ifp->if_flags & IFF_PROMISC)
853 val |= BFE_RXCONF_PROMISC;
855 val &= ~BFE_RXCONF_PROMISC;
857 if (ifp->if_flags & IFF_BROADCAST)
858 val &= ~BFE_RXCONF_DBCAST;
860 val |= BFE_RXCONF_DBCAST;
863 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
864 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
866 if (ifp->if_flags & IFF_ALLMULTI) {
867 val |= BFE_RXCONF_ALLMULTI;
869 val &= ~BFE_RXCONF_ALLMULTI;
870 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
871 if (ifma->ifma_addr->sa_family != AF_LINK)
874 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
878 CSR_WRITE_4(sc, BFE_RXCONF, val);
879 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
883 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
888 *ptr = segs->ds_addr;
892 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
897 /* The chip needs all addresses to be added to BFE_PCI_DMA */
898 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
902 bfe_dma_free(struct bfe_softc *sc)
904 if (sc->bfe_tx_tag != NULL) {
905 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
906 if (sc->bfe_tx_list != NULL) {
907 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
909 sc->bfe_tx_list = NULL;
911 bus_dma_tag_destroy(sc->bfe_tx_tag);
912 sc->bfe_tx_tag = NULL;
915 if (sc->bfe_rx_tag != NULL) {
916 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
917 if (sc->bfe_rx_list != NULL) {
918 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
920 sc->bfe_rx_list = NULL;
922 bus_dma_tag_destroy(sc->bfe_rx_tag);
923 sc->bfe_rx_tag = NULL;
926 if (sc->bfe_tag != NULL) {
929 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
930 bus_dmamap_destroy(sc->bfe_tag,
931 sc->bfe_tx_ring[i].bfe_map);
933 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
934 bus_dmamap_destroy(sc->bfe_tag,
935 sc->bfe_rx_ring[i].bfe_map);
938 bus_dma_tag_destroy(sc->bfe_tag);
942 if (sc->bfe_parent_tag != NULL) {
943 bus_dma_tag_destroy(sc->bfe_parent_tag);
944 sc->bfe_parent_tag = NULL;
949 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
952 uint16_t *ptr = (uint16_t *)data;
954 for (i = 0; i < 128; i += 2)
955 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
959 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
960 u_long timeout, const int clear)
964 for (i = 0; i < timeout; i++) {
965 uint32_t val = CSR_READ_4(sc, reg);
967 if (clear && !(val & bit))
969 if (!clear && (val & bit))
974 if_printf(&sc->arpcom.ac_if,
975 "BUG! Timeout waiting for bit %08x of register "
976 "%x to %s.\n", bit, reg,
977 (clear ? "clear" : "set"));
984 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
989 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
990 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
991 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
992 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
993 (reg << BFE_MDIO_RA_SHIFT) |
994 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
995 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
996 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1001 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
1005 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1006 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1007 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1008 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1009 (reg << BFE_MDIO_RA_SHIFT) |
1010 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1011 (val & BFE_MDIO_DATA_DATA)));
1012 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1018 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1022 bfe_setupphy(struct bfe_softc *sc)
1026 /* Enable activity LED */
1027 bfe_readphy(sc, 26, &val);
1028 bfe_writephy(sc, 26, val & 0x7fff);
1029 bfe_readphy(sc, 26, &val);
1031 /* Enable traffic meter LED mode */
1032 bfe_readphy(sc, 27, &val);
1033 bfe_writephy(sc, 27, val | (1 << 6));
1039 bfe_stats_update(struct bfe_softc *sc)
1044 val = &sc->bfe_hwstats.tx_good_octets;
1045 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1046 *val++ += CSR_READ_4(sc, reg);
1047 val = &sc->bfe_hwstats.rx_good_octets;
1048 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1049 *val++ += CSR_READ_4(sc, reg);
1053 bfe_txeof(struct bfe_softc *sc)
1055 struct ifnet *ifp = &sc->arpcom.ac_if;
1056 uint32_t i, chipidx;
1058 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1059 chipidx /= sizeof(struct bfe_desc);
1061 i = sc->bfe_tx_cons;
1062 /* Go through the mbufs and free those that have been transmitted */
1063 while (i != chipidx) {
1064 struct bfe_data *r = &sc->bfe_tx_ring[i];
1065 if (r->bfe_mbuf != NULL) {
1067 m_freem(r->bfe_mbuf);
1069 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1072 BFE_INC(i, BFE_TX_LIST_CNT);
1075 if (i != sc->bfe_tx_cons) {
1076 /* we freed up some mbufs */
1077 sc->bfe_tx_cons = i;
1078 ifp->if_flags &= ~IFF_OACTIVE;
1080 if (sc->bfe_tx_cnt == 0)
1086 /* Pass a received packet up the stack */
1088 bfe_rxeof(struct bfe_softc *sc)
1090 struct ifnet *ifp = &sc->arpcom.ac_if;
1092 struct bfe_rxheader *rxheader;
1094 uint32_t cons, status, current, len, flags;
1096 cons = sc->bfe_rx_cons;
1097 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1098 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1100 while (current != cons) {
1101 r = &sc->bfe_rx_ring[cons];
1103 rxheader = mtod(m, struct bfe_rxheader*);
1104 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE);
1105 len = rxheader->len;
1108 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1109 flags = rxheader->flags;
1111 len -= ETHER_CRC_LEN;
1113 /* flag an error and try again */
1114 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1116 if (flags & BFE_RX_FLAG_SERR)
1117 ifp->if_collisions++;
1118 bfe_list_newbuf(sc, cons, m);
1119 BFE_INC(cons, BFE_RX_LIST_CNT);
1123 /* Go past the rx header */
1124 if (bfe_list_newbuf(sc, cons, NULL) != 0) {
1125 bfe_list_newbuf(sc, cons, m);
1126 BFE_INC(cons, BFE_RX_LIST_CNT);
1131 m_adj(m, BFE_RX_OFFSET);
1132 m->m_len = m->m_pkthdr.len = len;
1135 m->m_pkthdr.rcvif = ifp;
1137 ifp->if_input(ifp, m);
1138 BFE_INC(cons, BFE_RX_LIST_CNT);
1140 sc->bfe_rx_cons = cons;
1146 struct bfe_softc *sc = xsc;
1147 struct ifnet *ifp = &sc->arpcom.ac_if;
1148 uint32_t istat, imask, flag;
1150 istat = CSR_READ_4(sc, BFE_ISTAT);
1151 imask = CSR_READ_4(sc, BFE_IMASK);
1154 * Defer unsolicited interrupts - This is necessary because setting the
1155 * chips interrupt mask register to 0 doesn't actually stop the
1159 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1160 CSR_READ_4(sc, BFE_ISTAT);
1162 /* not expecting this interrupt, disregard it */
1167 if (istat & BFE_ISTAT_ERRORS) {
1168 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1169 if (flag & BFE_STAT_EMASK)
1172 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1173 if (flag & BFE_RX_FLAG_ERRORS)
1176 ifp->if_flags &= ~IFF_RUNNING;
1180 /* A packet was received */
1181 if (istat & BFE_ISTAT_RX)
1184 /* A packet was sent */
1185 if (istat & BFE_ISTAT_TX)
1188 /* We have packets pending, fire them out */
1189 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1194 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1196 struct bfe_desc *d = NULL;
1197 struct bfe_data *r = NULL;
1199 uint32_t frag, cur, cnt = 0;
1201 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2)
1205 * Start packing the mbufs in this chain into
1206 * the fragment pointers. Stop when we run out
1207 * of fragments or hit the end of the mbuf chain.
1210 cur = frag = *txidx;
1213 for (m = m_head; m != NULL; m = m->m_next) {
1214 if (m->m_len != 0) {
1215 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2)
1218 d = &sc->bfe_tx_list[cur];
1219 r = &sc->bfe_tx_ring[cur];
1220 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1221 /* always intterupt on completion */
1222 d->bfe_ctrl |= BFE_DESC_IOC;
1224 /* Set start of frame */
1225 d->bfe_ctrl |= BFE_DESC_SOF;
1226 if (cur == BFE_TX_LIST_CNT - 1)
1228 * Tell the chip to wrap to the start of the
1231 d->bfe_ctrl |= BFE_DESC_EOT;
1233 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*),
1234 m->m_len, bfe_dma_map_desc, d, 0);
1235 bus_dmamap_sync(sc->bfe_tag, r->bfe_map,
1236 BUS_DMASYNC_PREREAD);
1239 BFE_INC(cur, BFE_TX_LIST_CNT);
1247 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1248 sc->bfe_tx_ring[frag].bfe_mbuf = m_head;
1249 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
1252 sc->bfe_tx_cnt += cnt;
1257 * Set up to transmit a packet
1260 bfe_start(struct ifnet *ifp)
1262 struct bfe_softc *sc = ifp->if_softc;
1263 struct mbuf *m_head = NULL;
1264 int idx, need_trans;
1267 * Not much point trying to send if the link is down
1268 * or we have nothing to send.
1273 if (ifp->if_flags & IFF_OACTIVE)
1276 idx = sc->bfe_tx_prod;
1279 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1280 m_head = ifq_poll(&ifp->if_snd);
1285 * Pack the data into the tx ring. If we don't have
1286 * enough room, let the chip drain the ring.
1288 if (bfe_encap(sc, m_head, &idx)) {
1289 ifp->if_flags |= IFF_OACTIVE;
1292 ifq_dequeue(&ifp->if_snd, m_head);
1296 * If there's a BPF listener, bounce a copy of this frame
1299 BPF_MTAP(ifp, m_head);
1305 sc->bfe_tx_prod = idx;
1306 /* Transmit - twice due to apparent hardware bug */
1307 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1308 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1311 * Set a timeout in case the chip goes out to lunch.
1319 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1320 struct ifnet *ifp = &sc->arpcom.ac_if;
1322 if (ifp->if_flags & IFF_RUNNING)
1328 if (bfe_list_rx_init(sc) == ENOBUFS) {
1329 if_printf(ifp, "bfe_init failed. "
1330 " Not enough memory for list buffers\n");
1335 bfe_set_rx_mode(sc);
1337 /* Enable the chip and core */
1338 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1339 /* Enable interrupts */
1340 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1342 bfe_ifmedia_upd(ifp);
1343 ifp->if_flags |= IFF_RUNNING;
1344 ifp->if_flags &= ~IFF_OACTIVE;
1346 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1350 * Set media options.
1353 bfe_ifmedia_upd(struct ifnet *ifp)
1355 struct bfe_softc *sc = ifp->if_softc;
1356 struct mii_data *mii;
1358 mii = device_get_softc(sc->bfe_miibus);
1360 if (mii->mii_instance) {
1361 struct mii_softc *miisc;
1362 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1363 miisc = LIST_NEXT(miisc, mii_list))
1364 mii_phy_reset(miisc);
1374 * Report current media status.
1377 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1379 struct bfe_softc *sc = ifp->if_softc;
1380 struct mii_data *mii;
1382 mii = device_get_softc(sc->bfe_miibus);
1384 ifmr->ifm_active = mii->mii_media_active;
1385 ifmr->ifm_status = mii->mii_media_status;
1389 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1391 struct bfe_softc *sc = ifp->if_softc;
1392 struct ifreq *ifr = (struct ifreq *) data;
1393 struct mii_data *mii;
1398 if (ifp->if_flags & IFF_UP)
1399 if (ifp->if_flags & IFF_RUNNING)
1400 bfe_set_rx_mode(sc);
1403 else if (ifp->if_flags & IFF_RUNNING)
1408 if (ifp->if_flags & IFF_RUNNING)
1409 bfe_set_rx_mode(sc);
1413 mii = device_get_softc(sc->bfe_miibus);
1414 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1418 error = ether_ioctl(ifp, command, data);
1425 bfe_watchdog(struct ifnet *ifp)
1427 struct bfe_softc *sc = ifp->if_softc;
1429 if_printf(ifp, "watchdog timeout -- resetting\n");
1431 ifp->if_flags &= ~IFF_RUNNING;
1440 struct bfe_softc *sc = xsc;
1441 struct mii_data *mii;
1442 struct ifnet *ifp = &sc->arpcom.ac_if;
1444 mii = device_get_softc(sc->bfe_miibus);
1446 lwkt_serialize_enter(ifp->if_serializer);
1448 bfe_stats_update(sc);
1449 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1451 if (sc->bfe_link == NULL) {
1453 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1454 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1460 lwkt_serialize_exit(ifp->if_serializer);
1464 * Stop the adapter and free any mbufs allocated to the
1468 bfe_stop(struct bfe_softc *sc)
1470 struct ifnet *ifp = &sc->arpcom.ac_if;
1472 callout_stop(&sc->bfe_stat_timer);
1475 bfe_tx_ring_free(sc);
1476 bfe_rx_ring_free(sc);
1478 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);