sys/platform/pc64/apic/ioapic_abi.c

   1 /*
   2  * Copyright (c) 1991 The Regents of the University of California.
   3  * Copyright (c) 1996, by Steve Passe.  All rights reserved.
   4  * Copyright (c) 2005,2008 The DragonFly Project.  All rights reserved.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The DragonFly Project
   8  * by Matthew Dillon <dillon@backplane.com>
   9  *
  10  * This code is derived from software contributed to Berkeley by
  11  * William Jolitz.
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  * 3. Neither the name of The DragonFly Project nor the names of its
  24  *    contributors may be used to endorse or promote products derived
  25  *    from this software without specific, prior written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  31  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  35  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  37  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  *
  40  * $DragonFly: src/sys/platform/pc64/apic/apic_abi.c,v 1.1 2008/08/29 17:07:12 dillon Exp $
  41  */
  42
  43 #include <sys/param.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/machintr.h>
  47 #include <sys/interrupt.h>
  48 #include <sys/bus.h>
  49
  50 #include <machine/smp.h>
  51 #include <machine/segments.h>
  52 #include <machine/md_var.h>
  53 #include <machine/intr_machdep.h>
  54 #include <machine/globaldata.h>
  55
  56 #include <sys/thread2.h>
  57
  58 #include <machine_base/isa/isa_intr.h>
  59 #include <machine_base/icu/icu.h>
  60 #include <machine_base/icu/icu_var.h>
  61 #include <machine_base/apic/ioapic.h>
  62 #include <machine_base/apic/ioapic_abi.h>
  63 #include <machine_base/apic/ioapic_ipl.h>
  64 #include <machine_base/apic/apicreg.h>
  65
  66 #define IOAPIC_HWI_VECTORS      IDT_HWI_VECTORS
  67
  68 extern inthand_t
  69         IDTVEC(ioapic_intr0),
  70         IDTVEC(ioapic_intr1),
  71         IDTVEC(ioapic_intr2),
  72         IDTVEC(ioapic_intr3),
  73         IDTVEC(ioapic_intr4),
  74         IDTVEC(ioapic_intr5),
  75         IDTVEC(ioapic_intr6),
  76         IDTVEC(ioapic_intr7),
  77         IDTVEC(ioapic_intr8),
  78         IDTVEC(ioapic_intr9),
  79         IDTVEC(ioapic_intr10),
  80         IDTVEC(ioapic_intr11),
  81         IDTVEC(ioapic_intr12),
  82         IDTVEC(ioapic_intr13),
  83         IDTVEC(ioapic_intr14),
  84         IDTVEC(ioapic_intr15),
  85         IDTVEC(ioapic_intr16),
  86         IDTVEC(ioapic_intr17),
  87         IDTVEC(ioapic_intr18),
  88         IDTVEC(ioapic_intr19),
  89         IDTVEC(ioapic_intr20),
  90         IDTVEC(ioapic_intr21),
  91         IDTVEC(ioapic_intr22),
  92         IDTVEC(ioapic_intr23),
  93         IDTVEC(ioapic_intr24),
  94         IDTVEC(ioapic_intr25),
  95         IDTVEC(ioapic_intr26),
  96         IDTVEC(ioapic_intr27),
  97         IDTVEC(ioapic_intr28),
  98         IDTVEC(ioapic_intr29),
  99         IDTVEC(ioapic_intr30),
 100         IDTVEC(ioapic_intr31),
 101         IDTVEC(ioapic_intr32),
 102         IDTVEC(ioapic_intr33),
 103         IDTVEC(ioapic_intr34),
 104         IDTVEC(ioapic_intr35),
 105         IDTVEC(ioapic_intr36),
 106         IDTVEC(ioapic_intr37),
 107         IDTVEC(ioapic_intr38),
 108         IDTVEC(ioapic_intr39),
 109         IDTVEC(ioapic_intr40),
 110         IDTVEC(ioapic_intr41),
 111         IDTVEC(ioapic_intr42),
 112         IDTVEC(ioapic_intr43),
 113         IDTVEC(ioapic_intr44),
 114         IDTVEC(ioapic_intr45),
 115         IDTVEC(ioapic_intr46),
 116         IDTVEC(ioapic_intr47),
 117         IDTVEC(ioapic_intr48),
 118         IDTVEC(ioapic_intr49),
 119         IDTVEC(ioapic_intr50),
 120         IDTVEC(ioapic_intr51),
 121         IDTVEC(ioapic_intr52),
 122         IDTVEC(ioapic_intr53),
 123         IDTVEC(ioapic_intr54),
 124         IDTVEC(ioapic_intr55),
 125         IDTVEC(ioapic_intr56),
 126         IDTVEC(ioapic_intr57),
 127         IDTVEC(ioapic_intr58),
 128         IDTVEC(ioapic_intr59),
 129         IDTVEC(ioapic_intr60),
 130         IDTVEC(ioapic_intr61),
 131         IDTVEC(ioapic_intr62),
 132         IDTVEC(ioapic_intr63),
 133         IDTVEC(ioapic_intr64),
 134         IDTVEC(ioapic_intr65),
 135         IDTVEC(ioapic_intr66),
 136         IDTVEC(ioapic_intr67),
 137         IDTVEC(ioapic_intr68),
 138         IDTVEC(ioapic_intr69),
 139         IDTVEC(ioapic_intr70),
 140         IDTVEC(ioapic_intr71),
 141         IDTVEC(ioapic_intr72),
 142         IDTVEC(ioapic_intr73),
 143         IDTVEC(ioapic_intr74),
 144         IDTVEC(ioapic_intr75),
 145         IDTVEC(ioapic_intr76),
 146         IDTVEC(ioapic_intr77),
 147         IDTVEC(ioapic_intr78),
 148         IDTVEC(ioapic_intr79),
 149         IDTVEC(ioapic_intr80),
 150         IDTVEC(ioapic_intr81),
 151         IDTVEC(ioapic_intr82),
 152         IDTVEC(ioapic_intr83),
 153         IDTVEC(ioapic_intr84),
 154         IDTVEC(ioapic_intr85),
 155         IDTVEC(ioapic_intr86),
 156         IDTVEC(ioapic_intr87),
 157         IDTVEC(ioapic_intr88),
 158         IDTVEC(ioapic_intr89),
 159         IDTVEC(ioapic_intr90),
 160         IDTVEC(ioapic_intr91),
 161         IDTVEC(ioapic_intr92),
 162         IDTVEC(ioapic_intr93),
 163         IDTVEC(ioapic_intr94),
 164         IDTVEC(ioapic_intr95),
 165         IDTVEC(ioapic_intr96),
 166         IDTVEC(ioapic_intr97),
 167         IDTVEC(ioapic_intr98),
 168         IDTVEC(ioapic_intr99),
 169         IDTVEC(ioapic_intr100),
 170         IDTVEC(ioapic_intr101),
 171         IDTVEC(ioapic_intr102),
 172         IDTVEC(ioapic_intr103),
 173         IDTVEC(ioapic_intr104),
 174         IDTVEC(ioapic_intr105),
 175         IDTVEC(ioapic_intr106),
 176         IDTVEC(ioapic_intr107),
 177         IDTVEC(ioapic_intr108),
 178         IDTVEC(ioapic_intr109),
 179         IDTVEC(ioapic_intr110),
 180         IDTVEC(ioapic_intr111),
 181         IDTVEC(ioapic_intr112),
 182         IDTVEC(ioapic_intr113),
 183         IDTVEC(ioapic_intr114),
 184         IDTVEC(ioapic_intr115),
 185         IDTVEC(ioapic_intr116),
 186         IDTVEC(ioapic_intr117),
 187         IDTVEC(ioapic_intr118),
 188         IDTVEC(ioapic_intr119),
 189         IDTVEC(ioapic_intr120),
 190         IDTVEC(ioapic_intr121),
 191         IDTVEC(ioapic_intr122),
 192         IDTVEC(ioapic_intr123),
 193         IDTVEC(ioapic_intr124),
 194         IDTVEC(ioapic_intr125),
 195         IDTVEC(ioapic_intr126),
 196         IDTVEC(ioapic_intr127),
 197         IDTVEC(ioapic_intr128),
 198         IDTVEC(ioapic_intr129),
 199         IDTVEC(ioapic_intr130),
 200         IDTVEC(ioapic_intr131),
 201         IDTVEC(ioapic_intr132),
 202         IDTVEC(ioapic_intr133),
 203         IDTVEC(ioapic_intr134),
 204         IDTVEC(ioapic_intr135),
 205         IDTVEC(ioapic_intr136),
 206         IDTVEC(ioapic_intr137),
 207         IDTVEC(ioapic_intr138),
 208         IDTVEC(ioapic_intr139),
 209         IDTVEC(ioapic_intr140),
 210         IDTVEC(ioapic_intr141),
 211         IDTVEC(ioapic_intr142),
 212         IDTVEC(ioapic_intr143),
 213         IDTVEC(ioapic_intr144),
 214         IDTVEC(ioapic_intr145),
 215         IDTVEC(ioapic_intr146),
 216         IDTVEC(ioapic_intr147),
 217         IDTVEC(ioapic_intr148),
 218         IDTVEC(ioapic_intr149),
 219         IDTVEC(ioapic_intr150),
 220         IDTVEC(ioapic_intr151),
 221         IDTVEC(ioapic_intr152),
 222         IDTVEC(ioapic_intr153),
 223         IDTVEC(ioapic_intr154),
 224         IDTVEC(ioapic_intr155),
 225         IDTVEC(ioapic_intr156),
 226         IDTVEC(ioapic_intr157),
 227         IDTVEC(ioapic_intr158),
 228         IDTVEC(ioapic_intr159),
 229         IDTVEC(ioapic_intr160),
 230         IDTVEC(ioapic_intr161),
 231         IDTVEC(ioapic_intr162),
 232         IDTVEC(ioapic_intr163),
 233         IDTVEC(ioapic_intr164),
 234         IDTVEC(ioapic_intr165),
 235         IDTVEC(ioapic_intr166),
 236         IDTVEC(ioapic_intr167),
 237         IDTVEC(ioapic_intr168),
 238         IDTVEC(ioapic_intr169),
 239         IDTVEC(ioapic_intr170),
 240         IDTVEC(ioapic_intr171),
 241         IDTVEC(ioapic_intr172),
 242         IDTVEC(ioapic_intr173),
 243         IDTVEC(ioapic_intr174),
 244         IDTVEC(ioapic_intr175),
 245         IDTVEC(ioapic_intr176),
 246         IDTVEC(ioapic_intr177),
 247         IDTVEC(ioapic_intr178),
 248         IDTVEC(ioapic_intr179),
 249         IDTVEC(ioapic_intr180),
 250         IDTVEC(ioapic_intr181),
 251         IDTVEC(ioapic_intr182),
 252         IDTVEC(ioapic_intr183),
 253         IDTVEC(ioapic_intr184),
 254         IDTVEC(ioapic_intr185),
 255         IDTVEC(ioapic_intr186),
 256         IDTVEC(ioapic_intr187),
 257         IDTVEC(ioapic_intr188),
 258         IDTVEC(ioapic_intr189),
 259         IDTVEC(ioapic_intr190),
 260         IDTVEC(ioapic_intr191);
 261
 262 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
 263         &IDTVEC(ioapic_intr0),
 264         &IDTVEC(ioapic_intr1),
 265         &IDTVEC(ioapic_intr2),
 266         &IDTVEC(ioapic_intr3),
 267         &IDTVEC(ioapic_intr4),
 268         &IDTVEC(ioapic_intr5),
 269         &IDTVEC(ioapic_intr6),
 270         &IDTVEC(ioapic_intr7),
 271         &IDTVEC(ioapic_intr8),
 272         &IDTVEC(ioapic_intr9),
 273         &IDTVEC(ioapic_intr10),
 274         &IDTVEC(ioapic_intr11),
 275         &IDTVEC(ioapic_intr12),
 276         &IDTVEC(ioapic_intr13),
 277         &IDTVEC(ioapic_intr14),
 278         &IDTVEC(ioapic_intr15),
 279         &IDTVEC(ioapic_intr16),
 280         &IDTVEC(ioapic_intr17),
 281         &IDTVEC(ioapic_intr18),
 282         &IDTVEC(ioapic_intr19),
 283         &IDTVEC(ioapic_intr20),
 284         &IDTVEC(ioapic_intr21),
 285         &IDTVEC(ioapic_intr22),
 286         &IDTVEC(ioapic_intr23),
 287         &IDTVEC(ioapic_intr24),
 288         &IDTVEC(ioapic_intr25),
 289         &IDTVEC(ioapic_intr26),
 290         &IDTVEC(ioapic_intr27),
 291         &IDTVEC(ioapic_intr28),
 292         &IDTVEC(ioapic_intr29),
 293         &IDTVEC(ioapic_intr30),
 294         &IDTVEC(ioapic_intr31),
 295         &IDTVEC(ioapic_intr32),
 296         &IDTVEC(ioapic_intr33),
 297         &IDTVEC(ioapic_intr34),
 298         &IDTVEC(ioapic_intr35),
 299         &IDTVEC(ioapic_intr36),
 300         &IDTVEC(ioapic_intr37),
 301         &IDTVEC(ioapic_intr38),
 302         &IDTVEC(ioapic_intr39),
 303         &IDTVEC(ioapic_intr40),
 304         &IDTVEC(ioapic_intr41),
 305         &IDTVEC(ioapic_intr42),
 306         &IDTVEC(ioapic_intr43),
 307         &IDTVEC(ioapic_intr44),
 308         &IDTVEC(ioapic_intr45),
 309         &IDTVEC(ioapic_intr46),
 310         &IDTVEC(ioapic_intr47),
 311         &IDTVEC(ioapic_intr48),
 312         &IDTVEC(ioapic_intr49),
 313         &IDTVEC(ioapic_intr50),
 314         &IDTVEC(ioapic_intr51),
 315         &IDTVEC(ioapic_intr52),
 316         &IDTVEC(ioapic_intr53),
 317         &IDTVEC(ioapic_intr54),
 318         &IDTVEC(ioapic_intr55),
 319         &IDTVEC(ioapic_intr56),
 320         &IDTVEC(ioapic_intr57),
 321         &IDTVEC(ioapic_intr58),
 322         &IDTVEC(ioapic_intr59),
 323         &IDTVEC(ioapic_intr60),
 324         &IDTVEC(ioapic_intr61),
 325         &IDTVEC(ioapic_intr62),
 326         &IDTVEC(ioapic_intr63),
 327         &IDTVEC(ioapic_intr64),
 328         &IDTVEC(ioapic_intr65),
 329         &IDTVEC(ioapic_intr66),
 330         &IDTVEC(ioapic_intr67),
 331         &IDTVEC(ioapic_intr68),
 332         &IDTVEC(ioapic_intr69),
 333         &IDTVEC(ioapic_intr70),
 334         &IDTVEC(ioapic_intr71),
 335         &IDTVEC(ioapic_intr72),
 336         &IDTVEC(ioapic_intr73),
 337         &IDTVEC(ioapic_intr74),
 338         &IDTVEC(ioapic_intr75),
 339         &IDTVEC(ioapic_intr76),
 340         &IDTVEC(ioapic_intr77),
 341         &IDTVEC(ioapic_intr78),
 342         &IDTVEC(ioapic_intr79),
 343         &IDTVEC(ioapic_intr80),
 344         &IDTVEC(ioapic_intr81),
 345         &IDTVEC(ioapic_intr82),
 346         &IDTVEC(ioapic_intr83),
 347         &IDTVEC(ioapic_intr84),
 348         &IDTVEC(ioapic_intr85),
 349         &IDTVEC(ioapic_intr86),
 350         &IDTVEC(ioapic_intr87),
 351         &IDTVEC(ioapic_intr88),
 352         &IDTVEC(ioapic_intr89),
 353         &IDTVEC(ioapic_intr90),
 354         &IDTVEC(ioapic_intr91),
 355         &IDTVEC(ioapic_intr92),
 356         &IDTVEC(ioapic_intr93),
 357         &IDTVEC(ioapic_intr94),
 358         &IDTVEC(ioapic_intr95),
 359         &IDTVEC(ioapic_intr96),
 360         &IDTVEC(ioapic_intr97),
 361         &IDTVEC(ioapic_intr98),
 362         &IDTVEC(ioapic_intr99),
 363         &IDTVEC(ioapic_intr100),
 364         &IDTVEC(ioapic_intr101),
 365         &IDTVEC(ioapic_intr102),
 366         &IDTVEC(ioapic_intr103),
 367         &IDTVEC(ioapic_intr104),
 368         &IDTVEC(ioapic_intr105),
 369         &IDTVEC(ioapic_intr106),
 370         &IDTVEC(ioapic_intr107),
 371         &IDTVEC(ioapic_intr108),
 372         &IDTVEC(ioapic_intr109),
 373         &IDTVEC(ioapic_intr110),
 374         &IDTVEC(ioapic_intr111),
 375         &IDTVEC(ioapic_intr112),
 376         &IDTVEC(ioapic_intr113),
 377         &IDTVEC(ioapic_intr114),
 378         &IDTVEC(ioapic_intr115),
 379         &IDTVEC(ioapic_intr116),
 380         &IDTVEC(ioapic_intr117),
 381         &IDTVEC(ioapic_intr118),
 382         &IDTVEC(ioapic_intr119),
 383         &IDTVEC(ioapic_intr120),
 384         &IDTVEC(ioapic_intr121),
 385         &IDTVEC(ioapic_intr122),
 386         &IDTVEC(ioapic_intr123),
 387         &IDTVEC(ioapic_intr124),
 388         &IDTVEC(ioapic_intr125),
 389         &IDTVEC(ioapic_intr126),
 390         &IDTVEC(ioapic_intr127),
 391         &IDTVEC(ioapic_intr128),
 392         &IDTVEC(ioapic_intr129),
 393         &IDTVEC(ioapic_intr130),
 394         &IDTVEC(ioapic_intr131),
 395         &IDTVEC(ioapic_intr132),
 396         &IDTVEC(ioapic_intr133),
 397         &IDTVEC(ioapic_intr134),
 398         &IDTVEC(ioapic_intr135),
 399         &IDTVEC(ioapic_intr136),
 400         &IDTVEC(ioapic_intr137),
 401         &IDTVEC(ioapic_intr138),
 402         &IDTVEC(ioapic_intr139),
 403         &IDTVEC(ioapic_intr140),
 404         &IDTVEC(ioapic_intr141),
 405         &IDTVEC(ioapic_intr142),
 406         &IDTVEC(ioapic_intr143),
 407         &IDTVEC(ioapic_intr144),
 408         &IDTVEC(ioapic_intr145),
 409         &IDTVEC(ioapic_intr146),
 410         &IDTVEC(ioapic_intr147),
 411         &IDTVEC(ioapic_intr148),
 412         &IDTVEC(ioapic_intr149),
 413         &IDTVEC(ioapic_intr150),
 414         &IDTVEC(ioapic_intr151),
 415         &IDTVEC(ioapic_intr152),
 416         &IDTVEC(ioapic_intr153),
 417         &IDTVEC(ioapic_intr154),
 418         &IDTVEC(ioapic_intr155),
 419         &IDTVEC(ioapic_intr156),
 420         &IDTVEC(ioapic_intr157),
 421         &IDTVEC(ioapic_intr158),
 422         &IDTVEC(ioapic_intr159),
 423         &IDTVEC(ioapic_intr160),
 424         &IDTVEC(ioapic_intr161),
 425         &IDTVEC(ioapic_intr162),
 426         &IDTVEC(ioapic_intr163),
 427         &IDTVEC(ioapic_intr164),
 428         &IDTVEC(ioapic_intr165),
 429         &IDTVEC(ioapic_intr166),
 430         &IDTVEC(ioapic_intr167),
 431         &IDTVEC(ioapic_intr168),
 432         &IDTVEC(ioapic_intr169),
 433         &IDTVEC(ioapic_intr170),
 434         &IDTVEC(ioapic_intr171),
 435         &IDTVEC(ioapic_intr172),
 436         &IDTVEC(ioapic_intr173),
 437         &IDTVEC(ioapic_intr174),
 438         &IDTVEC(ioapic_intr175),
 439         &IDTVEC(ioapic_intr176),
 440         &IDTVEC(ioapic_intr177),
 441         &IDTVEC(ioapic_intr178),
 442         &IDTVEC(ioapic_intr179),
 443         &IDTVEC(ioapic_intr180),
 444         &IDTVEC(ioapic_intr181),
 445         &IDTVEC(ioapic_intr182),
 446         &IDTVEC(ioapic_intr183),
 447         &IDTVEC(ioapic_intr184),
 448         &IDTVEC(ioapic_intr185),
 449         &IDTVEC(ioapic_intr186),
 450         &IDTVEC(ioapic_intr187),
 451         &IDTVEC(ioapic_intr188),
 452         &IDTVEC(ioapic_intr189),
 453         &IDTVEC(ioapic_intr190),
 454         &IDTVEC(ioapic_intr191)
 455 };
 456
 457 #define IOAPIC_HWI_SYSCALL      (IDT_OFFSET_SYSCALL - IDT_OFFSET)
 458
 459 static struct ioapic_irqmap {
 460         int                     im_type;        /* IOAPIC_IMT_ */
 461         enum intr_trigger       im_trig;
 462         enum intr_polarity      im_pola;
 463         int                     im_gsi;
 464         uint32_t                im_flags;       /* IOAPIC_IMF_ */
 465 } ioapic_irqmaps[IOAPIC_HWI_VECTORS];
 466
 467 #define IOAPIC_IMT_UNUSED       0
 468 #define IOAPIC_IMT_RESERVED     1
 469 #define IOAPIC_IMT_LINE         2
 470 #define IOAPIC_IMT_SYSCALL      3
 471
 472 #define IOAPIC_IMF_CONF         0x1
 473
 474 extern void     IOAPIC_INTREN(int);
 475 extern void     IOAPIC_INTRDIS(int);
 476
 477 extern int      imcr_present;
 478
 479 static void     ioapic_abi_intr_enable(int);
 480 static void     ioapic_abi_intr_disable(int);
 481 static void     ioapic_abi_intr_setup(int, int);
 482 static void     ioapic_abi_intr_teardown(int);
 483 static void     ioapic_abi_intr_config(int,
 484                     enum intr_trigger, enum intr_polarity);
 485
 486 static void     ioapic_abi_finalize(void);
 487 static void     ioapic_abi_cleanup(void);
 488 static void     ioapic_abi_setdefault(void);
 489 static void     ioapic_abi_stabilize(void);
 490 static void     ioapic_abi_initmap(void);
 491
 492 struct machintr_abi MachIntrABI_IOAPIC = {
 493         MACHINTR_IOAPIC,
 494         .intr_disable   = ioapic_abi_intr_disable,
 495         .intr_enable    = ioapic_abi_intr_enable,
 496         .intr_setup     = ioapic_abi_intr_setup,
 497         .intr_teardown  = ioapic_abi_intr_teardown,
 498         .intr_config    = ioapic_abi_intr_config,
 499
 500         .finalize       = ioapic_abi_finalize,
 501         .cleanup        = ioapic_abi_cleanup,
 502         .setdefault     = ioapic_abi_setdefault,
 503         .stabilize      = ioapic_abi_stabilize,
 504         .initmap        = ioapic_abi_initmap
 505 };
 506
 507 static int      ioapic_abi_extint_irq = -1;
 508
 509 struct ioapic_irqinfo   ioapic_irqs[IOAPIC_HWI_VECTORS];
 510
 511 static void
 512 ioapic_abi_intr_enable(int irq)
 513 {
 514         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
 515                 kprintf("ioapic_abi_intr_enable invalid irq %d\n", irq);
 516                 return;
 517         }
 518         IOAPIC_INTREN(irq);
 519 }
 520
 521 static void
 522 ioapic_abi_intr_disable(int irq)
 523 {
 524         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
 525                 kprintf("ioapic_abi_intr_disable invalid irq %d\n", irq);
 526                 return;
 527         }
 528         IOAPIC_INTRDIS(irq);
 529 }
 530
 531 static void
 532 ioapic_abi_finalize(void)
 533 {
 534         KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
 535         KKASSERT(ioapic_enable);
 536
 537         /*
 538          * If an IMCR is present, program bit 0 to disconnect the 8259
 539          * from the BSP.
 540          */
 541         if (imcr_present) {
 542                 outb(0x22, 0x70);       /* select IMCR */
 543                 outb(0x23, 0x01);       /* disconnect 8259 */
 544         }
 545 }
 546
 547 /*
 548  * This routine is called after physical interrupts are enabled but before
 549  * the critical section is released.  We need to clean out any interrupts
 550  * that had already been posted to the cpu.
 551  */
 552 static void
 553 ioapic_abi_cleanup(void)
 554 {
 555         bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
 556 }
 557
 558 /* Must never be called */
 559 static void
 560 ioapic_abi_stabilize(void)
 561 {
 562         panic("ioapic_stabilize is called\n");
 563 }
 564
 565 static void
 566 ioapic_abi_intr_setup(int intr, int flags)
 567 {
 568         int vector, select;
 569         uint32_t value;
 570         register_t ef;
 571
 572         KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
 573             intr != IOAPIC_HWI_SYSCALL);
 574         KKASSERT(ioapic_irqs[intr].io_addr != NULL);
 575
 576         ef = read_rflags();
 577         cpu_disable_intr();
 578
 579         vector = IDT_OFFSET + intr;
 580         setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
 581
 582         /*
 583          * Now reprogram the vector in the IO APIC.  In order to avoid
 584          * losing an EOI for a level interrupt, which is vector based,
 585          * make sure that the IO APIC is programmed for edge-triggering
 586          * first, then reprogrammed with the new vector.  This should
 587          * clear the IRR bit.
 588          */
 589         imen_lock();
 590
 591         select = ioapic_irqs[intr].io_idx;
 592         value = ioapic_read(ioapic_irqs[intr].io_addr, select);
 593         value |= IOART_INTMSET;
 594
 595         ioapic_write(ioapic_irqs[intr].io_addr, select,
 596             (value & ~APIC_TRIGMOD_MASK));
 597         ioapic_write(ioapic_irqs[intr].io_addr, select,
 598             (value & ~IOART_INTVEC) | vector);
 599
 600         imen_unlock();
 601
 602         machintr_intr_enable(intr);
 603
 604         write_rflags(ef);
 605 }
 606
 607 static void
 608 ioapic_abi_intr_teardown(int intr)
 609 {
 610         int vector, select;
 611         uint32_t value;
 612         register_t ef;
 613
 614         KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
 615             intr != IOAPIC_HWI_SYSCALL);
 616         KKASSERT(ioapic_irqs[intr].io_addr != NULL);
 617
 618         ef = read_rflags();
 619         cpu_disable_intr();
 620
 621         /*
 622          * Teardown an interrupt vector.  The vector should already be
 623          * installed in the cpu's IDT, but make sure.
 624          */
 625         machintr_intr_disable(intr);
 626
 627         vector = IDT_OFFSET + intr;
 628         setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
 629
 630         /*
 631          * In order to avoid losing an EOI for a level interrupt, which
 632          * is vector based, make sure that the IO APIC is programmed for
 633          * edge-triggering first, then reprogrammed with the new vector.
 634          * This should clear the IRR bit.
 635          */
 636         imen_lock();
 637
 638         select = ioapic_irqs[intr].io_idx;
 639         value = ioapic_read(ioapic_irqs[intr].io_addr, select);
 640
 641         ioapic_write(ioapic_irqs[intr].io_addr, select,
 642             (value & ~APIC_TRIGMOD_MASK));
 643         ioapic_write(ioapic_irqs[intr].io_addr, select,
 644             (value & ~IOART_INTVEC) | vector);
 645
 646         imen_unlock();
 647
 648         write_rflags(ef);
 649 }
 650
 651 static void
 652 ioapic_abi_setdefault(void)
 653 {
 654         int intr;
 655
 656         for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
 657                 if (intr == IOAPIC_HWI_SYSCALL)
 658                         continue;
 659                 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYSIGT,
 660                        SEL_KPL, 0);
 661         }
 662 }
 663
 664 static void
 665 ioapic_abi_initmap(void)
 666 {
 667         int i;
 668
 669         for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
 670                 ioapic_irqmaps[i].im_gsi = -1;
 671         ioapic_irqmaps[IOAPIC_HWI_SYSCALL].im_type = IOAPIC_IMT_SYSCALL;
 672 }
 673
 674 void
 675 ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
 676     enum intr_polarity pola)
 677 {
 678         struct ioapic_irqinfo *info;
 679         struct ioapic_irqmap *map;
 680         void *ioaddr;
 681         int pin;
 682
 683         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 684         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 685
 686         KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
 687         map = &ioapic_irqmaps[irq];
 688
 689         KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
 690         map->im_type = IOAPIC_IMT_LINE;
 691
 692         map->im_gsi = gsi;
 693         map->im_trig = trig;
 694         map->im_pola = pola;
 695
 696         if (bootverbose) {
 697                 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
 698                         irq, map->im_gsi,
 699                         intr_str_trigger(map->im_trig),
 700                         intr_str_polarity(map->im_pola));
 701         }
 702
 703         pin = ioapic_gsi_pin(map->im_gsi);
 704         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 705
 706         info = &ioapic_irqs[irq];
 707
 708         imen_lock();
 709
 710         info->io_addr = ioaddr;
 711         info->io_idx = IOAPIC_REDTBL + (2 * pin);
 712         info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
 713         if (map->im_trig == INTR_TRIGGER_LEVEL)
 714                 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
 715
 716         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
 717             map->im_trig, map->im_pola);
 718
 719         imen_unlock();
 720 }
 721
 722 void
 723 ioapic_abi_fixup_irqmap(void)
 724 {
 725         int i;
 726
 727         for (i = 0; i < ISA_IRQ_CNT; ++i) {
 728                 struct ioapic_irqmap *map = &ioapic_irqmaps[i];
 729
 730                 if (map->im_type == IOAPIC_IMT_UNUSED) {
 731                         map->im_type = IOAPIC_IMT_RESERVED;
 732                         if (bootverbose)
 733                                 kprintf("IOAPIC: irq %d reserved\n", i);
 734                 }
 735         }
 736 }
 737
 738 int
 739 ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
 740 {
 741         int irq;
 742
 743         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 744         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 745
 746         for (irq = 0; irq < IOAPIC_HWI_VECTORS; ++irq) {
 747                 const struct ioapic_irqmap *map = &ioapic_irqmaps[irq];
 748
 749                 if (map->im_gsi == gsi) {
 750                         KKASSERT(map->im_type == IOAPIC_IMT_LINE);
 751
 752                         if (map->im_flags & IOAPIC_IMF_CONF) {
 753                                 if (map->im_trig != trig ||
 754                                     map->im_pola != pola)
 755                                         return -1;
 756                         }
 757                         return irq;
 758                 }
 759         }
 760         return -1;
 761 }
 762
 763 int
 764 ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
 765 {
 766         const struct ioapic_irqmap *map;
 767
 768         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 769         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 770
 771         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS)
 772                 return -1;
 773         map = &ioapic_irqmaps[irq];
 774
 775         if (map->im_type != IOAPIC_IMT_LINE)
 776                 return -1;
 777
 778         if (map->im_flags & IOAPIC_IMF_CONF) {
 779                 if (map->im_trig != trig || map->im_pola != pola)
 780                         return -1;
 781         }
 782         return irq;
 783 }
 784
 785 static void
 786 ioapic_abi_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
 787 {
 788         struct ioapic_irqinfo *info;
 789         struct ioapic_irqmap *map;
 790         void *ioaddr;
 791         int pin;
 792
 793         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 794         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 795
 796         KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
 797         map = &ioapic_irqmaps[irq];
 798
 799         KKASSERT(map->im_type == IOAPIC_IMT_LINE);
 800
 801 #ifdef notyet
 802         if (map->im_flags & IOAPIC_IMF_CONF) {
 803                 if (trig != map->im_trig) {
 804                         panic("ioapic_intr_config: trig %s -> %s\n",
 805                               intr_str_trigger(map->im_trig),
 806                               intr_str_trigger(trig));
 807                 }
 808                 if (pola != map->im_pola) {
 809                         panic("ioapic_intr_config: pola %s -> %s\n",
 810                               intr_str_polarity(map->im_pola),
 811                               intr_str_polarity(pola));
 812                 }
 813                 return;
 814         }
 815 #endif
 816         map->im_flags |= IOAPIC_IMF_CONF;
 817
 818         if (trig == map->im_trig && pola == map->im_pola)
 819                 return;
 820
 821         if (bootverbose) {
 822                 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
 823                         irq, map->im_gsi,
 824                         intr_str_trigger(map->im_trig),
 825                         intr_str_polarity(map->im_pola),
 826                         intr_str_trigger(trig),
 827                         intr_str_polarity(pola));
 828         }
 829         map->im_trig = trig;
 830         map->im_pola = pola;
 831
 832         pin = ioapic_gsi_pin(map->im_gsi);
 833         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 834
 835         info = &ioapic_irqs[irq];
 836
 837         imen_lock();
 838
 839         info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
 840         if (map->im_trig == INTR_TRIGGER_LEVEL)
 841                 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
 842
 843         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
 844             map->im_trig, map->im_pola);
 845
 846         imen_unlock();
 847 }
 848
 849 int
 850 ioapic_abi_extint_irqmap(int irq)
 851 {
 852         struct ioapic_irqinfo *info;
 853         struct ioapic_irqmap *map;
 854         void *ioaddr;
 855         int pin, error, vec;
 856
 857         vec = IDT_OFFSET + irq;
 858
 859         if (ioapic_abi_extint_irq == irq)
 860                 return 0;
 861         else if (ioapic_abi_extint_irq >= 0)
 862                 return EEXIST;
 863
 864         error = icu_ioapic_extint(irq, vec);
 865         if (error)
 866                 return error;
 867
 868         map = &ioapic_irqmaps[irq];
 869
 870         KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
 871                  map->im_type == IOAPIC_IMT_LINE);
 872         if (map->im_type == IOAPIC_IMT_LINE) {
 873                 if (map->im_flags & IOAPIC_IMF_CONF)
 874                         return EEXIST;
 875         }
 876         ioapic_abi_extint_irq = irq;
 877
 878         map->im_type = IOAPIC_IMT_LINE;
 879         map->im_trig = INTR_TRIGGER_EDGE;
 880         map->im_pola = INTR_POLARITY_HIGH;
 881         map->im_flags = IOAPIC_IMF_CONF;
 882
 883         map->im_gsi = ioapic_extpin_gsi();
 884         KKASSERT(map->im_gsi >= 0);
 885
 886         if (bootverbose) {
 887                 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
 888                         irq, map->im_gsi,
 889                         intr_str_trigger(map->im_trig),
 890                         intr_str_polarity(map->im_pola));
 891         }
 892
 893         pin = ioapic_gsi_pin(map->im_gsi);
 894         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 895
 896         info = &ioapic_irqs[irq];
 897
 898         imen_lock();
 899
 900         info->io_addr = ioaddr;
 901         info->io_idx = IOAPIC_REDTBL + (2 * pin);
 902         info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
 903
 904         ioapic_extpin_setup(ioaddr, pin, vec);
 905
 906         imen_unlock();
 907
 908         return 0;
 909 }