2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
21 #include "ah_internal.h"
23 #include "ar9300/ar9300.h"
24 #include "ar9300/ar9300reg.h"
25 #include "ar9300/ar9300phy.h"
26 #include "ar9300/ar9300desc.h"
28 #define TU_TO_USEC(_tu) ((_tu) << 10)
29 #define ONE_EIGHTH_TU_TO_USEC(_tu8) ((_tu8) << 7)
32 * Update Tx FIFO trigger level.
34 * Set b_inc_trig_level to TRUE to increase the trigger level.
35 * Set b_inc_trig_level to FALSE to decrease the trigger level.
37 * Returns TRUE if the trigger level was updated
40 ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level)
42 struct ath_hal_9300 *ahp = AH9300(ah);
43 u_int32_t txcfg, cur_level, new_level;
46 if (AH9300(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD &&
53 * Disable interrupts while futzing with the fifo level.
55 omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0);
57 txcfg = OS_REG_READ(ah, AR_TXCFG);
58 cur_level = MS(txcfg, AR_FTRIG);
59 new_level = cur_level;
61 if (b_inc_trig_level) { /* increase the trigger level */
62 if (cur_level < MAX_TX_FIFO_THRESHOLD) {
65 } else if (cur_level > MIN_TX_FIFO_THRESHOLD) {
69 if (new_level != cur_level) {
70 /* Update the trigger level */
72 AR_TXCFG, (txcfg &~ AR_FTRIG) | SM(new_level, AR_FTRIG));
75 /* re-enable chip interrupts */
76 ar9300_set_interrupts(ah, omask, 0);
78 AH9300(ah)->ah_tx_trig_level = new_level;
80 return (new_level != cur_level);
84 * Returns the value of Tx Trigger Level
87 ar9300_get_tx_trig_level(struct ath_hal *ah)
89 return (AH9300(ah)->ah_tx_trig_level);
93 * Set the properties of the tx queue with the parameters
97 ar9300_set_tx_queue_props(struct ath_hal *ah, int q, const HAL_TXQ_INFO *q_info)
99 struct ath_hal_9300 *ahp = AH9300(ah);
100 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
102 if (q >= p_cap->halTotalQueues) {
103 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
106 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], q_info);
110 * Return the properties for the specified tx queue.
113 ar9300_get_tx_queue_props(struct ath_hal *ah, int q, HAL_TXQ_INFO *q_info)
115 struct ath_hal_9300 *ahp = AH9300(ah);
116 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
119 if (q >= p_cap->halTotalQueues) {
120 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
123 return ath_hal_getTxQProps(ah, q_info, &ahp->ah_txq[q]);
127 AH_TX_QUEUE_MINUS_OFFSET_BEACON = 1,
128 AH_TX_QUEUE_MINUS_OFFSET_CAB = 2,
129 AH_TX_QUEUE_MINUS_OFFSET_UAPSD = 3,
130 AH_TX_QUEUE_MINUS_OFFSET_PAPRD = 4,
134 * Allocate and initialize a tx DCU/QCU combination.
137 ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type,
138 const HAL_TXQ_INFO *q_info)
140 struct ath_hal_9300 *ahp = AH9300(ah);
141 HAL_TX_QUEUE_INFO *qi;
142 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
145 /* XXX move queue assignment to driver */
147 case HAL_TX_QUEUE_BEACON:
148 /* highest priority */
149 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_BEACON;
151 case HAL_TX_QUEUE_CAB:
152 /* next highest priority */
153 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_CAB;
155 case HAL_TX_QUEUE_UAPSD:
156 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_UAPSD;
158 case HAL_TX_QUEUE_PAPRD:
159 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD;
161 case HAL_TX_QUEUE_DATA:
163 * don't infringe on top 4 queues, reserved for:
164 * beacon, CAB, UAPSD, PAPRD
167 q < p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD;
170 if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE) {
174 if (q == p_cap->halTotalQueues - 3) {
175 HALDEBUG(ah, HAL_DEBUG_QUEUE,
176 "%s: no available tx queue\n", __func__);
181 HALDEBUG(ah, HAL_DEBUG_QUEUE,
182 "%s: bad tx queue type %u\n", __func__, type);
186 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: queue %u\n", __func__, q);
188 qi = &ahp->ah_txq[q];
189 if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
190 HALDEBUG(ah, HAL_DEBUG_QUEUE,
191 "%s: tx queue %u already active\n", __func__, q);
195 OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
198 if (q_info == AH_NULL) {
199 /* by default enable OK+ERR+DESC+URN interrupts */
200 qi->tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
201 | HAL_TXQ_TXERRINT_ENABLE
202 | HAL_TXQ_TXDESCINT_ENABLE
203 | HAL_TXQ_TXURNINT_ENABLE;
204 qi->tqi_aifs = INIT_AIFS;
205 qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */
206 qi->tqi_cwmax = INIT_CWMAX;
207 qi->tqi_shretry = INIT_SH_RETRY;
208 qi->tqi_lgretry = INIT_LG_RETRY;
209 qi->tqi_physCompBuf = 0;
211 qi->tqi_physCompBuf = q_info->tqi_compBuf;
212 (void) ar9300_set_tx_queue_props(ah, q, q_info);
214 /* NB: must be followed by ar9300_reset_tx_queue */
219 * Update the h/w interrupt registers to reflect a tx q's configuration.
222 set_tx_q_interrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
224 struct ath_hal_9300 *ahp = AH9300(ah);
226 HALDEBUG(ah, HAL_DEBUG_INTERRUPT,
227 "%s: tx ok 0x%x err 0x%x eol 0x%x urn 0x%x\n",
229 ahp->ah_tx_ok_interrupt_mask,
230 ahp->ah_tx_err_interrupt_mask,
231 ahp->ah_tx_eol_interrupt_mask,
232 ahp->ah_tx_urn_interrupt_mask);
234 OS_REG_WRITE(ah, AR_IMR_S0,
235 SM(ahp->ah_tx_ok_interrupt_mask, AR_IMR_S0_QCU_TXOK));
236 OS_REG_WRITE(ah, AR_IMR_S1,
237 SM(ahp->ah_tx_err_interrupt_mask, AR_IMR_S1_QCU_TXERR)
238 | SM(ahp->ah_tx_eol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
240 AR_IMR_S2, AR_IMR_S2_QCU_TXURN, ahp->ah_tx_urn_interrupt_mask);
241 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2);
245 * Free a tx DCU/QCU combination.
248 ar9300_release_tx_queue(struct ath_hal *ah, u_int q)
250 struct ath_hal_9300 *ahp = AH9300(ah);
251 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
252 HAL_TX_QUEUE_INFO *qi;
254 if (q >= p_cap->halTotalQueues) {
255 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
259 qi = &ahp->ah_txq[q];
260 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
261 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q);
265 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: release queue %u\n", __func__, q);
267 qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
268 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q);
269 ahp->ah_tx_err_interrupt_mask &= ~(1 << q);
270 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q);
271 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q);
272 set_tx_q_interrupts(ah, qi);
278 * Set the retry, aifs, cwmin/max, ready_time regs for specified queue
280 * phw_channel has been set to point to the current channel
283 ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
285 struct ath_hal_9300 *ahp = AH9300(ah);
286 // struct ath_hal_private *ap = AH_PRIVATE(ah);
287 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
288 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
289 HAL_TX_QUEUE_INFO *qi;
290 u_int32_t cw_min, chan_cw_min, value;
292 if (q >= p_cap->halTotalQueues) {
293 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
297 qi = &ahp->ah_txq[q];
298 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
299 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q);
300 return AH_TRUE; /* XXX??? */
303 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: reset queue %u\n", __func__, q);
305 if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
307 * Select cwmin according to channel type.
308 * NB: chan can be NULL during attach
310 if (chan && IEEE80211_IS_CHAN_B(chan)) {
311 chan_cw_min = INIT_CWMIN_11B;
313 chan_cw_min = INIT_CWMIN;
315 /* make sure that the CWmin is of the form (2^n - 1) */
316 for (cw_min = 1; cw_min < chan_cw_min; cw_min = (cw_min << 1) | 1) {}
318 cw_min = qi->tqi_cwmin;
321 /* set cw_min/Max and AIFS values */
322 if (q > 3 || (!AH9300(ah)->ah_fccaifs))
323 /* values should not be overwritten if domain is FCC and manual rate
324 less than 24Mb is set, this check is making sure this */
326 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(cw_min, AR_D_LCL_IFS_CWMIN)
327 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
328 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
331 /* Set retry limit values */
332 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),
333 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
334 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
335 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
337 /* enable early termination on the QCU */
338 OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
340 /* enable DCU to wait for next fragment from QCU */
341 if (AR_SREV_WASP(ah) && (AH_PRIVATE((ah))->ah_macRev <= AR_SREV_REVISION_WASP_12)) {
342 /* WAR for EV#85395: Wasp Rx overrun issue - reduces Tx queue backoff
343 * threshold to 1 to avoid Rx overruns - Fixed in Wasp 1.3 */
344 OS_REG_WRITE(ah, AR_DMISC(q),
345 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
347 OS_REG_WRITE(ah, AR_DMISC(q),
348 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
351 /* multiqueue support */
352 if (qi->tqi_cbrPeriod) {
355 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
356 SM(qi->tqi_cbrOverflowLimit,
357 AR_Q_CBRCFG_OVF_THRESH));
358 OS_REG_WRITE(ah, AR_QMISC(q),
359 OS_REG_READ(ah, AR_QMISC(q)) |
361 (qi->tqi_cbrOverflowLimit ?
362 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
365 if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) {
366 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
367 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
371 OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
372 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
374 if (qi->tqi_burstTime &&
375 (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE))
377 OS_REG_WRITE(ah, AR_QMISC(q), OS_REG_READ(ah, AR_QMISC(q)) |
378 AR_Q_MISC_RDYTIME_EXP_POLICY);
381 if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE) {
382 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) |
383 AR_D_MISC_POST_FR_BKOFF_DIS);
386 if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE) {
387 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) |
388 AR_D_MISC_FRAG_BKOFF_EN);
391 switch (qi->tqi_type) {
392 case HAL_TX_QUEUE_BEACON: /* beacon frames */
393 OS_REG_WRITE(ah, AR_QMISC(q),
394 OS_REG_READ(ah, AR_QMISC(q))
395 | AR_Q_MISC_FSP_DBA_GATED
396 | AR_Q_MISC_BEACON_USE
397 | AR_Q_MISC_CBR_INCR_DIS1);
399 OS_REG_WRITE(ah, AR_DMISC(q),
400 OS_REG_READ(ah, AR_DMISC(q))
401 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
402 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
403 | AR_D_MISC_BEACON_USE
404 | AR_D_MISC_POST_FR_BKOFF_DIS);
405 /* XXX cwmin and cwmax should be 0 for beacon queue */
406 if (AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS) {
407 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
408 | SM(0, AR_D_LCL_IFS_CWMAX)
409 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
412 case HAL_TX_QUEUE_CAB: /* CAB frames */
414 * No longer Enable AR_Q_MISC_RDYTIME_EXP_POLICY,
415 * bug #6079. There is an issue with the CAB Queue
416 * not properly refreshing the Tx descriptor if
417 * the TXE clear setting is used.
419 OS_REG_WRITE(ah, AR_QMISC(q),
420 OS_REG_READ(ah, AR_QMISC(q))
421 | AR_Q_MISC_FSP_DBA_GATED
422 | AR_Q_MISC_CBR_INCR_DIS1
423 | AR_Q_MISC_CBR_INCR_DIS0);
425 value = TU_TO_USEC(qi->tqi_readyTime)
426 - (ah->ah_config.ah_sw_beacon_response_time
427 - ah->ah_config.ah_dma_beacon_response_time)
428 - ah->ah_config.ah_additional_swba_backoff;
429 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN);
431 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q))
432 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
433 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
435 case HAL_TX_QUEUE_PSPOLL:
437 * We may configure ps_poll QCU to be TIM-gated in the
438 * future; TIM_GATED bit is not enabled currently because
439 * of a hardware problem in Oahu that overshoots the TIM
440 * bitmap in beacon and may find matching associd bit in
441 * non-TIM elements and send PS-poll PS poll processing
442 * will be done in software
444 OS_REG_WRITE(ah, AR_QMISC(q),
445 OS_REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
447 case HAL_TX_QUEUE_UAPSD:
448 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q))
449 | AR_D_MISC_POST_FR_BKOFF_DIS);
451 default: /* NB: silence compiler */
455 #ifndef AH_DISABLE_WME
457 * Yes, this is a hack and not the right way to do it, but
458 * it does get the lockout bits and backoff set for the
459 * high-pri WME queues for testing. We need to either extend
460 * the meaning of queue_info->mode, or create something like
461 * queue_info->dcumode.
463 if (qi->tqi_intFlags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) {
464 OS_REG_WRITE(ah, AR_DMISC(q),
465 OS_REG_READ(ah, AR_DMISC(q)) |
466 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
467 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
468 AR_D_MISC_POST_FR_BKOFF_DIS);
472 OS_REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
475 * Always update the secondary interrupt mask registers - this
476 * could be a new queue getting enabled in a running system or
477 * hw getting re-initialized during a reset!
479 * Since we don't differentiate between tx interrupts corresponding
480 * to individual queues - secondary tx mask regs are always unmasked;
481 * tx interrupts are enabled/disabled for all queues collectively
482 * using the primary mask reg
484 if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE) {
485 ahp->ah_tx_ok_interrupt_mask |= (1 << q);
487 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q);
489 if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE) {
490 ahp->ah_tx_err_interrupt_mask |= (1 << q);
492 ahp->ah_tx_err_interrupt_mask &= ~(1 << q);
494 if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE) {
495 ahp->ah_tx_eol_interrupt_mask |= (1 << q);
497 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q);
499 if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE) {
500 ahp->ah_tx_urn_interrupt_mask |= (1 << q);
502 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q);
504 set_tx_q_interrupts(ah, qi);
510 * Get the TXDP for the specified queue
513 ar9300_get_tx_dp(struct ath_hal *ah, u_int q)
515 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
516 return OS_REG_READ(ah, AR_QTXDP(q));
520 * Set the tx_dp for the specified queue
523 ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp)
525 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
526 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
527 HALASSERT(txdp != 0);
529 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
535 * Transmit Enable is read-only now
538 ar9300_start_tx_dma(struct ath_hal *ah, u_int q)
544 * Return the number of pending frames or 0 if the specified
548 ar9300_num_tx_pending(struct ath_hal *ah, u_int q)
552 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
554 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
557 * Pending frame count (PFC) can momentarily go to zero
558 * while TXE remains asserted. In other words a PFC of
559 * zero is not sufficient to say that the queue has stopped.
561 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) {
562 npend = 1; /* arbitrarily return 1 */
566 if (npend && (AH9300(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
567 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
568 HALDEBUG(ah, HAL_DEBUG_QUEUE, "RTSD on CAB queue\n");
569 /* Clear the ready_time shutdown status bits */
570 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
574 HALASSERT((npend == 0) ||
575 (AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE));
581 * Stop transmit on the specified queue
584 ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout)
587 * Directly call abort. It is better, hardware-wise, to stop all
588 * queues at once than individual ones.
590 return ar9300_abort_tx_dma(ah);
593 #define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */
594 #define AH_TIME_QUANTUM 100 /* usec */
597 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
599 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
602 timeout = AH_TX_STOP_DMA_TIMEOUT;
605 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
607 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) {
608 if (ar9300_num_tx_pending(ah, q) == 0) {
611 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */
616 HALDEBUG(ah, HAL_DEBUG_QUEUE,
617 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q);
618 HALDEBUG(ah, HAL_DEBUG_QUEUE,
619 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n",
621 OS_REG_READ(ah, AR_QSTS(q)),
622 OS_REG_READ(ah, AR_Q_TXE),
623 OS_REG_READ(ah, AR_Q_TXD),
624 OS_REG_READ(ah, AR_QCBRCFG(q)));
625 HALDEBUG(ah, HAL_DEBUG_QUEUE,
626 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
628 OS_REG_READ(ah, AR_QMISC(q)),
629 OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
630 OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
632 #endif /* AH_DEBUG */
634 /* 2413+ and up can kill packets at the PCU level */
635 if (ar9300_num_tx_pending(ah, q)) {
636 u_int32_t tsf_low, j;
638 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n",
639 __func__, ar9300_num_tx_pending(ah, q), q);
641 /* Kill last PCU Tx Frame */
642 /* TODO - save off and restore current values of Q1/Q2? */
643 for (j = 0; j < 2; j++) {
644 tsf_low = OS_REG_READ(ah, AR_TSF_L32);
645 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
646 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
647 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10);
648 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
650 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) {
654 HALDEBUG(ah, HAL_DEBUG_QUEUE,
655 "%s: TSF have moved while trying to set "
656 "quiet time TSF: 0x%08x\n",
658 /* TSF shouldn't count twice or reg access is taking forever */
662 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
664 /* Allow the quiet mechanism to do its work */
666 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
668 /* Verify all transmit is dead */
669 wait = timeout / AH_TIME_QUANTUM;
670 while (ar9300_num_tx_pending(ah, q)) {
672 HALDEBUG(ah, HAL_DEBUG_TX,
673 "%s: Failed to stop Tx DMA in %d msec "
674 "after killing last frame\n",
675 __func__, timeout / 1000);
678 OS_DELAY(AH_TIME_QUANTUM);
681 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
684 OS_REG_WRITE(ah, AR_Q_TXD, 0);
687 #undef AH_TX_STOP_DMA_TIMEOUT
688 #undef AH_TIME_QUANTUM
693 * Really Stop transmit on the specified queue
696 ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout)
698 #define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */
699 #define AH_TIME_QUANTUM 100 /* usec */
702 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
704 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
707 timeout = AH_TX_STOP_DMA_TIMEOUT;
710 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
712 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) {
713 if (ar9300_num_tx_pending(ah, q) == 0) {
716 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */
721 HALDEBUG(ah, HAL_DEBUG_QUEUE,
722 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q);
723 HALDEBUG(ah, HAL_DEBUG_QUEUE,
724 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n",
726 OS_REG_READ(ah, AR_QSTS(q)),
727 OS_REG_READ(ah, AR_Q_TXE),
728 OS_REG_READ(ah, AR_Q_TXD),
729 OS_REG_READ(ah, AR_QCBRCFG(q)));
730 HALDEBUG(ah, HAL_DEBUG_QUEUE,
731 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
733 OS_REG_READ(ah, AR_QMISC(q)),
734 OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
735 OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
737 #endif /* AH_DEBUG */
739 /* 2413+ and up can kill packets at the PCU level */
740 if (ar9300_num_tx_pending(ah, q)) {
741 u_int32_t tsf_low, j;
743 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n",
744 __func__, ar9300_num_tx_pending(ah, q), q);
746 /* Kill last PCU Tx Frame */
747 /* TODO - save off and restore current values of Q1/Q2? */
748 for (j = 0; j < 2; j++) {
749 tsf_low = OS_REG_READ(ah, AR_TSF_L32);
750 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
751 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
752 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10);
753 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
755 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) {
759 HALDEBUG(ah, HAL_DEBUG_QUEUE,
760 "%s: TSF have moved while trying to set "
761 "quiet time TSF: 0x%08x\n",
763 /* TSF shouldn't count twice or reg access is taking forever */
767 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
769 /* Allow the quiet mechanism to do its work */
771 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
773 /* Verify all transmit is dead */
774 wait = timeout / AH_TIME_QUANTUM;
775 while (ar9300_num_tx_pending(ah, q)) {
777 HALDEBUG(ah, HAL_DEBUG_TX,
778 "%s: Failed to stop Tx DMA in %d msec "
779 "after killing last frame\n",
780 __func__, timeout / 1000);
783 OS_DELAY(AH_TIME_QUANTUM);
786 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
789 OS_REG_WRITE(ah, AR_Q_TXD, 0);
792 #undef AH_TX_STOP_DMA_TIMEOUT
793 #undef AH_TIME_QUANTUM
797 * Abort transmit on all queues
799 #define AR9300_ABORT_LOOPS 1000
800 #define AR9300_ABORT_WAIT 5
802 ar9300_abort_tx_dma(struct ath_hal *ah)
807 * set txd on all queues
809 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
812 * set tx abort bits (also disable rx)
814 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
815 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
816 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR));
817 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
819 /* Let TXE (all queues) clear before waiting on any pending frames */
820 for (i = 0; i < AR9300_ABORT_LOOPS; i++) {
821 if (OS_REG_READ(ah, AR_Q_TXE) == 0) {
824 OS_DELAY(AR9300_ABORT_WAIT);
826 if (i == AR9300_ABORT_LOOPS) {
827 HALDEBUG(ah, HAL_DEBUG_TX, "%s[%d] reached max wait on TXE\n",
832 * wait on all tx queues
834 for (q = 0; q < AR_NUM_QCU; q++) {
835 for (i = 0; i < AR9300_ABORT_LOOPS; i++) {
836 if (!ar9300_num_tx_pending(ah, q)) {
839 OS_DELAY(AR9300_ABORT_WAIT);
841 if (i == AR9300_ABORT_LOOPS) {
842 HALDEBUG(ah, HAL_DEBUG_TX,
843 "%s[%d] reached max wait on pending tx, q %d\n",
844 __func__, __LINE__, q);
850 * clear tx abort bits
852 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
853 OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
854 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR));
855 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
860 OS_REG_WRITE(ah, AR_Q_TXD, 0);
866 * Determine which tx queues need interrupt servicing.
869 ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *txqs)
871 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
872 "ar9300_get_tx_intr_queue: Should not be called\n");
874 struct ath_hal_9300 *ahp = AH9300(ah);
875 *txqs &= ahp->ah_intr_txqs;
876 ahp->ah_intr_txqs &= ~(*txqs);
881 ar9300_reset_tx_status_ring(struct ath_hal *ah)
883 struct ath_hal_9300 *ahp = AH9300(ah);
887 /* Zero out the status descriptors */
888 OS_MEMZERO((void *)ahp->ts_ring, ahp->ts_size * sizeof(struct ar9300_txs));
889 HALDEBUG(ah, HAL_DEBUG_QUEUE,
890 "%s: TS Start 0x%x End 0x%x Virt %p, Size %d\n", __func__,
891 ahp->ts_paddr_start, ahp->ts_paddr_end, ahp->ts_ring, ahp->ts_size);
893 OS_REG_WRITE(ah, AR_Q_STATUS_RING_START, ahp->ts_paddr_start);
894 OS_REG_WRITE(ah, AR_Q_STATUS_RING_END, ahp->ts_paddr_end);
898 ar9300_setup_tx_status_ring(struct ath_hal *ah, void *ts_start,
899 u_int32_t ts_paddr_start, u_int16_t size)
901 struct ath_hal_9300 *ahp = AH9300(ah);
903 ahp->ts_paddr_start = ts_paddr_start;
904 ahp->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9300_txs));
906 ahp->ts_ring = (struct ar9300_txs *)ts_start;
908 ar9300_reset_tx_status_ring(ah);