sys/dev/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_3_0_d.h"
  33 #include "oss/oss_3_0_sh_mask.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "tonga_sdma_pkt_open.h"
  46
  47 #include "ivsrcid/ivsrcid_vislands30.h"
  48
  49 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  50 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  51 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  52 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  53
  54 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
  56 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
  57 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
  58 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
  59 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
  60 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
  61 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
  65 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
  66 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
  67 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin");
  68 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin");
  69
  70
  71 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  72 {
  73         SDMA0_REGISTER_OFFSET,
  74         SDMA1_REGISTER_OFFSET
  75 };
  76
  77 static const u32 golden_settings_tonga_a11[] =
  78 {
  79         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  80         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  81         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  82         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  83         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  84         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  85         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  86         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  87         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  88         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  89 };
  90
  91 static const u32 tonga_mgcg_cgcg_init[] =
  92 {
  93         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  94         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  95 };
  96
  97 static const u32 golden_settings_fiji_a10[] =
  98 {
  99         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 100         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 101         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 102         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 103         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 104         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 105         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 106         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 107 };
 108
 109 static const u32 fiji_mgcg_cgcg_init[] =
 110 {
 111         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 112         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 113 };
 114
 115 static const u32 golden_settings_polaris11_a11[] =
 116 {
 117         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 118         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 119         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 120         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 121         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 122         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 123         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 124         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 125         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 126         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 127 };
 128
 129 static const u32 golden_settings_polaris10_a11[] =
 130 {
 131         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 132         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 133         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 134         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 135         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 136         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 137         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 138         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 139         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 140         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 141 };
 142
 143 static const u32 cz_golden_settings_a11[] =
 144 {
 145         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 146         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 147         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 148         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 149         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 150         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 151         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 152         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 153         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
 154         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
 155         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 156         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 157 };
 158
 159 static const u32 cz_mgcg_cgcg_init[] =
 160 {
 161         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 162         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 163 };
 164
 165 static const u32 stoney_golden_settings_a11[] =
 166 {
 167         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 168         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 169         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 170         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 171 };
 172
 173 static const u32 stoney_mgcg_cgcg_init[] =
 174 {
 175         mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
 176 };
 177
 178 /*
 179  * sDMA - System DMA
 180  * Starting with CIK, the GPU has new asynchronous
 181  * DMA engines.  These engines are used for compute
 182  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 183  * and each one supports 1 ring buffer used for gfx
 184  * and 2 queues used for compute.
 185  *
 186  * The programming model is very similar to the CP
 187  * (ring buffer, IBs, etc.), but sDMA has it's own
 188  * packet format that is different from the PM4 format
 189  * used by the CP. sDMA supports copying data, writing
 190  * embedded data, solid fills, and a number of other
 191  * things.  It also has support for tiling/detiling of
 192  * buffers.
 193  */
 194
 195 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 196 {
 197         switch (adev->asic_type) {
 198         case CHIP_FIJI:
 199                 amdgpu_device_program_register_sequence(adev,
 200                                                         fiji_mgcg_cgcg_init,
 201                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 202                 amdgpu_device_program_register_sequence(adev,
 203                                                         golden_settings_fiji_a10,
 204                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 205                 break;
 206         case CHIP_TONGA:
 207                 amdgpu_device_program_register_sequence(adev,
 208                                                         tonga_mgcg_cgcg_init,
 209                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 210                 amdgpu_device_program_register_sequence(adev,
 211                                                         golden_settings_tonga_a11,
 212                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 213                 break;
 214         case CHIP_POLARIS11:
 215         case CHIP_POLARIS12:
 216         case CHIP_VEGAM:
 217                 amdgpu_device_program_register_sequence(adev,
 218                                                         golden_settings_polaris11_a11,
 219                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 220                 break;
 221         case CHIP_POLARIS10:
 222                 amdgpu_device_program_register_sequence(adev,
 223                                                         golden_settings_polaris10_a11,
 224                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 225                 break;
 226         case CHIP_CARRIZO:
 227                 amdgpu_device_program_register_sequence(adev,
 228                                                         cz_mgcg_cgcg_init,
 229                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 230                 amdgpu_device_program_register_sequence(adev,
 231                                                         cz_golden_settings_a11,
 232                                                         ARRAY_SIZE(cz_golden_settings_a11));
 233                 break;
 234         case CHIP_STONEY:
 235                 amdgpu_device_program_register_sequence(adev,
 236                                                         stoney_mgcg_cgcg_init,
 237                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 238                 amdgpu_device_program_register_sequence(adev,
 239                                                         stoney_golden_settings_a11,
 240                                                         ARRAY_SIZE(stoney_golden_settings_a11));
 241                 break;
 242         default:
 243                 break;
 244         }
 245 }
 246
 247 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
 248 {
 249         int i;
 250         for (i = 0; i < adev->sdma.num_instances; i++) {
 251                 release_firmware(adev->sdma.instance[i].fw);
 252                 adev->sdma.instance[i].fw = NULL;
 253         }
 254 }
 255
 256 /**
 257  * sdma_v3_0_init_microcode - load ucode images from disk
 258  *
 259  * @adev: amdgpu_device pointer
 260  *
 261  * Use the firmware interface to load the ucode images into
 262  * the driver (not loaded into hw).
 263  * Returns 0 on success, error on failure.
 264  */
 265 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 266 {
 267         const char *chip_name;
 268         char fw_name[30];
 269         int err = 0, i;
 270         struct amdgpu_firmware_info *info = NULL;
 271         const struct common_firmware_header *header = NULL;
 272         const struct sdma_firmware_header_v1_0 *hdr;
 273
 274         DRM_DEBUG("\n");
 275
 276         switch (adev->asic_type) {
 277         case CHIP_TONGA:
 278                 chip_name = "tonga";
 279                 break;
 280         case CHIP_FIJI:
 281                 chip_name = "fiji";
 282                 break;
 283         case CHIP_POLARIS10:
 284                 chip_name = "polaris10";
 285                 break;
 286         case CHIP_POLARIS11:
 287                 chip_name = "polaris11";
 288                 break;
 289         case CHIP_POLARIS12:
 290                 chip_name = "polaris12";
 291                 break;
 292         case CHIP_VEGAM:
 293                 chip_name = "vegam";
 294                 break;
 295         case CHIP_CARRIZO:
 296                 chip_name = "carrizo";
 297                 break;
 298         case CHIP_STONEY:
 299                 chip_name = "stoney";
 300                 break;
 301         default: BUG();
 302         }
 303
 304         for (i = 0; i < adev->sdma.num_instances; i++) {
 305                 if (i == 0)
 306                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 307                 else
 308                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 309                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 310                 if (err)
 311                         goto out;
 312                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 313                 if (err)
 314                         goto out;
 315                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 316                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 317                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 318                 if (adev->sdma.instance[i].feature_version >= 20)
 319                         adev->sdma.instance[i].burst_nop = true;
 320
 321                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
 322                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 323                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 324                         info->fw = adev->sdma.instance[i].fw;
 325                         header = (const struct common_firmware_header *)info->fw->data;
 326                         adev->firmware.fw_size +=
 327                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 328                 }
 329         }
 330 out:
 331         if (err) {
 332                 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);
 333                 for (i = 0; i < adev->sdma.num_instances; i++) {
 334                         release_firmware(adev->sdma.instance[i].fw);
 335                         adev->sdma.instance[i].fw = NULL;
 336                 }
 337         }
 338         return err;
 339 }
 340
 341 /**
 342  * sdma_v3_0_ring_get_rptr - get the current read pointer
 343  *
 344  * @ring: amdgpu ring pointer
 345  *
 346  * Get the current rptr from the hardware (VI+).
 347  */
 348 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 349 {
 350         /* XXX check if swapping is necessary on BE */
 351         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 352 }
 353
 354 /**
 355  * sdma_v3_0_ring_get_wptr - get the current write pointer
 356  *
 357  * @ring: amdgpu ring pointer
 358  *
 359  * Get the current wptr from the hardware (VI+).
 360  */
 361 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 362 {
 363         struct amdgpu_device *adev = ring->adev;
 364         u32 wptr;
 365
 366         if (ring->use_doorbell || ring->use_pollmem) {
 367                 /* XXX check if swapping is necessary on BE */
 368                 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
 369         } else {
 370                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
 371         }
 372
 373         return wptr;
 374 }
 375
 376 /**
 377  * sdma_v3_0_ring_set_wptr - commit the write pointer
 378  *
 379  * @ring: amdgpu ring pointer
 380  *
 381  * Write the wptr back to the hardware (VI+).
 382  */
 383 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 384 {
 385         struct amdgpu_device *adev = ring->adev;
 386
 387         if (ring->use_doorbell) {
 388                 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
 389                 /* XXX check if swapping is necessary on BE */
 390                 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
 391                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
 392         } else if (ring->use_pollmem) {
 393                 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
 394
 395                 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
 396         } else {
 397                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
 398         }
 399 }
 400
 401 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 402 {
 403         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 404         int i;
 405
 406         for (i = 0; i < count; i++)
 407                 if (sdma && sdma->burst_nop && (i == 0))
 408                         amdgpu_ring_write(ring, ring->funcs->nop |
 409                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 410                 else
 411                         amdgpu_ring_write(ring, ring->funcs->nop);
 412 }
 413
 414 /**
 415  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 416  *
 417  * @ring: amdgpu ring pointer
 418  * @ib: IB object to schedule
 419  *
 420  * Schedule an IB in the DMA ring (VI).
 421  */
 422 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 423                                    struct amdgpu_ib *ib,
 424                                    unsigned vmid, bool ctx_switch)
 425 {
 426         /* IB packet must end on a 8 DW boundary */
 427         sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 428
 429         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 430                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 431         /* base must be 32 byte aligned */
 432         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 433         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 434         amdgpu_ring_write(ring, ib->length_dw);
 435         amdgpu_ring_write(ring, 0);
 436         amdgpu_ring_write(ring, 0);
 437
 438 }
 439
 440 /**
 441  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 442  *
 443  * @ring: amdgpu ring pointer
 444  *
 445  * Emit an hdp flush packet on the requested DMA ring.
 446  */
 447 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 448 {
 449         u32 ref_and_mask = 0;
 450
 451         if (ring->me == 0)
 452                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 453         else
 454                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 455
 456         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 457                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 458                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 459         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 460         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 461         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 462         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 463         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 464                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 465 }
 466
 467 /**
 468  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 469  *
 470  * @ring: amdgpu ring pointer
 471  * @fence: amdgpu fence object
 472  *
 473  * Add a DMA fence packet to the ring to write
 474  * the fence seq number and DMA trap packet to generate
 475  * an interrupt if needed (VI).
 476  */
 477 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 478                                       unsigned flags)
 479 {
 480         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 481         /* write the fence */
 482         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 483         amdgpu_ring_write(ring, lower_32_bits(addr));
 484         amdgpu_ring_write(ring, upper_32_bits(addr));
 485         amdgpu_ring_write(ring, lower_32_bits(seq));
 486
 487         /* optionally write high bits as well */
 488         if (write64bit) {
 489                 addr += 4;
 490                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 491                 amdgpu_ring_write(ring, lower_32_bits(addr));
 492                 amdgpu_ring_write(ring, upper_32_bits(addr));
 493                 amdgpu_ring_write(ring, upper_32_bits(seq));
 494         }
 495
 496         /* generate an interrupt */
 497         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 498         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 499 }
 500
 501 /**
 502  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 503  *
 504  * @adev: amdgpu_device pointer
 505  *
 506  * Stop the gfx async dma ring buffers (VI).
 507  */
 508 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 509 {
 510         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 511         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 512         u32 rb_cntl, ib_cntl;
 513         int i;
 514
 515         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 516             (adev->mman.buffer_funcs_ring == sdma1))
 517                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 518
 519         for (i = 0; i < adev->sdma.num_instances; i++) {
 520                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 521                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 522                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 523                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 524                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 525                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 526         }
 527         sdma0->ready = false;
 528         sdma1->ready = false;
 529 }
 530
 531 /**
 532  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 533  *
 534  * @adev: amdgpu_device pointer
 535  *
 536  * Stop the compute async dma queues (VI).
 537  */
 538 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 539 {
 540         /* XXX todo */
 541 }
 542
 543 /**
 544  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
 545  *
 546  * @adev: amdgpu_device pointer
 547  * @enable: enable/disable the DMA MEs context switch.
 548  *
 549  * Halt or unhalt the async dma engines context switch (VI).
 550  */
 551 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 552 {
 553         u32 f32_cntl, phase_quantum = 0;
 554         int i;
 555
 556         if (amdgpu_sdma_phase_quantum) {
 557                 unsigned value = amdgpu_sdma_phase_quantum;
 558                 unsigned unit = 0;
 559
 560                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 561                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 562                         value = (value + 1) >> 1;
 563                         unit++;
 564                 }
 565                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 566                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 567                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 568                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 569                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 570                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 571                         WARN_ONCE(1,
 572                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 573                                   value << unit);
 574                 }
 575                 phase_quantum =
 576                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 577                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 578         }
 579
 580         for (i = 0; i < adev->sdma.num_instances; i++) {
 581                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 582                 if (enable) {
 583                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 584                                         AUTO_CTXSW_ENABLE, 1);
 585                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 586                                         ATC_L1_ENABLE, 1);
 587                         if (amdgpu_sdma_phase_quantum) {
 588                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 589                                        phase_quantum);
 590                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 591                                        phase_quantum);
 592                         }
 593                 } else {
 594                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 595                                         AUTO_CTXSW_ENABLE, 0);
 596                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 597                                         ATC_L1_ENABLE, 1);
 598                 }
 599
 600                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 601         }
 602 }
 603
 604 /**
 605  * sdma_v3_0_enable - stop the async dma engines
 606  *
 607  * @adev: amdgpu_device pointer
 608  * @enable: enable/disable the DMA MEs.
 609  *
 610  * Halt or unhalt the async dma engines (VI).
 611  */
 612 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 613 {
 614         u32 f32_cntl;
 615         int i;
 616
 617         if (!enable) {
 618                 sdma_v3_0_gfx_stop(adev);
 619                 sdma_v3_0_rlc_stop(adev);
 620         }
 621
 622         for (i = 0; i < adev->sdma.num_instances; i++) {
 623                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 624                 if (enable)
 625                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 626                 else
 627                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 628                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 629         }
 630 }
 631
 632 /**
 633  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 634  *
 635  * @adev: amdgpu_device pointer
 636  *
 637  * Set up the gfx DMA ring buffers and enable them (VI).
 638  * Returns 0 for success, error for failure.
 639  */
 640 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 641 {
 642         struct amdgpu_ring *ring;
 643         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 644         u32 rb_bufsz;
 645         u32 wb_offset;
 646         u32 doorbell;
 647         u64 wptr_gpu_addr;
 648         int i, j, r;
 649
 650         for (i = 0; i < adev->sdma.num_instances; i++) {
 651                 ring = &adev->sdma.instance[i].ring;
 652                 amdgpu_ring_clear_ring(ring);
 653                 wb_offset = (ring->rptr_offs * 4);
 654
 655                 mutex_lock(&adev->srbm_mutex);
 656                 for (j = 0; j < 16; j++) {
 657                         vi_srbm_select(adev, 0, 0, 0, j);
 658                         /* SDMA GFX */
 659                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 660                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 661                 }
 662                 vi_srbm_select(adev, 0, 0, 0, 0);
 663                 mutex_unlock(&adev->srbm_mutex);
 664
 665                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 666                        adev->gfx.config.gb_addr_config & 0x70);
 667
 668                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 669
 670                 /* Set ring buffer size in dwords */
 671                 rb_bufsz = order_base_2(ring->ring_size / 4);
 672                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 673                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 674 #ifdef __BIG_ENDIAN
 675                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 676                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 677                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 678 #endif
 679                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 680
 681                 /* Initialize the ring buffer's read and write pointers */
 682                 ring->wptr = 0;
 683                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 684                 sdma_v3_0_ring_set_wptr(ring);
 685                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 686                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 687
 688                 /* set the wb address whether it's enabled or not */
 689                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 690                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 691                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 692                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 693
 694                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 695
 696                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 697                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 698
 699                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 700
 701                 if (ring->use_doorbell) {
 702                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 703                                                  OFFSET, ring->doorbell_index);
 704                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 705                 } else {
 706                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 707                 }
 708                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 709
 710                 /* setup the wptr shadow polling */
 711                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 712
 713                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
 714                        lower_32_bits(wptr_gpu_addr));
 715                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
 716                        upper_32_bits(wptr_gpu_addr));
 717                 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
 718                 if (ring->use_pollmem) {
 719                         /*wptr polling is not enogh fast, directly clean the wptr register */
 720                         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 721                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 722                                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
 723                                                        ENABLE, 1);
 724                 } else {
 725                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 726                                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
 727                                                        ENABLE, 0);
 728                 }
 729                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
 730
 731                 /* enable DMA RB */
 732                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 733                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 734
 735                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 736                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 737 #ifdef __BIG_ENDIAN
 738                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 739 #endif
 740                 /* enable DMA IBs */
 741                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 742
 743                 ring->ready = true;
 744         }
 745
 746         /* unhalt the MEs */
 747         sdma_v3_0_enable(adev, true);
 748         /* enable sdma ring preemption */
 749         sdma_v3_0_ctx_switch_enable(adev, true);
 750
 751         for (i = 0; i < adev->sdma.num_instances; i++) {
 752                 ring = &adev->sdma.instance[i].ring;
 753                 r = amdgpu_ring_test_ring(ring);
 754                 if (r) {
 755                         ring->ready = false;
 756                         return r;
 757                 }
 758
 759                 if (adev->mman.buffer_funcs_ring == ring)
 760                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 761         }
 762
 763         return 0;
 764 }
 765
 766 /**
 767  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 768  *
 769  * @adev: amdgpu_device pointer
 770  *
 771  * Set up the compute DMA queues and enable them (VI).
 772  * Returns 0 for success, error for failure.
 773  */
 774 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 775 {
 776         /* XXX todo */
 777         return 0;
 778 }
 779
 780 /**
 781  * sdma_v3_0_load_microcode - load the sDMA ME ucode
 782  *
 783  * @adev: amdgpu_device pointer
 784  *
 785  * Loads the sDMA0/1 ucode.
 786  * Returns 0 for success, -EINVAL if the ucode is not available.
 787  */
 788 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
 789 {
 790         const struct sdma_firmware_header_v1_0 *hdr;
 791         const __le32 *fw_data;
 792         u32 fw_size;
 793         int i, j;
 794
 795         /* halt the MEs */
 796         sdma_v3_0_enable(adev, false);
 797
 798         for (i = 0; i < adev->sdma.num_instances; i++) {
 799                 if (!adev->sdma.instance[i].fw)
 800                         return -EINVAL;
 801                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 802                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 803                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 804                 fw_data = (const __le32 *)
 805                         (adev->sdma.instance[i].fw->data +
 806                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 807                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 808                 for (j = 0; j < fw_size; j++)
 809                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 810                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 811         }
 812
 813         return 0;
 814 }
 815
 816 /**
 817  * sdma_v3_0_start - setup and start the async dma engines
 818  *
 819  * @adev: amdgpu_device pointer
 820  *
 821  * Set up the DMA engines and enable them (VI).
 822  * Returns 0 for success, error for failure.
 823  */
 824 static int sdma_v3_0_start(struct amdgpu_device *adev)
 825 {
 826         int r;
 827
 828         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 829                 r = sdma_v3_0_load_microcode(adev);
 830                 if (r)
 831                         return r;
 832         }
 833
 834         /* disable sdma engine before programing it */
 835         sdma_v3_0_ctx_switch_enable(adev, false);
 836         sdma_v3_0_enable(adev, false);
 837
 838         /* start the gfx rings and rlc compute queues */
 839         r = sdma_v3_0_gfx_resume(adev);
 840         if (r)
 841                 return r;
 842         r = sdma_v3_0_rlc_resume(adev);
 843         if (r)
 844                 return r;
 845
 846         return 0;
 847 }
 848
 849 /**
 850  * sdma_v3_0_ring_test_ring - simple async dma engine test
 851  *
 852  * @ring: amdgpu_ring structure holding ring information
 853  *
 854  * Test the DMA engine by writing using it to write an
 855  * value to memory. (VI).
 856  * Returns 0 for success, error for failure.
 857  */
 858 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 859 {
 860         struct amdgpu_device *adev = ring->adev;
 861         unsigned i;
 862         unsigned index;
 863         int r;
 864         u32 tmp;
 865         u64 gpu_addr;
 866
 867         r = amdgpu_device_wb_get(adev, &index);
 868         if (r) {
 869                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 870                 return r;
 871         }
 872
 873         gpu_addr = adev->wb.gpu_addr + (index * 4);
 874         tmp = 0xCAFEDEAD;
 875         adev->wb.wb[index] = cpu_to_le32(tmp);
 876
 877         r = amdgpu_ring_alloc(ring, 5);
 878         if (r) {
 879                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 880                 amdgpu_device_wb_free(adev, index);
 881                 return r;
 882         }
 883
 884         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 885                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 886         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 887         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 888         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 889         amdgpu_ring_write(ring, 0xDEADBEEF);
 890         amdgpu_ring_commit(ring);
 891
 892         for (i = 0; i < adev->usec_timeout; i++) {
 893                 tmp = le32_to_cpu(adev->wb.wb[index]);
 894                 if (tmp == 0xDEADBEEF)
 895                         break;
 896                 DRM_UDELAY(1);
 897         }
 898
 899         if (i < adev->usec_timeout) {
 900                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 901         } else {
 902                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 903                           ring->idx, tmp);
 904                 r = -EINVAL;
 905         }
 906         amdgpu_device_wb_free(adev, index);
 907
 908         return r;
 909 }
 910
 911 /**
 912  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 913  *
 914  * @ring: amdgpu_ring structure holding ring information
 915  *
 916  * Test a simple IB in the DMA ring (VI).
 917  * Returns 0 on success, error on failure.
 918  */
 919 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 920 {
 921         struct amdgpu_device *adev = ring->adev;
 922         struct amdgpu_ib ib;
 923         struct dma_fence *f = NULL;
 924         unsigned index;
 925         u32 tmp = 0;
 926         u64 gpu_addr;
 927         long r;
 928
 929         r = amdgpu_device_wb_get(adev, &index);
 930         if (r) {
 931                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 932                 return r;
 933         }
 934
 935         gpu_addr = adev->wb.gpu_addr + (index * 4);
 936         tmp = 0xCAFEDEAD;
 937         adev->wb.wb[index] = cpu_to_le32(tmp);
 938         memset(&ib, 0, sizeof(ib));
 939         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 940         if (r) {
 941                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 942                 goto err0;
 943         }
 944
 945         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 946                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 947         ib.ptr[1] = lower_32_bits(gpu_addr);
 948         ib.ptr[2] = upper_32_bits(gpu_addr);
 949         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 950         ib.ptr[4] = 0xDEADBEEF;
 951         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 952         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 953         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 954         ib.length_dw = 8;
 955
 956         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 957         if (r)
 958                 goto err1;
 959
 960         r = dma_fence_wait_timeout(f, false, timeout);
 961         if (r == 0) {
 962                 DRM_ERROR("amdgpu: IB test timed out\n");
 963                 r = -ETIMEDOUT;
 964                 goto err1;
 965         } else if (r < 0) {
 966                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 967                 goto err1;
 968         }
 969         tmp = le32_to_cpu(adev->wb.wb[index]);
 970         if (tmp == 0xDEADBEEF) {
 971                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 972                 r = 0;
 973         } else {
 974                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 975                 r = -EINVAL;
 976         }
 977 err1:
 978         amdgpu_ib_free(adev, &ib, NULL);
 979         dma_fence_put(f);
 980 err0:
 981         amdgpu_device_wb_free(adev, index);
 982         return r;
 983 }
 984
 985 /**
 986  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 987  *
 988  * @ib: indirect buffer to fill with commands
 989  * @pe: addr of the page entry
 990  * @src: src addr to copy from
 991  * @count: number of page entries to update
 992  *
 993  * Update PTEs by copying them from the GART using sDMA (CIK).
 994  */
 995 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 996                                   uint64_t pe, uint64_t src,
 997                                   unsigned count)
 998 {
 999         unsigned bytes = count * 8;
1000
1001         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1002                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1003         ib->ptr[ib->length_dw++] = bytes;
1004         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1005         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1006         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1007         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1008         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1009 }
1010
1011 /**
1012  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
1013  *
1014  * @ib: indirect buffer to fill with commands
1015  * @pe: addr of the page entry
1016  * @value: dst addr to write into pe
1017  * @count: number of page entries to update
1018  * @incr: increase next addr by incr bytes
1019  *
1020  * Update PTEs by writing them manually using sDMA (CIK).
1021  */
1022 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1023                                    uint64_t value, unsigned count,
1024                                    uint32_t incr)
1025 {
1026         unsigned ndw = count * 2;
1027
1028         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1029                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1030         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1031         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1032         ib->ptr[ib->length_dw++] = ndw;
1033         for (; ndw > 0; ndw -= 2) {
1034                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1035                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1036                 value += incr;
1037         }
1038 }
1039
1040 /**
1041  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
1042  *
1043  * @ib: indirect buffer to fill with commands
1044  * @pe: addr of the page entry
1045  * @addr: dst addr to write into pe
1046  * @count: number of page entries to update
1047  * @incr: increase next addr by incr bytes
1048  * @flags: access flags
1049  *
1050  * Update the page tables using sDMA (CIK).
1051  */
1052 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
1053                                      uint64_t addr, unsigned count,
1054                                      uint32_t incr, uint64_t flags)
1055 {
1056         /* for physically contiguous pages (vram) */
1057         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1058         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1059         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1060         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1061         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1062         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1063         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1064         ib->ptr[ib->length_dw++] = incr; /* increment size */
1065         ib->ptr[ib->length_dw++] = 0;
1066         ib->ptr[ib->length_dw++] = count; /* number of entries */
1067 }
1068
1069 /**
1070  * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1071  *
1072  * @ib: indirect buffer to fill with padding
1073  *
1074  */
1075 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1076 {
1077         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1078         u32 pad_count;
1079         int i;
1080
1081         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1082         for (i = 0; i < pad_count; i++)
1083                 if (sdma && sdma->burst_nop && (i == 0))
1084                         ib->ptr[ib->length_dw++] =
1085                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1086                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1087                 else
1088                         ib->ptr[ib->length_dw++] =
1089                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1090 }
1091
1092 /**
1093  * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1094  *
1095  * @ring: amdgpu_ring pointer
1096  *
1097  * Make sure all previous operations are completed (CIK).
1098  */
1099 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1100 {
1101         uint32_t seq = ring->fence_drv.sync_seq;
1102         uint64_t addr = ring->fence_drv.gpu_addr;
1103
1104         /* wait for idle */
1105         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1106                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1107                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1108                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1109         amdgpu_ring_write(ring, addr & 0xfffffffc);
1110         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1111         amdgpu_ring_write(ring, seq); /* reference */
1112         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1113         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1114                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1115 }
1116
1117 /**
1118  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1119  *
1120  * @ring: amdgpu_ring pointer
1121  * @vm: amdgpu_vm pointer
1122  *
1123  * Update the page table base and flush the VM TLB
1124  * using sDMA (VI).
1125  */
1126 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1127                                          unsigned vmid, uint64_t pd_addr)
1128 {
1129         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1130
1131         /* wait for flush */
1132         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1133                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1134                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1135         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1136         amdgpu_ring_write(ring, 0);
1137         amdgpu_ring_write(ring, 0); /* reference */
1138         amdgpu_ring_write(ring, 0); /* mask */
1139         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1140                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1141 }
1142
1143 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
1144                                      uint32_t reg, uint32_t val)
1145 {
1146         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1147                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1148         amdgpu_ring_write(ring, reg);
1149         amdgpu_ring_write(ring, val);
1150 }
1151
1152 static int sdma_v3_0_early_init(void *handle)
1153 {
1154         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1155
1156         switch (adev->asic_type) {
1157         case CHIP_STONEY:
1158                 adev->sdma.num_instances = 1;
1159                 break;
1160         default:
1161                 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1162                 break;
1163         }
1164
1165         sdma_v3_0_set_ring_funcs(adev);
1166         sdma_v3_0_set_buffer_funcs(adev);
1167         sdma_v3_0_set_vm_pte_funcs(adev);
1168         sdma_v3_0_set_irq_funcs(adev);
1169
1170         return 0;
1171 }
1172
1173 static int sdma_v3_0_sw_init(void *handle)
1174 {
1175         struct amdgpu_ring *ring;
1176         int r, i;
1177         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1178
1179         /* SDMA trap event */
1180         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
1181                               &adev->sdma.trap_irq);
1182         if (r)
1183                 return r;
1184
1185         /* SDMA Privileged inst */
1186         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
1187                               &adev->sdma.illegal_inst_irq);
1188         if (r)
1189                 return r;
1190
1191         /* SDMA Privileged inst */
1192         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
1193                               &adev->sdma.illegal_inst_irq);
1194         if (r)
1195                 return r;
1196
1197         r = sdma_v3_0_init_microcode(adev);
1198         if (r) {
1199                 DRM_ERROR("Failed to load sdma firmware!\n");
1200                 return r;
1201         }
1202
1203         for (i = 0; i < adev->sdma.num_instances; i++) {
1204                 ring = &adev->sdma.instance[i].ring;
1205                 ring->ring_obj = NULL;
1206                 if (!amdgpu_sriov_vf(adev)) {
1207                         ring->use_doorbell = true;
1208                         ring->doorbell_index = (i == 0) ?
1209                                 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1210                 } else {
1211                         ring->use_pollmem = true;
1212                 }
1213
1214                 sprintf(ring->name, "sdma%d", i);
1215                 r = amdgpu_ring_init(adev, ring, 1024,
1216                                      &adev->sdma.trap_irq,
1217                                      (i == 0) ?
1218                                      AMDGPU_SDMA_IRQ_TRAP0 :
1219                                      AMDGPU_SDMA_IRQ_TRAP1);
1220                 if (r)
1221                         return r;
1222         }
1223
1224         return r;
1225 }
1226
1227 static int sdma_v3_0_sw_fini(void *handle)
1228 {
1229         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1230         int i;
1231
1232         for (i = 0; i < adev->sdma.num_instances; i++)
1233                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1234
1235         sdma_v3_0_free_microcode(adev);
1236         return 0;
1237 }
1238
1239 static int sdma_v3_0_hw_init(void *handle)
1240 {
1241         int r;
1242         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1243
1244         sdma_v3_0_init_golden_registers(adev);
1245
1246         r = sdma_v3_0_start(adev);
1247         if (r)
1248                 return r;
1249
1250         return r;
1251 }
1252
1253 static int sdma_v3_0_hw_fini(void *handle)
1254 {
1255         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1256
1257         sdma_v3_0_ctx_switch_enable(adev, false);
1258         sdma_v3_0_enable(adev, false);
1259
1260         return 0;
1261 }
1262
1263 static int sdma_v3_0_suspend(void *handle)
1264 {
1265         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1266
1267         return sdma_v3_0_hw_fini(adev);
1268 }
1269
1270 static int sdma_v3_0_resume(void *handle)
1271 {
1272         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1273
1274         return sdma_v3_0_hw_init(adev);
1275 }
1276
1277 static bool sdma_v3_0_is_idle(void *handle)
1278 {
1279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1280         u32 tmp = RREG32(mmSRBM_STATUS2);
1281
1282         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1283                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1284             return false;
1285
1286         return true;
1287 }
1288
1289 static int sdma_v3_0_wait_for_idle(void *handle)
1290 {
1291         unsigned i;
1292         u32 tmp;
1293         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1294
1295         for (i = 0; i < adev->usec_timeout; i++) {
1296                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1297                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1298
1299                 if (!tmp)
1300                         return 0;
1301                 udelay(1);
1302         }
1303         return -ETIMEDOUT;
1304 }
1305
1306 static bool sdma_v3_0_check_soft_reset(void *handle)
1307 {
1308         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1309         u32 srbm_soft_reset = 0;
1310         u32 tmp = RREG32(mmSRBM_STATUS2);
1311
1312         if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1313             (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1314                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1315                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1316         }
1317
1318         if (srbm_soft_reset) {
1319                 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1320                 return true;
1321         } else {
1322                 adev->sdma.srbm_soft_reset = 0;
1323                 return false;
1324         }
1325 }
1326
1327 static int sdma_v3_0_pre_soft_reset(void *handle)
1328 {
1329         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1330         u32 srbm_soft_reset = 0;
1331
1332         if (!adev->sdma.srbm_soft_reset)
1333                 return 0;
1334
1335         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1336
1337         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1338             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1339                 sdma_v3_0_ctx_switch_enable(adev, false);
1340                 sdma_v3_0_enable(adev, false);
1341         }
1342
1343         return 0;
1344 }
1345
1346 static int sdma_v3_0_post_soft_reset(void *handle)
1347 {
1348         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1349         u32 srbm_soft_reset = 0;
1350
1351         if (!adev->sdma.srbm_soft_reset)
1352                 return 0;
1353
1354         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1355
1356         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1357             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1358                 sdma_v3_0_gfx_resume(adev);
1359                 sdma_v3_0_rlc_resume(adev);
1360         }
1361
1362         return 0;
1363 }
1364
1365 static int sdma_v3_0_soft_reset(void *handle)
1366 {
1367         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1368         u32 srbm_soft_reset = 0;
1369         u32 tmp;
1370
1371         if (!adev->sdma.srbm_soft_reset)
1372                 return 0;
1373
1374         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1375
1376         if (srbm_soft_reset) {
1377                 tmp = RREG32(mmSRBM_SOFT_RESET);
1378                 tmp |= srbm_soft_reset;
1379                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1380                 WREG32(mmSRBM_SOFT_RESET, tmp);
1381                 tmp = RREG32(mmSRBM_SOFT_RESET);
1382
1383                 udelay(50);
1384
1385                 tmp &= ~srbm_soft_reset;
1386                 WREG32(mmSRBM_SOFT_RESET, tmp);
1387                 tmp = RREG32(mmSRBM_SOFT_RESET);
1388
1389                 /* Wait a little for things to settle down */
1390                 udelay(50);
1391         }
1392
1393         return 0;
1394 }
1395
1396 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1397                                         struct amdgpu_irq_src *source,
1398                                         unsigned type,
1399                                         enum amdgpu_interrupt_state state)
1400 {
1401         u32 sdma_cntl;
1402
1403         switch (type) {
1404         case AMDGPU_SDMA_IRQ_TRAP0:
1405                 switch (state) {
1406                 case AMDGPU_IRQ_STATE_DISABLE:
1407                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1408                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1409                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1410                         break;
1411                 case AMDGPU_IRQ_STATE_ENABLE:
1412                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1413                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1414                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1415                         break;
1416                 default:
1417                         break;
1418                 }
1419                 break;
1420         case AMDGPU_SDMA_IRQ_TRAP1:
1421                 switch (state) {
1422                 case AMDGPU_IRQ_STATE_DISABLE:
1423                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1424                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1425                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1426                         break;
1427                 case AMDGPU_IRQ_STATE_ENABLE:
1428                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1429                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1430                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1431                         break;
1432                 default:
1433                         break;
1434                 }
1435                 break;
1436         default:
1437                 break;
1438         }
1439         return 0;
1440 }
1441
1442 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1443                                       struct amdgpu_irq_src *source,
1444                                       struct amdgpu_iv_entry *entry)
1445 {
1446         u8 instance_id, queue_id;
1447
1448         instance_id = (entry->ring_id & 0x3) >> 0;
1449         queue_id = (entry->ring_id & 0xc) >> 2;
1450         DRM_DEBUG("IH: SDMA trap\n");
1451         switch (instance_id) {
1452         case 0:
1453                 switch (queue_id) {
1454                 case 0:
1455                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1456                         break;
1457                 case 1:
1458                         /* XXX compute */
1459                         break;
1460                 case 2:
1461                         /* XXX compute */
1462                         break;
1463                 }
1464                 break;
1465         case 1:
1466                 switch (queue_id) {
1467                 case 0:
1468                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1469                         break;
1470                 case 1:
1471                         /* XXX compute */
1472                         break;
1473                 case 2:
1474                         /* XXX compute */
1475                         break;
1476                 }
1477                 break;
1478         }
1479         return 0;
1480 }
1481
1482 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1483                                               struct amdgpu_irq_src *source,
1484                                               struct amdgpu_iv_entry *entry)
1485 {
1486         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1487         schedule_work(&adev->reset_work);
1488         return 0;
1489 }
1490
1491 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1492                 struct amdgpu_device *adev,
1493                 bool enable)
1494 {
1495         uint32_t temp, data;
1496         int i;
1497
1498         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1499                 for (i = 0; i < adev->sdma.num_instances; i++) {
1500                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1501                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1502                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1503                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1504                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1505                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1506                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1507                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1508                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1509                         if (data != temp)
1510                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1511                 }
1512         } else {
1513                 for (i = 0; i < adev->sdma.num_instances; i++) {
1514                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1515                         data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1516                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1517                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1518                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1519                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1520                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1521                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1522                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1523
1524                         if (data != temp)
1525                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1526                 }
1527         }
1528 }
1529
1530 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1531                 struct amdgpu_device *adev,
1532                 bool enable)
1533 {
1534         uint32_t temp, data;
1535         int i;
1536
1537         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1538                 for (i = 0; i < adev->sdma.num_instances; i++) {
1539                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1540                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1541
1542                         if (temp != data)
1543                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1544                 }
1545         } else {
1546                 for (i = 0; i < adev->sdma.num_instances; i++) {
1547                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1548                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1549
1550                         if (temp != data)
1551                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1552                 }
1553         }
1554 }
1555
1556 static int sdma_v3_0_set_clockgating_state(void *handle,
1557                                           enum amd_clockgating_state state)
1558 {
1559         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1560
1561         if (amdgpu_sriov_vf(adev))
1562                 return 0;
1563
1564         switch (adev->asic_type) {
1565         case CHIP_FIJI:
1566         case CHIP_CARRIZO:
1567         case CHIP_STONEY:
1568                 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1569                                 state == AMD_CG_STATE_GATE);
1570                 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1571                                 state == AMD_CG_STATE_GATE);
1572                 break;
1573         default:
1574                 break;
1575         }
1576         return 0;
1577 }
1578
1579 static int sdma_v3_0_set_powergating_state(void *handle,
1580                                           enum amd_powergating_state state)
1581 {
1582         return 0;
1583 }
1584
1585 static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags)
1586 {
1587         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1588         int data;
1589
1590         if (amdgpu_sriov_vf(adev))
1591                 *flags = 0;
1592
1593         /* AMD_CG_SUPPORT_SDMA_MGCG */
1594         data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
1595         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
1596                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1597
1598         /* AMD_CG_SUPPORT_SDMA_LS */
1599         data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
1600         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1601                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1602 }
1603
1604 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1605         .name = "sdma_v3_0",
1606         .early_init = sdma_v3_0_early_init,
1607         .late_init = NULL,
1608         .sw_init = sdma_v3_0_sw_init,
1609         .sw_fini = sdma_v3_0_sw_fini,
1610         .hw_init = sdma_v3_0_hw_init,
1611         .hw_fini = sdma_v3_0_hw_fini,
1612         .suspend = sdma_v3_0_suspend,
1613         .resume = sdma_v3_0_resume,
1614         .is_idle = sdma_v3_0_is_idle,
1615         .wait_for_idle = sdma_v3_0_wait_for_idle,
1616         .check_soft_reset = sdma_v3_0_check_soft_reset,
1617         .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1618         .post_soft_reset = sdma_v3_0_post_soft_reset,
1619         .soft_reset = sdma_v3_0_soft_reset,
1620         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1621         .set_powergating_state = sdma_v3_0_set_powergating_state,
1622         .get_clockgating_state = sdma_v3_0_get_clockgating_state,
1623 };
1624
1625 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1626         .type = AMDGPU_RING_TYPE_SDMA,
1627         .align_mask = 0xf,
1628         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1629         .support_64bit_ptrs = false,
1630         .get_rptr = sdma_v3_0_ring_get_rptr,
1631         .get_wptr = sdma_v3_0_ring_get_wptr,
1632         .set_wptr = sdma_v3_0_ring_set_wptr,
1633         .emit_frame_size =
1634                 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1635                 3 + /* hdp invalidate */
1636                 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1637                 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
1638                 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1639         .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
1640         .emit_ib = sdma_v3_0_ring_emit_ib,
1641         .emit_fence = sdma_v3_0_ring_emit_fence,
1642         .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1643         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1644         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1645         .test_ring = sdma_v3_0_ring_test_ring,
1646         .test_ib = sdma_v3_0_ring_test_ib,
1647         .insert_nop = sdma_v3_0_ring_insert_nop,
1648         .pad_ib = sdma_v3_0_ring_pad_ib,
1649         .emit_wreg = sdma_v3_0_ring_emit_wreg,
1650 };
1651
1652 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1653 {
1654         int i;
1655
1656         for (i = 0; i < adev->sdma.num_instances; i++) {
1657                 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1658                 adev->sdma.instance[i].ring.me = i;
1659         }
1660 }
1661
1662 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1663         .set = sdma_v3_0_set_trap_irq_state,
1664         .process = sdma_v3_0_process_trap_irq,
1665 };
1666
1667 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1668         .process = sdma_v3_0_process_illegal_inst_irq,
1669 };
1670
1671 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1672 {
1673         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1674         adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1675         adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1676 }
1677
1678 /**
1679  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1680  *
1681  * @ring: amdgpu_ring structure holding ring information
1682  * @src_offset: src GPU address
1683  * @dst_offset: dst GPU address
1684  * @byte_count: number of bytes to xfer
1685  *
1686  * Copy GPU buffers using the DMA engine (VI).
1687  * Used by the amdgpu ttm implementation to move pages if
1688  * registered as the asic copy callback.
1689  */
1690 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1691                                        uint64_t src_offset,
1692                                        uint64_t dst_offset,
1693                                        uint32_t byte_count)
1694 {
1695         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1696                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1697         ib->ptr[ib->length_dw++] = byte_count;
1698         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1699         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1700         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1701         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1702         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1703 }
1704
1705 /**
1706  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1707  *
1708  * @ring: amdgpu_ring structure holding ring information
1709  * @src_data: value to write to buffer
1710  * @dst_offset: dst GPU address
1711  * @byte_count: number of bytes to xfer
1712  *
1713  * Fill GPU buffers using the DMA engine (VI).
1714  */
1715 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1716                                        uint32_t src_data,
1717                                        uint64_t dst_offset,
1718                                        uint32_t byte_count)
1719 {
1720         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1721         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1722         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1723         ib->ptr[ib->length_dw++] = src_data;
1724         ib->ptr[ib->length_dw++] = byte_count;
1725 }
1726
1727 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1728         .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1729         .copy_num_dw = 7,
1730         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1731
1732         .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1733         .fill_num_dw = 5,
1734         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1735 };
1736
1737 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1738 {
1739         if (adev->mman.buffer_funcs == NULL) {
1740                 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1741                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1742         }
1743 }
1744
1745 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1746         .copy_pte_num_dw = 7,
1747         .copy_pte = sdma_v3_0_vm_copy_pte,
1748
1749         .write_pte = sdma_v3_0_vm_write_pte,
1750         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1751 };
1752
1753 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1754 {
1755         unsigned i;
1756
1757         if (adev->vm_manager.vm_pte_funcs == NULL) {
1758                 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1759                 for (i = 0; i < adev->sdma.num_instances; i++)
1760                         adev->vm_manager.vm_pte_rings[i] =
1761                                 &adev->sdma.instance[i].ring;
1762
1763                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1764         }
1765 }
1766
1767 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1768 {
1769         .type = AMD_IP_BLOCK_TYPE_SDMA,
1770         .major = 3,
1771         .minor = 0,
1772         .rev = 0,
1773         .funcs = &sdma_v3_0_ip_funcs,
1774 };
1775
1776 const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1777 {
1778         .type = AMD_IP_BLOCK_TYPE_SDMA,
1779         .major = 3,
1780         .minor = 1,
1781         .rev = 0,
1782         .funcs = &sdma_v3_0_ip_funcs,
1783 };