sys/dev/sound/pci/hda/hdac.c

   1 /*-
   2  * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
   3  * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.36.2.6 2007/10/26 20:48:18 ariff Exp $
  28  * $DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.12 2007/11/30 07:53:53 hasso Exp $
  29  */
  30
  31 /*
  32  * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised
  33  * that this driver still in its early stage, and possible of rewrite are
  34  * pretty much guaranteed. There are supposedly several distinct parent/child
  35  * busses to make this "perfect", but as for now and for the sake of
  36  * simplicity, everything is gobble up within single source.
  37  *
  38  * List of subsys:
  39  *     1) HDA Controller support
  40  *     2) HDA Codecs support, which may include
  41  *        - HDA
  42  *        - Modem
  43  *        - HDMI
  44  *     3) Widget parser - the real magic of why this driver works on so
  45  *        many hardwares with minimal vendor specific quirk. The original
  46  *        parser was written using Ruby and can be found at
  47  *        http://people.freebsd.org/~ariff/HDA/parser.rb . This crude
  48  *        ruby parser take the verbose dmesg dump as its input. Refer to
  49  *        http://www.microsoft.com/whdc/device/audio/default.mspx for various
  50  *        interesting documents, especially UAA (Universal Audio Architecture).
  51  *     4) Possible vendor specific support.
  52  *        (snd_hda_intel, snd_hda_ati, etc..)
  53  *
  54  * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the
  55  * Compaq V3000 with Conexant HDA.
  56  *
  57  *    * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
  58  *    *                                                                 *
  59  *    *        This driver is a collaborative effort made by:           *
  60  *    *                                                                 *
  61  *    *          Stephane E. Potvin <sepotvin@videotron.ca>             *
  62  *    *               Andrea Bittau <a.bittau@cs.ucl.ac.uk>             *
  63  *    *               Wesley Morgan <morganw@chemikals.org>             *
  64  *    *              Daniel Eischen <deischen@FreeBSD.org>              *
  65  *    *             Maxime Guillaud <bsd-ports@mguillaud.net>           *
  66  *    *              Ariff Abdullah <ariff@FreeBSD.org>                 *
  67  *    *                                                                 *
  68  *    *   ....and various people from freebsd-multimedia@FreeBSD.org    *
  69  *    *                                                                 *
  70  *    * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
  71  */
  72
  73 #include <dev/sound/pcm/sound.h>
  74 #include <bus/pci/pcireg.h>
  75 #include <bus/pci/pcivar.h>
  76
  77 #include <sys/ctype.h>
  78 #include <sys/taskqueue.h>
  79
  80 #include <dev/sound/pci/hda/hdac_private.h>
  81 #include <dev/sound/pci/hda/hdac_reg.h>
  82 #include <dev/sound/pci/hda/hda_reg.h>
  83 #include <dev/sound/pci/hda/hdac.h>
  84
  85 #include "mixer_if.h"
  86
  87 #define HDA_DRV_TEST_REV        "20071020_0048"
  88 #define HDA_WIDGET_PARSER_REV   1
  89
  90 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.12 2007/11/30 07:53:53 hasso Exp $");
  91
  92 #define HDA_BOOTVERBOSE(stmt)   do {                    \
  93         if (bootverbose != 0) {                         \
  94                 stmt                                    \
  95         }                                               \
  96 } while(0)
  97
  98 #if 1
  99 #undef HDAC_INTR_EXTRA
 100 #define HDAC_INTR_EXTRA         1
 101 #endif
 102
 103 #define hdac_lock(sc)           snd_mtxlock((sc)->lock)
 104 #define hdac_unlock(sc)         snd_mtxunlock((sc)->lock)
 105 #define hdac_lockassert(sc)     snd_mtxassert((sc)->lock)
 106 #define hdac_lockowned(sc)      (1)/* mtx_owned((sc)->lock) */
 107
 108 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
 109 #include <machine/specialreg.h>
 110 #define HDAC_DMA_ATTR(sc, v, s, attr)   do {                            \
 111         vm_offset_t va = (vm_offset_t)(v);                              \
 112         vm_size_t sz = (vm_size_t)(s);                                  \
 113         if ((sc) != NULL && ((sc)->flags & HDAC_F_DMA_NOCACHE) &&       \
 114             va != 0 && sz != 0)                                         \
 115                 (void)pmap_change_attr(va, sz, (attr));                 \
 116 } while(0)
 117 #else
 118 #define HDAC_DMA_ATTR(...)
 119 #endif
 120
 121 #define HDA_FLAG_MATCH(fl, v)   (((fl) & (v)) == (v))
 122 #define HDA_DEV_MATCH(fl, v)    ((fl) == (v) || \
 123                                 (fl) == 0xffffffff || \
 124                                 (((fl) & 0xffff0000) == 0xffff0000 && \
 125                                 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
 126                                 (((fl) & 0x0000ffff) == 0x0000ffff && \
 127                                 ((fl) & 0xffff0000) == ((v) & 0xffff0000)))
 128 #define HDA_MATCH_ALL           0xffffffff
 129 #define HDAC_INVALID            0xffffffff
 130
 131 /* Default controller / jack sense poll: 250ms */
 132 #define HDAC_POLL_INTERVAL      max(hz >> 2, 1)
 133
 134 /*
 135  * Make room for possible 4096 playback/record channels, in 100 years to come.
 136  */
 137 #define HDAC_TRIGGER_NONE       0x00000000
 138 #define HDAC_TRIGGER_PLAY       0x00000fff
 139 #define HDAC_TRIGGER_REC        0x00fff000
 140 #define HDAC_TRIGGER_UNSOL      0x80000000
 141
 142 #define HDA_MODEL_CONSTRUCT(vendor, model)      \
 143                 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
 144
 145 /* Controller models */
 146
 147 /* Intel */
 148 #define INTEL_VENDORID          0x8086
 149 #define HDA_INTEL_82801F        HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
 150 #define HDA_INTEL_63XXESB       HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
 151 #define HDA_INTEL_82801G        HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
 152 #define HDA_INTEL_82801H        HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
 153 #define HDA_INTEL_82801I        HDA_MODEL_CONSTRUCT(INTEL, 0x293e)
 154 #define HDA_INTEL_ALL           HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
 155
 156 /* Nvidia */
 157 #define NVIDIA_VENDORID         0x10de
 158 #define HDA_NVIDIA_MCP51        HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
 159 #define HDA_NVIDIA_MCP55        HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
 160 #define HDA_NVIDIA_MCP61A       HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
 161 #define HDA_NVIDIA_MCP61B       HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
 162 #define HDA_NVIDIA_MCP65A       HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
 163 #define HDA_NVIDIA_MCP65B       HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
 164 #define HDA_NVIDIA_ALL          HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
 165
 166 /* ATI */
 167 #define ATI_VENDORID            0x1002
 168 #define HDA_ATI_SB450           HDA_MODEL_CONSTRUCT(ATI, 0x437b)
 169 #define HDA_ATI_SB600           HDA_MODEL_CONSTRUCT(ATI, 0x4383)
 170 #define HDA_ATI_ALL             HDA_MODEL_CONSTRUCT(ATI, 0xffff)
 171
 172 /* VIA */
 173 #define VIA_VENDORID            0x1106
 174 #define HDA_VIA_VT82XX          HDA_MODEL_CONSTRUCT(VIA, 0x3288)
 175 #define HDA_VIA_ALL             HDA_MODEL_CONSTRUCT(VIA, 0xffff)
 176
 177 /* SiS */
 178 #define SIS_VENDORID            0x1039
 179 #define HDA_SIS_966             HDA_MODEL_CONSTRUCT(SIS, 0x7502)
 180 #define HDA_SIS_ALL             HDA_MODEL_CONSTRUCT(SIS, 0xffff)
 181
 182 /* OEM/subvendors */
 183
 184 /* Intel */
 185 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600)
 186
 187 /* HP/Compaq */
 188 #define HP_VENDORID             0x103c
 189 #define HP_V3000_SUBVENDOR      HDA_MODEL_CONSTRUCT(HP, 0x30b5)
 190 #define HP_NX7400_SUBVENDOR     HDA_MODEL_CONSTRUCT(HP, 0x30a2)
 191 #define HP_NX6310_SUBVENDOR     HDA_MODEL_CONSTRUCT(HP, 0x30aa)
 192 #define HP_NX6325_SUBVENDOR     HDA_MODEL_CONSTRUCT(HP, 0x30b0)
 193 #define HP_XW4300_SUBVENDOR     HDA_MODEL_CONSTRUCT(HP, 0x3013)
 194 #define HP_3010_SUBVENDOR       HDA_MODEL_CONSTRUCT(HP, 0x3010)
 195 #define HP_DV5000_SUBVENDOR     HDA_MODEL_CONSTRUCT(HP, 0x30a5)
 196 #define HP_DC7700_SUBVENDOR     HDA_MODEL_CONSTRUCT(HP, 0x2802)
 197 #define HP_ALL_SUBVENDOR        HDA_MODEL_CONSTRUCT(HP, 0xffff)
 198 /* What is wrong with XN 2563 anyway? (Got the picture ?) */
 199 #define HP_NX6325_SUBVENDORX    0x103c30b0
 200
 201 /* Dell */
 202 #define DELL_VENDORID           0x1028
 203 #define DELL_D820_SUBVENDOR     HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
 204 #define DELL_I1300_SUBVENDOR    HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
 205 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7)
 206 #define DELL_OPLX745_SUBVENDOR  HDA_MODEL_CONSTRUCT(DELL, 0x01da)
 207 #define DELL_ALL_SUBVENDOR      HDA_MODEL_CONSTRUCT(DELL, 0xffff)
 208
 209 /* Clevo */
 210 #define CLEVO_VENDORID          0x1558
 211 #define CLEVO_D900T_SUBVENDOR   HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
 212 #define CLEVO_ALL_SUBVENDOR     HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
 213
 214 /* Acer */
 215 #define ACER_VENDORID           0x1025
 216 #define ACER_A5050_SUBVENDOR    HDA_MODEL_CONSTRUCT(ACER, 0x010f)
 217 #define ACER_3681WXM_SUBVENDOR  HDA_MODEL_CONSTRUCT(ACER, 0x0110)
 218 #define ACER_ALL_SUBVENDOR      HDA_MODEL_CONSTRUCT(ACER, 0xffff)
 219
 220 /* Asus */
 221 #define ASUS_VENDORID           0x1043
 222 #define ASUS_M5200_SUBVENDOR    HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
 223 #define ASUS_U5F_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
 224 #define ASUS_A8JC_SUBVENDOR     HDA_MODEL_CONSTRUCT(ASUS, 0x1153)
 225 #define ASUS_P1AH2_SUBVENDOR    HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
 226 #define ASUS_A7M_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x1323)
 227 #define ASUS_A7T_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)
 228 #define ASUS_W6F_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
 229 #define ASUS_W2J_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x1971)
 230 #define ASUS_F3JC_SUBVENDOR     HDA_MODEL_CONSTRUCT(ASUS, 0x1338)
 231 #define ASUS_M2V_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)
 232 #define ASUS_M2N_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x8234)
 233 #define ASUS_M2NPVMX_SUBVENDOR  HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
 234 #define ASUS_P5BWD_SUBVENDOR    HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)
 235 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84)
 236 #define ASUS_ALL_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
 237
 238 /* IBM / Lenovo */
 239 #define IBM_VENDORID            0x1014
 240 #define IBM_M52_SUBVENDOR       HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
 241 #define IBM_ALL_SUBVENDOR       HDA_MODEL_CONSTRUCT(IBM, 0xffff)
 242
 243 /* Lenovo */
 244 #define LENOVO_VENDORID         0x17aa
 245 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)
 246 #define LENOVO_TCA55_SUBVENDOR  HDA_MODEL_CONSTRUCT(LENOVO, 0x1015)
 247 #define LENOVO_ALL_SUBVENDOR    HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)
 248
 249 /* Samsung */
 250 #define SAMSUNG_VENDORID        0x144d
 251 #define SAMSUNG_Q1_SUBVENDOR    HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)
 252 #define SAMSUNG_ALL_SUBVENDOR   HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)
 253
 254 /* Medion ? */
 255 #define MEDION_VENDORID                 0x161f
 256 #define MEDION_MD95257_SUBVENDOR        HDA_MODEL_CONSTRUCT(MEDION, 0x203d)
 257 #define MEDION_ALL_SUBVENDOR            HDA_MODEL_CONSTRUCT(MEDION, 0xffff)
 258
 259 /*
 260  * Apple Intel MacXXXX seems using Sigmatel codec/vendor id
 261  * instead of their own, which is beyond my comprehension
 262  * (see HDA_CODEC_STAC9221 below).
 263  */
 264 #define APPLE_INTEL_MAC         0x76808384
 265
 266 /* LG Electronics */
 267 #define LG_VENDORID             0x1854
 268 #define LG_LW20_SUBVENDOR       HDA_MODEL_CONSTRUCT(LG, 0x0018)
 269 #define LG_ALL_SUBVENDOR        HDA_MODEL_CONSTRUCT(LG, 0xffff)
 270
 271 /* Fujitsu Siemens */
 272 #define FS_VENDORID             0x1734
 273 #define FS_PA1510_SUBVENDOR     HDA_MODEL_CONSTRUCT(FS, 0x10b8)
 274 #define FS_SI1848_SUBVENDOR     HDA_MODEL_CONSTRUCT(FS, 0x10cd)
 275 #define FS_ALL_SUBVENDOR        HDA_MODEL_CONSTRUCT(FS, 0xffff)
 276
 277 /* Fujitsu Limited */
 278 #define FL_VENDORID             0x10cf
 279 #define FL_S7020D_SUBVENDOR     HDA_MODEL_CONSTRUCT(FL, 0x1326)
 280 #define FL_ALL_SUBVENDOR        HDA_MODEL_CONSTRUCT(FL, 0xffff)
 281
 282 /* Toshiba */
 283 #define TOSHIBA_VENDORID        0x1179
 284 #define TOSHIBA_U200_SUBVENDOR  HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)
 285 #define TOSHIBA_ALL_SUBVENDOR   HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)
 286
 287 /* Micro-Star International (MSI) */
 288 #define MSI_VENDORID            0x1462
 289 #define MSI_MS1034_SUBVENDOR    HDA_MODEL_CONSTRUCT(MSI, 0x0349)
 290 #define MSI_MS034A_SUBVENDOR    HDA_MODEL_CONSTRUCT(MSI, 0x034a)
 291 #define MSI_ALL_SUBVENDOR       HDA_MODEL_CONSTRUCT(MSI, 0xffff)
 292
 293 /* Giga-Byte Technology */
 294 #define GB_VENDORID             0x1458
 295 #define GB_G33S2H_SUBVENDOR     HDA_MODEL_CONSTRUCT(GB, 0xa022)
 296 #define GP_ALL_SUBVENDOR        HDA_MODEL_CONSTRUCT(GB, 0xffff)
 297
 298 /* Uniwill ? */
 299 #define UNIWILL_VENDORID        0x1584
 300 #define UNIWILL_9075_SUBVENDOR  HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)
 301 #define UNIWILL_9080_SUBVENDOR  HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)
 302
 303
 304 /* Misc constants.. */
 305 #define HDA_AMP_MUTE_DEFAULT    (0xffffffff)
 306 #define HDA_AMP_MUTE_NONE       (0)
 307 #define HDA_AMP_MUTE_LEFT       (1 << 0)
 308 #define HDA_AMP_MUTE_RIGHT      (1 << 1)
 309 #define HDA_AMP_MUTE_ALL        (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT)
 310
 311 #define HDA_AMP_LEFT_MUTED(v)   ((v) & (HDA_AMP_MUTE_LEFT))
 312 #define HDA_AMP_RIGHT_MUTED(v)  (((v) & HDA_AMP_MUTE_RIGHT) >> 1)
 313
 314 #define HDA_DAC_PATH    (1 << 0)
 315 #define HDA_ADC_PATH    (1 << 1)
 316 #define HDA_ADC_RECSEL  (1 << 2)
 317
 318 #define HDA_DAC_LOCKED  (1 << 3)
 319 #define HDA_ADC_LOCKED  (1 << 4)
 320
 321 #define HDA_CTL_OUT     (1 << 0)
 322 #define HDA_CTL_IN      (1 << 1)
 323 #define HDA_CTL_BOTH    (HDA_CTL_IN | HDA_CTL_OUT)
 324
 325 #define HDA_GPIO_MAX            8
 326 /* 0 - 7 = GPIO , 8 = Flush */
 327 #define HDA_QUIRK_GPIO0         (1 << 0)
 328 #define HDA_QUIRK_GPIO1         (1 << 1)
 329 #define HDA_QUIRK_GPIO2         (1 << 2)
 330 #define HDA_QUIRK_GPIO3         (1 << 3)
 331 #define HDA_QUIRK_GPIO4         (1 << 4)
 332 #define HDA_QUIRK_GPIO5         (1 << 5)
 333 #define HDA_QUIRK_GPIO6         (1 << 6)
 334 #define HDA_QUIRK_GPIO7         (1 << 7)
 335 #define HDA_QUIRK_GPIOFLUSH     (1 << 8)
 336
 337 /* 9 - 25 = anything else */
 338 #define HDA_QUIRK_SOFTPCMVOL    (1 << 9)
 339 #define HDA_QUIRK_FIXEDRATE     (1 << 10)
 340 #define HDA_QUIRK_FORCESTEREO   (1 << 11)
 341 #define HDA_QUIRK_EAPDINV       (1 << 12)
 342 #define HDA_QUIRK_DMAPOS        (1 << 13)
 343
 344 /* 26 - 31 = vrefs */
 345 #define HDA_QUIRK_IVREF50       (1 << 26)
 346 #define HDA_QUIRK_IVREF80       (1 << 27)
 347 #define HDA_QUIRK_IVREF100      (1 << 28)
 348 #define HDA_QUIRK_OVREF50       (1 << 29)
 349 #define HDA_QUIRK_OVREF80       (1 << 30)
 350 #define HDA_QUIRK_OVREF100      (1 << 31)
 351
 352 #define HDA_QUIRK_IVREF         (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \
 353                                                         HDA_QUIRK_IVREF100)
 354 #define HDA_QUIRK_OVREF         (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \
 355                                                         HDA_QUIRK_OVREF100)
 356 #define HDA_QUIRK_VREF          (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF)
 357
 358 #define SOUND_MASK_SKIP         (1 << 30)
 359 #define SOUND_MASK_DISABLE      (1 << 31)
 360
 361 static const struct {
 362         char *key;
 363         uint32_t value;
 364 } hdac_quirks_tab[] = {
 365         { "gpio0", HDA_QUIRK_GPIO0 },
 366         { "gpio1", HDA_QUIRK_GPIO1 },
 367         { "gpio2", HDA_QUIRK_GPIO2 },
 368         { "gpio3", HDA_QUIRK_GPIO3 },
 369         { "gpio4", HDA_QUIRK_GPIO4 },
 370         { "gpio5", HDA_QUIRK_GPIO5 },
 371         { "gpio6", HDA_QUIRK_GPIO6 },
 372         { "gpio7", HDA_QUIRK_GPIO7 },
 373         { "gpioflush", HDA_QUIRK_GPIOFLUSH },
 374         { "softpcmvol", HDA_QUIRK_SOFTPCMVOL },
 375         { "fixedrate", HDA_QUIRK_FIXEDRATE },
 376         { "forcestereo", HDA_QUIRK_FORCESTEREO },
 377         { "eapdinv", HDA_QUIRK_EAPDINV },
 378         { "dmapos", HDA_QUIRK_DMAPOS },
 379         { "ivref50", HDA_QUIRK_IVREF50 },
 380         { "ivref80", HDA_QUIRK_IVREF80 },
 381         { "ivref100", HDA_QUIRK_IVREF100 },
 382         { "ovref50", HDA_QUIRK_OVREF50 },
 383         { "ovref80", HDA_QUIRK_OVREF80 },
 384         { "ovref100", HDA_QUIRK_OVREF100 },
 385         { "ivref", HDA_QUIRK_IVREF },
 386         { "ovref", HDA_QUIRK_OVREF },
 387         { "vref", HDA_QUIRK_VREF },
 388 };
 389 #define HDAC_QUIRKS_TAB_LEN     \
 390                 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
 391
 392 #define HDA_BDL_MIN     2
 393 #define HDA_BDL_MAX     256
 394 #define HDA_BDL_DEFAULT HDA_BDL_MIN
 395
 396 #define HDA_BLK_MIN     HDAC_DMA_ALIGNMENT
 397 #define HDA_BLK_ALIGN   (~(HDA_BLK_MIN - 1))
 398
 399 #define HDA_BUFSZ_MIN           4096
 400 #define HDA_BUFSZ_MAX           65536
 401 #define HDA_BUFSZ_DEFAULT       16384
 402
 403 #define HDA_PARSE_MAXDEPTH      10
 404
 405 #define HDAC_UNSOLTAG_EVENT_HP          0x00
 406 #define HDAC_UNSOLTAG_EVENT_TEST        0x01
 407
 408 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller");
 409
 410 enum {
 411         HDA_PARSE_MIXER,
 412         HDA_PARSE_DIRECT
 413 };
 414
 415 /* Default */
 416 static uint32_t hdac_fmt[] = {
 417         AFMT_STEREO | AFMT_S16_LE,
 418         0
 419 };
 420
 421 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0};
 422
 423 static const struct {
 424         uint32_t        model;
 425         char            *desc;
 426 } hdac_devices[] = {
 427         { HDA_INTEL_82801F,  "Intel 82801F" },
 428         { HDA_INTEL_63XXESB, "Intel 631x/632xESB" },
 429         { HDA_INTEL_82801G,  "Intel 82801G" },
 430         { HDA_INTEL_82801H,  "Intel 82801H" },
 431         { HDA_INTEL_82801I,  "Intel 82801I" },
 432         { HDA_NVIDIA_MCP51,  "NVidia MCP51" },
 433         { HDA_NVIDIA_MCP55,  "NVidia MCP55" },
 434         { HDA_NVIDIA_MCP61A, "NVidia MCP61A" },
 435         { HDA_NVIDIA_MCP61B, "NVidia MCP61B" },
 436         { HDA_NVIDIA_MCP65A, "NVidia MCP65A" },
 437         { HDA_NVIDIA_MCP65B, "NVidia MCP65B" },
 438         { HDA_ATI_SB450,     "ATI SB450"    },
 439         { HDA_ATI_SB600,     "ATI SB600"    },
 440         { HDA_VIA_VT82XX,    "VIA VT8251/8237A" },
 441         { HDA_SIS_966,       "SiS 966" },
 442         /* Unknown */
 443         { HDA_INTEL_ALL,  "Intel (Unknown)"  },
 444         { HDA_NVIDIA_ALL, "NVidia (Unknown)" },
 445         { HDA_ATI_ALL,    "ATI (Unknown)"    },
 446         { HDA_VIA_ALL,    "VIA (Unknown)"    },
 447         { HDA_SIS_ALL,    "SiS (Unknown)"    },
 448 };
 449 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
 450
 451 static const struct {
 452         uint16_t vendor;
 453         uint8_t reg;
 454         uint8_t mask;
 455         uint8_t enable;
 456 } hdac_pcie_snoop[] = {
 457         {  INTEL_VENDORID, 0x00, 0x00, 0x00 },
 458         {    ATI_VENDORID, 0x42, 0xf8, 0x02 },
 459         { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
 460 };
 461 #define HDAC_PCIESNOOP_LEN      \
 462                         (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0]))
 463
 464 static const struct {
 465         uint32_t        rate;
 466         int             valid;
 467         uint16_t        base;
 468         uint16_t        mul;
 469         uint16_t        div;
 470 } hda_rate_tab[] = {
 471         {   8000, 1, 0x0000, 0x0000, 0x0500 },  /* (48000 * 1) / 6 */
 472         {   9600, 0, 0x0000, 0x0000, 0x0400 },  /* (48000 * 1) / 5 */
 473         {  12000, 0, 0x0000, 0x0000, 0x0300 },  /* (48000 * 1) / 4 */
 474         {  16000, 1, 0x0000, 0x0000, 0x0200 },  /* (48000 * 1) / 3 */
 475         {  18000, 0, 0x0000, 0x1000, 0x0700 },  /* (48000 * 3) / 8 */
 476         {  19200, 0, 0x0000, 0x0800, 0x0400 },  /* (48000 * 2) / 5 */
 477         {  24000, 0, 0x0000, 0x0000, 0x0100 },  /* (48000 * 1) / 2 */
 478         {  28800, 0, 0x0000, 0x1000, 0x0400 },  /* (48000 * 3) / 5 */
 479         {  32000, 1, 0x0000, 0x0800, 0x0200 },  /* (48000 * 2) / 3 */
 480         {  36000, 0, 0x0000, 0x1000, 0x0300 },  /* (48000 * 3) / 4 */
 481         {  38400, 0, 0x0000, 0x1800, 0x0400 },  /* (48000 * 4) / 5 */
 482         {  48000, 1, 0x0000, 0x0000, 0x0000 },  /* (48000 * 1) / 1 */
 483         {  64000, 0, 0x0000, 0x1800, 0x0200 },  /* (48000 * 4) / 3 */
 484         {  72000, 0, 0x0000, 0x1000, 0x0100 },  /* (48000 * 3) / 2 */
 485         {  96000, 1, 0x0000, 0x0800, 0x0000 },  /* (48000 * 2) / 1 */
 486         { 144000, 0, 0x0000, 0x1000, 0x0000 },  /* (48000 * 3) / 1 */
 487         { 192000, 1, 0x0000, 0x1800, 0x0000 },  /* (48000 * 4) / 1 */
 488         {   8820, 0, 0x4000, 0x0000, 0x0400 },  /* (44100 * 1) / 5 */
 489         {  11025, 1, 0x4000, 0x0000, 0x0300 },  /* (44100 * 1) / 4 */
 490         {  12600, 0, 0x4000, 0x0800, 0x0600 },  /* (44100 * 2) / 7 */
 491         {  14700, 0, 0x4000, 0x0000, 0x0200 },  /* (44100 * 1) / 3 */
 492         {  17640, 0, 0x4000, 0x0800, 0x0400 },  /* (44100 * 2) / 5 */
 493         {  18900, 0, 0x4000, 0x1000, 0x0600 },  /* (44100 * 3) / 7 */
 494         {  22050, 1, 0x4000, 0x0000, 0x0100 },  /* (44100 * 1) / 2 */
 495         {  25200, 0, 0x4000, 0x1800, 0x0600 },  /* (44100 * 4) / 7 */
 496         {  26460, 0, 0x4000, 0x1000, 0x0400 },  /* (44100 * 3) / 5 */
 497         {  29400, 0, 0x4000, 0x0800, 0x0200 },  /* (44100 * 2) / 3 */
 498         {  33075, 0, 0x4000, 0x1000, 0x0300 },  /* (44100 * 3) / 4 */
 499         {  35280, 0, 0x4000, 0x1800, 0x0400 },  /* (44100 * 4) / 5 */
 500         {  44100, 1, 0x4000, 0x0000, 0x0000 },  /* (44100 * 1) / 1 */
 501         {  58800, 0, 0x4000, 0x1800, 0x0200 },  /* (44100 * 4) / 3 */
 502         {  66150, 0, 0x4000, 0x1000, 0x0100 },  /* (44100 * 3) / 2 */
 503         {  88200, 1, 0x4000, 0x0800, 0x0000 },  /* (44100 * 2) / 1 */
 504         { 132300, 0, 0x4000, 0x1000, 0x0000 },  /* (44100 * 3) / 1 */
 505         { 176400, 1, 0x4000, 0x1800, 0x0000 },  /* (44100 * 4) / 1 */
 506 };
 507 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0]))
 508
 509 /* All codecs you can eat... */
 510 #define HDA_CODEC_CONSTRUCT(vendor, id) \
 511                 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
 512
 513 /* Realtek */
 514 #define REALTEK_VENDORID        0x10ec
 515 #define HDA_CODEC_ALC260        HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
 516 #define HDA_CODEC_ALC262        HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)
 517 #define HDA_CODEC_ALC268        HDA_CODEC_CONSTRUCT(REALTEK, 0x0268)
 518 #define HDA_CODEC_ALC660        HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)
 519 #define HDA_CODEC_ALC861        HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
 520 #define HDA_CODEC_ALC861VD      HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)
 521 #define HDA_CODEC_ALC880        HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
 522 #define HDA_CODEC_ALC882        HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
 523 #define HDA_CODEC_ALC883        HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
 524 #define HDA_CODEC_ALC885        HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)
 525 #define HDA_CODEC_ALC888        HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)
 526 #define HDA_CODEC_ALCXXXX       HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
 527
 528 /* Analog Devices */
 529 #define ANALOGDEVICES_VENDORID  0x11d4
 530 #define HDA_CODEC_AD1981HD      HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)
 531 #define HDA_CODEC_AD1983        HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)
 532 #define HDA_CODEC_AD1986A       HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)
 533 #define HDA_CODEC_AD1988        HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)
 534 #define HDA_CODEC_AD1988B       HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)
 535 #define HDA_CODEC_ADXXXX        HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)
 536
 537 /* CMedia */
 538 #define CMEDIA_VENDORID         0x434d
 539 #define HDA_CODEC_CMI9880       HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
 540 #define HDA_CODEC_CMIXXXX       HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
 541
 542 /* Sigmatel */
 543 #define SIGMATEL_VENDORID       0x8384
 544 #define HDA_CODEC_STAC9221      HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
 545 #define HDA_CODEC_STAC9221D     HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
 546 #define HDA_CODEC_STAC9220      HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
 547 #define HDA_CODEC_STAC922XD     HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
 548 #define HDA_CODEC_STAC9227      HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)
 549 #define HDA_CODEC_STAC9271D     HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)
 550 #define HDA_CODEC_STACXXXX      HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
 551
 552 /*
 553  * Conexant
 554  *
 555  * Ok, the truth is, I don't have any idea at all whether
 556  * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only
 557  * place that tell me it is "Venice" is from its Windows driver INF.
 558  *
 559  *  Venice - CX?????
 560  * Waikiki - CX20551-22
 561  */
 562 #define CONEXANT_VENDORID       0x14f1
 563 #define HDA_CODEC_CXVENICE      HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
 564 #define HDA_CODEC_CXWAIKIKI     HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
 565 #define HDA_CODEC_CXXXXX        HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
 566
 567 /* VIA */
 568 #define HDA_CODEC_VT1708_8      HDA_CODEC_CONSTRUCT(VIA, 0x1708)
 569 #define HDA_CODEC_VT1708_9      HDA_CODEC_CONSTRUCT(VIA, 0x1709)
 570 #define HDA_CODEC_VT1708_A      HDA_CODEC_CONSTRUCT(VIA, 0x170a)
 571 #define HDA_CODEC_VT1708_B      HDA_CODEC_CONSTRUCT(VIA, 0x170b)
 572 #define HDA_CODEC_VT1709_0      HDA_CODEC_CONSTRUCT(VIA, 0xe710)
 573 #define HDA_CODEC_VT1709_1      HDA_CODEC_CONSTRUCT(VIA, 0xe711)
 574 #define HDA_CODEC_VT1709_2      HDA_CODEC_CONSTRUCT(VIA, 0xe712)
 575 #define HDA_CODEC_VT1709_3      HDA_CODEC_CONSTRUCT(VIA, 0xe713)
 576 #define HDA_CODEC_VT1709_4      HDA_CODEC_CONSTRUCT(VIA, 0xe714)
 577 #define HDA_CODEC_VT1709_5      HDA_CODEC_CONSTRUCT(VIA, 0xe715)
 578 #define HDA_CODEC_VT1709_6      HDA_CODEC_CONSTRUCT(VIA, 0xe716)
 579 #define HDA_CODEC_VT1709_7      HDA_CODEC_CONSTRUCT(VIA, 0xe717)
 580 #define HDA_CODEC_VTXXXX        HDA_CODEC_CONSTRUCT(VIA, 0xffff)
 581
 582
 583 /* Codecs */
 584 static const struct {
 585         uint32_t id;
 586         char *name;
 587 } hdac_codecs[] = {
 588         { HDA_CODEC_ALC260,    "Realtek ALC260" },
 589         { HDA_CODEC_ALC262,    "Realtek ALC262" },
 590         { HDA_CODEC_ALC268,    "Realtek ALC268" },
 591         { HDA_CODEC_ALC660,    "Realtek ALC660" },
 592         { HDA_CODEC_ALC861,    "Realtek ALC861" },
 593         { HDA_CODEC_ALC861VD,  "Realtek ALC861-VD" },
 594         { HDA_CODEC_ALC880,    "Realtek ALC880" },
 595         { HDA_CODEC_ALC882,    "Realtek ALC882" },
 596         { HDA_CODEC_ALC883,    "Realtek ALC883" },
 597         { HDA_CODEC_ALC885,    "Realtek ALC885" },
 598         { HDA_CODEC_ALC888,    "Realtek ALC888" },
 599         { HDA_CODEC_AD1981HD,  "Analog Devices AD1981HD" },
 600         { HDA_CODEC_AD1983,    "Analog Devices AD1983" },
 601         { HDA_CODEC_AD1986A,   "Analog Devices AD1986A" },
 602         { HDA_CODEC_AD1988,    "Analog Devices AD1988" },
 603         { HDA_CODEC_AD1988B,   "Analog Devices AD1988B" },
 604         { HDA_CODEC_CMI9880,   "CMedia CMI9880" },
 605         { HDA_CODEC_STAC9221,  "Sigmatel STAC9221" },
 606         { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" },
 607         { HDA_CODEC_STAC9220,  "Sigmatel STAC9220" },
 608         { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" },
 609         { HDA_CODEC_STAC9227,  "Sigmatel STAC9227" },
 610         { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" },
 611         { HDA_CODEC_CXVENICE,  "Conexant Venice" },
 612         { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" },
 613         { HDA_CODEC_VT1708_8,  "VIA VT1708_8" },
 614         { HDA_CODEC_VT1708_9,  "VIA VT1708_9" },
 615         { HDA_CODEC_VT1708_A,  "VIA VT1708_A" },
 616         { HDA_CODEC_VT1708_B,  "VIA VT1708_B" },
 617         { HDA_CODEC_VT1709_0,  "VIA VT1709_0" },
 618         { HDA_CODEC_VT1709_1,  "VIA VT1709_1" },
 619         { HDA_CODEC_VT1709_2,  "VIA VT1709_2" },
 620         { HDA_CODEC_VT1709_3,  "VIA VT1709_3" },
 621         { HDA_CODEC_VT1709_4,  "VIA VT1709_4" },
 622         { HDA_CODEC_VT1709_5,  "VIA VT1709_5" },
 623         { HDA_CODEC_VT1709_6,  "VIA VT1709_6" },
 624         { HDA_CODEC_VT1709_7,  "VIA VT1709_7" },
 625         /* Unknown codec */
 626         { HDA_CODEC_ALCXXXX,   "Realtek (Unknown)" },
 627         { HDA_CODEC_ADXXXX,    "Analog Devices (Unknown)" },
 628         { HDA_CODEC_CMIXXXX,   "CMedia (Unknown)" },
 629         { HDA_CODEC_STACXXXX,  "Sigmatel (Unknown)" },
 630         { HDA_CODEC_CXXXXX,    "Conexant (Unknown)" },
 631         { HDA_CODEC_VTXXXX,    "VIA (Unknown)" },
 632 };
 633 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0]))
 634
 635 enum {
 636         HDAC_HP_SWITCH_CTL,
 637         HDAC_HP_SWITCH_CTRL,
 638         HDAC_HP_SWITCH_DEBUG
 639 };
 640
 641 static const struct {
 642         uint32_t model;
 643         uint32_t id;
 644         int type;
 645         int inverted;
 646         int polling;
 647         int execsense;
 648         nid_t hpnid;
 649         nid_t spkrnid[8];
 650         nid_t eapdnid;
 651 } hdac_hp_switch[] = {
 652         /* Specific OEM models */
 653         { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
 654             0, 0, -1, 17, { 16, -1 }, 16 },
 655         /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL,
 656             0, 0, -1, 21, { 16, 17, -1 }, -1 } */
 657         /* { HP_3010_SUBVENDOR,  HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG,
 658             0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */
 659         { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
 660             0, 0, -1, 6, { 5, -1 }, 5 },
 661         { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
 662             0, 0, -1, 6, { 5, -1 }, 5 },
 663         { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
 664             0, 0, -1, 6, { 5, -1 }, 5 },
 665         /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL,
 666             0, 0, -1, 21, { 22, 27, -1 }, -1 }, */
 667         { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
 668             0, 0, -1, 6, { 5, -1 }, -1 },
 669         { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
 670             0, 0, -1, 13, { 14, -1 }, -1 },
 671         { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
 672             0, 0, -1, 13, { 14, -1 }, -1 },
 673         { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL,
 674             0, 0, -1, 6, { 5, 7, -1 }, -1 },
 675         { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL,
 676             0, 0, -1, 10, { 13, -1 }, -1 },
 677         { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
 678             1, 0, -1, 26, { 27, -1 }, -1 },
 679         /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
 680             0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */
 681         { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL,
 682             0, 0, -1, 27, { 20, -1 }, -1 },
 683         { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
 684             0, 0, -1, 20, { 21, -1 }, -1 },
 685         { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
 686             0, 0, -1, 20, { 21, -1 }, -1 },
 687         { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
 688             0, 0, -1, 20, { 21, -1 }, -1 },
 689         { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
 690             0, 0, -1, 20, { 27, -1 }, -1 },
 691         { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
 692             0, 0, -1, 20, { 27, -1 }, -1 },
 693         { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
 694             0, 0, -1, 20, { 21, -1 }, -1 },
 695         { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL,
 696             0, 0, -1, 20, { 16, -1 }, -1 },
 697         /*
 698          * All models that at least come from the same vendor with
 699          * simmilar codec.
 700          */
 701         { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
 702             0, 0, -1, 17, { 16, -1 }, 16 },
 703         { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
 704             0, 0, -1, 6, { 5, -1 }, 5 },
 705         { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
 706             0, 0, -1, 6, { 5, -1 }, -1 },
 707         { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
 708             0, 0, -1, 13, { 14, -1 }, -1 },
 709 #if 0
 710         { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
 711             1, 0, -1, 26, { 27, -1 }, -1 },
 712         { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
 713             0, 0, -1, 20, { 21, -1 }, -1 },
 714 #endif
 715 };
 716 #define HDAC_HP_SWITCH_LEN      \
 717                 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0]))
 718
 719 static const struct {
 720         uint32_t model;
 721         uint32_t id;
 722         nid_t eapdnid;
 723         int hp_switch;
 724 } hdac_eapd_switch[] = {
 725         { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 },
 726         { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
 727         { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
 728 };
 729 #define HDAC_EAPD_SWITCH_LEN    \
 730                 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0]))
 731
 732 /****************************************************************************
 733  * Function prototypes
 734  ****************************************************************************/
 735 static void     hdac_intr_handler(void *);
 736 static int      hdac_reset(struct hdac_softc *);
 737 static int      hdac_get_capabilities(struct hdac_softc *);
 738 static void     hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
 739 static int      hdac_dma_alloc(struct hdac_softc *,
 740                                         struct hdac_dma *, bus_size_t);
 741 static void     hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
 742 static int      hdac_mem_alloc(struct hdac_softc *);
 743 static void     hdac_mem_free(struct hdac_softc *);
 744 static int      hdac_irq_alloc(struct hdac_softc *);
 745 static void     hdac_irq_free(struct hdac_softc *);
 746 static void     hdac_corb_init(struct hdac_softc *);
 747 static void     hdac_rirb_init(struct hdac_softc *);
 748 static void     hdac_corb_start(struct hdac_softc *);
 749 static void     hdac_rirb_start(struct hdac_softc *);
 750 static void     hdac_scan_codecs(struct hdac_softc *, int);
 751 static int      hdac_probe_codec(struct hdac_codec *);
 752 static struct   hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t);
 753 static void     hdac_add_child(struct hdac_softc *, struct hdac_devinfo *);
 754
 755 static void     hdac_attach2(void *);
 756
 757 static uint32_t hdac_command_sendone_internal(struct hdac_softc *,
 758                                                         uint32_t, int);
 759 static void     hdac_command_send_internal(struct hdac_softc *,
 760                                         struct hdac_command_list *, int);
 761
 762 static int      hdac_probe(device_t);
 763 static int      hdac_attach(device_t);
 764 static int      hdac_detach(device_t);
 765 static void     hdac_widget_connection_select(struct hdac_widget *, uint8_t);
 766 static void     hdac_audio_ctl_amp_set(struct hdac_audio_ctl *,
 767                                                 uint32_t, int, int);
 768 static struct   hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *,
 769                                                         nid_t, int, int);
 770 static void     hdac_audio_ctl_amp_set_internal(struct hdac_softc *,
 771                                 nid_t, nid_t, int, int, int, int, int, int);
 772 static int      hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *);
 773 static struct   hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t);
 774
 775 static int      hdac_rirb_flush(struct hdac_softc *sc);
 776 static int      hdac_unsolq_flush(struct hdac_softc *sc);
 777
 778 #define hdac_command(a1, a2, a3)        \
 779                 hdac_command_sendone_internal(a1, a2, a3)
 780
 781 #define hdac_codec_id(d)                                                \
 782                 ((uint32_t)((d == NULL) ? 0x00000000 :                  \
 783                 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) |      \
 784                 ((uint32_t)(d)->device_id & 0x0000ffff))))
 785
 786 static char *
 787 hdac_codec_name(struct hdac_devinfo *devinfo)
 788 {
 789         uint32_t id;
 790         int i;
 791
 792         id = hdac_codec_id(devinfo);
 793
 794         for (i = 0; i < HDAC_CODECS_LEN; i++) {
 795                 if (HDA_DEV_MATCH(hdac_codecs[i].id, id))
 796                         return (hdac_codecs[i].name);
 797         }
 798
 799         return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec");
 800 }
 801
 802 static char *
 803 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask)
 804 {
 805         static char *ossname[] = SOUND_DEVICE_NAMES;
 806         static char *unknown = "???";
 807         int i;
 808
 809         for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) {
 810                 if (devmask & (1 << i))
 811                         return (ossname[i]);
 812         }
 813         return (unknown);
 814 }
 815
 816 static void
 817 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len)
 818 {
 819         static char *ossname[] = SOUND_DEVICE_NAMES;
 820         int i, first = 1;
 821
 822         bzero(buf, len);
 823         for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
 824                 if (mask & (1 << i)) {
 825                         if (first == 0)
 826                                 strlcat(buf, ", ", len);
 827                         strlcat(buf, ossname[i], len);
 828                         first = 0;
 829                 }
 830         }
 831 }
 832
 833 static struct hdac_audio_ctl *
 834 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index)
 835 {
 836         if (devinfo == NULL ||
 837             devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ||
 838             index == NULL || devinfo->function.audio.ctl == NULL ||
 839             devinfo->function.audio.ctlcnt < 1 ||
 840             *index < 0 || *index >= devinfo->function.audio.ctlcnt)
 841                 return (NULL);
 842         return (&devinfo->function.audio.ctl[(*index)++]);
 843 }
 844
 845 static struct hdac_audio_ctl *
 846 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid,
 847                                                 int index, int cnt)
 848 {
 849         struct hdac_audio_ctl *ctl, *retctl = NULL;
 850         int i, at, atindex, found = 0;
 851
 852         if (devinfo == NULL || devinfo->function.audio.ctl == NULL)
 853                 return (NULL);
 854
 855         at = cnt;
 856         if (at == 0)
 857                 at = 1;
 858         else if (at < 0)
 859                 at = -1;
 860         atindex = index;
 861         if (atindex < 0)
 862                 atindex = -1;
 863
 864         i = 0;
 865         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
 866                 if (ctl->enable == 0 || ctl->widget == NULL)
 867                         continue;
 868                 if (!(ctl->widget->nid == nid && (atindex == -1 ||
 869                     ctl->index == atindex)))
 870                         continue;
 871                 found++;
 872                 if (found == cnt)
 873                         return (ctl);
 874                 retctl = ctl;
 875         }
 876
 877         return ((at == -1) ? retctl : NULL);
 878 }
 879
 880 static void
 881 hdac_hp_switch_handler(struct hdac_devinfo *devinfo)
 882 {
 883         struct hdac_softc *sc;
 884         struct hdac_widget *w;
 885         struct hdac_audio_ctl *ctl;
 886         uint32_t val, id, res;
 887         int i = 0, j, timeout, forcemute;
 888         nid_t cad;
 889
 890         if (devinfo == NULL || devinfo->codec == NULL ||
 891             devinfo->codec->sc == NULL)
 892                 return;
 893
 894         sc = devinfo->codec->sc;
 895         cad = devinfo->codec->cad;
 896         id = hdac_codec_id(devinfo);
 897         for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
 898                 if (HDA_DEV_MATCH(hdac_hp_switch[i].model,
 899                     sc->pci_subvendor) &&
 900                     hdac_hp_switch[i].id == id)
 901                         break;
 902         }
 903
 904         if (i >= HDAC_HP_SWITCH_LEN)
 905                 return;
 906
 907         forcemute = 0;
 908         if (hdac_hp_switch[i].eapdnid != -1) {
 909                 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid);
 910                 if (w != NULL && w->param.eapdbtl != HDAC_INVALID)
 911                         forcemute = (w->param.eapdbtl &
 912                             HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1;
 913         }
 914
 915         if (hdac_hp_switch[i].execsense != -1)
 916                 hdac_command(sc,
 917                     HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
 918                     hdac_hp_switch[i].execsense), cad);
 919
 920         timeout = 10000;
 921         do {
 922                 res = hdac_command(sc,
 923                     HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid),
 924                     cad);
 925                 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff)
 926                         break;
 927                 DELAY(10);
 928         } while (--timeout != 0);
 929
 930         HDA_BOOTVERBOSE(
 931                 device_printf(sc->dev,
 932                     "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n",
 933                     hdac_hp_switch[i].hpnid, timeout, res);
 934         );
 935
 936         res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res);
 937         res ^= hdac_hp_switch[i].inverted;
 938
 939         switch (hdac_hp_switch[i].type) {
 940         case HDAC_HP_SWITCH_CTL:
 941                 ctl = hdac_audio_ctl_amp_get(devinfo,
 942                     hdac_hp_switch[i].hpnid, 0, 1);
 943                 if (ctl != NULL) {
 944                         val = (res != 0 && forcemute == 0) ?
 945                             HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL;
 946                         if (val != ctl->muted) {
 947                                 ctl->muted = val;
 948                                 hdac_audio_ctl_amp_set(ctl,
 949                                     HDA_AMP_MUTE_DEFAULT, ctl->left,
 950                                     ctl->right);
 951                         }
 952                 }
 953                 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
 954                         ctl = hdac_audio_ctl_amp_get(devinfo,
 955                             hdac_hp_switch[i].spkrnid[j], 0, 1);
 956                         if (ctl == NULL)
 957                                 continue;
 958                         val = (res != 0 || forcemute == 1) ?
 959                             HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE;
 960                         if (val == ctl->muted)
 961                                 continue;
 962                         ctl->muted = val;
 963                         hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
 964                             ctl->left, ctl->right);
 965                 }
 966                 break;
 967         case HDAC_HP_SWITCH_CTRL:
 968                 if (res != 0) {
 969                         /* HP in */
 970                         w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
 971                         if (w != NULL && w->type ==
 972                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
 973                                 if (forcemute == 0)
 974                                         val = w->wclass.pin.ctrl |
 975                                             HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
 976                                 else
 977                                         val = w->wclass.pin.ctrl &
 978                                             ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
 979                                 if (val != w->wclass.pin.ctrl) {
 980                                         w->wclass.pin.ctrl = val;
 981                                         hdac_command(sc,
 982                                             HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
 983                                             w->nid, w->wclass.pin.ctrl), cad);
 984                                 }
 985                         }
 986                         for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
 987                                 w = hdac_widget_get(devinfo,
 988                                     hdac_hp_switch[i].spkrnid[j]);
 989                                 if (w == NULL || w->type !=
 990                                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
 991                                         continue;
 992                                 val = w->wclass.pin.ctrl &
 993                                     ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
 994                                 if (val == w->wclass.pin.ctrl)
 995                                         continue;
 996                                 w->wclass.pin.ctrl = val;
 997                                 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
 998                                     cad, w->nid, w->wclass.pin.ctrl), cad);
 999                         }
1000                 } else {
1001                         /* HP out */
1002                         w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
1003                         if (w != NULL && w->type ==
1004                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
1005                                 val = w->wclass.pin.ctrl &
1006                                     ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1007                                 if (val != w->wclass.pin.ctrl) {
1008                                         w->wclass.pin.ctrl = val;
1009                                         hdac_command(sc,
1010                                             HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
1011                                             w->nid, w->wclass.pin.ctrl), cad);
1012                                 }
1013                         }
1014                         for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
1015                                 w = hdac_widget_get(devinfo,
1016                                     hdac_hp_switch[i].spkrnid[j]);
1017                                 if (w == NULL || w->type !=
1018                                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1019                                         continue;
1020                                 if (forcemute == 0)
1021                                         val = w->wclass.pin.ctrl |
1022                                             HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1023                                 else
1024                                         val = w->wclass.pin.ctrl &
1025                                             ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1026                                 if (val == w->wclass.pin.ctrl)
1027                                         continue;
1028                                 w->wclass.pin.ctrl = val;
1029                                 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
1030                                     cad, w->nid, w->wclass.pin.ctrl), cad);
1031                         }
1032                 }
1033                 break;
1034         case HDAC_HP_SWITCH_DEBUG:
1035                 if (hdac_hp_switch[i].execsense != -1)
1036                         hdac_command(sc,
1037                             HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
1038                             hdac_hp_switch[i].execsense), cad);
1039                 res = hdac_command(sc,
1040                     HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad);
1041                 device_printf(sc->dev,
1042                     "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1043                     hdac_hp_switch[i].hpnid, res);
1044                 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
1045                         w = hdac_widget_get(devinfo,
1046                             hdac_hp_switch[i].spkrnid[j]);
1047                         if (w == NULL || w->type !=
1048                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1049                                 continue;
1050                         if (hdac_hp_switch[i].execsense != -1)
1051                                 hdac_command(sc,
1052                                     HDA_CMD_SET_PIN_SENSE(cad, w->nid,
1053                                     hdac_hp_switch[i].execsense), cad);
1054                         res = hdac_command(sc,
1055                             HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
1056                         device_printf(sc->dev,
1057                             "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1058                             j + 1, w->nid, res);
1059                 }
1060                 break;
1061         default:
1062                 break;
1063         }
1064 }
1065
1066 static void
1067 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag)
1068 {
1069         struct hdac_softc *sc;
1070         struct hdac_devinfo *devinfo = NULL;
1071         device_t *devlist = NULL;
1072         int devcount, i;
1073
1074         if (codec == NULL || codec->sc == NULL)
1075                 return;
1076
1077         sc = codec->sc;
1078
1079         HDA_BOOTVERBOSE(
1080                 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag);
1081         );
1082
1083         device_get_children(sc->dev, &devlist, &devcount);
1084         for (i = 0; devlist != NULL && i < devcount; i++) {
1085                 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
1086                 if (devinfo != NULL && devinfo->node_type ==
1087                     HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
1088                     devinfo->codec != NULL &&
1089                     devinfo->codec->cad == codec->cad) {
1090                         break;
1091                 } else
1092                         devinfo = NULL;
1093         }
1094         if (devlist != NULL)
1095                 kfree(devlist, M_TEMP);
1096
1097         if (devinfo == NULL)
1098                 return;
1099
1100         switch (tag) {
1101         case HDAC_UNSOLTAG_EVENT_HP:
1102                 hdac_hp_switch_handler(devinfo);
1103                 break;
1104         case HDAC_UNSOLTAG_EVENT_TEST:
1105                 device_printf(sc->dev, "Unsol Test!\n");
1106                 break;
1107         default:
1108                 break;
1109         }
1110 }
1111
1112 static int
1113 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch)
1114 {
1115         /* XXX to be removed */
1116 #ifdef HDAC_INTR_EXTRA
1117         uint32_t res;
1118 #endif
1119
1120         if (!(ch->flags & HDAC_CHN_RUNNING))
1121                 return (0);
1122
1123         /* XXX to be removed */
1124 #ifdef HDAC_INTR_EXTRA
1125         res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS);
1126 #endif
1127
1128         /* XXX to be removed */
1129 #ifdef HDAC_INTR_EXTRA
1130         HDA_BOOTVERBOSE(
1131                 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE))
1132                         device_printf(sc->dev,
1133                             "PCMDIR_%s intr triggered beyond stream boundary:"
1134                             "%08x\n",
1135                             (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res);
1136         );
1137 #endif
1138
1139         HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS,
1140             HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
1141
1142         /* XXX to be removed */
1143 #ifdef HDAC_INTR_EXTRA
1144         if (res & HDAC_SDSTS_BCIS) {
1145 #endif
1146                 return (1);
1147         /* XXX to be removed */
1148 #ifdef HDAC_INTR_EXTRA
1149         }
1150 #endif
1151
1152         return (0);
1153 }
1154
1155 /****************************************************************************
1156  * void hdac_intr_handler(void *)
1157  *
1158  * Interrupt handler. Processes interrupts received from the hdac.
1159  ****************************************************************************/
1160 static void
1161 hdac_intr_handler(void *context)
1162 {
1163         struct hdac_softc *sc;
1164         uint32_t intsts;
1165         uint8_t rirbsts;
1166         struct hdac_rirb *rirb_base;
1167         uint32_t trigger;
1168
1169         sc = (struct hdac_softc *)context;
1170
1171         hdac_lock(sc);
1172         if (sc->polling != 0) {
1173                 hdac_unlock(sc);
1174                 return;
1175         }
1176
1177         /* Do we have anything to do? */
1178         intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
1179         if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) {
1180                 hdac_unlock(sc);
1181                 return;
1182         }
1183
1184         trigger = 0;
1185
1186         /* Was this a controller interrupt? */
1187         if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) {
1188                 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
1189                 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1190                 /* Get as many responses that we can */
1191                 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) {
1192                         HDAC_WRITE_1(&sc->mem,
1193                             HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
1194                         if (hdac_rirb_flush(sc) != 0)
1195                                 trigger |= HDAC_TRIGGER_UNSOL;
1196                         rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1197                 }
1198                 /* XXX to be removed */
1199                 /* Clear interrupt and exit */
1200 #ifdef HDAC_INTR_EXTRA
1201                 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS);
1202 #endif
1203         }
1204
1205         if (intsts & HDAC_INTSTS_SIS_MASK) {
1206                 if ((intsts & (1 << sc->num_iss)) &&
1207                     hdac_stream_intr(sc, &sc->play) != 0)
1208                         trigger |= HDAC_TRIGGER_PLAY;
1209                 if ((intsts & (1 << 0)) &&
1210                     hdac_stream_intr(sc, &sc->rec) != 0)
1211                         trigger |= HDAC_TRIGGER_REC;
1212                 /* XXX to be removed */
1213 #ifdef HDAC_INTR_EXTRA
1214                 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts &
1215                     HDAC_INTSTS_SIS_MASK);
1216 #endif
1217         }
1218
1219         hdac_unlock(sc);
1220
1221         if (trigger & HDAC_TRIGGER_PLAY)
1222                 chn_intr(sc->play.c);
1223         if (trigger & HDAC_TRIGGER_REC)
1224                 chn_intr(sc->rec.c);
1225         if (trigger & HDAC_TRIGGER_UNSOL)
1226                 taskqueue_enqueue(taskqueue_swi, &sc->unsolq_task);
1227 }
1228
1229 /****************************************************************************
1230  * int hdac_reset(hdac_softc *)
1231  *
1232  * Reset the hdac to a quiescent and known state.
1233  ****************************************************************************/
1234 static int
1235 hdac_reset(struct hdac_softc *sc)
1236 {
1237         uint32_t gctl;
1238         int count, i;
1239
1240         /*
1241          * Stop all Streams DMA engine
1242          */
1243         for (i = 0; i < sc->num_iss; i++)
1244                 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
1245         for (i = 0; i < sc->num_oss; i++)
1246                 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
1247         for (i = 0; i < sc->num_bss; i++)
1248                 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
1249
1250         /*
1251          * Stop Control DMA engines.
1252          */
1253         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
1254         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
1255
1256         /*
1257          * Reset DMA position buffer.
1258          */
1259         HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
1260         HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
1261
1262         /*
1263          * Reset the controller. The reset must remain asserted for
1264          * a minimum of 100us.
1265          */
1266         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1267         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
1268         count = 10000;
1269         do {
1270                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1271                 if (!(gctl & HDAC_GCTL_CRST))
1272                         break;
1273                 DELAY(10);
1274         } while (--count);
1275         if (gctl & HDAC_GCTL_CRST) {
1276                 device_printf(sc->dev, "Unable to put hdac in reset\n");
1277                 return (ENXIO);
1278         }
1279         DELAY(100);
1280         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1281         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
1282         count = 10000;
1283         do {
1284                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1285                 if (gctl & HDAC_GCTL_CRST)
1286                         break;
1287                 DELAY(10);
1288         } while (--count);
1289         if (!(gctl & HDAC_GCTL_CRST)) {
1290                 device_printf(sc->dev, "Device stuck in reset\n");
1291                 return (ENXIO);
1292         }
1293
1294         /*
1295          * Wait for codecs to finish their own reset sequence. The delay here
1296          * should be of 250us but for some reasons, on it's not enough on my
1297          * computer. Let's use twice as much as necessary to make sure that
1298          * it's reset properly.
1299          */
1300         DELAY(1000);
1301
1302         return (0);
1303 }
1304
1305
1306 /****************************************************************************
1307  * int hdac_get_capabilities(struct hdac_softc *);
1308  *
1309  * Retreive the general capabilities of the hdac;
1310  *      Number of Input Streams
1311  *      Number of Output Streams
1312  *      Number of bidirectional Streams
1313  *      64bit ready
1314  *      CORB and RIRB sizes
1315  ****************************************************************************/
1316 static int
1317 hdac_get_capabilities(struct hdac_softc *sc)
1318 {
1319         uint16_t gcap;
1320         uint8_t corbsize, rirbsize;
1321
1322         gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
1323         sc->num_iss = HDAC_GCAP_ISS(gcap);
1324         sc->num_oss = HDAC_GCAP_OSS(gcap);
1325         sc->num_bss = HDAC_GCAP_BSS(gcap);
1326
1327         sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK);
1328
1329         corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
1330         if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
1331             HDAC_CORBSIZE_CORBSZCAP_256)
1332                 sc->corb_size = 256;
1333         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
1334             HDAC_CORBSIZE_CORBSZCAP_16)
1335                 sc->corb_size = 16;
1336         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
1337             HDAC_CORBSIZE_CORBSZCAP_2)
1338                 sc->corb_size = 2;
1339         else {
1340                 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
1341                     __func__, corbsize);
1342                 return (ENXIO);
1343         }
1344
1345         rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
1346         if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
1347             HDAC_RIRBSIZE_RIRBSZCAP_256)
1348                 sc->rirb_size = 256;
1349         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
1350             HDAC_RIRBSIZE_RIRBSZCAP_16)
1351                 sc->rirb_size = 16;
1352         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
1353             HDAC_RIRBSIZE_RIRBSZCAP_2)
1354                 sc->rirb_size = 2;
1355         else {
1356                 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
1357                     __func__, rirbsize);
1358                 return (ENXIO);
1359         }
1360
1361         return (0);
1362 }
1363
1364
1365 /****************************************************************************
1366  * void hdac_dma_cb
1367  *
1368  * This function is called by bus_dmamap_load when the mapping has been
1369  * established. We just record the physical address of the mapping into
1370  * the struct hdac_dma passed in.
1371  ****************************************************************************/
1372 static void
1373 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
1374 {
1375         struct hdac_dma *dma;
1376
1377         if (error == 0) {
1378                 dma = (struct hdac_dma *)callback_arg;
1379                 dma->dma_paddr = segs[0].ds_addr;
1380         }
1381 }
1382
1383
1384 /****************************************************************************
1385  * int hdac_dma_alloc
1386  *
1387  * This function allocate and setup a dma region (struct hdac_dma).
1388  * It must be freed by a corresponding hdac_dma_free.
1389  ****************************************************************************/
1390 static int
1391 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
1392 {
1393         bus_size_t roundsz;
1394         int result;
1395         int lowaddr;
1396
1397         roundsz = roundup2(size, HDAC_DMA_ALIGNMENT);
1398         lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1399             BUS_SPACE_MAXADDR_32BIT;
1400         bzero(dma, sizeof(*dma));
1401
1402         /*
1403          * Create a DMA tag
1404          */
1405         result = bus_dma_tag_create(NULL,       /* parent */
1406             HDAC_DMA_ALIGNMENT,                 /* alignment */
1407             0,                                  /* boundary */
1408             lowaddr,                            /* lowaddr */
1409             BUS_SPACE_MAXADDR,                  /* highaddr */
1410             NULL,                               /* filtfunc */
1411             NULL,                               /* fistfuncarg */
1412             roundsz,                            /* maxsize */
1413             1,                                  /* nsegments */
1414             roundsz,                            /* maxsegsz */
1415             0,                                  /* flags */
1416             &dma->dma_tag);                     /* dmat */
1417         if (result != 0) {
1418                 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
1419                     __func__, result);
1420                 goto hdac_dma_alloc_fail;
1421         }
1422
1423         /*
1424          * Allocate DMA memory
1425          */
1426 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
1427         result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1428             BUS_DMA_NOWAIT | BUS_DMA_ZERO |
1429             ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
1430             &dma->dma_map);
1431 #else
1432         result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1433             BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map);
1434 #endif
1435         if (result != 0) {
1436                 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
1437                     __func__, result);
1438                 goto hdac_dma_alloc_fail;
1439         }
1440
1441         dma->dma_size = roundsz;
1442
1443         /*
1444          * Map the memory
1445          */
1446         result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
1447             (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
1448         if (result != 0 || dma->dma_paddr == 0) {
1449                 if (result == 0)
1450                         result = ENOMEM;
1451                 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
1452                     __func__, result);
1453                 goto hdac_dma_alloc_fail;
1454         }
1455
1456         HDA_BOOTVERBOSE(
1457                 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
1458                     __func__, (uintmax_t)size, (uintmax_t)roundsz);
1459         );
1460
1461         return (0);
1462
1463 hdac_dma_alloc_fail:
1464         hdac_dma_free(sc, dma);
1465
1466         return (result);
1467 }
1468
1469
1470 /****************************************************************************
1471  * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
1472  *
1473  * Free a struct dhac_dma that has been previously allocated via the
1474  * hdac_dma_alloc function.
1475  ****************************************************************************/
1476 static void
1477 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
1478 {
1479         if (dma->dma_map != NULL) {
1480 #if 0
1481                 /* Flush caches */
1482                 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
1483                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1484 #endif
1485                 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1486         }
1487         if (dma->dma_vaddr != NULL) {
1488                 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1489                 dma->dma_vaddr = NULL;
1490         }
1491         dma->dma_map = NULL;
1492         if (dma->dma_tag != NULL) {
1493                 bus_dma_tag_destroy(dma->dma_tag);
1494                 dma->dma_tag = NULL;
1495         }
1496         dma->dma_size = 0;
1497 }
1498
1499 /****************************************************************************
1500  * int hdac_mem_alloc(struct hdac_softc *)
1501  *
1502  * Allocate all the bus resources necessary to speak with the physical
1503  * controller.
1504  ****************************************************************************/
1505 static int
1506 hdac_mem_alloc(struct hdac_softc *sc)
1507 {
1508         struct hdac_mem *mem;
1509
1510         mem = &sc->mem;
1511         mem->mem_rid = PCIR_BAR(0);
1512         mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1513             &mem->mem_rid, RF_ACTIVE);
1514         if (mem->mem_res == NULL) {
1515                 device_printf(sc->dev,
1516                     "%s: Unable to allocate memory resource\n", __func__);
1517                 return (ENOMEM);
1518         }
1519         mem->mem_tag = rman_get_bustag(mem->mem_res);
1520         mem->mem_handle = rman_get_bushandle(mem->mem_res);
1521
1522         return (0);
1523 }
1524
1525 /****************************************************************************
1526  * void hdac_mem_free(struct hdac_softc *)
1527  *
1528  * Free up resources previously allocated by hdac_mem_alloc.
1529  ****************************************************************************/
1530 static void
1531 hdac_mem_free(struct hdac_softc *sc)
1532 {
1533         struct hdac_mem *mem;
1534
1535         mem = &sc->mem;
1536         if (mem->mem_res != NULL)
1537                 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
1538                     mem->mem_res);
1539         mem->mem_res = NULL;
1540 }
1541
1542 /****************************************************************************
1543  * int hdac_irq_alloc(struct hdac_softc *)
1544  *
1545  * Allocate and setup the resources necessary for interrupt handling.
1546  ****************************************************************************/
1547 static int
1548 hdac_irq_alloc(struct hdac_softc *sc)
1549 {
1550         struct hdac_irq *irq;
1551         int result;
1552
1553         irq = &sc->irq;
1554         irq->irq_rid = 0x0;
1555
1556 #if 0 /* TODO: No MSI support in DragonFly yet. */
1557         if ((sc->flags & HDAC_F_MSI) &&
1558             (result = pci_msi_count(sc->dev)) == 1 &&
1559             pci_alloc_msi(sc->dev, &result) == 0)
1560                 irq->irq_rid = 0x1;
1561         else
1562 #endif
1563                 sc->flags &= ~HDAC_F_MSI;
1564
1565         irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
1566             &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
1567         if (irq->irq_res == NULL) {
1568                 device_printf(sc->dev, "%s: Unable to allocate irq\n",
1569                     __func__);
1570                 goto hdac_irq_alloc_fail;
1571         }
1572         result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE,
1573             hdac_intr_handler, sc, &irq->irq_handle);
1574         if (result != 0) {
1575                 device_printf(sc->dev,
1576                     "%s: Unable to setup interrupt handler (%x)\n",
1577                     __func__, result);
1578                 goto hdac_irq_alloc_fail;
1579         }
1580
1581         return (0);
1582
1583 hdac_irq_alloc_fail:
1584         hdac_irq_free(sc);
1585
1586         return (ENXIO);
1587 }
1588
1589 /****************************************************************************
1590  * void hdac_irq_free(struct hdac_softc *)
1591  *
1592  * Free up resources previously allocated by hdac_irq_alloc.
1593  ****************************************************************************/
1594 static void
1595 hdac_irq_free(struct hdac_softc *sc)
1596 {
1597         struct hdac_irq *irq;
1598
1599         irq = &sc->irq;
1600         if (irq->irq_res != NULL && irq->irq_handle != NULL)
1601                 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
1602         if (irq->irq_res != NULL)
1603                 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1604                     irq->irq_res);
1605 #if 0 /* TODO: No MSI support in DragonFly yet. */
1606         if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1)
1607                 pci_release_msi(sc->dev);
1608 #endif
1609         irq->irq_handle = NULL;
1610         irq->irq_res = NULL;
1611         irq->irq_rid = 0x0;
1612 }
1613
1614 /****************************************************************************
1615  * void hdac_corb_init(struct hdac_softc *)
1616  *
1617  * Initialize the corb registers for operations but do not start it up yet.
1618  * The CORB engine must not be running when this function is called.
1619  ****************************************************************************/
1620 static void
1621 hdac_corb_init(struct hdac_softc *sc)
1622 {
1623         uint8_t corbsize;
1624         uint64_t corbpaddr;
1625
1626         /* Setup the CORB size. */
1627         switch (sc->corb_size) {
1628         case 256:
1629                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
1630                 break;
1631         case 16:
1632                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
1633                 break;
1634         case 2:
1635                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
1636                 break;
1637         default:
1638                 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
1639         }
1640         HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
1641
1642         /* Setup the CORB Address in the hdac */
1643         corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
1644         HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
1645         HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
1646
1647         /* Set the WP and RP */
1648         sc->corb_wp = 0;
1649         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1650         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
1651         /*
1652          * The HDA specification indicates that the CORBRPRST bit will always
1653          * read as zero. Unfortunately, it seems that at least the 82801G
1654          * doesn't reset the bit to zero, which stalls the corb engine.
1655          * manually reset the bit to zero before continuing.
1656          */
1657         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
1658
1659         /* Enable CORB error reporting */
1660 #if 0
1661         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
1662 #endif
1663 }
1664
1665 /****************************************************************************
1666  * void hdac_rirb_init(struct hdac_softc *)
1667  *
1668  * Initialize the rirb registers for operations but do not start it up yet.
1669  * The RIRB engine must not be running when this function is called.
1670  ****************************************************************************/
1671 static void
1672 hdac_rirb_init(struct hdac_softc *sc)
1673 {
1674         uint8_t rirbsize;
1675         uint64_t rirbpaddr;
1676
1677         /* Setup the RIRB size. */
1678         switch (sc->rirb_size) {
1679         case 256:
1680                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
1681                 break;
1682         case 16:
1683                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
1684                 break;
1685         case 2:
1686                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
1687                 break;
1688         default:
1689                 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
1690         }
1691         HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
1692
1693         /* Setup the RIRB Address in the hdac */
1694         rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
1695         HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
1696         HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
1697
1698         /* Setup the WP and RP */
1699         sc->rirb_rp = 0;
1700         HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
1701
1702         if (sc->polling == 0) {
1703                 /* Setup the interrupt threshold */
1704                 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
1705
1706                 /* Enable Overrun and response received reporting */
1707 #if 0
1708                 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
1709                     HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
1710 #else
1711                 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
1712 #endif
1713         }
1714
1715 #if 0
1716         /*
1717          * Make sure that the Host CPU cache doesn't contain any dirty
1718          * cache lines that falls in the rirb. If I understood correctly, it
1719          * should be sufficient to do this only once as the rirb is purely
1720          * read-only from now on.
1721          */
1722         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
1723             BUS_DMASYNC_PREREAD);
1724 #endif
1725 }
1726
1727 /****************************************************************************
1728  * void hdac_corb_start(hdac_softc *)
1729  *
1730  * Startup the corb DMA engine
1731  ****************************************************************************/
1732 static void
1733 hdac_corb_start(struct hdac_softc *sc)
1734 {
1735         uint32_t corbctl;
1736
1737         corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
1738         corbctl |= HDAC_CORBCTL_CORBRUN;
1739         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
1740 }
1741
1742 /****************************************************************************
1743  * void hdac_rirb_start(hdac_softc *)
1744  *
1745  * Startup the rirb DMA engine
1746  ****************************************************************************/
1747 static void
1748 hdac_rirb_start(struct hdac_softc *sc)
1749 {
1750         uint32_t rirbctl;
1751
1752         rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
1753         rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
1754         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
1755 }
1756
1757
1758 /****************************************************************************
1759  * void hdac_scan_codecs(struct hdac_softc *, int)
1760  *
1761  * Scan the bus for available codecs, starting with num.
1762  ****************************************************************************/
1763 static void
1764 hdac_scan_codecs(struct hdac_softc *sc, int num)
1765 {
1766         struct hdac_codec *codec;
1767         int i;
1768         uint16_t statests;
1769
1770         if (num < 0)
1771                 num = 0;
1772         if (num >= HDAC_CODEC_MAX)
1773                 num = HDAC_CODEC_MAX - 1;
1774
1775         statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1776         for (i = num; i < HDAC_CODEC_MAX; i++) {
1777                 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1778                         /* We have found a codec. */
1779                         codec = (struct hdac_codec *)kmalloc(sizeof(*codec),
1780                             M_HDAC, M_ZERO | M_NOWAIT);
1781                         if (codec == NULL) {
1782                                 device_printf(sc->dev,
1783                                     "Unable to allocate memory for codec\n");
1784                                 continue;
1785                         }
1786                         codec->commands = NULL;
1787                         codec->responses_received = 0;
1788                         codec->verbs_sent = 0;
1789                         codec->sc = sc;
1790                         codec->cad = i;
1791                         sc->codecs[i] = codec;
1792                         if (hdac_probe_codec(codec) != 0)
1793                                 break;
1794                 }
1795         }
1796         /* All codecs have been probed, now try to attach drivers to them */
1797         /* bus_generic_attach(sc->dev); */
1798 }
1799
1800 /****************************************************************************
1801  * void hdac_probe_codec(struct hdac_softc *, int)
1802  *
1803  * Probe a the given codec_id for available function groups.
1804  ****************************************************************************/
1805 static int
1806 hdac_probe_codec(struct hdac_codec *codec)
1807 {
1808         struct hdac_softc *sc = codec->sc;
1809         struct hdac_devinfo *devinfo;
1810         uint32_t vendorid, revisionid, subnode;
1811         int startnode;
1812         int endnode;
1813         int i;
1814         nid_t cad = codec->cad;
1815
1816         HDA_BOOTVERBOSE(
1817                 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad);
1818         );
1819         vendorid = hdac_command(sc,
1820             HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID),
1821             cad);
1822         revisionid = hdac_command(sc,
1823             HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID),
1824             cad);
1825         subnode = hdac_command(sc,
1826             HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT),
1827             cad);
1828         startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
1829         endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
1830
1831         HDA_BOOTVERBOSE(
1832                 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n",
1833                     startnode, endnode);
1834         );
1835         for (i = startnode; i < endnode; i++) {
1836                 devinfo = hdac_probe_function(codec, i);
1837                 if (devinfo != NULL) {
1838                         /* XXX Ignore other FG. */
1839                         devinfo->vendor_id =
1840                             HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1841                         devinfo->device_id =
1842                             HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1843                         devinfo->revision_id =
1844                             HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1845                         devinfo->stepping_id =
1846                             HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1847                         HDA_BOOTVERBOSE(
1848                                 device_printf(sc->dev,
1849                                     "HDA_DEBUG: \tFound AFG nid=%d "
1850                                     "[startnode=%d endnode=%d]\n",
1851                                     devinfo->nid, startnode, endnode);
1852                         );
1853                         return (1);
1854                 }
1855         }
1856
1857         HDA_BOOTVERBOSE(
1858                 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n");
1859         );
1860         return (0);
1861 }
1862
1863 static struct hdac_devinfo *
1864 hdac_probe_function(struct hdac_codec *codec, nid_t nid)
1865 {
1866         struct hdac_softc *sc = codec->sc;
1867         struct hdac_devinfo *devinfo;
1868         uint32_t fctgrptype;
1869         nid_t cad = codec->cad;
1870
1871         fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc,
1872             HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad));
1873
1874         /* XXX For now, ignore other FG. */
1875         if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO)
1876                 return (NULL);
1877
1878         devinfo = (struct hdac_devinfo *)kmalloc(sizeof(*devinfo), M_HDAC,
1879             M_NOWAIT | M_ZERO);
1880         if (devinfo == NULL) {
1881                 device_printf(sc->dev, "%s: Unable to allocate ivar\n",
1882                     __func__);
1883                 return (NULL);
1884         }
1885
1886         devinfo->nid = nid;
1887         devinfo->node_type = fctgrptype;
1888         devinfo->codec = codec;
1889
1890         hdac_add_child(sc, devinfo);
1891
1892         return (devinfo);
1893 }
1894
1895 static void
1896 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo)
1897 {
1898         devinfo->dev = device_add_child(sc->dev, NULL, -1);
1899         device_set_ivars(devinfo->dev, (void *)devinfo);
1900         /* XXX - Print more information when booting verbose??? */
1901 }
1902
1903 static void
1904 hdac_widget_connection_parse(struct hdac_widget *w)
1905 {
1906         struct hdac_softc *sc = w->devinfo->codec->sc;
1907         uint32_t res;
1908         int i, j, max, ents, entnum;
1909         nid_t cad = w->devinfo->codec->cad;
1910         nid_t nid = w->nid;
1911         nid_t cnid, addcnid, prevcnid;
1912
1913         w->nconns = 0;
1914
1915         res = hdac_command(sc,
1916             HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad);
1917
1918         ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res);
1919
1920         if (ents < 1)
1921                 return;
1922
1923         entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4;
1924         max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1;
1925         prevcnid = 0;
1926
1927 #define CONN_RMASK(e)           (1 << ((32 / (e)) - 1))
1928 #define CONN_NMASK(e)           (CONN_RMASK(e) - 1)
1929 #define CONN_RESVAL(r, e, n)    ((r) >> ((32 / (e)) * (n)))
1930 #define CONN_RANGE(r, e, n)     (CONN_RESVAL(r, e, n) & CONN_RMASK(e))
1931 #define CONN_CNID(r, e, n)      (CONN_RESVAL(r, e, n) & CONN_NMASK(e))
1932
1933         for (i = 0; i < ents; i += entnum) {
1934                 res = hdac_command(sc,
1935                     HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad);
1936                 for (j = 0; j < entnum; j++) {
1937                         cnid = CONN_CNID(res, entnum, j);
1938                         if (cnid == 0) {
1939                                 if (w->nconns < ents)
1940                                         device_printf(sc->dev,
1941                                             "%s: nid=%d WARNING: zero cnid "
1942                                             "entnum=%d j=%d index=%d "
1943                                             "entries=%d found=%d res=0x%08x\n",
1944                                             __func__, nid, entnum, j, i,
1945                                             ents, w->nconns, res);
1946                                 else
1947                                         goto getconns_out;
1948                         }
1949                         if (cnid < w->devinfo->startnode ||
1950                             cnid >= w->devinfo->endnode) {
1951                                 HDA_BOOTVERBOSE(
1952                                         device_printf(sc->dev,
1953                                             "%s: GHOST: nid=%d j=%d "
1954                                             "entnum=%d index=%d res=0x%08x\n",
1955                                             __func__, nid, j, entnum, i, res);
1956                                 );
1957                         }
1958                         if (CONN_RANGE(res, entnum, j) == 0)
1959                                 addcnid = cnid;
1960                         else if (prevcnid == 0 || prevcnid >= cnid) {
1961                                 device_printf(sc->dev,
1962                                     "%s: WARNING: Invalid child range "
1963                                     "nid=%d index=%d j=%d entnum=%d "
1964                                     "prevcnid=%d cnid=%d res=0x%08x\n",
1965                                     __func__, nid, i, j, entnum, prevcnid,
1966                                     cnid, res);
1967                                 addcnid = cnid;
1968                         } else
1969                                 addcnid = prevcnid + 1;
1970                         while (addcnid <= cnid) {
1971                                 if (w->nconns > max) {
1972                                         device_printf(sc->dev,
1973                                             "%s: nid=%d: Adding %d: "
1974                                             "Max connection reached! max=%d\n",
1975                                             __func__, nid, addcnid, max + 1);
1976                                         goto getconns_out;
1977                                 }
1978                                 w->conns[w->nconns++] = addcnid++;
1979                         }
1980                         prevcnid = cnid;
1981                 }
1982         }
1983
1984 getconns_out:
1985         HDA_BOOTVERBOSE(
1986                 device_printf(sc->dev,
1987                     "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n",
1988                     __func__, nid, ents, w->nconns);
1989         );
1990         return;
1991 }
1992
1993 static uint32_t
1994 hdac_widget_pin_getconfig(struct hdac_widget *w)
1995 {
1996         struct hdac_softc *sc;
1997         uint32_t config, orig, id;
1998         nid_t cad, nid;
1999
2000         sc = w->devinfo->codec->sc;
2001         cad = w->devinfo->codec->cad;
2002         nid = w->nid;
2003         id = hdac_codec_id(w->devinfo);
2004
2005         config = hdac_command(sc,
2006             HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid),
2007             cad);
2008         orig = config;
2009
2010         /*
2011          * XXX REWRITE!!!! Don't argue!
2012          */
2013         if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) {
2014                 switch (nid) {
2015                 case 26:
2016                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2017                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2018                         break;
2019                 case 27:
2020                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2021                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;
2022                         break;
2023                 default:
2024                         break;
2025                 }
2026         } else if (id == HDA_CODEC_ALC880 &&
2027             (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR ||
2028             sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) {
2029                 /*
2030                  * Super broken BIOS
2031                  */
2032                 switch (nid) {
2033                 case 20:
2034                         break;
2035                 case 21:
2036                         break;
2037                 case 22:
2038                         break;
2039                 case 23:
2040                         break;
2041                 case 24:        /* MIC1 */
2042                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2043                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2044                         break;
2045                 case 25:        /* XXX MIC2 */
2046                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2047                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2048                         break;
2049                 case 26:        /* LINE1 */
2050                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2051                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2052                         break;
2053                 case 27:        /* XXX LINE2 */
2054                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2055                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2056                         break;
2057                 case 28:        /* CD */
2058                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2059                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
2060                         break;
2061                 case 30:
2062                         break;
2063                 case 31:
2064                         break;
2065                 default:
2066                         break;
2067                 }
2068         } else if (id == HDA_CODEC_ALC883 &&
2069             (sc->pci_subvendor == MSI_MS034A_SUBVENDOR ||
2070             HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) {
2071                 switch (nid) {
2072                 case 25:
2073                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2074                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2075                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2076                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2077                         break;
2078                 case 28:
2079                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2080                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2081                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2082                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2083                         break;
2084                 default:
2085                         break;
2086                 }
2087         } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor ==
2088             HP_V3000_SUBVENDOR) {
2089                 switch (nid) {
2090                 case 18:
2091                         config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2092                         config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2093                         break;
2094                 case 20:
2095                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2096                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2097                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2098                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2099                         break;
2100                 case 21:
2101                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2102                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2103                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2104                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2105                         break;
2106                 default:
2107                         break;
2108                 }
2109         } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor ==
2110             HP_DV5000_SUBVENDOR) {
2111                 switch (nid) {
2112                 case 20:
2113                 case 21:
2114                         config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2115                         config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2116                         break;
2117                 default:
2118                         break;
2119                 }
2120         } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2121             ASUS_W6F_SUBVENDOR) {
2122                 switch (nid) {
2123                 case 11:
2124                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2125                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2126                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
2127                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2128                         break;
2129                 case 15:
2130                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2131                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2132                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2133                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2134                         break;
2135                 default:
2136                         break;
2137                 }
2138         } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2139             UNIWILL_9075_SUBVENDOR) {
2140                 switch (nid) {
2141                 case 15:
2142                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2143                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2144                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2145                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2146                         break;
2147                 default:
2148                         break;
2149                 }
2150         } else if (id == HDA_CODEC_AD1986A &&
2151             (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR ||
2152             sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) {
2153                 switch (nid) {
2154                 case 28:        /* LINE */
2155                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2156                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2157                         break;
2158                 case 29:        /* MIC */
2159                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2160                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2161                         break;
2162                 default:
2163                         break;
2164                 }
2165         }
2166
2167         HDA_BOOTVERBOSE(
2168                 if (config != orig)
2169                         device_printf(sc->dev,
2170                             "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n",
2171                             nid, orig, config);
2172         );
2173
2174         return (config);
2175 }
2176
2177 static uint32_t
2178 hdac_widget_pin_getcaps(struct hdac_widget *w)
2179 {
2180         struct hdac_softc *sc;
2181         uint32_t caps, orig, id;
2182         nid_t cad, nid;
2183
2184         sc = w->devinfo->codec->sc;
2185         cad = w->devinfo->codec->cad;
2186         nid = w->nid;
2187         id = hdac_codec_id(w->devinfo);
2188
2189         caps = hdac_command(sc,
2190             HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad);
2191         orig = caps;
2192
2193         HDA_BOOTVERBOSE(
2194                 if (caps != orig)
2195                         device_printf(sc->dev,
2196                             "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n",
2197                             nid, orig, caps);
2198         );
2199
2200         return (caps);
2201 }
2202
2203 static void
2204 hdac_widget_pin_parse(struct hdac_widget *w)
2205 {
2206         struct hdac_softc *sc = w->devinfo->codec->sc;
2207         uint32_t config, pincap;
2208         char *devstr, *connstr;
2209         nid_t cad = w->devinfo->codec->cad;
2210         nid_t nid = w->nid;
2211
2212         config = hdac_widget_pin_getconfig(w);
2213         w->wclass.pin.config = config;
2214
2215         pincap = hdac_widget_pin_getcaps(w);
2216         w->wclass.pin.cap = pincap;
2217
2218         w->wclass.pin.ctrl = hdac_command(sc,
2219             HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) &
2220             ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
2221             HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
2222             HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
2223             HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
2224
2225         if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
2226                 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
2227         if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
2228                 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
2229         if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
2230                 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
2231         if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) {
2232                 w->param.eapdbtl = hdac_command(sc,
2233                     HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad);
2234                 w->param.eapdbtl &= 0x7;
2235                 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2236         } else
2237                 w->param.eapdbtl = HDAC_INVALID;
2238
2239         switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
2240         case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT:
2241                 devstr = "line out";
2242                 break;
2243         case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
2244                 devstr = "speaker";
2245                 break;
2246         case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT:
2247                 devstr = "headphones out";
2248                 break;
2249         case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
2250                 devstr = "CD";
2251                 break;
2252         case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT:
2253                 devstr = "SPDIF out";
2254                 break;
2255         case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT:
2256                 devstr = "digital (other) out";
2257                 break;
2258         case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE:
2259                 devstr = "modem, line side";
2260                 break;
2261         case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET:
2262                 devstr = "modem, handset side";
2263                 break;
2264         case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
2265                 devstr = "line in";
2266                 break;
2267         case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX:
2268                 devstr = "AUX";
2269                 break;
2270         case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
2271                 devstr = "Mic in";
2272                 break;
2273         case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY:
2274                 devstr = "telephony";
2275                 break;
2276         case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN:
2277                 devstr = "SPDIF in";
2278                 break;
2279         case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN:
2280                 devstr = "digital (other) in";
2281                 break;
2282         case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER:
2283                 devstr = "other";
2284                 break;
2285         default:
2286                 devstr = "unknown";
2287                 break;
2288         }
2289
2290         switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) {
2291         case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK:
2292                 connstr = "jack";
2293                 break;
2294         case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE:
2295                 connstr = "none";
2296                 break;
2297         case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED:
2298                 connstr = "fixed";
2299                 break;
2300         case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH:
2301                 connstr = "jack / fixed";
2302                 break;
2303         default:
2304                 connstr = "unknown";
2305                 break;
2306         }
2307
2308         strlcat(w->name, ": ", sizeof(w->name));
2309         strlcat(w->name, devstr, sizeof(w->name));
2310         strlcat(w->name, " (", sizeof(w->name));
2311         strlcat(w->name, connstr, sizeof(w->name));
2312         strlcat(w->name, ")", sizeof(w->name));
2313 }
2314
2315 static void
2316 hdac_widget_parse(struct hdac_widget *w)
2317 {
2318         struct hdac_softc *sc = w->devinfo->codec->sc;
2319         uint32_t wcap, cap;
2320         char *typestr;
2321         nid_t cad = w->devinfo->codec->cad;
2322         nid_t nid = w->nid;
2323
2324         wcap = hdac_command(sc,
2325             HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP),
2326             cad);
2327         w->param.widget_cap = wcap;
2328         w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap);
2329
2330         switch (w->type) {
2331         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
2332                 typestr = "audio output";
2333                 break;
2334         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
2335                 typestr = "audio input";
2336                 break;
2337         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
2338                 typestr = "audio mixer";
2339                 break;
2340         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
2341                 typestr = "audio selector";
2342                 break;
2343         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
2344                 typestr = "pin";
2345                 break;
2346         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET:
2347                 typestr = "power widget";
2348                 break;
2349         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET:
2350                 typestr = "volume widget";
2351                 break;
2352         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
2353                 typestr = "beep widget";
2354                 break;
2355         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET:
2356                 typestr = "vendor widget";
2357                 break;
2358         default:
2359                 typestr = "unknown type";
2360                 break;
2361         }
2362
2363         strlcpy(w->name, typestr, sizeof(w->name));
2364
2365         if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) {
2366                 hdac_command(sc,
2367                     HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0),
2368                     cad);
2369                 DELAY(1000);
2370         }
2371
2372         hdac_widget_connection_parse(w);
2373
2374         if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) {
2375                 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2376                         w->param.outamp_cap =
2377                             hdac_command(sc,
2378                             HDA_CMD_GET_PARAMETER(cad, nid,
2379                             HDA_PARAM_OUTPUT_AMP_CAP), cad);
2380                 else
2381                         w->param.outamp_cap =
2382                             w->devinfo->function.audio.outamp_cap;
2383         } else
2384                 w->param.outamp_cap = 0;
2385
2386         if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) {
2387                 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2388                         w->param.inamp_cap =
2389                             hdac_command(sc,
2390                             HDA_CMD_GET_PARAMETER(cad, nid,
2391                             HDA_PARAM_INPUT_AMP_CAP), cad);
2392                 else
2393                         w->param.inamp_cap =
2394                             w->devinfo->function.audio.inamp_cap;
2395         } else
2396                 w->param.inamp_cap = 0;
2397
2398         if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
2399             w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
2400                 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) {
2401                         cap = hdac_command(sc,
2402                             HDA_CMD_GET_PARAMETER(cad, nid,
2403                             HDA_PARAM_SUPP_STREAM_FORMATS), cad);
2404                         w->param.supp_stream_formats = (cap != 0) ? cap :
2405                             w->devinfo->function.audio.supp_stream_formats;
2406                         cap = hdac_command(sc,
2407                             HDA_CMD_GET_PARAMETER(cad, nid,
2408                             HDA_PARAM_SUPP_PCM_SIZE_RATE), cad);
2409                         w->param.supp_pcm_size_rate = (cap != 0) ? cap :
2410                             w->devinfo->function.audio.supp_pcm_size_rate;
2411                 } else {
2412                         w->param.supp_stream_formats =
2413                             w->devinfo->function.audio.supp_stream_formats;
2414                         w->param.supp_pcm_size_rate =
2415                             w->devinfo->function.audio.supp_pcm_size_rate;
2416                 }
2417         } else {
2418                 w->param.supp_stream_formats = 0;
2419                 w->param.supp_pcm_size_rate = 0;
2420         }
2421
2422         if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
2423                 hdac_widget_pin_parse(w);
2424 }
2425
2426 static struct hdac_widget *
2427 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid)
2428 {
2429         if (devinfo == NULL || devinfo->widget == NULL ||
2430                     nid < devinfo->startnode || nid >= devinfo->endnode)
2431                 return (NULL);
2432         return (&devinfo->widget[nid - devinfo->startnode]);
2433 }
2434
2435 static __inline int
2436 hda_poll_channel(struct hdac_chan *ch)
2437 {
2438         uint32_t sz, delta;
2439         volatile uint32_t ptr;
2440
2441         if (!(ch->flags & HDAC_CHN_RUNNING))
2442                 return (0);
2443
2444         sz = ch->blksz * ch->blkcnt;
2445         if (ch->dmapos != NULL)
2446                 ptr = *(ch->dmapos);
2447         else
2448                 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem,
2449                     ch->off + HDAC_SDLPIB);
2450         ch->ptr = ptr;
2451         ptr %= sz;
2452         ptr &= ~(ch->blksz - 1);
2453         delta = (sz + ptr - ch->prevptr) % sz;
2454
2455         if (delta < ch->blksz)
2456                 return (0);
2457
2458         ch->prevptr = ptr;
2459
2460         return (1);
2461 }
2462
2463 #define hda_chan_active(sc)    (((sc)->play.flags | (sc)->rec.flags) & \
2464                                 HDAC_CHN_RUNNING)
2465
2466 static void
2467 hda_poll_callback(void *arg)
2468 {
2469         struct hdac_softc *sc = arg;
2470         uint32_t trigger;
2471
2472         if (sc == NULL)
2473                 return;
2474
2475         hdac_lock(sc);
2476         if (sc->polling == 0 || hda_chan_active(sc) == 0) {
2477                 hdac_unlock(sc);
2478                 return;
2479         }
2480
2481         trigger = 0;
2482         trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0;
2483         trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0;
2484
2485         /* XXX */
2486         callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/,
2487             hda_poll_callback, sc);
2488
2489         hdac_unlock(sc);
2490
2491         if (trigger & HDAC_TRIGGER_PLAY)
2492                 chn_intr(sc->play.c);
2493         if (trigger & HDAC_TRIGGER_REC)
2494                 chn_intr(sc->rec.c);
2495 }
2496
2497 static int
2498 hdac_rirb_flush(struct hdac_softc *sc)
2499 {
2500         struct hdac_rirb *rirb_base, *rirb;
2501         struct hdac_codec *codec;
2502         struct hdac_command_list *commands;
2503         nid_t cad;
2504         uint32_t resp;
2505         uint8_t rirbwp;
2506         int ret;
2507
2508         rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2509         rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
2510 #if 0
2511         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2512             BUS_DMASYNC_POSTREAD);
2513 #endif
2514         ret = 0;
2515
2516         while (sc->rirb_rp != rirbwp) {
2517                 sc->rirb_rp++;
2518                 sc->rirb_rp %= sc->rirb_size;
2519                 rirb = &rirb_base[sc->rirb_rp];
2520                 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
2521                 if (cad < 0 || cad >= HDAC_CODEC_MAX ||
2522                     sc->codecs[cad] == NULL)
2523                         continue;
2524                 resp = rirb->response;
2525                 codec = sc->codecs[cad];
2526                 commands = codec->commands;
2527                 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
2528                         sc->unsolq[sc->unsolq_wp++] = (cad << 16) |
2529                             ((resp >> 26) & 0xffff);
2530                         sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
2531                 } else if (commands != NULL && commands->num_commands > 0 &&
2532                     codec->responses_received < commands->num_commands)
2533                         commands->responses[codec->responses_received++] =
2534                             resp;
2535                 ret++;
2536         }
2537
2538         return (ret);
2539 }
2540
2541 static int
2542 hdac_unsolq_flush(struct hdac_softc *sc)
2543 {
2544         nid_t cad;
2545         uint32_t tag;
2546         int ret = 0;
2547
2548         if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
2549                 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
2550                 while (sc->unsolq_rp != sc->unsolq_wp) {
2551                         cad = sc->unsolq[sc->unsolq_rp] >> 16;
2552                         tag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
2553                         sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
2554                         hdac_unsolicited_handler(sc->codecs[cad], tag);
2555                         ret++;
2556                 }
2557                 sc->unsolq_st = HDAC_UNSOLQ_READY;
2558         }
2559
2560         return (ret);
2561 }
2562
2563 static void
2564 hdac_poll_callback(void *arg)
2565 {
2566         struct hdac_softc *sc = arg;
2567         if (sc == NULL)
2568                 return;
2569
2570         hdac_lock(sc);
2571         if (sc->polling == 0 || sc->poll_ival == 0) {
2572                 hdac_unlock(sc);
2573                 return;
2574         }
2575         if (hdac_rirb_flush(sc) != 0)
2576                 hdac_unsolq_flush(sc);
2577         callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc);
2578         hdac_unlock(sc);
2579 }
2580
2581 static void
2582 hdac_stream_stop(struct hdac_chan *ch)
2583 {
2584         struct hdac_softc *sc = ch->devinfo->codec->sc;
2585         uint32_t ctl;
2586
2587         ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2588         ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2589             HDAC_SDCTL_RUN);
2590         HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2591
2592         ch->flags &= ~HDAC_CHN_RUNNING;
2593
2594         if (sc->polling != 0) {
2595                 int pollticks;
2596
2597                 if (hda_chan_active(sc) == 0) {
2598                         callout_stop(&sc->poll_hda);
2599                         sc->poll_ticks = 1;
2600                 } else {
2601                         if (sc->play.flags & HDAC_CHN_RUNNING)
2602                                 ch = &sc->play;
2603                         else
2604                                 ch = &sc->rec;
2605                         pollticks = ((uint64_t)hz * ch->blksz) /
2606                             ((uint64_t)sndbuf_getbps(ch->b) *
2607                             sndbuf_getspd(ch->b));
2608                         pollticks >>= 2;
2609                         if (pollticks > hz)
2610                                 pollticks = hz;
2611                         if (pollticks < 1) {
2612                                 HDA_BOOTVERBOSE(
2613                                         device_printf(sc->dev,
2614                                             "%s: pollticks=%d < 1 !\n",
2615                                             __func__, pollticks);
2616                                 );
2617                                 pollticks = 1;
2618                         }
2619                         if (pollticks > sc->poll_ticks) {
2620                                 HDA_BOOTVERBOSE(
2621                                         device_printf(sc->dev,
2622                                             "%s: pollticks %d -> %d\n",
2623                                             __func__, sc->poll_ticks,
2624                                             pollticks);
2625                                 );
2626                                 sc->poll_ticks = pollticks;
2627                                 callout_reset(&sc->poll_hda, 1,
2628                                     hda_poll_callback, sc);
2629                         }
2630                 }
2631         } else {
2632                 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2633                 ctl &= ~(1 << (ch->off >> 5));
2634                 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2635         }
2636 }
2637
2638 static void
2639 hdac_stream_start(struct hdac_chan *ch)
2640 {
2641         struct hdac_softc *sc = ch->devinfo->codec->sc;
2642         uint32_t ctl;
2643
2644         if (sc->polling != 0) {
2645                 int pollticks;
2646
2647                 pollticks = ((uint64_t)hz * ch->blksz) /
2648                     ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b));
2649                 pollticks >>= 2;
2650                 if (pollticks > hz)
2651                         pollticks = hz;
2652                 if (pollticks < 1) {
2653                         HDA_BOOTVERBOSE(
2654                                 device_printf(sc->dev,
2655                                     "%s: pollticks=%d < 1 !\n",
2656                                     __func__, pollticks);
2657                         );
2658                         pollticks = 1;
2659                 }
2660                 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) {
2661                         HDA_BOOTVERBOSE(
2662                                 if (hda_chan_active(sc) == 0) {
2663                                         device_printf(sc->dev,
2664                                             "%s: pollticks=%d\n",
2665                                             __func__, pollticks);
2666                                 } else {
2667                                         device_printf(sc->dev,
2668                                             "%s: pollticks %d -> %d\n",
2669                                             __func__, sc->poll_ticks,
2670                                             pollticks);
2671                                 }
2672                         );
2673                         sc->poll_ticks = pollticks;
2674                         callout_reset(&sc->poll_hda, 1, hda_poll_callback,
2675                             sc);
2676                 }
2677                 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2678                 ctl |= HDAC_SDCTL_RUN;
2679         } else {
2680                 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2681                 ctl |= 1 << (ch->off >> 5);
2682                 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2683                 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2684                 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2685                     HDAC_SDCTL_RUN;
2686         }
2687         HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2688
2689         ch->flags |= HDAC_CHN_RUNNING;
2690 }
2691
2692 static void
2693 hdac_stream_reset(struct hdac_chan *ch)
2694 {
2695         struct hdac_softc *sc = ch->devinfo->codec->sc;
2696         int timeout = 1000;
2697         int to = timeout;
2698         uint32_t ctl;
2699
2700         ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2701         ctl |= HDAC_SDCTL_SRST;
2702         HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2703         do {
2704                 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2705                 if (ctl & HDAC_SDCTL_SRST)
2706                         break;
2707                 DELAY(10);
2708         } while (--to);
2709         if (!(ctl & HDAC_SDCTL_SRST)) {
2710                 device_printf(sc->dev, "timeout in reset\n");
2711         }
2712         ctl &= ~HDAC_SDCTL_SRST;
2713         HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2714         to = timeout;
2715         do {
2716                 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2717                 if (!(ctl & HDAC_SDCTL_SRST))
2718                         break;
2719                 DELAY(10);
2720         } while (--to);
2721         if (ctl & HDAC_SDCTL_SRST)
2722                 device_printf(sc->dev, "can't reset!\n");
2723 }
2724
2725 static void
2726 hdac_stream_setid(struct hdac_chan *ch)
2727 {
2728         struct hdac_softc *sc = ch->devinfo->codec->sc;
2729         uint32_t ctl;
2730
2731         ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2);
2732         ctl &= ~HDAC_SDCTL2_STRM_MASK;
2733         ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT;
2734         HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl);
2735 }
2736
2737 static void
2738 hdac_bdl_setup(struct hdac_chan *ch)
2739 {
2740         struct hdac_softc *sc = ch->devinfo->codec->sc;
2741         struct hdac_bdle *bdle;
2742         uint64_t addr;
2743         uint32_t blksz, blkcnt;
2744         int i;
2745
2746         addr = (uint64_t)sndbuf_getbufaddr(ch->b);
2747         bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr;
2748
2749         if (sc->polling != 0) {
2750                 blksz = ch->blksz * ch->blkcnt;
2751                 blkcnt = 1;
2752         } else {
2753                 blksz = ch->blksz;
2754                 blkcnt = ch->blkcnt;
2755         }
2756
2757         for (i = 0; i < blkcnt; i++, bdle++) {
2758                 bdle->addrl = (uint32_t)addr;
2759                 bdle->addrh = (uint32_t)(addr >> 32);
2760                 bdle->len = blksz;
2761                 bdle->ioc = 1 ^ sc->polling;
2762                 addr += blksz;
2763         }
2764
2765         HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt);
2766         HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1);
2767         addr = ch->bdl_dma.dma_paddr;
2768         HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr);
2769         HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
2770         if (ch->dmapos != NULL &&
2771             !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) {
2772                 addr = sc->pos_dma.dma_paddr;
2773                 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
2774                     ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001);
2775                 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32));
2776         }
2777 }
2778
2779 static int
2780 hdac_bdl_alloc(struct hdac_chan *ch)
2781 {
2782         struct hdac_softc *sc = ch->devinfo->codec->sc;
2783         int rc;
2784
2785         rc = hdac_dma_alloc(sc, &ch->bdl_dma,
2786             sizeof(struct hdac_bdle) * HDA_BDL_MAX);
2787         if (rc) {
2788                 device_printf(sc->dev, "can't alloc bdl\n");
2789                 return (rc);
2790         }
2791
2792         return (0);
2793 }
2794
2795 static void
2796 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid,
2797                                         int index, int lmute, int rmute,
2798                                         int left, int right, int dir)
2799 {
2800         uint16_t v = 0;
2801
2802         if (sc == NULL)
2803                 return;
2804
2805         if (left != right || lmute != rmute) {
2806                 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) |
2807                     (lmute << 7) | left;
2808                 hdac_command(sc,
2809                     HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2810                 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) |
2811                     (rmute << 7) | right;
2812         } else
2813                 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) |
2814                     (lmute << 7) | left;
2815
2816         hdac_command(sc,
2817             HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2818 }
2819
2820 static void
2821 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute,
2822                                                 int left, int right)
2823 {
2824         struct hdac_softc *sc;
2825         nid_t nid, cad;
2826         int lmute, rmute;
2827
2828         if (ctl == NULL || ctl->widget == NULL ||
2829             ctl->widget->devinfo == NULL ||
2830             ctl->widget->devinfo->codec == NULL ||
2831             ctl->widget->devinfo->codec->sc == NULL)
2832                 return;
2833
2834         sc = ctl->widget->devinfo->codec->sc;
2835         cad = ctl->widget->devinfo->codec->cad;
2836         nid = ctl->widget->nid;
2837
2838         if (mute == HDA_AMP_MUTE_DEFAULT) {
2839                 lmute = HDA_AMP_LEFT_MUTED(ctl->muted);
2840                 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted);
2841         } else {
2842                 lmute = HDA_AMP_LEFT_MUTED(mute);
2843                 rmute = HDA_AMP_RIGHT_MUTED(mute);
2844         }
2845
2846         if (ctl->dir & HDA_CTL_OUT)
2847                 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2848                     lmute, rmute, left, right, 0);
2849         if (ctl->dir & HDA_CTL_IN)
2850                 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2851                     lmute, rmute, left, right, 1);
2852         ctl->left = left;
2853         ctl->right = right;
2854 }
2855
2856 static void
2857 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index)
2858 {
2859         if (w == NULL || w->nconns < 1 || index > (w->nconns - 1))
2860                 return;
2861         hdac_command(w->devinfo->codec->sc,
2862             HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad,
2863             w->nid, index), w->devinfo->codec->cad);
2864         w->selconn = index;
2865 }
2866
2867
2868 /****************************************************************************
2869  * uint32_t hdac_command_sendone_internal
2870  *
2871  * Wrapper function that sends only one command to a given codec
2872  ****************************************************************************/
2873 static uint32_t
2874 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad)
2875 {
2876         struct hdac_command_list cl;
2877         uint32_t response = HDAC_INVALID;
2878
2879         if (!hdac_lockowned(sc))
2880                 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
2881         cl.num_commands = 1;
2882         cl.verbs = &verb;
2883         cl.responses = &response;
2884
2885         hdac_command_send_internal(sc, &cl, cad);
2886
2887         return (response);
2888 }
2889
2890 /****************************************************************************
2891  * hdac_command_send_internal
2892  *
2893  * Send a command list to the codec via the corb. We queue as much verbs as
2894  * we can and msleep on the codec. When the interrupt get the responses
2895  * back from the rirb, it will wake us up so we can queue the remaining verbs
2896  * if any.
2897  ****************************************************************************/
2898 static void
2899 hdac_command_send_internal(struct hdac_softc *sc,
2900                         struct hdac_command_list *commands, nid_t cad)
2901 {
2902         struct hdac_codec *codec;
2903         int corbrp;
2904         uint32_t *corb;
2905         int timeout;
2906         int retry = 10;
2907         struct hdac_rirb *rirb_base;
2908
2909         if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL ||
2910             commands->num_commands < 1)
2911                 return;
2912
2913         codec = sc->codecs[cad];
2914         codec->commands = commands;
2915         codec->responses_received = 0;
2916         codec->verbs_sent = 0;
2917         corb = (uint32_t *)sc->corb_dma.dma_vaddr;
2918         rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2919
2920         do {
2921                 if (codec->verbs_sent != commands->num_commands) {
2922                         /* Queue as many verbs as possible */
2923                         corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP);
2924 #if 0
2925                         bus_dmamap_sync(sc->corb_dma.dma_tag,
2926                             sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
2927 #endif
2928                         while (codec->verbs_sent != commands->num_commands &&
2929                             ((sc->corb_wp + 1) % sc->corb_size) != corbrp) {
2930                                 sc->corb_wp++;
2931                                 sc->corb_wp %= sc->corb_size;
2932                                 corb[sc->corb_wp] =
2933                                     commands->verbs[codec->verbs_sent++];
2934                         }
2935
2936                         /* Send the verbs to the codecs */
2937 #if 0
2938                         bus_dmamap_sync(sc->corb_dma.dma_tag,
2939                             sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
2940 #endif
2941                         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
2942                 }
2943
2944                 timeout = 1000;
2945                 while (hdac_rirb_flush(sc) == 0 && --timeout)
2946                         DELAY(10);
2947         } while ((codec->verbs_sent != commands->num_commands ||
2948             codec->responses_received != commands->num_commands) && --retry);
2949
2950         if (retry == 0)
2951                 device_printf(sc->dev,
2952                     "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n",
2953                     __func__, commands->num_commands, codec->verbs_sent,
2954                     codec->responses_received);
2955
2956         codec->commands = NULL;
2957         codec->responses_received = 0;
2958         codec->verbs_sent = 0;
2959
2960         hdac_unsolq_flush(sc);
2961 }
2962
2963
2964 /****************************************************************************
2965  * Device Methods
2966  ****************************************************************************/
2967
2968 /****************************************************************************
2969  * int hdac_probe(device_t)
2970  *
2971  * Probe for the presence of an hdac. If none is found, check for a generic
2972  * match using the subclass of the device.
2973  ****************************************************************************/
2974 static int
2975 hdac_probe(device_t dev)
2976 {
2977         int i, result;
2978         uint32_t model;
2979         uint16_t class, subclass;
2980         char desc[64];
2981
2982         model = (uint32_t)pci_get_device(dev) << 16;
2983         model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
2984         class = pci_get_class(dev);
2985         subclass = pci_get_subclass(dev);
2986
2987         bzero(desc, sizeof(desc));
2988         result = ENXIO;
2989         for (i = 0; i < HDAC_DEVICES_LEN; i++) {
2990                 if (hdac_devices[i].model == model) {
2991                         strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2992                         result = BUS_PROBE_DEFAULT;
2993                         break;
2994                 }
2995                 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
2996                     class == PCIC_MULTIMEDIA &&
2997                     subclass == PCIS_MULTIMEDIA_HDA) {
2998                         strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2999                         result = BUS_PROBE_GENERIC;
3000                         break;
3001                 }
3002         }
3003         if (result == ENXIO && class == PCIC_MULTIMEDIA &&
3004             subclass == PCIS_MULTIMEDIA_HDA) {
3005                 strlcpy(desc, "Generic", sizeof(desc));
3006                 result = BUS_PROBE_GENERIC;
3007         }
3008         if (result != ENXIO) {
3009                 strlcat(desc, " High Definition Audio Controller",
3010                     sizeof(desc));
3011                 device_set_desc_copy(dev, desc);
3012         }
3013
3014         return (result);
3015 }
3016
3017 static void *
3018 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b,
3019                                         struct pcm_channel *c, int dir)
3020 {
3021         struct hdac_devinfo *devinfo = data;
3022         struct hdac_softc *sc = devinfo->codec->sc;
3023         struct hdac_chan *ch;
3024
3025         hdac_lock(sc);
3026         if (dir == PCMDIR_PLAY) {
3027                 ch = &sc->play;
3028                 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5;
3029                 devinfo->function.audio.playcnt++;
3030         } else {
3031                 ch = &sc->rec;
3032                 ch->off = devinfo->function.audio.reccnt << 5;
3033                 devinfo->function.audio.reccnt++;
3034         }
3035         if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) {
3036                 ch->caps.minspeed = ch->caps.maxspeed = 48000;
3037                 ch->pcmrates[0] = 48000;
3038                 ch->pcmrates[1] = 0;
3039         }
3040         if (sc->pos_dma.dma_vaddr != NULL)
3041                 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr +
3042                     (sc->streamcnt * 8));
3043         else
3044                 ch->dmapos = NULL;
3045         ch->sid = ++sc->streamcnt;
3046         ch->dir = dir;
3047         ch->b = b;
3048         ch->c = c;
3049         ch->devinfo = devinfo;
3050         ch->blksz = sc->chan_size / sc->chan_blkcnt;
3051         ch->blkcnt = sc->chan_blkcnt;
3052         hdac_unlock(sc);
3053
3054         if (hdac_bdl_alloc(ch) != 0) {
3055                 ch->blkcnt = 0;
3056                 return (NULL);
3057         }
3058
3059         if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0)
3060                 return (NULL);
3061
3062         HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), sndbuf_getmaxsize(ch->b),
3063             PAT_UNCACHEABLE);
3064
3065         return (ch);
3066 }
3067
3068 static int
3069 hdac_channel_free(kobj_t obj, void *data)
3070 {
3071         struct hdac_softc *sc;
3072         struct hdac_chan *ch;
3073
3074         ch = (struct hdac_chan *)data;
3075         sc = (ch != NULL && ch->devinfo != NULL && ch->devinfo->codec != NULL) ?
3076             ch->devinfo->codec->sc : NULL;
3077         if (ch != NULL && sc != NULL) {
3078                 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b),
3079                     sndbuf_getmaxsize(ch->b), PAT_WRITE_BACK);
3080         }
3081
3082         return (1);
3083 }
3084
3085 static int
3086 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format)
3087 {
3088         struct hdac_chan *ch = data;
3089         int i;
3090
3091         for (i = 0; ch->caps.fmtlist[i] != 0; i++) {
3092                 if (format == ch->caps.fmtlist[i]) {
3093                         ch->fmt = format;
3094                         return (0);
3095                 }
3096         }
3097
3098         return (EINVAL);
3099 }
3100
3101 static int
3102 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed)
3103 {
3104         struct hdac_chan *ch = data;
3105         uint32_t spd = 0, threshold;
3106         int i;
3107
3108         for (i = 0; ch->pcmrates[i] != 0; i++) {
3109                 spd = ch->pcmrates[i];
3110                 threshold = spd + ((ch->pcmrates[i + 1] != 0) ?
3111                     ((ch->pcmrates[i + 1] - spd) >> 1) : 0);
3112                 if (speed < threshold)
3113                         break;
3114         }
3115
3116         if (spd == 0)   /* impossible */
3117                 ch->spd = 48000;
3118         else
3119                 ch->spd = spd;
3120
3121         return (ch->spd);
3122 }
3123
3124 static void
3125 hdac_stream_setup(struct hdac_chan *ch)
3126 {
3127         struct hdac_softc *sc = ch->devinfo->codec->sc;
3128         int i;
3129         nid_t cad = ch->devinfo->codec->cad;
3130         uint16_t fmt;
3131
3132         fmt = 0;
3133         if (ch->fmt & AFMT_S16_LE)
3134                 fmt |= ch->bit16 << 4;
3135         else if (ch->fmt & AFMT_S32_LE)
3136                 fmt |= ch->bit32 << 4;
3137         else
3138                 fmt |= 1 << 4;
3139
3140         for (i = 0; i < HDA_RATE_TAB_LEN; i++) {
3141                 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) {
3142                         fmt |= hda_rate_tab[i].base;
3143                         fmt |= hda_rate_tab[i].mul;
3144                         fmt |= hda_rate_tab[i].div;
3145                         break;
3146                 }
3147         }
3148
3149         if (ch->fmt & AFMT_STEREO)
3150                 fmt |= 1;
3151
3152         HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt);
3153
3154         for (i = 0; ch->io[i] != -1; i++) {
3155                 HDA_BOOTVERBOSE(
3156                         device_printf(sc->dev,
3157                             "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d "
3158                             "fmt=0x%08x\n",
3159                             (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3160                             ch->io[i], fmt);
3161                 );
3162                 hdac_command(sc,
3163                     HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad);
3164                 hdac_command(sc,
3165                     HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3166                     ch->sid << 4), cad);
3167         }
3168 }
3169
3170 static int
3171 hdac_channel_setfragments(kobj_t obj, void *data,
3172                                         uint32_t blksz, uint32_t blkcnt)
3173 {
3174         struct hdac_chan *ch = data;
3175         struct hdac_softc *sc = ch->devinfo->codec->sc;
3176
3177         blksz &= HDA_BLK_ALIGN;
3178
3179         if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN))
3180                 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN;
3181         if (blksz < HDA_BLK_MIN)
3182                 blksz = HDA_BLK_MIN;
3183         if (blkcnt > HDA_BDL_MAX)
3184                 blkcnt = HDA_BDL_MAX;
3185         if (blkcnt < HDA_BDL_MIN)
3186                 blkcnt = HDA_BDL_MIN;
3187
3188         while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) {
3189                 if ((blkcnt >> 1) >= HDA_BDL_MIN)
3190                         blkcnt >>= 1;
3191                 else if ((blksz >> 1) >= HDA_BLK_MIN)
3192                         blksz >>= 1;
3193                 else
3194                         break;
3195         }
3196
3197         if ((sndbuf_getblksz(ch->b) != blksz ||
3198             sndbuf_getblkcnt(ch->b) != blkcnt) &&
3199             sndbuf_resize(ch->b, blkcnt, blksz) != 0)
3200                 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
3201                     __func__, blksz, blkcnt);
3202
3203         ch->blksz = sndbuf_getblksz(ch->b);
3204         ch->blkcnt = sndbuf_getblkcnt(ch->b);
3205
3206         return (1);
3207 }
3208
3209 static int
3210 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz)
3211 {
3212         struct hdac_chan *ch = data;
3213         struct hdac_softc *sc = ch->devinfo->codec->sc;
3214
3215         hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt);
3216
3217         return (ch->blksz);
3218 }
3219
3220 static void
3221 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch)
3222 {
3223         struct hdac_devinfo *devinfo = ch->devinfo;
3224         nid_t cad = devinfo->codec->cad;
3225         int i;
3226
3227         hdac_stream_stop(ch);
3228
3229         for (i = 0; ch->io[i] != -1; i++) {
3230                 hdac_command(sc,
3231                     HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3232                     0), cad);
3233         }
3234 }
3235
3236 static void
3237 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch)
3238 {
3239         ch->ptr = 0;
3240         ch->prevptr = 0;
3241         hdac_stream_stop(ch);
3242         hdac_stream_reset(ch);
3243         hdac_bdl_setup(ch);
3244         hdac_stream_setid(ch);
3245         hdac_stream_setup(ch);
3246         hdac_stream_start(ch);
3247 }
3248
3249 static int
3250 hdac_channel_trigger(kobj_t obj, void *data, int go)
3251 {
3252         struct hdac_chan *ch = data;
3253         struct hdac_softc *sc = ch->devinfo->codec->sc;
3254
3255         if (!(go == PCMTRIG_START || go == PCMTRIG_STOP || go == PCMTRIG_ABORT))
3256                 return (0);
3257
3258         hdac_lock(sc);
3259         switch (go) {
3260         case PCMTRIG_START:
3261                 hdac_channel_start(sc, ch);
3262                 break;
3263         case PCMTRIG_STOP:
3264         case PCMTRIG_ABORT:
3265                 hdac_channel_stop(sc, ch);
3266                 break;
3267         default:
3268                 break;
3269         }
3270         hdac_unlock(sc);
3271
3272         return (0);
3273 }
3274
3275 static int
3276 hdac_channel_getptr(kobj_t obj, void *data)
3277 {
3278         struct hdac_chan *ch = data;
3279         struct hdac_softc *sc = ch->devinfo->codec->sc;
3280         uint32_t ptr;
3281
3282         hdac_lock(sc);
3283         if (sc->polling != 0)
3284                 ptr = ch->ptr;
3285         else if (ch->dmapos != NULL)
3286                 ptr = *(ch->dmapos);
3287         else
3288                 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB);
3289         hdac_unlock(sc);
3290
3291         /*
3292          * Round to available space and force 128 bytes aligment.
3293          */
3294         ptr %= ch->blksz * ch->blkcnt;
3295         ptr &= HDA_BLK_ALIGN;
3296
3297         return (ptr);
3298 }
3299
3300 static struct pcmchan_caps *
3301 hdac_channel_getcaps(kobj_t obj, void *data)
3302 {
3303         return (&((struct hdac_chan *)data)->caps);
3304 }
3305
3306 static kobj_method_t hdac_channel_methods[] = {
3307         KOBJMETHOD(channel_init,                hdac_channel_init),
3308         KOBJMETHOD(channel_free,                hdac_channel_free),
3309         KOBJMETHOD(channel_setformat,           hdac_channel_setformat),
3310         KOBJMETHOD(channel_setspeed,            hdac_channel_setspeed),
3311         KOBJMETHOD(channel_setblocksize,        hdac_channel_setblocksize),
3312         KOBJMETHOD(channel_trigger,             hdac_channel_trigger),
3313         KOBJMETHOD(channel_getptr,              hdac_channel_getptr),
3314         KOBJMETHOD(channel_getcaps,             hdac_channel_getcaps),
3315         { 0, 0 }
3316 };
3317 CHANNEL_DECLARE(hdac_channel);
3318
3319 static void
3320 hdac_jack_poll_callback(void *arg)
3321 {
3322         struct hdac_devinfo *devinfo = arg;
3323         struct hdac_softc *sc;
3324
3325         if (devinfo == NULL || devinfo->codec == NULL ||
3326             devinfo->codec->sc == NULL)
3327                 return;
3328         sc = devinfo->codec->sc;
3329         hdac_lock(sc);
3330         if (sc->poll_ival == 0) {
3331                 hdac_unlock(sc);
3332                 return;
3333         }
3334         hdac_hp_switch_handler(devinfo);
3335         callout_reset(&sc->poll_jack, sc->poll_ival,
3336             hdac_jack_poll_callback, devinfo);
3337         hdac_unlock(sc);
3338 }
3339
3340 static int
3341 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m)
3342 {
3343         struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3344         struct hdac_softc *sc = devinfo->codec->sc;
3345         struct hdac_widget *w, *cw;
3346         struct hdac_audio_ctl *ctl;
3347         uint32_t mask, recmask, id;
3348         int i, j, softpcmvol;
3349         nid_t cad;
3350
3351         hdac_lock(sc);
3352
3353         mask = 0;
3354         recmask = 0;
3355
3356         id = hdac_codec_id(devinfo);
3357         cad = devinfo->codec->cad;
3358         for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
3359                 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model,
3360                     sc->pci_subvendor) && hdac_hp_switch[i].id == id))
3361                         continue;
3362                 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
3363                 if (w == NULL || w->enable == 0 || w->type !=
3364                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
3365                         continue;
3366                 if (hdac_hp_switch[i].polling != 0)
3367                         callout_reset(&sc->poll_jack, 1,
3368                             hdac_jack_poll_callback, devinfo);
3369                 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap))
3370                         hdac_command(sc,
3371                             HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid,
3372                             HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE |
3373                             HDAC_UNSOLTAG_EVENT_HP), cad);
3374                 else
3375                         continue;
3376                 hdac_hp_switch_handler(devinfo);
3377                 HDA_BOOTVERBOSE(
3378                         device_printf(sc->dev,
3379                             "HDA_DEBUG: Enabling headphone/speaker "
3380                             "audio routing switching:\n");
3381                         device_printf(sc->dev,
3382                             "HDA_DEBUG: \tindex=%d nid=%d "
3383                             "pci_subvendor=0x%08x "
3384                             "codec=0x%08x [%s]\n",
3385                             i, w->nid, sc->pci_subvendor, id,
3386                             (hdac_hp_switch[i].polling != 0) ? "POLL" :
3387                             "UNSOL");
3388                 );
3389                 break;
3390         }
3391         for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3392                 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3393                     sc->pci_subvendor) &&
3394                     hdac_eapd_switch[i].id == id))
3395                         continue;
3396                 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3397                 if (w == NULL || w->enable == 0)
3398                         break;
3399                 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3400                     w->param.eapdbtl == HDAC_INVALID)
3401                         break;
3402                 mask |= SOUND_MASK_OGAIN;
3403                 break;
3404         }
3405
3406         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3407                 w = hdac_widget_get(devinfo, i);
3408                 if (w == NULL || w->enable == 0)
3409                         continue;
3410                 mask |= w->ctlflags;
3411                 if (!(w->pflags & HDA_ADC_RECSEL))
3412                         continue;
3413                 for (j = 0; j < w->nconns; j++) {
3414                         cw = hdac_widget_get(devinfo, w->conns[j]);
3415                         if (cw == NULL || cw->enable == 0)
3416                                 continue;
3417                         recmask |= cw->ctlflags;
3418                 }
3419         }
3420
3421         if (!(mask & SOUND_MASK_PCM)) {
3422                 softpcmvol = 1;
3423                 mask |= SOUND_MASK_PCM;
3424         } else
3425                 softpcmvol = (devinfo->function.audio.quirks &
3426                     HDA_QUIRK_SOFTPCMVOL) ? 1 : 0;
3427
3428         i = 0;
3429         ctl = NULL;
3430         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3431                 if (ctl->widget == NULL || ctl->enable == 0)
3432                         continue;
3433                 if (!(ctl->ossmask & SOUND_MASK_PCM))
3434                         continue;
3435                 if (ctl->step > 0)
3436                         break;
3437         }
3438
3439         if (softpcmvol == 1 || ctl == NULL) {
3440                 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL);
3441                 HDA_BOOTVERBOSE(
3442                         device_printf(sc->dev,
3443                             "HDA_DEBUG: %s Soft PCM volume\n",
3444                             (softpcmvol == 1) ?
3445                             "Forcing" : "Enabling");
3446                 );
3447                 i = 0;
3448                 /*
3449                  * XXX Temporary quirk for STAC9220, until the parser
3450                  *     become smarter.
3451                  */
3452                 if (id == HDA_CODEC_STAC9220) {
3453                         mask |= SOUND_MASK_VOLUME;
3454                         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3455                             NULL) {
3456                                 if (ctl->widget == NULL || ctl->enable == 0)
3457                                         continue;
3458                                 if (ctl->widget->nid == 11 && ctl->index == 0) {
3459                                         ctl->ossmask = SOUND_MASK_VOLUME;
3460                                         ctl->ossval = 100 | (100 << 8);
3461                                 } else
3462                                         ctl->ossmask &= ~SOUND_MASK_VOLUME;
3463                         }
3464                 } else if (id == HDA_CODEC_STAC9221) {
3465                         mask |= SOUND_MASK_VOLUME;
3466                         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3467                             NULL) {
3468                                 if (ctl->widget == NULL)
3469                                         continue;
3470                                 if (ctl->widget->type ==
3471                                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
3472                                     ctl->index == 0 && (ctl->widget->nid == 2 ||
3473                                     ctl->widget->enable != 0)) {
3474                                         ctl->enable = 1;
3475                                         ctl->ossmask = SOUND_MASK_VOLUME;
3476                                         ctl->ossval = 100 | (100 << 8);
3477                                 } else if (ctl->enable == 0)
3478                                         continue;
3479                                 else
3480                                         ctl->ossmask &= ~SOUND_MASK_VOLUME;
3481                         }
3482                 } else {
3483                         mix_setparentchild(m, SOUND_MIXER_VOLUME,
3484                             SOUND_MASK_PCM);
3485                         if (!(mask & SOUND_MASK_VOLUME))
3486                                 mix_setrealdev(m, SOUND_MIXER_VOLUME,
3487                                     SOUND_MIXER_NONE);
3488                         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3489                             NULL) {
3490                                 if (ctl->widget == NULL || ctl->enable == 0)
3491                                         continue;
3492                                 if (!HDA_FLAG_MATCH(ctl->ossmask,
3493                                     SOUND_MASK_VOLUME | SOUND_MASK_PCM))
3494                                         continue;
3495                                 if (!(ctl->mute == 1 && ctl->step == 0))
3496                                         ctl->enable = 0;
3497                         }
3498                 }
3499         }
3500
3501         recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER |
3502             SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN |
3503             SOUND_MASK_OGAIN);
3504         recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3505         mask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3506
3507         mix_setrecdevs(m, recmask);
3508         mix_setdevs(m, mask);
3509
3510         hdac_unlock(sc);
3511
3512         return (0);
3513 }
3514
3515 static int
3516 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev,
3517                                         unsigned left, unsigned right)
3518 {
3519         struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3520         struct hdac_softc *sc = devinfo->codec->sc;
3521         struct hdac_widget *w;
3522         struct hdac_audio_ctl *ctl;
3523         uint32_t id, mute;
3524         int lvol, rvol, mlvol, mrvol;
3525         int i = 0;
3526
3527         hdac_lock(sc);
3528         if (dev == SOUND_MIXER_OGAIN) {
3529                 uint32_t orig;
3530                 /*if (left != right || !(left == 0 || left == 1)) {
3531                         hdac_unlock(sc);
3532                         return (-1);
3533                 }*/
3534                 id = hdac_codec_id(devinfo);
3535                 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3536                         if (HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3537                             sc->pci_subvendor) &&
3538                             hdac_eapd_switch[i].id == id)
3539                                 break;
3540                 }
3541                 if (i >= HDAC_EAPD_SWITCH_LEN) {
3542                         hdac_unlock(sc);
3543                         return (-1);
3544                 }
3545                 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3546                 if (w == NULL ||
3547                     w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3548                     w->param.eapdbtl == HDAC_INVALID) {
3549                         hdac_unlock(sc);
3550                         return (-1);
3551                 }
3552                 orig = w->param.eapdbtl;
3553                 if (left == 0)
3554                         w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3555                 else
3556                         w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3557                 if (orig != w->param.eapdbtl) {
3558                         uint32_t val;
3559
3560                         if (hdac_eapd_switch[i].hp_switch != 0)
3561                                 hdac_hp_switch_handler(devinfo);
3562                         val = w->param.eapdbtl;
3563                         if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV)
3564                                 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3565                         hdac_command(sc,
3566                             HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad,
3567                             w->nid, val), devinfo->codec->cad);
3568                 }
3569                 hdac_unlock(sc);
3570                 return (left | (left << 8));
3571         }
3572         if (dev == SOUND_MIXER_VOLUME)
3573                 devinfo->function.audio.mvol = left | (right << 8);
3574
3575         mlvol = devinfo->function.audio.mvol & 0x7f;
3576         mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f;
3577         lvol = 0;
3578         rvol = 0;
3579
3580         i = 0;
3581         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3582                 if (ctl->widget == NULL || ctl->enable == 0 ||
3583                     !(ctl->ossmask & (1 << dev)))
3584                         continue;
3585                 switch (dev) {
3586                 case SOUND_MIXER_VOLUME:
3587                         lvol = ((ctl->ossval & 0x7f) * left) / 100;
3588                         lvol = (lvol * ctl->step) / 100;
3589                         rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100;
3590                         rvol = (rvol * ctl->step) / 100;
3591                         break;
3592                 default:
3593                         if (ctl->ossmask & SOUND_MASK_VOLUME) {
3594                                 lvol = (left * mlvol) / 100;
3595                                 lvol = (lvol * ctl->step) / 100;
3596                                 rvol = (right * mrvol) / 100;
3597                                 rvol = (rvol * ctl->step) / 100;
3598                         } else {
3599                                 lvol = (left * ctl->step) / 100;
3600                                 rvol = (right * ctl->step) / 100;
3601                         }
3602                         ctl->ossval = left | (right << 8);
3603                         break;
3604                 }
3605                 mute = 0;
3606                 if (ctl->step < 1) {
3607                         mute |= (left == 0) ? HDA_AMP_MUTE_LEFT :
3608                             (ctl->muted & HDA_AMP_MUTE_LEFT);
3609                         mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT :
3610                             (ctl->muted & HDA_AMP_MUTE_RIGHT);
3611                 } else {
3612                         mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT :
3613                             (ctl->muted & HDA_AMP_MUTE_LEFT);
3614                         mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT :
3615                             (ctl->muted & HDA_AMP_MUTE_RIGHT);
3616                 }
3617                 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol);
3618         }
3619         hdac_unlock(sc);
3620
3621         return (left | (right << 8));
3622 }
3623
3624 static int
3625 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src)
3626 {
3627         struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3628         struct hdac_widget *w, *cw;
3629         struct hdac_softc *sc = devinfo->codec->sc;
3630         uint32_t ret = src, target;
3631         int i, j;
3632
3633         target = 0;
3634         for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
3635                 if (src & (1 << i)) {
3636                         target = 1 << i;
3637                         break;
3638                 }
3639         }
3640
3641         hdac_lock(sc);
3642
3643         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3644                 w = hdac_widget_get(devinfo, i);
3645                 if (w == NULL || w->enable == 0)
3646                         continue;
3647                 if (!(w->pflags & HDA_ADC_RECSEL))
3648                         continue;
3649                 for (j = 0; j < w->nconns; j++) {
3650                         cw = hdac_widget_get(devinfo, w->conns[j]);
3651                         if (cw == NULL || cw->enable == 0)
3652                                 continue;
3653                         if ((target == SOUND_MASK_VOLUME &&
3654                             cw->type !=
3655                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
3656                             (target != SOUND_MASK_VOLUME &&
3657                             cw->type ==
3658                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER))
3659                                 continue;
3660                         if (cw->ctlflags & target) {
3661                                 if (!(w->pflags & HDA_ADC_LOCKED))
3662                                         hdac_widget_connection_select(w, j);
3663                                 ret = target;
3664                                 j += w->nconns;
3665                         }
3666                 }
3667         }
3668
3669         hdac_unlock(sc);
3670
3671         return (ret);
3672 }
3673
3674 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = {
3675         KOBJMETHOD(mixer_init,          hdac_audio_ctl_ossmixer_init),
3676         KOBJMETHOD(mixer_set,           hdac_audio_ctl_ossmixer_set),
3677         KOBJMETHOD(mixer_setrecsrc,     hdac_audio_ctl_ossmixer_setrecsrc),
3678         { 0, 0 }
3679 };
3680 MIXER_DECLARE(hdac_audio_ctl_ossmixer);
3681
3682 static void
3683 hdac_unsolq_task(void *context, int pending)
3684 {
3685         struct hdac_softc *sc;
3686
3687         sc = (struct hdac_softc *)context;
3688
3689         hdac_lock(sc);
3690         hdac_unsolq_flush(sc);
3691         hdac_unlock(sc);
3692 }
3693
3694 /****************************************************************************
3695  * int hdac_attach(device_t)
3696  *
3697  * Attach the device into the kernel. Interrupts usually won't be enabled
3698  * when this function is called. Setup everything that doesn't require
3699  * interrupts and defer probing of codecs until interrupts are enabled.
3700  ****************************************************************************/
3701 static int
3702 hdac_attach(device_t dev)
3703 {
3704         struct hdac_softc *sc;
3705         int result;
3706         int i;
3707         uint16_t vendor;
3708         uint8_t v;
3709
3710         sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
3711         sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME);
3712         sc->dev = dev;
3713         sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16;
3714         sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff;
3715         vendor = pci_get_vendor(dev);
3716
3717         if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) {
3718                 /* Screw nx6325 - subdevice/subvendor swapped */
3719                 sc->pci_subvendor = HP_NX6325_SUBVENDOR;
3720         }
3721
3722         callout_init(&sc->poll_hda);
3723         callout_init(&sc->poll_hdac);
3724         callout_init(&sc->poll_jack);
3725
3726         TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
3727
3728         sc->poll_ticks = 1;
3729         sc->poll_ival = HDAC_POLL_INTERVAL;
3730         if (resource_int_value(device_get_name(dev),
3731             device_get_unit(dev), "polling", &i) == 0 && i != 0)
3732                 sc->polling = 1;
3733         else
3734                 sc->polling = 0;
3735
3736         sc->chan_size = pcm_getbuffersize(dev,
3737             HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX);
3738
3739         if (resource_int_value(device_get_name(dev),
3740             device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
3741                 i &= HDA_BLK_ALIGN;
3742                 if (i < HDA_BLK_MIN)
3743                         i = HDA_BLK_MIN;
3744                 sc->chan_blkcnt = sc->chan_size / i;
3745                 i = 0;
3746                 while (sc->chan_blkcnt >> i)
3747                         i++;
3748                 sc->chan_blkcnt = 1 << (i - 1);
3749                 if (sc->chan_blkcnt < HDA_BDL_MIN)
3750                         sc->chan_blkcnt = HDA_BDL_MIN;
3751                 else if (sc->chan_blkcnt > HDA_BDL_MAX)
3752                         sc->chan_blkcnt = HDA_BDL_MAX;
3753         } else
3754                 sc->chan_blkcnt = HDA_BDL_DEFAULT;
3755
3756         result = bus_dma_tag_create(NULL,       /* parent */
3757             HDAC_DMA_ALIGNMENT,                 /* alignment */
3758             0,                                  /* boundary */
3759             BUS_SPACE_MAXADDR_32BIT,            /* lowaddr */
3760             BUS_SPACE_MAXADDR,                  /* highaddr */
3761             NULL,                               /* filtfunc */
3762             NULL,                               /* fistfuncarg */
3763             sc->chan_size,                      /* maxsize */
3764             1,                                  /* nsegments */
3765             sc->chan_size,                      /* maxsegsz */
3766             0,                                  /* flags */
3767             &sc->chan_dmat);                    /* dmat */
3768         if (result != 0) {
3769                 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
3770                      __func__, result);
3771                 snd_mtxfree(sc->lock);
3772                 kfree(sc, M_DEVBUF);
3773                 return (ENXIO);
3774         }
3775
3776
3777         sc->hdabus = NULL;
3778         for (i = 0; i < HDAC_CODEC_MAX; i++)
3779                 sc->codecs[i] = NULL;
3780
3781         pci_enable_busmaster(dev);
3782
3783         if (vendor == INTEL_VENDORID) {
3784                 /* TCSEL -> TC0 */
3785                 v = pci_read_config(dev, 0x44, 1);
3786                 pci_write_config(dev, 0x44, v & 0xf8, 1);
3787                 HDA_BOOTVERBOSE(
3788                         device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
3789                             pci_read_config(dev, 0x44, 1));
3790                 );
3791         }
3792 #if 0 /* TODO: No MSI support yet in DragonFly. */
3793         if (resource_int_value(device_get_name(dev),
3794             device_get_unit(dev), "msi", &i) == 0 && i != 0 &&
3795             pci_msi_count(dev) == 1)
3796                 sc->flags |= HDAC_F_MSI;
3797         else
3798 #endif
3799                 sc->flags &= ~HDAC_F_MSI;
3800
3801 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3802         sc->flags |= HDAC_F_DMA_NOCACHE;
3803
3804         if (resource_int_value(device_get_name(dev),
3805             device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
3806 #else
3807         sc->flags &= ~HDAC_F_DMA_NOCACHE;
3808 #endif
3809                 /*
3810                  * Try to enable PCIe snoop to avoid messing around with
3811                  * uncacheable DMA attribute. Since PCIe snoop register
3812                  * config is pretty much vendor specific, there are no
3813                  * general solutions on how to enable it, forcing us (even
3814                  * Microsoft) to enable uncacheable or write combined DMA
3815                  * by default.
3816                  *
3817                  * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
3818                  */
3819                 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
3820                         if (hdac_pcie_snoop[i].vendor != vendor)
3821                                 continue;
3822                         sc->flags &= ~HDAC_F_DMA_NOCACHE;
3823                         if (hdac_pcie_snoop[i].reg == 0x00)
3824                                 break;
3825                         v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3826                         if ((v & hdac_pcie_snoop[i].enable) ==
3827                             hdac_pcie_snoop[i].enable)
3828                                 break;
3829                         v &= hdac_pcie_snoop[i].mask;
3830                         v |= hdac_pcie_snoop[i].enable;
3831                         pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
3832                         v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3833                         if ((v & hdac_pcie_snoop[i].enable) !=
3834                             hdac_pcie_snoop[i].enable) {
3835                                 HDA_BOOTVERBOSE(
3836                                         device_printf(dev,
3837                                             "WARNING: Failed to enable PCIe "
3838                                             "snoop!\n");
3839                                 );
3840 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3841                                 sc->flags |= HDAC_F_DMA_NOCACHE;
3842 #endif
3843                         }
3844                         break;
3845                 }
3846 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3847         }
3848 #endif
3849
3850         HDA_BOOTVERBOSE(
3851                 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
3852                     (sc->flags & HDAC_F_DMA_NOCACHE) ?
3853                     "Uncacheable" : "PCIe snoop", vendor);
3854         );
3855
3856         /* Allocate resources */
3857         result = hdac_mem_alloc(sc);
3858         if (result != 0)
3859                 goto hdac_attach_fail;
3860         result = hdac_irq_alloc(sc);
3861         if (result != 0)
3862                 goto hdac_attach_fail;
3863
3864         /* Get Capabilities */
3865         result = hdac_get_capabilities(sc);
3866         if (result != 0)
3867                 goto hdac_attach_fail;
3868
3869         /* Allocate CORB and RIRB dma memory */
3870         result = hdac_dma_alloc(sc, &sc->corb_dma,
3871             sc->corb_size * sizeof(uint32_t));
3872         if (result != 0)
3873                 goto hdac_attach_fail;
3874         result = hdac_dma_alloc(sc, &sc->rirb_dma,
3875             sc->rirb_size * sizeof(struct hdac_rirb));
3876         if (result != 0)
3877                 goto hdac_attach_fail;
3878
3879         /* Quiesce everything */
3880         hdac_reset(sc);
3881
3882         /* Initialize the CORB and RIRB */
3883         hdac_corb_init(sc);
3884         hdac_rirb_init(sc);
3885
3886         /* Defer remaining of initialization until interrupts are enabled */
3887         sc->intrhook.ich_func = hdac_attach2;
3888         sc->intrhook.ich_arg = (void *)sc;
3889         if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
3890                 sc->intrhook.ich_func = NULL;
3891                 hdac_attach2((void *)sc);
3892         }
3893
3894         return (0);
3895
3896 hdac_attach_fail:
3897         hdac_irq_free(sc);
3898         hdac_dma_free(sc, &sc->rirb_dma);
3899         hdac_dma_free(sc, &sc->corb_dma);
3900         hdac_mem_free(sc);
3901         snd_mtxfree(sc->lock);
3902         kfree(sc, M_DEVBUF);
3903
3904         return (ENXIO);
3905 }
3906
3907 static void
3908 hdac_audio_parse(struct hdac_devinfo *devinfo)
3909 {
3910         struct hdac_softc *sc = devinfo->codec->sc;
3911         struct hdac_widget *w;
3912         uint32_t res;
3913         int i;
3914         nid_t cad, nid;
3915
3916         cad = devinfo->codec->cad;
3917         nid = devinfo->nid;
3918
3919         hdac_command(sc,
3920             HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad);
3921
3922         DELAY(100);
3923
3924         res = hdac_command(sc,
3925             HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad);
3926
3927         devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res);
3928         devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res);
3929         devinfo->endnode = devinfo->startnode + devinfo->nodecnt;
3930
3931         res = hdac_command(sc,
3932             HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad);
3933         devinfo->function.audio.gpio = res;
3934
3935         HDA_BOOTVERBOSE(
3936                 device_printf(sc->dev, "       Vendor: 0x%08x\n",
3937                     devinfo->vendor_id);
3938                 device_printf(sc->dev, "       Device: 0x%08x\n",
3939                     devinfo->device_id);
3940                 device_printf(sc->dev, "     Revision: 0x%08x\n",
3941                     devinfo->revision_id);
3942                 device_printf(sc->dev, "     Stepping: 0x%08x\n",
3943                     devinfo->stepping_id);
3944                 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n",
3945                     sc->pci_subvendor);
3946                 device_printf(sc->dev, "        Nodes: start=%d "
3947                     "endnode=%d total=%d\n",
3948                     devinfo->startnode, devinfo->endnode, devinfo->nodecnt);
3949                 device_printf(sc->dev, "    CORB size: %d\n", sc->corb_size);
3950                 device_printf(sc->dev, "    RIRB size: %d\n", sc->rirb_size);
3951                 device_printf(sc->dev, "      Streams: ISS=%d OSS=%d BSS=%d\n",
3952                     sc->num_iss, sc->num_oss, sc->num_bss);
3953                 device_printf(sc->dev, "         GPIO: 0x%08x\n",
3954                     devinfo->function.audio.gpio);
3955                 device_printf(sc->dev, "               NumGPIO=%d NumGPO=%d "
3956                     "NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
3957                     HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
3958                     HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
3959                     HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
3960                     HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
3961                     HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
3962         );
3963
3964         res = hdac_command(sc,
3965             HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS),
3966             cad);
3967         devinfo->function.audio.supp_stream_formats = res;
3968
3969         res = hdac_command(sc,
3970             HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE),
3971             cad);
3972         devinfo->function.audio.supp_pcm_size_rate = res;
3973
3974         res = hdac_command(sc,
3975             HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP),
3976             cad);
3977         devinfo->function.audio.outamp_cap = res;
3978
3979         res = hdac_command(sc,
3980             HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP),
3981             cad);
3982         devinfo->function.audio.inamp_cap = res;
3983
3984         if (devinfo->nodecnt > 0)
3985                 devinfo->widget = (struct hdac_widget *)kmalloc(
3986                     sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC,
3987                     M_NOWAIT | M_ZERO);
3988         else
3989                 devinfo->widget = NULL;
3990
3991         if (devinfo->widget == NULL) {
3992                 device_printf(sc->dev, "unable to allocate widgets!\n");
3993                 devinfo->endnode = devinfo->startnode;
3994                 devinfo->nodecnt = 0;
3995                 return;
3996         }
3997
3998         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3999                 w = hdac_widget_get(devinfo, i);
4000                 if (w == NULL)
4001                         device_printf(sc->dev, "Ghost widget! nid=%d!\n", i);
4002                 else {
4003                         w->devinfo = devinfo;
4004                         w->nid = i;
4005                         w->enable = 1;
4006                         w->selconn = -1;
4007                         w->pflags = 0;
4008                         w->ctlflags = 0;
4009                         w->param.eapdbtl = HDAC_INVALID;
4010                         hdac_widget_parse(w);
4011                 }
4012         }
4013 }
4014
4015 static void
4016 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo)
4017 {
4018         struct hdac_softc *sc = devinfo->codec->sc;
4019         struct hdac_audio_ctl *ctls;
4020         struct hdac_widget *w, *cw;
4021         int i, j, cnt, max, ocap, icap;
4022         int mute, offset, step, size;
4023
4024         /* XXX This is redundant */
4025         max = 0;
4026         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4027                 w = hdac_widget_get(devinfo, i);
4028                 if (w == NULL || w->enable == 0)
4029                         continue;
4030                 if (w->param.outamp_cap != 0)
4031                         max++;
4032                 if (w->param.inamp_cap != 0) {
4033                         switch (w->type) {
4034                         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4035                         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4036                                 for (j = 0; j < w->nconns; j++) {
4037                                         cw = hdac_widget_get(devinfo,
4038                                             w->conns[j]);
4039                                         if (cw == NULL || cw->enable == 0)
4040                                                 continue;
4041                                         max++;
4042                                 }
4043                                 break;
4044                         default:
4045                                 max++;
4046                                 break;
4047                         }
4048                 }
4049         }
4050
4051         devinfo->function.audio.ctlcnt = max;
4052
4053         if (max < 1)
4054                 return;
4055
4056         ctls = (struct hdac_audio_ctl *)kmalloc(
4057             sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT);
4058
4059         if (ctls == NULL) {
4060                 /* Blekh! */
4061                 device_printf(sc->dev, "unable to allocate ctls!\n");
4062                 devinfo->function.audio.ctlcnt = 0;
4063                 return;
4064         }
4065
4066         cnt = 0;
4067         for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) {
4068                 if (cnt >= max) {
4069                         device_printf(sc->dev, "%s: Ctl overflow!\n",
4070                             __func__);
4071                         break;
4072                 }
4073                 w = hdac_widget_get(devinfo, i);
4074                 if (w == NULL || w->enable == 0)
4075                         continue;
4076                 ocap = w->param.outamp_cap;
4077                 icap = w->param.inamp_cap;
4078                 if (ocap != 0) {
4079                         mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap);
4080                         step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap);
4081                         size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap);
4082                         offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap);
4083                         /*if (offset > step) {
4084                                 HDA_BOOTVERBOSE(
4085                                         device_printf(sc->dev,
4086                                             "HDA_DEBUG: BUGGY outamp: nid=%d "
4087                                             "[offset=%d > step=%d]\n",
4088                                             w->nid, offset, step);
4089                                 );
4090                                 offset = step;
4091                         }*/
4092                         ctls[cnt].enable = 1;
4093                         ctls[cnt].widget = w;
4094                         ctls[cnt].mute = mute;
4095                         ctls[cnt].step = step;
4096                         ctls[cnt].size = size;
4097                         ctls[cnt].offset = offset;
4098                         ctls[cnt].left = offset;
4099                         ctls[cnt].right = offset;
4100                         ctls[cnt++].dir = HDA_CTL_OUT;
4101                 }
4102
4103                 if (icap != 0) {
4104                         mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap);
4105                         step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap);
4106                         size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap);
4107                         offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap);
4108                         /*if (offset > step) {
4109                                 HDA_BOOTVERBOSE(
4110                                         device_printf(sc->dev,
4111                                             "HDA_DEBUG: BUGGY inamp: nid=%d "
4112                                             "[offset=%d > step=%d]\n",
4113                                             w->nid, offset, step);
4114                                 );
4115                                 offset = step;
4116                         }*/
4117                         switch (w->type) {
4118                         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4119                         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4120                                 for (j = 0; j < w->nconns; j++) {
4121                                         if (cnt >= max) {
4122                                                 device_printf(sc->dev,
4123                                                     "%s: Ctl overflow!\n",
4124                                                     __func__);
4125                                                 break;
4126                                         }
4127                                         cw = hdac_widget_get(devinfo,
4128                                             w->conns[j]);
4129                                         if (cw == NULL || cw->enable == 0)
4130                                                 continue;
4131                                         ctls[cnt].enable = 1;
4132                                         ctls[cnt].widget = w;
4133                                         ctls[cnt].childwidget = cw;
4134                                         ctls[cnt].index = j;
4135                                         ctls[cnt].mute = mute;
4136                                         ctls[cnt].step = step;
4137                                         ctls[cnt].size = size;
4138                                         ctls[cnt].offset = offset;
4139                                         ctls[cnt].left = offset;
4140                                         ctls[cnt].right = offset;
4141                                         ctls[cnt++].dir = HDA_CTL_IN;
4142                                 }
4143                                 break;
4144                         default:
4145                                 if (cnt >= max) {
4146                                         device_printf(sc->dev,
4147                                             "%s: Ctl overflow!\n",
4148                                             __func__);
4149                                         break;
4150                                 }
4151                                 ctls[cnt].enable = 1;
4152                                 ctls[cnt].widget = w;
4153                                 ctls[cnt].mute = mute;
4154                                 ctls[cnt].step = step;
4155                                 ctls[cnt].size = size;
4156                                 ctls[cnt].offset = offset;
4157                                 ctls[cnt].left = offset;
4158                                 ctls[cnt].right = offset;
4159                                 ctls[cnt++].dir = HDA_CTL_IN;
4160                                 break;
4161                         }
4162                 }
4163         }
4164
4165         devinfo->function.audio.ctl = ctls;
4166 }
4167
4168 static const struct {
4169         uint32_t model;
4170         uint32_t id;
4171         uint32_t set, unset;
4172 } hdac_quirks[] = {
4173         /*
4174          * XXX Force stereo quirk. Monoural recording / playback
4175          *     on few codecs (especially ALC880) seems broken or
4176          *     perhaps unsupported.
4177          */
4178         { HDA_MATCH_ALL, HDA_MATCH_ALL,
4179             HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 },
4180         { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL,
4181             HDA_QUIRK_GPIO0, 0 },
4182         { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880,
4183             HDA_QUIRK_GPIO0, 0 },
4184         { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880,
4185             HDA_QUIRK_GPIO0, 0 },
4186         { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882,
4187             HDA_QUIRK_GPIO0, 0 },
4188         { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882,
4189             HDA_QUIRK_GPIO0, 0 },
4190         { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A,
4191             HDA_QUIRK_EAPDINV, 0 },
4192         { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A,
4193             HDA_QUIRK_EAPDINV, 0 },
4194         { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861,
4195             HDA_QUIRK_OVREF, 0 },
4196         { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861,
4197             HDA_QUIRK_OVREF, 0 },
4198         { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861,
4199             HDA_QUIRK_OVREF, 0 },
4200         /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988,
4201             HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/
4202         { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880,
4203             HDA_QUIRK_GPIO1, 0 },
4204         { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A,
4205             HDA_QUIRK_EAPDINV, 0 },
4206         { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A,
4207             HDA_QUIRK_EAPDINV, 0 },
4208         { APPLE_INTEL_MAC, HDA_CODEC_STAC9221,
4209             HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 },
4210         { HDA_MATCH_ALL, HDA_CODEC_AD1988,
4211             HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4212         { HDA_MATCH_ALL, HDA_CODEC_AD1988B,
4213             HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4214         { HDA_MATCH_ALL, HDA_CODEC_CXVENICE,
4215             0, HDA_QUIRK_FORCESTEREO },
4216         { HDA_MATCH_ALL, HDA_CODEC_STACXXXX,
4217             HDA_QUIRK_SOFTPCMVOL, 0 }
4218 };
4219 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0]))
4220
4221 static void
4222 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo)
4223 {
4224         struct hdac_widget *w;
4225         struct hdac_audio_ctl *ctl;
4226         uint32_t id, subvendor;
4227         int i;
4228
4229         id = hdac_codec_id(devinfo);
4230         subvendor = devinfo->codec->sc->pci_subvendor;
4231
4232         /*
4233          * Quirks
4234          */
4235         for (i = 0; i < HDAC_QUIRKS_LEN; i++) {
4236                 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) &&
4237                     HDA_DEV_MATCH(hdac_quirks[i].id, id)))
4238                         continue;
4239                 if (hdac_quirks[i].set != 0)
4240                         devinfo->function.audio.quirks |=
4241                             hdac_quirks[i].set;
4242                 if (hdac_quirks[i].unset != 0)
4243                         devinfo->function.audio.quirks &=
4244                             ~(hdac_quirks[i].unset);
4245         }
4246
4247         switch (id) {
4248         case HDA_CODEC_ALC260:
4249                 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4250                         w = hdac_widget_get(devinfo, i);
4251                         if (w == NULL || w->enable == 0)
4252                                 continue;
4253                         if (w->type !=
4254                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
4255                                 continue;
4256                         if (w->nid != 5)
4257                                 w->enable = 0;
4258                 }
4259                 if (subvendor == HP_XW4300_SUBVENDOR) {
4260                         ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4261                         if (ctl != NULL && ctl->widget != NULL) {
4262                                 ctl->ossmask = SOUND_MASK_SPEAKER;
4263                                 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4264                         }
4265                         ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4266                         if (ctl != NULL && ctl->widget != NULL) {
4267                                 ctl->ossmask = SOUND_MASK_SPEAKER;
4268                                 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4269                         }
4270                 } else if (subvendor == HP_3010_SUBVENDOR) {
4271                         ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4272                         if (ctl != NULL && ctl->widget != NULL) {
4273                                 ctl->ossmask = SOUND_MASK_SPEAKER;
4274                                 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4275                         }
4276                         ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1);
4277                         if (ctl != NULL && ctl->widget != NULL) {
4278                                 ctl->ossmask = SOUND_MASK_SPEAKER;
4279                                 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4280                         }
4281                 }
4282                 break;
4283         case HDA_CODEC_ALC262:
4284                 if (subvendor == HP_DC7700_SUBVENDOR) {
4285                         ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1);
4286                         if (ctl != NULL && ctl->widget != NULL) {
4287                                 ctl->ossmask = SOUND_MASK_SPEAKER;
4288                                 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4289                         }
4290                         ctl = hdac_audio_ctl_amp_get(devinfo, 27, 0, 1);
4291                         if (ctl != NULL && ctl->widget != NULL) {
4292                                 ctl->ossmask = SOUND_MASK_SPEAKER;
4293                                 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4294                         }
4295                 }
4296                 break;
4297         case HDA_CODEC_ALC861:
4298                 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1);
4299                 if (ctl != NULL)
4300                         ctl->muted = HDA_AMP_MUTE_ALL;
4301                 break;
4302         case HDA_CODEC_ALC880:
4303                 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4304                         w = hdac_widget_get(devinfo, i);
4305                         if (w == NULL || w->enable == 0)
4306                                 continue;
4307                         if (w->type ==
4308                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4309                             w->nid != 9 && w->nid != 29) {
4310                                         w->enable = 0;
4311                         } else if (w->type !=
4312                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET &&
4313                             w->nid == 29) {
4314                                 w->type =
4315                                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET;
4316                                 w->param.widget_cap &=
4317                                     ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK;
4318                                 w->param.widget_cap |=
4319                                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET <<
4320                                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT;
4321                                 strlcpy(w->name, "beep widget", sizeof(w->name));
4322                         }
4323                 }
4324                 break;
4325         case HDA_CODEC_ALC883:
4326                 /*
4327                  * nid: 24/25 = External (jack) or Internal (fixed) Mic.
4328                  *              Clear vref cap for jack connectivity.
4329                  */
4330                 w = hdac_widget_get(devinfo, 24);
4331                 if (w != NULL && w->enable != 0 && w->type ==
4332                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4333                     (w->wclass.pin.config &
4334                     HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4335                     HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4336                         w->wclass.pin.cap &= ~(
4337                             HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4338                             HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4339                             HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4340                 w = hdac_widget_get(devinfo, 25);
4341                 if (w != NULL && w->enable != 0 && w->type ==
4342                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4343                     (w->wclass.pin.config &
4344                     HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4345                     HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4346                         w->wclass.pin.cap &= ~(
4347                             HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4348                             HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4349                             HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4350                 /*
4351                  * nid: 26 = Line-in, leave it alone.
4352                  */
4353                 break;
4354         case HDA_CODEC_AD1981HD:
4355                 w = hdac_widget_get(devinfo, 11);
4356                 if (w != NULL && w->enable != 0 && w->nconns > 3)
4357                         w->selconn = 3;
4358                 if (subvendor == IBM_M52_SUBVENDOR) {
4359                         ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1);
4360                         if (ctl != NULL)
4361                                 ctl->ossmask = SOUND_MASK_SPEAKER;
4362                 }
4363                 break;
4364         case HDA_CODEC_AD1986A:
4365                 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4366                         w = hdac_widget_get(devinfo, i);
4367                         if (w == NULL || w->enable == 0)
4368                                 continue;
4369                         if (w->type !=
4370                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4371                                 continue;
4372                         if (w->nid != 3)
4373                                 w->enable = 0;
4374                 }
4375                 if (subvendor == ASUS_M2NPVMX_SUBVENDOR ||
4376                     subvendor == ASUS_A8NVMCSM_SUBVENDOR) {
4377                         /* nid 28 is mic, nid 29 is line-in */
4378                         w = hdac_widget_get(devinfo, 15);
4379                         if (w != NULL)
4380                                 w->selconn = 2;
4381                         w = hdac_widget_get(devinfo, 16);
4382                         if (w != NULL)
4383                                 w->selconn = 1;
4384                 }
4385                 break;
4386         case HDA_CODEC_AD1988:
4387         case HDA_CODEC_AD1988B:
4388                 /*w = hdac_widget_get(devinfo, 12);
4389                 if (w != NULL) {
4390                         w->selconn = 1;
4391                         w->pflags |= HDA_ADC_LOCKED;
4392                 }
4393                 w = hdac_widget_get(devinfo, 13);
4394                 if (w != NULL) {
4395                         w->selconn = 4;
4396                         w->pflags |= HDA_ADC_LOCKED;
4397                 }
4398                 w = hdac_widget_get(devinfo, 14);
4399                 if (w != NULL) {
4400                         w->selconn = 2;
4401                         w->pflags |= HDA_ADC_LOCKED;
4402                 }*/
4403                 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1);
4404                 if (ctl != NULL) {
4405                         ctl->ossmask = SOUND_MASK_IGAIN;
4406                         ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4407                 }
4408                 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1);
4409                 if (ctl != NULL) {
4410                         ctl->ossmask = SOUND_MASK_IGAIN;
4411                         ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4412                 }
4413                 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1);
4414                 if (ctl != NULL) {
4415                         ctl->ossmask = SOUND_MASK_IGAIN;
4416                         ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4417                 }
4418                 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1);
4419                 if (ctl != NULL) {
4420                         ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4421                         ctl->widget->ctlflags |= SOUND_MASK_MIC;
4422                 }
4423                 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1);
4424                 if (ctl != NULL) {
4425                         ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4426                         ctl->widget->ctlflags |= SOUND_MASK_MIC;
4427                 }
4428                 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1);
4429                 if (ctl != NULL) {
4430                         ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4431                         ctl->widget->ctlflags |= SOUND_MASK_LINE;
4432                 }
4433                 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1);
4434                 if (ctl != NULL) {
4435                         ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME;
4436                         ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4437                 }
4438                 break;
4439         case HDA_CODEC_STAC9221:
4440                 /*
4441                  * Dell XPS M1210 need all DACs for each output jacks
4442                  */
4443                 if (subvendor == DELL_XPSM1210_SUBVENDOR)
4444                         break;
4445                 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4446                         w = hdac_widget_get(devinfo, i);
4447                         if (w == NULL || w->enable == 0)
4448                                 continue;
4449                         if (w->type !=
4450                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4451                                 continue;
4452                         if (w->nid != 2)
4453                                 w->enable = 0;
4454                 }
4455                 break;
4456         case HDA_CODEC_STAC9221D:
4457                 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4458                         w = hdac_widget_get(devinfo, i);
4459                         if (w == NULL || w->enable == 0)
4460                                 continue;
4461                         if (w->type ==
4462                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4463                             w->nid != 6)
4464                                 w->enable = 0;
4465
4466                 }
4467                 break;
4468         case HDA_CODEC_STAC9227:
4469                 w = hdac_widget_get(devinfo, 8);
4470                 if (w != NULL)
4471                         w->enable = 0;
4472                 w = hdac_widget_get(devinfo, 9);
4473                 if (w != NULL)
4474                         w->enable = 0;
4475                 break;
4476         case HDA_CODEC_CXWAIKIKI:
4477                 if (subvendor == HP_DV5000_SUBVENDOR) {
4478                         w = hdac_widget_get(devinfo, 27);
4479                         if (w != NULL)
4480                                 w->enable = 0;
4481                 }
4482                 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4483                 if (ctl != NULL)
4484                         ctl->ossmask = SOUND_MASK_SKIP;
4485                 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1);
4486                 if (ctl != NULL && ctl->childwidget != NULL &&
4487                     ctl->childwidget->enable != 0) {
4488                         ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME;
4489                         ctl->childwidget->ctlflags |= SOUND_MASK_PCM;
4490                 }
4491                 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1);
4492                 if (ctl != NULL && ctl->childwidget != NULL &&
4493                     ctl->childwidget->enable != 0) {
4494                         ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4495                         ctl->childwidget->ctlflags |= SOUND_MASK_LINE;
4496                 }
4497                 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1);
4498                 if (ctl != NULL && ctl->childwidget != NULL &&
4499                     ctl->childwidget->enable != 0) {
4500                         ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4501                         ctl->childwidget->ctlflags |= SOUND_MASK_MIC;
4502                 }
4503                 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1);
4504                 if (ctl != NULL) {
4505                         ctl->ossmask = SOUND_MASK_SKIP;
4506                         /* XXX mixer \=rec mic broken.. why?!? */
4507                         /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */
4508                 }
4509                 break;
4510         default:
4511                 break;
4512         }
4513 }
4514
4515 static int
4516 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo)
4517 {
4518         int *dev = &devinfo->function.audio.ossidx;
4519
4520         while (*dev < SOUND_MIXER_NRDEVICES) {
4521                 switch (*dev) {
4522                 case SOUND_MIXER_VOLUME:
4523                 case SOUND_MIXER_BASS:
4524                 case SOUND_MIXER_TREBLE:
4525                 case SOUND_MIXER_PCM:
4526                 case SOUND_MIXER_SPEAKER:
4527                 case SOUND_MIXER_LINE:
4528                 case SOUND_MIXER_MIC:
4529                 case SOUND_MIXER_CD:
4530                 case SOUND_MIXER_RECLEV:
4531                 case SOUND_MIXER_IGAIN:
4532                 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */
4533                         (*dev)++;
4534                         break;
4535                 default:
4536                         return (*dev)++;
4537                         break;
4538                 }
4539         }
4540
4541         return (-1);
4542 }
4543
4544 static int
4545 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4546 {
4547         struct hdac_widget *w;
4548         int i, ret = 0;
4549
4550         if (depth > HDA_PARSE_MAXDEPTH)
4551                 return (0);
4552         w = hdac_widget_get(devinfo, nid);
4553         if (w == NULL || w->enable == 0)
4554                 return (0);
4555         switch (w->type) {
4556         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
4557                 w->pflags |= HDA_DAC_PATH;
4558                 ret = 1;
4559                 break;
4560         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4561         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4562                 for (i = 0; i < w->nconns; i++) {
4563                         if (hdac_widget_find_dac_path(devinfo,
4564                             w->conns[i], depth + 1) != 0) {
4565                                 if (w->selconn == -1)
4566                                         w->selconn = i;
4567                                 ret = 1;
4568                                 w->pflags |= HDA_DAC_PATH;
4569                         }
4570                 }
4571                 break;
4572         default:
4573                 break;
4574         }
4575         return (ret);
4576 }
4577
4578 static int
4579 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4580 {
4581         struct hdac_widget *w;
4582         int i, conndev, ret = 0;
4583
4584         if (depth > HDA_PARSE_MAXDEPTH)
4585                 return (0);
4586         w = hdac_widget_get(devinfo, nid);
4587         if (w == NULL || w->enable == 0)
4588                 return (0);
4589         switch (w->type) {
4590         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
4591         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4592         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4593                 for (i = 0; i < w->nconns; i++) {
4594                         if (hdac_widget_find_adc_path(devinfo, w->conns[i],
4595                             depth + 1) != 0) {
4596                                 if (w->selconn == -1)
4597                                         w->selconn = i;
4598                                 w->pflags |= HDA_ADC_PATH;
4599                                 ret = 1;
4600                         }
4601                 }
4602                 break;
4603         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
4604                 conndev = w->wclass.pin.config &
4605                     HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4606                 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4607                     (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD ||
4608                     conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN ||
4609                     conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) {
4610                         w->pflags |= HDA_ADC_PATH;
4611                         ret = 1;
4612                 }
4613                 break;
4614         /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4615                 if (w->pflags & HDA_DAC_PATH) {
4616                         w->pflags |= HDA_ADC_PATH;
4617                         ret = 1;
4618                 }
4619                 break;*/
4620         default:
4621                 break;
4622         }
4623         return (ret);
4624 }
4625
4626 static uint32_t
4627 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo,
4628                                 nid_t nid, nid_t pnid, int index, int depth)
4629 {
4630         struct hdac_widget *w, *pw;
4631         struct hdac_audio_ctl *ctl;
4632         uint32_t fl = 0;
4633         int i, ossdev, conndev, strategy;
4634
4635         if (depth > HDA_PARSE_MAXDEPTH)
4636                 return (0);
4637
4638         w = hdac_widget_get(devinfo, nid);
4639         if (w == NULL || w->enable == 0)
4640                 return (0);
4641
4642         pw = hdac_widget_get(devinfo, pnid);
4643         strategy = devinfo->function.audio.parsing_strategy;
4644
4645         if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER
4646             || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) {
4647                 for (i = 0; i < w->nconns; i++) {
4648                         fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i],
4649                             w->nid, i, depth + 1);
4650                 }
4651                 w->ctlflags |= fl;
4652                 return (fl);
4653         } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
4654             (w->pflags & HDA_DAC_PATH)) {
4655                 i = 0;
4656                 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4657                         if (ctl->enable == 0 || ctl->widget == NULL)
4658                                 continue;
4659                         /* XXX This should be compressed! */
4660                         if (((ctl->widget->nid == w->nid) ||
4661                             (ctl->widget->nid == pnid && ctl->index == index &&
4662                             (ctl->dir & HDA_CTL_IN)) ||
4663                             (ctl->widget->nid == pnid && pw != NULL &&
4664                             pw->type ==
4665                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4666                             (pw->nconns < 2 || pw->selconn == index ||
4667                             pw->selconn == -1) &&
4668                             (ctl->dir & HDA_CTL_OUT)) ||
4669                             (strategy == HDA_PARSE_DIRECT &&
4670                             ctl->widget->nid == w->nid)) &&
4671                             !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4672                                 /*if (pw != NULL && pw->selconn == -1)
4673                                         pw->selconn = index;
4674                                 fl |= SOUND_MASK_VOLUME;
4675                                 fl |= SOUND_MASK_PCM;
4676                                 ctl->ossmask |= SOUND_MASK_VOLUME;
4677                                 ctl->ossmask |= SOUND_MASK_PCM;
4678                                 ctl->ossdev = SOUND_MIXER_PCM;*/
4679                                 if (!(w->ctlflags & SOUND_MASK_PCM) ||
4680                                     (pw != NULL &&
4681                                     !(pw->ctlflags & SOUND_MASK_PCM))) {
4682                                         fl |= SOUND_MASK_VOLUME;
4683                                         fl |= SOUND_MASK_PCM;
4684                                         ctl->ossmask |= SOUND_MASK_VOLUME;
4685                                         ctl->ossmask |= SOUND_MASK_PCM;
4686                                         ctl->ossdev = SOUND_MIXER_PCM;
4687                                         w->ctlflags |= SOUND_MASK_VOLUME;
4688                                         w->ctlflags |= SOUND_MASK_PCM;
4689                                         if (pw != NULL) {
4690                                                 if (pw->selconn == -1)
4691                                                         pw->selconn = index;
4692                                                 pw->ctlflags |=
4693                                                     SOUND_MASK_VOLUME;
4694                                                 pw->ctlflags |=
4695                                                     SOUND_MASK_PCM;
4696                                         }
4697                                 }
4698                         }
4699                 }
4700                 w->ctlflags |= fl;
4701                 return (fl);
4702         } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4703             HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4704             (w->pflags & HDA_ADC_PATH)) {
4705                 conndev = w->wclass.pin.config &
4706                     HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4707                 i = 0;
4708                 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4709                         if (ctl->enable == 0 || ctl->widget == NULL)
4710                                 continue;
4711                         /* XXX This should be compressed! */
4712                         if (((ctl->widget->nid == pnid && ctl->index == index &&
4713                             (ctl->dir & HDA_CTL_IN)) ||
4714                             (ctl->widget->nid == pnid && pw != NULL &&
4715                             pw->type ==
4716                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4717                             (pw->nconns < 2 || pw->selconn == index ||
4718                             pw->selconn == -1) &&
4719                             (ctl->dir & HDA_CTL_OUT)) ||
4720                             (strategy == HDA_PARSE_DIRECT &&
4721                             ctl->widget->nid == w->nid)) &&
4722                             !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4723                                 if (pw != NULL && pw->selconn == -1)
4724                                         pw->selconn = index;
4725                                 ossdev = 0;
4726                                 switch (conndev) {
4727                                 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
4728                                         ossdev = SOUND_MIXER_MIC;
4729                                         break;
4730                                 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
4731                                         ossdev = SOUND_MIXER_LINE;
4732                                         break;
4733                                 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
4734                                         ossdev = SOUND_MIXER_CD;
4735                                         break;
4736                                 default:
4737                                         ossdev =
4738                                             hdac_audio_ctl_ossmixer_getnextdev(
4739                                             devinfo);
4740                                         if (ossdev < 0)
4741                                                 ossdev = 0;
4742                                         break;
4743                                 }
4744                                 if (strategy == HDA_PARSE_MIXER) {
4745                                         fl |= SOUND_MASK_VOLUME;
4746                                         ctl->ossmask |= SOUND_MASK_VOLUME;
4747                                 }
4748                                 fl |= 1 << ossdev;
4749                                 ctl->ossmask |= 1 << ossdev;
4750                                 ctl->ossdev = ossdev;
4751                         }
4752                 }
4753                 w->ctlflags |= fl;
4754                 return (fl);
4755         } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
4756                 i = 0;
4757                 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4758                         if (ctl->enable == 0 || ctl->widget == NULL)
4759                                 continue;
4760                         /* XXX This should be compressed! */
4761                         if (((ctl->widget->nid == pnid && ctl->index == index &&
4762                             (ctl->dir & HDA_CTL_IN)) ||
4763                             (ctl->widget->nid == pnid && pw != NULL &&
4764                             pw->type ==
4765                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4766                             (pw->nconns < 2 || pw->selconn == index ||
4767                             pw->selconn == -1) &&
4768                             (ctl->dir & HDA_CTL_OUT)) ||
4769                             (strategy == HDA_PARSE_DIRECT &&
4770                             ctl->widget->nid == w->nid)) &&
4771                             !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4772                                 if (pw != NULL && pw->selconn == -1)
4773                                         pw->selconn = index;
4774                                 fl |= SOUND_MASK_VOLUME;
4775                                 fl |= SOUND_MASK_SPEAKER;
4776                                 ctl->ossmask |= SOUND_MASK_VOLUME;
4777                                 ctl->ossmask |= SOUND_MASK_SPEAKER;
4778                                 ctl->ossdev = SOUND_MIXER_SPEAKER;
4779                         }
4780                 }
4781                 w->ctlflags |= fl;
4782                 return (fl);
4783         }
4784         return (0);
4785 }
4786
4787 static uint32_t
4788 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4789 {
4790         struct hdac_widget *w, *cw;
4791         struct hdac_audio_ctl *ctl;
4792         uint32_t fl;
4793         int i;
4794
4795         if (depth > HDA_PARSE_MAXDEPTH)
4796                 return (0);
4797
4798         w = hdac_widget_get(devinfo, nid);
4799         if (w == NULL || w->enable == 0)
4800                 return (0);
4801         /*if (!(w->pflags & HDA_ADC_PATH))
4802                 return (0);
4803         if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4804             w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4805                 return (0);*/
4806         i = 0;
4807         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4808                 if (ctl->enable == 0 || ctl->widget == NULL)
4809                         continue;
4810                 if (ctl->widget->nid == nid) {
4811                         ctl->ossmask |= SOUND_MASK_RECLEV;
4812                         w->ctlflags |= SOUND_MASK_RECLEV;
4813                         return (SOUND_MASK_RECLEV);
4814                 }
4815         }
4816         for (i = 0; i < w->nconns; i++) {
4817                 cw = hdac_widget_get(devinfo, w->conns[i]);
4818                 if (cw == NULL || cw->enable == 0)
4819                         continue;
4820                 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
4821                         continue;
4822                 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1);
4823                 if (fl != 0) {
4824                         cw->ctlflags |= fl;
4825                         w->ctlflags |= fl;
4826                         return (fl);
4827                 }
4828         }
4829         return (0);
4830 }
4831
4832 static int
4833 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4834 {
4835         struct hdac_widget *w, *cw;
4836         int i, child = 0;
4837
4838         if (depth > HDA_PARSE_MAXDEPTH)
4839                 return (0);
4840
4841         w = hdac_widget_get(devinfo, nid);
4842         if (w == NULL || w->enable == 0)
4843                 return (0);
4844         /*if (!(w->pflags & HDA_ADC_PATH))
4845                 return (0);
4846         if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4847             w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4848                 return (0);*/
4849         /* XXX weak! */
4850         for (i = 0; i < w->nconns; i++) {
4851                 cw = hdac_widget_get(devinfo, w->conns[i]);
4852                 if (cw == NULL)
4853                         continue;
4854                 if (++child > 1) {
4855                         w->pflags |= HDA_ADC_RECSEL;
4856                         return (1);
4857                 }
4858         }
4859         for (i = 0; i < w->nconns; i++) {
4860                 if (hdac_audio_ctl_recsel_build(devinfo,
4861                     w->conns[i], depth + 1) != 0)
4862                         return (1);
4863         }
4864         return (0);
4865 }
4866
4867 static int
4868 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo)
4869 {
4870         struct hdac_widget *w, *cw;
4871         int i, j, conndev, found_dac = 0;
4872         int strategy;
4873
4874         strategy = devinfo->function.audio.parsing_strategy;
4875
4876         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4877                 w = hdac_widget_get(devinfo, i);
4878                 if (w == NULL || w->enable == 0)
4879                         continue;
4880                 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4881                         continue;
4882                 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap))
4883                         continue;
4884                 conndev = w->wclass.pin.config &
4885                     HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4886                 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT ||
4887                     conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER ||
4888                     conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT))
4889                         continue;
4890                 for (j = 0; j < w->nconns; j++) {
4891                         cw = hdac_widget_get(devinfo, w->conns[j]);
4892                         if (cw == NULL || cw->enable == 0)
4893                                 continue;
4894                         if (strategy == HDA_PARSE_MIXER && !(cw->type ==
4895                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
4896                             cw->type ==
4897                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4898                                 continue;
4899                         if (hdac_widget_find_dac_path(devinfo, cw->nid, 0)
4900                             != 0) {
4901                                 if (w->selconn == -1)
4902                                         w->selconn = j;
4903                                 w->pflags |= HDA_DAC_PATH;
4904                                 found_dac++;
4905                         }
4906                 }
4907         }
4908
4909         return (found_dac);
4910 }
4911
4912 static void
4913 hdac_audio_build_tree(struct hdac_devinfo *devinfo)
4914 {
4915         struct hdac_widget *w;
4916         struct hdac_audio_ctl *ctl;
4917         int i, j, dacs, strategy;
4918
4919         /* Construct DAC path */
4920         strategy = HDA_PARSE_MIXER;
4921         devinfo->function.audio.parsing_strategy = strategy;
4922         HDA_BOOTVERBOSE(
4923                 device_printf(devinfo->codec->sc->dev,
4924                     "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n",
4925                     HDA_WIDGET_PARSER_REV);
4926         );
4927         dacs = hdac_audio_build_tree_strategy(devinfo);
4928         if (dacs == 0) {
4929                 HDA_BOOTVERBOSE(
4930                         device_printf(devinfo->codec->sc->dev,
4931                             "HDA_DEBUG: HWiP: 0 DAC path found! "
4932                             "Retrying parser "
4933                             "using HDA_PARSE_DIRECT strategy.\n");
4934                 );
4935                 strategy = HDA_PARSE_DIRECT;
4936                 devinfo->function.audio.parsing_strategy = strategy;
4937                 dacs = hdac_audio_build_tree_strategy(devinfo);
4938         }
4939
4940         HDA_BOOTVERBOSE(
4941                 device_printf(devinfo->codec->sc->dev,
4942                     "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s "
4943                     "strategy.\n",
4944                     dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT");
4945         );
4946
4947         /* Construct ADC path */
4948         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4949                 w = hdac_widget_get(devinfo, i);
4950                 if (w == NULL || w->enable == 0)
4951                         continue;
4952                 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
4953                         continue;
4954                 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0);
4955         }
4956
4957         /* Output mixers */
4958         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4959                 w = hdac_widget_get(devinfo, i);
4960                 if (w == NULL || w->enable == 0)
4961                         continue;
4962                 if ((strategy == HDA_PARSE_MIXER &&
4963                     (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
4964                     w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
4965                     && (w->pflags & HDA_DAC_PATH)) ||
4966                     (strategy == HDA_PARSE_DIRECT && (w->pflags &
4967                     (HDA_DAC_PATH | HDA_ADC_PATH)))) {
4968                         w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo,
4969                             w->nid, devinfo->startnode - 1, 0, 0);
4970                 } else if (w->type ==
4971                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
4972                         j = 0;
4973                         while ((ctl = hdac_audio_ctl_each(devinfo, &j)) !=
4974                             NULL) {
4975                                 if (ctl->enable == 0 || ctl->widget == NULL)
4976                                         continue;
4977                                 if (ctl->widget->nid != w->nid)
4978                                         continue;
4979                                 ctl->ossmask |= SOUND_MASK_VOLUME;
4980                                 ctl->ossmask |= SOUND_MASK_SPEAKER;
4981                                 ctl->ossdev = SOUND_MIXER_SPEAKER;
4982                                 w->ctlflags |= SOUND_MASK_VOLUME;
4983                                 w->ctlflags |= SOUND_MASK_SPEAKER;
4984                         }
4985                 }
4986         }
4987
4988         /* Input mixers (rec) */
4989         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4990                 w = hdac_widget_get(devinfo, i);
4991                 if (w == NULL || w->enable == 0)
4992                         continue;
4993                 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4994                     w->pflags & HDA_ADC_PATH))
4995                         continue;
4996                 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0);
4997                 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0);
4998         }
4999 }
5000
5001 #define HDA_COMMIT_CONN (1 << 0)
5002 #define HDA_COMMIT_CTRL (1 << 1)
5003 #define HDA_COMMIT_EAPD (1 << 2)
5004 #define HDA_COMMIT_GPIO (1 << 3)
5005 #define HDA_COMMIT_MISC (1 << 4)
5006 #define HDA_COMMIT_ALL  (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \
5007                         HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC)
5008
5009 static void
5010 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl)
5011 {
5012         struct hdac_softc *sc = devinfo->codec->sc;
5013         struct hdac_widget *w;
5014         nid_t cad;
5015         int i;
5016
5017         if (!(cfl & HDA_COMMIT_ALL))
5018                 return;
5019
5020         cad = devinfo->codec->cad;
5021
5022         if ((cfl & HDA_COMMIT_MISC)) {
5023                 if (sc->pci_subvendor == APPLE_INTEL_MAC)
5024                         hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid,
5025                             0x7e7, 0), cad);
5026         }
5027
5028         if (cfl & HDA_COMMIT_GPIO) {
5029                 uint32_t gdata, gmask, gdir;
5030                 int commitgpio, numgpio;
5031
5032                 gdata = 0;
5033                 gmask = 0;
5034                 gdir = 0;
5035                 commitgpio = 0;
5036
5037                 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO(
5038                     devinfo->function.audio.gpio);
5039
5040                 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH)
5041                         commitgpio = (numgpio > 0) ? 1 : 0;
5042                 else {
5043                         for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) {
5044                                 if (!(devinfo->function.audio.quirks &
5045                                     (1 << i)))
5046                                         continue;
5047                                 if (commitgpio == 0) {
5048                                         commitgpio = 1;
5049                                         HDA_BOOTVERBOSE(
5050                                                 gdata = hdac_command(sc,
5051                                                     HDA_CMD_GET_GPIO_DATA(cad,
5052                                                     devinfo->nid), cad);
5053                                                 gmask = hdac_command(sc,
5054                                                     HDA_CMD_GET_GPIO_ENABLE_MASK(cad,
5055                                                     devinfo->nid), cad);
5056                                                 gdir = hdac_command(sc,
5057                                                     HDA_CMD_GET_GPIO_DIRECTION(cad,
5058                                                     devinfo->nid), cad);
5059                                                 device_printf(sc->dev,
5060                                                     "GPIO init: data=0x%08x "
5061                                                     "mask=0x%08x dir=0x%08x\n",
5062                                                     gdata, gmask, gdir);
5063                                                 gdata = 0;
5064                                                 gmask = 0;
5065                                                 gdir = 0;
5066                                         );
5067                                 }
5068                                 gdata |= 1 << i;
5069                                 gmask |= 1 << i;
5070                                 gdir |= 1 << i;
5071                         }
5072                 }
5073
5074                 if (commitgpio != 0) {
5075                         HDA_BOOTVERBOSE(
5076                                 device_printf(sc->dev,
5077                                     "GPIO commit: data=0x%08x mask=0x%08x "
5078                                     "dir=0x%08x\n",
5079                                     gdata, gmask, gdir);
5080                         );
5081                         hdac_command(sc,
5082                             HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid,
5083                             gmask), cad);
5084                         hdac_command(sc,
5085                             HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid,
5086                             gdir), cad);
5087                         hdac_command(sc,
5088                             HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid,
5089                             gdata), cad);
5090                 }
5091         }
5092
5093         for (i = 0; i < devinfo->nodecnt; i++) {
5094                 w = &devinfo->widget[i];
5095                 if (w == NULL || w->enable == 0)
5096                         continue;
5097                 if (cfl & HDA_COMMIT_CONN) {
5098                         if (w->selconn == -1)
5099                                 w->selconn = 0;
5100                         if (w->nconns > 0)
5101                                 hdac_widget_connection_select(w, w->selconn);
5102                 }
5103                 if ((cfl & HDA_COMMIT_CTRL) &&
5104                     w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5105                         uint32_t pincap;
5106
5107                         pincap = w->wclass.pin.cap;
5108
5109                         if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) ==
5110                             (HDA_DAC_PATH | HDA_ADC_PATH))
5111                                 device_printf(sc->dev, "WARNING: node %d "
5112                                     "participate both for DAC/ADC!\n", w->nid);
5113                         if (w->pflags & HDA_DAC_PATH) {
5114                                 w->wclass.pin.ctrl &=
5115                                     ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
5116                                 if ((w->wclass.pin.config &
5117                                     HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) !=
5118                                     HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT)
5119                                         w->wclass.pin.ctrl &=
5120                                             ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
5121                                 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) &&
5122                                     HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5123                                         w->wclass.pin.ctrl |=
5124                                             HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5125                                             HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
5126                                 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) &&
5127                                     HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5128                                         w->wclass.pin.ctrl |=
5129                                             HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5130                                             HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
5131                                 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) &&
5132                                     HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5133                                         w->wclass.pin.ctrl |=
5134                                             HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5135                                             HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
5136                         } else if (w->pflags & HDA_ADC_PATH) {
5137                                 w->wclass.pin.ctrl &=
5138                                     ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
5139                                     HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE);
5140                                 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) &&
5141                                     HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5142                                         w->wclass.pin.ctrl |=
5143                                             HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5144                                             HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
5145                                 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) &&
5146                                     HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5147                                         w->wclass.pin.ctrl |=
5148                                             HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5149                                             HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
5150                                 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) &&
5151                                     HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5152                                         w->wclass.pin.ctrl |=
5153                                             HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5154                                             HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
5155                         } else
5156                                 w->wclass.pin.ctrl &= ~(
5157                                     HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
5158                                     HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
5159                                     HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
5160                                     HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
5161                         hdac_command(sc,
5162                             HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid,
5163                             w->wclass.pin.ctrl), cad);
5164                 }
5165                 if ((cfl & HDA_COMMIT_EAPD) &&
5166                     w->param.eapdbtl != HDAC_INVALID) {
5167                         uint32_t val;
5168
5169                         val = w->param.eapdbtl;
5170                         if (devinfo->function.audio.quirks &
5171                             HDA_QUIRK_EAPDINV)
5172                                 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
5173                         hdac_command(sc,
5174                             HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid,
5175                             val), cad);
5176
5177                 }
5178                 DELAY(1000);
5179         }
5180 }
5181
5182 static void
5183 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo)
5184 {
5185         struct hdac_softc *sc = devinfo->codec->sc;
5186         struct hdac_audio_ctl *ctl;
5187         int i;
5188
5189         devinfo->function.audio.mvol = 100 | (100 << 8);
5190         i = 0;
5191         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5192                 if (ctl->enable == 0 || ctl->widget == NULL) {
5193                         HDA_BOOTVERBOSE(
5194                                 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5195                                     i, (ctl->widget != NULL) ?
5196                                     ctl->widget->nid : -1);
5197                                 if (ctl->childwidget != NULL)
5198                                         kprintf(" childnid=%d",
5199                                             ctl->childwidget->nid);
5200                                 if (ctl->widget == NULL)
5201                                         kprintf(" NULL WIDGET!");
5202                                 kprintf(" DISABLED\n");
5203                         );
5204                         continue;
5205                 }
5206                 HDA_BOOTVERBOSE(
5207                         if (ctl->ossmask == 0) {
5208                                 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5209                                     i, ctl->widget->nid);
5210                                 if (ctl->childwidget != NULL)
5211                                         kprintf(" childnid=%d",
5212                                         ctl->childwidget->nid);
5213                                 kprintf(" Bind to NONE\n");
5214                         }
5215                 );
5216                 if (ctl->step > 0) {
5217                         ctl->ossval = (ctl->left * 100) / ctl->step;
5218                         ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8;
5219                 } else
5220                         ctl->ossval = 0;
5221                 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
5222                     ctl->left, ctl->right);
5223         }
5224 }
5225
5226 static int
5227 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir)
5228 {
5229         struct hdac_chan *ch;
5230         struct hdac_widget *w;
5231         uint32_t cap, fmtcap, pcmcap, path;
5232         int i, type, ret, max;
5233
5234         if (dir == PCMDIR_PLAY) {
5235                 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT;
5236                 ch = &devinfo->codec->sc->play;
5237                 path = HDA_DAC_PATH;
5238         } else {
5239                 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT;
5240                 ch = &devinfo->codec->sc->rec;
5241                 path = HDA_ADC_PATH;
5242         }
5243
5244         ch->caps = hdac_caps;
5245         ch->caps.fmtlist = ch->fmtlist;
5246         ch->bit16 = 1;
5247         ch->bit32 = 0;
5248         ch->pcmrates[0] = 48000;
5249         ch->pcmrates[1] = 0;
5250
5251         ret = 0;
5252         fmtcap = devinfo->function.audio.supp_stream_formats;
5253         pcmcap = devinfo->function.audio.supp_pcm_size_rate;
5254         max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1;
5255
5256         for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) {
5257                 w = hdac_widget_get(devinfo, i);
5258                 if (w == NULL || w->enable == 0 || w->type != type ||
5259                     !(w->pflags & path))
5260                         continue;
5261                 cap = w->param.widget_cap;
5262                 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap))
5263                         continue;*/
5264                 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap))
5265                         continue;
5266                 cap = w->param.supp_stream_formats;
5267                 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) {
5268                 }
5269                 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) {
5270                 }*/
5271                 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5272                         continue;
5273                 if (ret == 0) {
5274                         fmtcap = w->param.supp_stream_formats;
5275                         pcmcap = w->param.supp_pcm_size_rate;
5276                 } else {
5277                         fmtcap &= w->param.supp_stream_formats;
5278                         pcmcap &= w->param.supp_pcm_size_rate;
5279                 }
5280                 ch->io[ret++] = i;
5281         }
5282         ch->io[ret] = -1;
5283
5284         ch->supp_stream_formats = fmtcap;
5285         ch->supp_pcm_size_rate = pcmcap;
5286
5287         /*
5288          *  8bit = 0
5289          * 16bit = 1
5290          * 20bit = 2
5291          * 24bit = 3
5292          * 32bit = 4
5293          */
5294         if (ret > 0) {
5295                 cap = pcmcap;
5296                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5297                         ch->bit16 = 1;
5298                 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5299                         ch->bit16 = 0;
5300                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5301                         ch->bit32 = 4;
5302                 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5303                         ch->bit32 = 3;
5304                 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5305                         ch->bit32 = 2;
5306                 i = 0;
5307                 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO))
5308                         ch->fmtlist[i++] = AFMT_S16_LE;
5309                 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO;
5310                 if (ch->bit32 > 0) {
5311                         if (!(devinfo->function.audio.quirks &
5312                             HDA_QUIRK_FORCESTEREO))
5313                                 ch->fmtlist[i++] = AFMT_S32_LE;
5314                         ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO;
5315                 }
5316                 ch->fmtlist[i] = 0;
5317                 i = 0;
5318                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5319                         ch->pcmrates[i++] = 8000;
5320                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5321                         ch->pcmrates[i++] = 11025;
5322                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5323                         ch->pcmrates[i++] = 16000;
5324                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5325                         ch->pcmrates[i++] = 22050;
5326                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5327                         ch->pcmrates[i++] = 32000;
5328                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5329                         ch->pcmrates[i++] = 44100;
5330                 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */
5331                 ch->pcmrates[i++] = 48000;
5332                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5333                         ch->pcmrates[i++] = 88200;
5334                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5335                         ch->pcmrates[i++] = 96000;
5336                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5337                         ch->pcmrates[i++] = 176400;
5338                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5339                         ch->pcmrates[i++] = 192000;
5340                 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */
5341                 ch->pcmrates[i] = 0;
5342                 if (i > 0) {
5343                         ch->caps.minspeed = ch->pcmrates[0];
5344                         ch->caps.maxspeed = ch->pcmrates[i - 1];
5345                 }
5346         }
5347
5348         return (ret);
5349 }
5350
5351 static void
5352 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag)
5353 {
5354         struct hdac_audio_ctl *ctl;
5355         struct hdac_softc *sc = devinfo->codec->sc;
5356         int i;
5357         uint32_t fl = 0;
5358
5359
5360         if (flag == 0) {
5361                 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM |
5362                     SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV |
5363                     SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN;
5364         }
5365
5366         i = 0;
5367         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5368                 if (ctl->enable == 0 || ctl->widget == NULL ||
5369                     ctl->widget->enable == 0 || (ctl->ossmask &
5370                     (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)))
5371                         continue;
5372                 if ((flag == 0 && (ctl->ossmask & ~fl)) ||
5373                     (flag != 0 && (ctl->ossmask & flag))) {
5374                         if (banner != NULL) {
5375                                 device_printf(sc->dev, "\n");
5376                                 device_printf(sc->dev, "%s\n", banner);
5377                         }
5378                         goto hdac_ctl_dump_it_all;
5379                 }
5380         }
5381
5382         return;
5383
5384 hdac_ctl_dump_it_all:
5385         i = 0;
5386         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5387                 if (ctl->enable == 0 || ctl->widget == NULL ||
5388                     ctl->widget->enable == 0)
5389                         continue;
5390                 if (!((flag == 0 && (ctl->ossmask & ~fl)) ||
5391                     (flag != 0 && (ctl->ossmask & flag))))
5392                         continue;
5393                 if (flag == 0) {
5394                         device_printf(sc->dev, "\n");
5395                         device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n",
5396                             hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask));
5397                 }
5398                 device_printf(sc->dev, "   |\n");
5399                 device_printf(sc->dev, "   +-  nid: %2d index: %2d ",
5400                     ctl->widget->nid, ctl->index);
5401                 if (ctl->childwidget != NULL)
5402                         kprintf("(nid: %2d) ", ctl->childwidget->nid);
5403                 else
5404                         kprintf("          ");
5405                 kprintf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n",
5406                     ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir,
5407                     ctl->ossmask);
5408         }
5409 }
5410
5411 static void
5412 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap)
5413 {
5414         uint32_t cap;
5415
5416         cap = fcap;
5417         if (cap != 0) {
5418                 device_printf(sc->dev, "     Stream cap: 0x%08x\n", cap);
5419                 device_printf(sc->dev, "         Format:");
5420                 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
5421                         kprintf(" AC3");
5422                 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap))
5423                         kprintf(" FLOAT32");
5424                 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5425                         kprintf(" PCM");
5426                 kprintf("\n");
5427         }
5428         cap = pcmcap;
5429         if (cap != 0) {
5430                 device_printf(sc->dev, "        PCM cap: 0x%08x\n", cap);
5431                 device_printf(sc->dev, "       PCM size:");
5432                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5433                         kprintf(" 8");
5434                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5435                         kprintf(" 16");
5436                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5437                         kprintf(" 20");
5438                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5439                         kprintf(" 24");
5440                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5441                         kprintf(" 32");
5442                 kprintf("\n");
5443                 device_printf(sc->dev, "       PCM rate:");
5444                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5445                         kprintf(" 8");
5446                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5447                         kprintf(" 11");
5448                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5449                         kprintf(" 16");
5450                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5451                         kprintf(" 22");
5452                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5453                         kprintf(" 32");
5454                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5455                         kprintf(" 44");
5456                 kprintf(" 48");
5457                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5458                         kprintf(" 88");
5459                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5460                         kprintf(" 96");
5461                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5462                         kprintf(" 176");
5463                 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5464                         kprintf(" 192");
5465                 kprintf("\n");
5466         }
5467 }
5468
5469 static void
5470 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w)
5471 {
5472         uint32_t pincap, wcap;
5473
5474         pincap = w->wclass.pin.cap;
5475         wcap = w->param.widget_cap;
5476
5477         device_printf(sc->dev, "        Pin cap: 0x%08x\n", pincap);
5478         device_printf(sc->dev, "                ");
5479         if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap))
5480                 kprintf(" ISC");
5481         if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap))
5482                 kprintf(" TRQD");
5483         if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap))
5484                 kprintf(" PDC");
5485         if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
5486                 kprintf(" HP");
5487         if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
5488                 kprintf(" OUT");
5489         if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
5490                 kprintf(" IN");
5491         if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap))
5492                 kprintf(" BAL");
5493         if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) {
5494                 kprintf(" VREF[");
5495                 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5496                         kprintf(" 50");
5497                 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5498                         kprintf(" 80");
5499                 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5500                         kprintf(" 100");
5501                 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap))
5502                         kprintf(" GROUND");
5503                 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap))
5504                         kprintf(" HIZ");
5505                 kprintf(" ]");
5506         }
5507         if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap))
5508                 kprintf(" EAPD");
5509         if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap))
5510                 kprintf(" : UNSOL");
5511         kprintf("\n");
5512         device_printf(sc->dev, "     Pin config: 0x%08x\n",
5513             w->wclass.pin.config);
5514         device_printf(sc->dev, "    Pin control: 0x%08x", w->wclass.pin.ctrl);
5515         if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE)
5516                 kprintf(" HP");
5517         if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE)
5518                 kprintf(" IN");
5519         if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE)
5520                 kprintf(" OUT");
5521         kprintf("\n");
5522 }
5523
5524 static void
5525 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner)
5526 {
5527         device_printf(sc->dev, "     %s amp: 0x%08x\n", banner, cap);
5528         device_printf(sc->dev, "                 "
5529             "mute=%d step=%d size=%d offset=%d\n",
5530             HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap),
5531             HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap),
5532             HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap),
5533             HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap));
5534 }
5535
5536 static void
5537 hdac_dump_nodes(struct hdac_devinfo *devinfo)
5538 {
5539         struct hdac_softc *sc = devinfo->codec->sc;
5540         struct hdac_widget *w, *cw;
5541         int i, j;
5542
5543         device_printf(sc->dev, "\n");
5544         device_printf(sc->dev, "Default Parameter\n");
5545         device_printf(sc->dev, "-----------------\n");
5546         hdac_dump_audio_formats(sc,
5547             devinfo->function.audio.supp_stream_formats,
5548             devinfo->function.audio.supp_pcm_size_rate);
5549         device_printf(sc->dev, "         IN amp: 0x%08x\n",
5550             devinfo->function.audio.inamp_cap);
5551         device_printf(sc->dev, "        OUT amp: 0x%08x\n",
5552             devinfo->function.audio.outamp_cap);
5553         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5554                 w = hdac_widget_get(devinfo, i);
5555                 if (w == NULL) {
5556                         device_printf(sc->dev, "Ghost widget nid=%d\n", i);
5557                         continue;
5558                 }
5559                 device_printf(sc->dev, "\n");
5560                 device_printf(sc->dev, "            nid: %d [%s]%s\n", w->nid,
5561                     HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ?
5562                     "DIGITAL" : "ANALOG",
5563                     (w->enable == 0) ? " [DISABLED]" : "");
5564                 device_printf(sc->dev, "           name: %s\n", w->name);
5565                 device_printf(sc->dev, "     widget_cap: 0x%08x\n",
5566                     w->param.widget_cap);
5567                 device_printf(sc->dev, "    Parse flags: 0x%08x\n",
5568                     w->pflags);
5569                 device_printf(sc->dev, "      Ctl flags: 0x%08x\n",
5570                     w->ctlflags);
5571                 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
5572                     w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
5573                         hdac_dump_audio_formats(sc,
5574                             w->param.supp_stream_formats,
5575                             w->param.supp_pcm_size_rate);
5576                 } else if (w->type ==
5577                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5578                         hdac_dump_pin(sc, w);
5579                 if (w->param.eapdbtl != HDAC_INVALID)
5580                         device_printf(sc->dev, "           EAPD: 0x%08x\n",
5581                             w->param.eapdbtl);
5582                 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) &&
5583                     w->param.outamp_cap != 0)
5584                         hdac_dump_amp(sc, w->param.outamp_cap, "Output");
5585                 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) &&
5586                     w->param.inamp_cap != 0)
5587                         hdac_dump_amp(sc, w->param.inamp_cap, " Input");
5588                 device_printf(sc->dev, "    connections: %d\n", w->nconns);
5589                 for (j = 0; j < w->nconns; j++) {
5590                         cw = hdac_widget_get(devinfo, w->conns[j]);
5591                         device_printf(sc->dev, "          |\n");
5592                         device_printf(sc->dev, "          + <- nid=%d [%s]",
5593                             w->conns[j], (cw == NULL) ? "GHOST!" : cw->name);
5594                         if (cw == NULL)
5595                                 kprintf(" [UNKNOWN]");
5596                         else if (cw->enable == 0)
5597                                 kprintf(" [DISABLED]");
5598                         if (w->nconns > 1 && w->selconn == j && w->type !=
5599                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5600                                 kprintf(" (selected)");
5601                         kprintf("\n");
5602                 }
5603         }
5604
5605 }
5606
5607 static int
5608 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth)
5609 {
5610         struct hdac_widget *w, *cw;
5611         struct hdac_softc *sc = devinfo->codec->sc;
5612         int i;
5613
5614         if (depth > HDA_PARSE_MAXDEPTH)
5615                 return (0);
5616
5617         w = hdac_widget_get(devinfo, nid);
5618         if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH))
5619                 return (0);
5620
5621         if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5622                 device_printf(sc->dev, "\n");
5623                 device_printf(sc->dev, "    nid=%d [%s]\n", w->nid, w->name);
5624                 device_printf(sc->dev, "      ^\n");
5625                 device_printf(sc->dev, "      |\n");
5626                 device_printf(sc->dev, "      +-----<------+\n");
5627         } else {
5628                 device_printf(sc->dev, "                   ^\n");
5629                 device_printf(sc->dev, "                   |\n");
5630                 device_printf(sc->dev, "               ");
5631                 kprintf("  nid=%d [%s]\n", w->nid, w->name);
5632         }
5633
5634         if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) {
5635                 return (1);
5636         } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) {
5637                 for (i = 0; i < w->nconns; i++) {
5638                         cw = hdac_widget_get(devinfo, w->conns[i]);
5639                         if (cw == NULL || cw->enable == 0 || cw->type ==
5640                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5641                                 continue;
5642                         if (hdac_dump_dac_internal(devinfo, cw->nid,
5643                             depth + 1) != 0)
5644                                 return (1);
5645                 }
5646         } else if ((w->type ==
5647             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR ||
5648             w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) &&
5649             w->selconn > -1 && w->selconn < w->nconns) {
5650                 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn],
5651                     depth + 1) != 0)
5652                         return (1);
5653         }
5654
5655         return (0);
5656 }
5657
5658 static void
5659 hdac_dump_dac(struct hdac_devinfo *devinfo)
5660 {
5661         struct hdac_widget *w;
5662         struct hdac_softc *sc = devinfo->codec->sc;
5663         int i, printed = 0;
5664
5665         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5666                 w = hdac_widget_get(devinfo, i);
5667                 if (w == NULL || w->enable == 0)
5668                         continue;
5669                 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
5670                     !(w->pflags & HDA_DAC_PATH))
5671                         continue;
5672                 if (printed == 0) {
5673                         printed = 1;
5674                         device_printf(sc->dev, "\n");
5675                         device_printf(sc->dev, "Playback path:\n");
5676                 }
5677                 hdac_dump_dac_internal(devinfo, w->nid, 0);
5678         }
5679 }
5680
5681 static void
5682 hdac_dump_adc(struct hdac_devinfo *devinfo)
5683 {
5684         struct hdac_widget *w, *cw;
5685         struct hdac_softc *sc = devinfo->codec->sc;
5686         int i, j;
5687         int printed = 0;
5688         char ossdevs[256];
5689
5690         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5691                 w = hdac_widget_get(devinfo, i);
5692                 if (w == NULL || w->enable == 0)
5693                         continue;
5694                 if (!(w->pflags & HDA_ADC_RECSEL))
5695                         continue;
5696                 if (printed == 0) {
5697                         printed = 1;
5698                         device_printf(sc->dev, "\n");
5699                         device_printf(sc->dev, "Recording sources:\n");
5700                 }
5701                 device_printf(sc->dev, "\n");
5702                 device_printf(sc->dev, "    nid=%d [%s]\n", w->nid, w->name);
5703                 for (j = 0; j < w->nconns; j++) {
5704                         cw = hdac_widget_get(devinfo, w->conns[j]);
5705                         if (cw == NULL || cw->enable == 0)
5706                                 continue;
5707                         hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags,
5708                             ossdevs, sizeof(ossdevs));
5709                         device_printf(sc->dev, "      |\n");
5710                         device_printf(sc->dev, "      + <- nid=%d [%s]",
5711                             cw->nid, cw->name);
5712                         if (strlen(ossdevs) > 0) {
5713                                 kprintf(" [recsrc: %s]", ossdevs);
5714                         }
5715                         kprintf("\n");
5716                 }
5717         }
5718 }
5719
5720 static void
5721 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt)
5722 {
5723         nid_t *nids;
5724
5725         if (pcnt > 0) {
5726                 device_printf(sc->dev, "\n");
5727                 device_printf(sc->dev, "   PCM Playback: %d\n", pcnt);
5728                 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5729                     sc->play.supp_pcm_size_rate);
5730                 device_printf(sc->dev, "            DAC:");
5731                 for (nids = sc->play.io; *nids != -1; nids++)
5732                         kprintf(" %d", *nids);
5733                 kprintf("\n");
5734         }
5735
5736         if (rcnt > 0) {
5737                 device_printf(sc->dev, "\n");
5738                 device_printf(sc->dev, "     PCM Record: %d\n", rcnt);
5739                 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5740                     sc->rec.supp_pcm_size_rate);
5741                 device_printf(sc->dev, "            ADC:");
5742                 for (nids = sc->rec.io; *nids != -1; nids++)
5743                         kprintf(" %d", *nids);
5744                 kprintf("\n");
5745         }
5746 }
5747
5748 static void
5749 hdac_release_resources(struct hdac_softc *sc)
5750 {
5751         struct hdac_devinfo *devinfo = NULL;
5752         device_t *devlist = NULL;
5753         int i, devcount;
5754
5755         if (sc == NULL)
5756                 return;
5757
5758         hdac_lock(sc);
5759         sc->polling = 0;
5760         sc->poll_ival = 0;
5761         callout_stop(&sc->poll_hda);
5762         callout_stop(&sc->poll_hdac);
5763         callout_stop(&sc->poll_jack);
5764         hdac_reset(sc);
5765         hdac_unlock(sc);
5766
5767         hdac_irq_free(sc);
5768
5769         /* give pending interrupts stuck on the lock a chance to clear */
5770         /* bad hack */
5771         tsleep(&sc->irq, 0, "hdaslp", hz / 10);
5772
5773         device_get_children(sc->dev, &devlist, &devcount);
5774         for (i = 0; devlist != NULL && i < devcount; i++) {
5775                 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
5776                 if (devinfo == NULL)
5777                         continue;
5778                 if (devinfo->widget != NULL)
5779                         kfree(devinfo->widget, M_HDAC);
5780                 if (devinfo->node_type ==
5781                     HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
5782                     devinfo->function.audio.ctl != NULL)
5783                         kfree(devinfo->function.audio.ctl, M_HDAC);
5784                 kfree(devinfo, M_HDAC);
5785                 device_delete_child(sc->dev, devlist[i]);
5786         }
5787         if (devlist != NULL)
5788                 kfree(devlist, M_TEMP);
5789
5790         for (i = 0; i < HDAC_CODEC_MAX; i++) {
5791                 if (sc->codecs[i] != NULL)
5792                         kfree(sc->codecs[i], M_HDAC);
5793                 sc->codecs[i] = NULL;
5794         }
5795
5796         hdac_dma_free(sc, &sc->pos_dma);
5797         hdac_dma_free(sc, &sc->rirb_dma);
5798         hdac_dma_free(sc, &sc->corb_dma);
5799         if (sc->play.blkcnt > 0)
5800                 hdac_dma_free(sc, &sc->play.bdl_dma);
5801         if (sc->rec.blkcnt > 0)
5802                 hdac_dma_free(sc, &sc->rec.bdl_dma);
5803         if (sc->chan_dmat != NULL) {
5804                 bus_dma_tag_destroy(sc->chan_dmat);
5805                 sc->chan_dmat = NULL;
5806         }
5807         hdac_mem_free(sc);
5808         snd_mtxfree(sc->lock);
5809         kfree(sc, M_DEVBUF);
5810 }
5811
5812 /* This function surely going to make its way into upper level someday. */
5813 static void
5814 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
5815 {
5816         char *res = NULL;
5817         int i = 0, j, k, len, inv;
5818
5819         if (on != NULL)
5820                 *on = 0;
5821         if (off != NULL)
5822                 *off = 0;
5823         if (sc == NULL)
5824                 return;
5825         if (resource_string_value(device_get_name(sc->dev),
5826             device_get_unit(sc->dev), "config", &res) != 0)
5827                 return;
5828         if (!(res != NULL && strlen(res) > 0))
5829                 return;
5830         HDA_BOOTVERBOSE(
5831                 device_printf(sc->dev, "HDA_DEBUG: HDA Config:");
5832         );
5833         for (;;) {
5834                 while (res[i] != '\0' &&
5835                     (res[i] == ',' || isspace(res[i]) != 0))
5836                         i++;
5837                 if (res[i] == '\0') {
5838                         HDA_BOOTVERBOSE(
5839                                 kprintf("\n");
5840                         );
5841                         return;
5842                 }
5843                 j = i;
5844                 while (res[j] != '\0' &&
5845                     !(res[j] == ',' || isspace(res[j]) != 0))
5846                         j++;
5847                 len = j - i;
5848                 if (len > 2 && strncmp(res + i, "no", 2) == 0)
5849                         inv = 2;
5850                 else
5851                         inv = 0;
5852                 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) {
5853                         if (strncmp(res + i + inv,
5854                             hdac_quirks_tab[k].key, len - inv) != 0)
5855                                 continue;
5856                         if (len - inv != strlen(hdac_quirks_tab[k].key))
5857                                 break;
5858                         HDA_BOOTVERBOSE(
5859                                 kprintf(" %s%s", (inv != 0) ? "no" : "",
5860                                     hdac_quirks_tab[k].key);
5861                         );
5862                         if (inv == 0 && on != NULL)
5863                                 *on |= hdac_quirks_tab[k].value;
5864                         else if (inv != 0 && off != NULL)
5865                                 *off |= hdac_quirks_tab[k].value;
5866                         break;
5867                 }
5868                 i = j;
5869         }
5870 }
5871
5872 #ifdef SND_DYNSYSCTL
5873 static int
5874 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
5875 {
5876         struct hdac_softc *sc;
5877         struct hdac_devinfo *devinfo;
5878         device_t dev;
5879         uint32_t ctl;
5880         int err, val;
5881
5882         dev = oidp->oid_arg1;
5883         devinfo = pcm_getdevinfo(dev);
5884         if (devinfo == NULL || devinfo->codec == NULL ||
5885             devinfo->codec->sc == NULL)
5886                 return (EINVAL);
5887         sc = devinfo->codec->sc;
5888         hdac_lock(sc);
5889         val = sc->polling;
5890         hdac_unlock(sc);
5891         err = sysctl_handle_int(oidp, &val, 0, req);
5892
5893         if (err != 0 || req->newptr == NULL)
5894                 return (err);
5895         if (val < 0 || val > 1)
5896                 return (EINVAL);
5897
5898         hdac_lock(sc);
5899         if (val != sc->polling) {
5900                 if (hda_chan_active(sc) != 0)
5901                         err = EBUSY;
5902                 else if (val == 0) {
5903                         callout_stop(&sc->poll_hdac);
5904                         hdac_unlock(sc);
5905                         hdac_lock(sc);
5906                         HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT,
5907                             sc->rirb_size / 2);
5908                         ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
5909                         ctl |= HDAC_RIRBCTL_RINTCTL;
5910                         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl);
5911                         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
5912                             HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
5913                         sc->polling = 0;
5914                         DELAY(1000);
5915                 } else {
5916                         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0);
5917                         HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0);
5918                         ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
5919                         ctl &= ~HDAC_RIRBCTL_RINTCTL;
5920                         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl);
5921                         callout_reset(&sc->poll_hdac, 1, hdac_poll_callback,
5922                             sc);
5923                         sc->polling = 1;
5924                         DELAY(1000);
5925                 }
5926         }
5927         hdac_unlock(sc);
5928
5929         return (err);
5930 }
5931
5932 static int
5933 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS)
5934 {
5935         struct hdac_softc *sc;
5936         struct hdac_devinfo *devinfo;
5937         device_t dev;
5938         int err, val;
5939
5940         dev = oidp->oid_arg1;
5941         devinfo = pcm_getdevinfo(dev);
5942         if (devinfo == NULL || devinfo->codec == NULL ||
5943             devinfo->codec->sc == NULL)
5944                 return (EINVAL);
5945         sc = devinfo->codec->sc;
5946         hdac_lock(sc);
5947         val = ((uint64_t)sc->poll_ival * 1000) / hz;
5948         hdac_unlock(sc);
5949         err = sysctl_handle_int(oidp, &val, 0, req);
5950
5951         if (err != 0 || req->newptr == NULL)
5952                 return (err);
5953
5954         if (val < 1)
5955                 val = 1;
5956         if (val > 5000)
5957                 val = 5000;
5958         val = ((uint64_t)val * hz) / 1000;
5959         if (val < 1)
5960                 val = 1;
5961         if (val > (hz * 5))
5962                 val = hz * 5;
5963
5964         hdac_lock(sc);
5965         sc->poll_ival = val;
5966         hdac_unlock(sc);
5967
5968         return (err);
5969 }
5970
5971 #ifdef SND_DEBUG
5972 static int
5973 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
5974 {
5975         struct hdac_softc *sc;
5976         struct hdac_devinfo *devinfo;
5977         struct hdac_widget *w;
5978         device_t dev;
5979         uint32_t res, pincap, execres;
5980         int i, err, val;
5981         nid_t cad;
5982
5983         dev = oidp->oid_arg1;
5984         devinfo = pcm_getdevinfo(dev);
5985         if (devinfo == NULL || devinfo->codec == NULL ||
5986             devinfo->codec->sc == NULL)
5987                 return (EINVAL);
5988         val = 0;
5989         err = sysctl_handle_int(oidp, &val, 0, req);
5990         if (err != 0 || req->newptr == NULL || val == 0)
5991                 return (err);
5992         sc = devinfo->codec->sc;
5993         cad = devinfo->codec->cad;
5994         hdac_lock(sc);
5995         device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid);
5996         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5997                 w = hdac_widget_get(devinfo, i);
5998                 if (w == NULL || w->type !=
5999                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6000                         continue;
6001                 pincap = w->wclass.pin.cap;
6002                 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) ||
6003                     HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) &&
6004                     HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) {
6005                         timeout = 10000;
6006                         hdac_command(sc,
6007                             HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad);
6008                         do {
6009                                 res = hdac_command(sc,
6010                                     HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
6011                                 if (res != 0x7fffffff)
6012                                         break;
6013                                 DELAY(10);
6014                         } while (--timeout != 0);
6015                 } else {
6016                         timeout = -1;
6017                         res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad,
6018                             w->nid), cad);
6019                 }
6020                 device_printf(dev,
6021                     "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n",
6022                     w->nid, timeout, res,
6023                     (w->enable == 0) ? "DISABLED" : "ENABLED");
6024         }
6025         device_printf(dev,
6026             "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
6027             HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
6028             HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
6029             HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
6030             HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
6031             HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
6032         if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) {
6033                 device_printf(dev, " GPI:");
6034                 res = hdac_command(sc,
6035                     HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad);
6036                 kprintf(" data=0x%08x", res);
6037                 res = hdac_command(sc,
6038                     HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid),
6039                     cad);
6040                 kprintf(" wake=0x%08x", res);
6041                 res = hdac_command(sc,
6042                     HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
6043                     cad);
6044                 kprintf(" unsol=0x%08x", res);
6045                 res = hdac_command(sc,
6046                     HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad);
6047                 kprintf(" sticky=0x%08x\n", res);
6048         }
6049         if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) {
6050                 device_printf(dev, " GPO:");
6051                 res = hdac_command(sc,
6052                     HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad);
6053                 kprintf(" data=0x%08x\n", res);
6054         }
6055         if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) {
6056                 device_printf(dev, "GPI0:");
6057                 res = hdac_command(sc,
6058                     HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad);
6059                 kprintf(" data=0x%08x", res);
6060                 res = hdac_command(sc,
6061                     HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad);
6062                 kprintf(" enable=0x%08x", res);
6063                 res = hdac_command(sc,
6064                     HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad);
6065                 kprintf(" direction=0x%08x\n", res);
6066                 res = hdac_command(sc,
6067                     HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad);
6068                 device_printf(dev, "      wake=0x%08x", res);
6069                 res = hdac_command(sc,
6070                     HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
6071                     cad);
6072                 kprintf("  unsol=0x%08x", res);
6073                 res = hdac_command(sc,
6074                     HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad);
6075                 kprintf("    sticky=0x%08x\n", res);
6076         }
6077         hdac_unlock(sc);
6078         return (0);
6079 }
6080 #endif
6081 #endif
6082
6083 static void
6084 hdac_attach2(void *arg)
6085 {
6086         struct hdac_softc *sc;
6087         struct hdac_widget *w;
6088         struct hdac_audio_ctl *ctl;
6089         uint32_t quirks_on, quirks_off;
6090         int pcnt, rcnt, codec_index;
6091         int i;
6092         char status[SND_STATUSLEN];
6093         device_t *devlist = NULL;
6094         int devcount;
6095         struct hdac_devinfo *devinfo = NULL;
6096
6097         sc = (struct hdac_softc *)arg;
6098
6099         hdac_config_fetch(sc, &quirks_on, &quirks_off);
6100
6101         HDA_BOOTVERBOSE(
6102                 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n",
6103                     quirks_on, quirks_off);
6104         );
6105
6106         if (resource_int_value(device_get_name(sc->dev),
6107             device_get_unit(sc->dev), "codec_index", &codec_index) != 0) {
6108                 switch (sc->pci_subvendor) {
6109                 case GB_G33S2H_SUBVENDOR:
6110                         codec_index = 2;
6111                         break;
6112                 default:
6113                         codec_index = 0;
6114                         break;
6115                 }
6116         }
6117
6118         hdac_lock(sc);
6119
6120         /* Remove ourselves from the config hooks */
6121         if (sc->intrhook.ich_func != NULL) {
6122                 config_intrhook_disestablish(&sc->intrhook);
6123                 sc->intrhook.ich_func = NULL;
6124         }
6125
6126         /* Start the corb and rirb engines */
6127         HDA_BOOTVERBOSE(
6128                 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n");
6129         );
6130         hdac_corb_start(sc);
6131         HDA_BOOTVERBOSE(
6132                 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n");
6133         );
6134         hdac_rirb_start(sc);
6135
6136         HDA_BOOTVERBOSE(
6137                 device_printf(sc->dev,
6138                     "HDA_DEBUG: Enabling controller interrupt...\n");
6139         );
6140         if (sc->polling == 0)
6141                 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
6142                     HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
6143         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
6144             HDAC_GCTL_UNSOL);
6145
6146         DELAY(1000);
6147
6148         HDA_BOOTVERBOSE(
6149                 device_printf(sc->dev,
6150                     "HDA_DEBUG: Scanning HDA codecs [start index=%d] ...\n",
6151                     codec_index);
6152         );
6153         hdac_scan_codecs(sc, codec_index);
6154
6155         device_get_children(sc->dev, &devlist, &devcount);
6156         for (i = 0; devlist != NULL && i < devcount; i++) {
6157                 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
6158                 if (devinfo != NULL && devinfo->node_type ==
6159                     HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
6160                         break;
6161                 } else
6162                         devinfo = NULL;
6163         }
6164         if (devlist != NULL)
6165                 kfree(devlist, M_TEMP);
6166
6167         if (devinfo == NULL) {
6168                 hdac_unlock(sc);
6169                 device_printf(sc->dev, "Audio Function Group not found!\n");
6170                 hdac_release_resources(sc);
6171                 return;
6172         }
6173
6174         HDA_BOOTVERBOSE(
6175                 device_printf(sc->dev,
6176                     "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n",
6177                     devinfo->nid, devinfo->codec->cad);
6178         );
6179         hdac_audio_parse(devinfo);
6180         HDA_BOOTVERBOSE(
6181                 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n");
6182         );
6183         hdac_audio_ctl_parse(devinfo);
6184         HDA_BOOTVERBOSE(
6185                 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n");
6186         );
6187         hdac_vendor_patch_parse(devinfo);
6188         if (quirks_on != 0)
6189                 devinfo->function.audio.quirks |= quirks_on;
6190         if (quirks_off != 0)
6191                 devinfo->function.audio.quirks &= ~quirks_off;
6192
6193         /* XXX Disable all DIGITAL path. */
6194         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6195                 w = hdac_widget_get(devinfo, i);
6196                 if (w == NULL)
6197                         continue;
6198                 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
6199                         w->enable = 0;
6200                         continue;
6201                 }
6202                 /* XXX Disable useless pin ? */
6203                 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6204                     (w->wclass.pin.config &
6205                     HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
6206                     HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE)
6207                         w->enable = 0;
6208         }
6209         i = 0;
6210         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6211                 if (ctl->widget == NULL)
6212                         continue;
6213                 if (ctl->ossmask & SOUND_MASK_DISABLE)
6214                         ctl->enable = 0;
6215                 w = ctl->widget;
6216                 if (w->enable == 0 ||
6217                     HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6218                         ctl->enable = 0;
6219                 w = ctl->childwidget;
6220                 if (w == NULL)
6221                         continue;
6222                 if (w->enable == 0 ||
6223                     HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6224                         ctl->enable = 0;
6225         }
6226
6227         HDA_BOOTVERBOSE(
6228                 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n");
6229         );
6230         hdac_audio_build_tree(devinfo);
6231
6232         i = 0;
6233         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6234                 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))
6235                         ctl->ossmask = 0;
6236         }
6237         HDA_BOOTVERBOSE(
6238                 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n");
6239         );
6240         hdac_audio_commit(devinfo, HDA_COMMIT_ALL);
6241         HDA_BOOTVERBOSE(
6242                 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n");
6243         );
6244         hdac_audio_ctl_commit(devinfo);
6245
6246         HDA_BOOTVERBOSE(
6247                 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n");
6248         );
6249         pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY);
6250         HDA_BOOTVERBOSE(
6251                 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n");
6252         );
6253         rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC);
6254
6255         hdac_unlock(sc);
6256         HDA_BOOTVERBOSE(
6257                 device_printf(sc->dev,
6258                     "HDA_DEBUG: OSS mixer initialization...\n");
6259         );
6260
6261         /*
6262          * There is no point of return after this. If the driver failed,
6263          * so be it. Let the detach procedure do all the cleanup.
6264          */
6265         if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0)
6266                 device_printf(sc->dev, "Can't register mixer\n");
6267
6268         if (pcnt > 0)
6269                 pcnt = 1;
6270         if (rcnt > 0)
6271                 rcnt = 1;
6272
6273         HDA_BOOTVERBOSE(
6274                 device_printf(sc->dev,
6275                     "HDA_DEBUG: Registering PCM channels...\n");
6276         );
6277         if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0)
6278                 device_printf(sc->dev, "Can't register PCM\n");
6279
6280         sc->registered++;
6281
6282         if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) &&
6283             hdac_dma_alloc(sc, &sc->pos_dma,
6284             (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) {
6285                 HDA_BOOTVERBOSE(
6286                         device_printf(sc->dev,
6287                             "Failed to allocate DMA pos buffer (non-fatal)\n");
6288                 );
6289         }
6290
6291         for (i = 0; i < pcnt; i++)
6292                 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo);
6293         for (i = 0; i < rcnt; i++)
6294                 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo);
6295
6296 #ifdef SND_DYNSYSCTL
6297         SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6298             SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6299             "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
6300             sysctl_hdac_polling, "I", "Enable polling mode");
6301         SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6302             SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6303             "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev,
6304             sizeof(sc->dev), sysctl_hdac_polling_interval, "I",
6305             "Controller/Jack Sense polling interval (1-1000 ms)");
6306 #ifdef SND_DEBUG
6307         SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6308             SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6309             "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
6310             sysctl_hdac_pindump, "I", "Dump pin states/data");
6311 #endif
6312 #endif
6313
6314         ksnprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]",
6315             rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res),
6316             PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV);
6317         pcm_setstatus(sc->dev, status);
6318         device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo));
6319         HDA_BOOTVERBOSE(
6320                 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n",
6321                     hdac_codec_id(devinfo));
6322         );
6323         device_printf(sc->dev, "<HDA Driver Revision: %s>\n",
6324             HDA_DRV_TEST_REV);
6325
6326         HDA_BOOTVERBOSE(
6327                 if (devinfo->function.audio.quirks != 0) {
6328                         device_printf(sc->dev, "\n");
6329                         device_printf(sc->dev, "HDA config/quirks:");
6330                         for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) {
6331                                 if ((devinfo->function.audio.quirks &
6332                                     hdac_quirks_tab[i].value) ==
6333                                     hdac_quirks_tab[i].value)
6334                                         kprintf(" %s", hdac_quirks_tab[i].key);
6335                         }
6336                         kprintf("\n");
6337                 }
6338                 device_printf(sc->dev, "\n");
6339                 device_printf(sc->dev, "+-------------------+\n");
6340                 device_printf(sc->dev, "| DUMPING HDA NODES |\n");
6341                 device_printf(sc->dev, "+-------------------+\n");
6342                 hdac_dump_nodes(devinfo);
6343                 device_printf(sc->dev, "\n");
6344                 device_printf(sc->dev, "+------------------------+\n");
6345                 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n");
6346                 device_printf(sc->dev, "+------------------------+\n");
6347                 device_printf(sc->dev, "\n");
6348                 i = 0;
6349                 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6350                         device_printf(sc->dev, "%3d: nid=%d", i,
6351                             (ctl->widget != NULL) ? ctl->widget->nid : -1);
6352                         if (ctl->childwidget != NULL)
6353                                 kprintf(" cnid=%d", ctl->childwidget->nid);
6354                         kprintf(" dir=0x%x index=%d "
6355                             "ossmask=0x%08x ossdev=%d%s\n",
6356                             ctl->dir, ctl->index,
6357                             ctl->ossmask, ctl->ossdev,
6358                             (ctl->enable == 0) ? " [DISABLED]" : "");
6359                 }
6360                 device_printf(sc->dev, "\n");
6361                 device_printf(sc->dev, "+-----------------------------------+\n");
6362                 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n");
6363                 device_printf(sc->dev, "+-----------------------------------+\n");
6364                 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME);
6365                 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM);
6366                 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD);
6367                 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC);
6368                 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE);
6369                 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV);
6370                 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER);
6371                 hdac_dump_ctls(devinfo, NULL, 0);
6372                 hdac_dump_dac(devinfo);
6373                 hdac_dump_adc(devinfo);
6374                 device_printf(sc->dev, "\n");
6375                 device_printf(sc->dev, "+--------------------------------------+\n");
6376                 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n");
6377                 device_printf(sc->dev, "+--------------------------------------+\n");
6378                 hdac_dump_pcmchannels(sc, pcnt, rcnt);
6379         );
6380
6381         if (sc->polling != 0) {
6382                 hdac_lock(sc);
6383                 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
6384                 hdac_unlock(sc);
6385         }
6386 }
6387
6388 /****************************************************************************
6389  * int hdac_detach(device_t)
6390  *
6391  * Detach and free up resources utilized by the hdac device.
6392  ****************************************************************************/
6393 static int
6394 hdac_detach(device_t dev)
6395 {
6396         struct hdac_softc *sc = NULL;
6397         struct hdac_devinfo *devinfo = NULL;
6398         int err;
6399
6400         devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev);
6401         if (devinfo != NULL && devinfo->codec != NULL)
6402                 sc = devinfo->codec->sc;
6403         if (sc == NULL)
6404                 return (0);
6405
6406         if (sc->registered > 0) {
6407                 err = pcm_unregister(dev);
6408                 if (err != 0)
6409                         return (err);
6410         }
6411
6412         hdac_release_resources(sc);
6413
6414         return (0);
6415 }
6416
6417 static device_method_t hdac_methods[] = {
6418         /* device interface */
6419         DEVMETHOD(device_probe,         hdac_probe),
6420         DEVMETHOD(device_attach,        hdac_attach),
6421         DEVMETHOD(device_detach,        hdac_detach),
6422         { 0, 0 }
6423 };
6424
6425 static driver_t hdac_driver = {
6426         "pcm",
6427         hdac_methods,
6428         PCM_SOFTC_SIZE,
6429 };
6430
6431 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0);
6432 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
6433 MODULE_VERSION(snd_hda, 1);