sys/dev/netif/ig_hal/e1000_nvm.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2014, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD:$*/
  34
  35 #include "e1000_api.h"
  36
  37 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
  38
  39 /**
  40  *  e1000_init_nvm_ops_generic - Initialize NVM function pointers
  41  *  @hw: pointer to the HW structure
  42  *
  43  *  Setups up the function pointers to no-op functions
  44  **/
  45 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
  46 {
  47         struct e1000_nvm_info *nvm = &hw->nvm;
  48         DEBUGFUNC("e1000_init_nvm_ops_generic");
  49
  50         /* Initialize function pointers */
  51         nvm->ops.init_params = e1000_null_ops_generic;
  52         nvm->ops.acquire = e1000_null_ops_generic;
  53         nvm->ops.read = e1000_null_read_nvm;
  54         nvm->ops.release = e1000_null_nvm_generic;
  55         nvm->ops.reload = e1000_reload_nvm_generic;
  56         nvm->ops.update = e1000_null_ops_generic;
  57         nvm->ops.valid_led_default = e1000_null_led_default;
  58         nvm->ops.validate = e1000_null_ops_generic;
  59         nvm->ops.write = e1000_null_write_nvm;
  60 }
  61
  62 /**
  63  *  e1000_null_nvm_read - No-op function, return 0
  64  *  @hw: pointer to the HW structure
  65  **/
  66 s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
  67                         u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
  68                         u16 E1000_UNUSEDARG *c)
  69 {
  70         DEBUGFUNC("e1000_null_read_nvm");
  71         return E1000_SUCCESS;
  72 }
  73
  74 /**
  75  *  e1000_null_nvm_generic - No-op function, return void
  76  *  @hw: pointer to the HW structure
  77  **/
  78 void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
  79 {
  80         DEBUGFUNC("e1000_null_nvm_generic");
  81         return;
  82 }
  83
  84 /**
  85  *  e1000_null_led_default - No-op function, return 0
  86  *  @hw: pointer to the HW structure
  87  **/
  88 s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
  89                            u16 E1000_UNUSEDARG *data)
  90 {
  91         DEBUGFUNC("e1000_null_led_default");
  92         return E1000_SUCCESS;
  93 }
  94
  95 /**
  96  *  e1000_null_write_nvm - No-op function, return 0
  97  *  @hw: pointer to the HW structure
  98  **/
  99 s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
 100                          u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
 101                          u16 E1000_UNUSEDARG *c)
 102 {
 103         DEBUGFUNC("e1000_null_write_nvm");
 104         return E1000_SUCCESS;
 105 }
 106
 107 /**
 108  *  e1000_raise_eec_clk - Raise EEPROM clock
 109  *  @hw: pointer to the HW structure
 110  *  @eecd: pointer to the EEPROM
 111  *
 112  *  Enable/Raise the EEPROM clock bit.
 113  **/
 114 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
 115 {
 116         *eecd = *eecd | E1000_EECD_SK;
 117         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 118         E1000_WRITE_FLUSH(hw);
 119         usec_delay(hw->nvm.delay_usec);
 120 }
 121
 122 /**
 123  *  e1000_lower_eec_clk - Lower EEPROM clock
 124  *  @hw: pointer to the HW structure
 125  *  @eecd: pointer to the EEPROM
 126  *
 127  *  Clear/Lower the EEPROM clock bit.
 128  **/
 129 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
 130 {
 131         *eecd = *eecd & ~E1000_EECD_SK;
 132         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 133         E1000_WRITE_FLUSH(hw);
 134         usec_delay(hw->nvm.delay_usec);
 135 }
 136
 137 /**
 138  *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
 139  *  @hw: pointer to the HW structure
 140  *  @data: data to send to the EEPROM
 141  *  @count: number of bits to shift out
 142  *
 143  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
 144  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
 145  *  In order to do this, "data" must be broken down into bits.
 146  **/
 147 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
 148 {
 149         struct e1000_nvm_info *nvm = &hw->nvm;
 150         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 151         u32 mask;
 152
 153         DEBUGFUNC("e1000_shift_out_eec_bits");
 154
 155         mask = 0x01 << (count - 1);
 156         if (nvm->type == e1000_nvm_eeprom_microwire)
 157                 eecd &= ~E1000_EECD_DO;
 158         else
 159         if (nvm->type == e1000_nvm_eeprom_spi)
 160                 eecd |= E1000_EECD_DO;
 161
 162         do {
 163                 eecd &= ~E1000_EECD_DI;
 164
 165                 if (data & mask)
 166                         eecd |= E1000_EECD_DI;
 167
 168                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 169                 E1000_WRITE_FLUSH(hw);
 170
 171                 usec_delay(nvm->delay_usec);
 172
 173                 e1000_raise_eec_clk(hw, &eecd);
 174                 e1000_lower_eec_clk(hw, &eecd);
 175
 176                 mask >>= 1;
 177         } while (mask);
 178
 179         eecd &= ~E1000_EECD_DI;
 180         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 181 }
 182
 183 /**
 184  *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
 185  *  @hw: pointer to the HW structure
 186  *  @count: number of bits to shift in
 187  *
 188  *  In order to read a register from the EEPROM, we need to shift 'count' bits
 189  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
 190  *  the EEPROM (setting the SK bit), and then reading the value of the data out
 191  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
 192  *  always be clear.
 193  **/
 194 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
 195 {
 196         u32 eecd;
 197         u32 i;
 198         u16 data;
 199
 200         DEBUGFUNC("e1000_shift_in_eec_bits");
 201
 202         eecd = E1000_READ_REG(hw, E1000_EECD);
 203
 204         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 205         data = 0;
 206
 207         for (i = 0; i < count; i++) {
 208                 data <<= 1;
 209                 e1000_raise_eec_clk(hw, &eecd);
 210
 211                 eecd = E1000_READ_REG(hw, E1000_EECD);
 212
 213                 eecd &= ~E1000_EECD_DI;
 214                 if (eecd & E1000_EECD_DO)
 215                         data |= 1;
 216
 217                 e1000_lower_eec_clk(hw, &eecd);
 218         }
 219
 220         return data;
 221 }
 222
 223 /**
 224  *  e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
 225  *  @hw: pointer to the HW structure
 226  *  @ee_reg: EEPROM flag for polling
 227  *
 228  *  Polls the EEPROM status bit for either read or write completion based
 229  *  upon the value of 'ee_reg'.
 230  **/
 231 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
 232 {
 233         u32 attempts = 100000;
 234         u32 i, reg = 0;
 235
 236         DEBUGFUNC("e1000_poll_eerd_eewr_done");
 237
 238         for (i = 0; i < attempts; i++) {
 239                 if (ee_reg == E1000_NVM_POLL_READ)
 240                         reg = E1000_READ_REG(hw, E1000_EERD);
 241                 else
 242                         reg = E1000_READ_REG(hw, E1000_EEWR);
 243
 244                 if (reg & E1000_NVM_RW_REG_DONE)
 245                         return E1000_SUCCESS;
 246
 247                 usec_delay(5);
 248         }
 249
 250         return -E1000_ERR_NVM;
 251 }
 252
 253 /**
 254  *  e1000_acquire_nvm_generic - Generic request for access to EEPROM
 255  *  @hw: pointer to the HW structure
 256  *
 257  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 258  *  Return successful if access grant bit set, else clear the request for
 259  *  EEPROM access and return -E1000_ERR_NVM (-1).
 260  **/
 261 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
 262 {
 263         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 264         s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
 265
 266         DEBUGFUNC("e1000_acquire_nvm_generic");
 267
 268         E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
 269         eecd = E1000_READ_REG(hw, E1000_EECD);
 270
 271         while (timeout) {
 272                 if (eecd & E1000_EECD_GNT)
 273                         break;
 274                 usec_delay(5);
 275                 eecd = E1000_READ_REG(hw, E1000_EECD);
 276                 timeout--;
 277         }
 278
 279         if (!timeout) {
 280                 eecd &= ~E1000_EECD_REQ;
 281                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 282                 DEBUGOUT("Could not acquire NVM grant\n");
 283                 return -E1000_ERR_NVM;
 284         }
 285
 286         return E1000_SUCCESS;
 287 }
 288
 289 /**
 290  *  e1000_standby_nvm - Return EEPROM to standby state
 291  *  @hw: pointer to the HW structure
 292  *
 293  *  Return the EEPROM to a standby state.
 294  **/
 295 static void e1000_standby_nvm(struct e1000_hw *hw)
 296 {
 297         struct e1000_nvm_info *nvm = &hw->nvm;
 298         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 299
 300         DEBUGFUNC("e1000_standby_nvm");
 301
 302         if (nvm->type == e1000_nvm_eeprom_microwire) {
 303                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 304                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 305                 E1000_WRITE_FLUSH(hw);
 306                 usec_delay(nvm->delay_usec);
 307
 308                 e1000_raise_eec_clk(hw, &eecd);
 309
 310                 /* Select EEPROM */
 311                 eecd |= E1000_EECD_CS;
 312                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 313                 E1000_WRITE_FLUSH(hw);
 314                 usec_delay(nvm->delay_usec);
 315
 316                 e1000_lower_eec_clk(hw, &eecd);
 317         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 318                 /* Toggle CS to flush commands */
 319                 eecd |= E1000_EECD_CS;
 320                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 321                 E1000_WRITE_FLUSH(hw);
 322                 usec_delay(nvm->delay_usec);
 323                 eecd &= ~E1000_EECD_CS;
 324                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 325                 E1000_WRITE_FLUSH(hw);
 326                 usec_delay(nvm->delay_usec);
 327         }
 328 }
 329
 330 /**
 331  *  e1000_stop_nvm - Terminate EEPROM command
 332  *  @hw: pointer to the HW structure
 333  *
 334  *  Terminates the current command by inverting the EEPROM's chip select pin.
 335  **/
 336 #ifdef NO_82542_SUPPORT
 337 static void e1000_stop_nvm(struct e1000_hw *hw)
 338 #else
 339 void e1000_stop_nvm(struct e1000_hw *hw)
 340 #endif
 341 {
 342         u32 eecd;
 343
 344         DEBUGFUNC("e1000_stop_nvm");
 345
 346         eecd = E1000_READ_REG(hw, E1000_EECD);
 347         if (hw->nvm.type == e1000_nvm_eeprom_spi) {
 348                 /* Pull CS high */
 349                 eecd |= E1000_EECD_CS;
 350                 e1000_lower_eec_clk(hw, &eecd);
 351         } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
 352                 /* CS on Microwire is active-high */
 353                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 354                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 355                 e1000_raise_eec_clk(hw, &eecd);
 356                 e1000_lower_eec_clk(hw, &eecd);
 357         }
 358 }
 359
 360 /**
 361  *  e1000_release_nvm_generic - Release exclusive access to EEPROM
 362  *  @hw: pointer to the HW structure
 363  *
 364  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 365  **/
 366 void e1000_release_nvm_generic(struct e1000_hw *hw)
 367 {
 368         u32 eecd;
 369
 370         DEBUGFUNC("e1000_release_nvm_generic");
 371
 372         e1000_stop_nvm(hw);
 373
 374         eecd = E1000_READ_REG(hw, E1000_EECD);
 375         eecd &= ~E1000_EECD_REQ;
 376         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 377 }
 378
 379 /**
 380  *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
 381  *  @hw: pointer to the HW structure
 382  *
 383  *  Setups the EEPROM for reading and writing.
 384  **/
 385 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
 386 {
 387         struct e1000_nvm_info *nvm = &hw->nvm;
 388         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 389         u8 spi_stat_reg;
 390
 391         DEBUGFUNC("e1000_ready_nvm_eeprom");
 392
 393         if (nvm->type == e1000_nvm_eeprom_microwire) {
 394                 /* Clear SK and DI */
 395                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 396                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 397                 /* Set CS */
 398                 eecd |= E1000_EECD_CS;
 399                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 400         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 401                 u16 timeout = NVM_MAX_RETRY_SPI;
 402
 403                 /* Clear SK and CS */
 404                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 405                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 406                 E1000_WRITE_FLUSH(hw);
 407                 usec_delay(1);
 408
 409                 /* Read "Status Register" repeatedly until the LSB is cleared.
 410                  * The EEPROM will signal that the command has been completed
 411                  * by clearing bit 0 of the internal status register.  If it's
 412                  * not cleared within 'timeout', then error out.
 413                  */
 414                 while (timeout) {
 415                         e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
 416                                                  hw->nvm.opcode_bits);
 417                         spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
 418                         if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
 419                                 break;
 420
 421                         usec_delay(5);
 422                         e1000_standby_nvm(hw);
 423                         timeout--;
 424                 }
 425
 426                 if (!timeout) {
 427                         DEBUGOUT("SPI NVM Status error\n");
 428                         return -E1000_ERR_NVM;
 429                 }
 430         }
 431
 432         return E1000_SUCCESS;
 433 }
 434
 435 /**
 436  *  e1000_read_nvm_spi - Read EEPROM's using SPI
 437  *  @hw: pointer to the HW structure
 438  *  @offset: offset of word in the EEPROM to read
 439  *  @words: number of words to read
 440  *  @data: word read from the EEPROM
 441  *
 442  *  Reads a 16 bit word from the EEPROM.
 443  **/
 444 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 445 {
 446         struct e1000_nvm_info *nvm = &hw->nvm;
 447         u32 i = 0;
 448         s32 ret_val;
 449         u16 word_in;
 450         u8 read_opcode = NVM_READ_OPCODE_SPI;
 451
 452         DEBUGFUNC("e1000_read_nvm_spi");
 453
 454         /* A check for invalid values:  offset too large, too many words,
 455          * and not enough words.
 456          */
 457         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 458             (words == 0)) {
 459                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 460                 return -E1000_ERR_NVM;
 461         }
 462
 463         ret_val = nvm->ops.acquire(hw);
 464         if (ret_val)
 465                 return ret_val;
 466
 467         ret_val = e1000_ready_nvm_eeprom(hw);
 468         if (ret_val)
 469                 goto release;
 470
 471         e1000_standby_nvm(hw);
 472
 473         if ((nvm->address_bits == 8) && (offset >= 128))
 474                 read_opcode |= NVM_A8_OPCODE_SPI;
 475
 476         /* Send the READ command (opcode + addr) */
 477         e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 478         e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
 479
 480         /* Read the data.  SPI NVMs increment the address with each byte
 481          * read and will roll over if reading beyond the end.  This allows
 482          * us to read the whole NVM from any offset
 483          */
 484         for (i = 0; i < words; i++) {
 485                 word_in = e1000_shift_in_eec_bits(hw, 16);
 486                 data[i] = (word_in >> 8) | (word_in << 8);
 487         }
 488
 489 release:
 490         nvm->ops.release(hw);
 491
 492         return ret_val;
 493 }
 494
 495 /**
 496  *  e1000_read_nvm_microwire - Reads EEPROM's using microwire
 497  *  @hw: pointer to the HW structure
 498  *  @offset: offset of word in the EEPROM to read
 499  *  @words: number of words to read
 500  *  @data: word read from the EEPROM
 501  *
 502  *  Reads a 16 bit word from the EEPROM.
 503  **/
 504 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 505                              u16 *data)
 506 {
 507         struct e1000_nvm_info *nvm = &hw->nvm;
 508         u32 i = 0;
 509         s32 ret_val;
 510         u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
 511
 512         DEBUGFUNC("e1000_read_nvm_microwire");
 513
 514         /* A check for invalid values:  offset too large, too many words,
 515          * and not enough words.
 516          */
 517         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 518             (words == 0)) {
 519                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 520                 return -E1000_ERR_NVM;
 521         }
 522
 523         ret_val = nvm->ops.acquire(hw);
 524         if (ret_val)
 525                 return ret_val;
 526
 527         ret_val = e1000_ready_nvm_eeprom(hw);
 528         if (ret_val)
 529                 goto release;
 530
 531         for (i = 0; i < words; i++) {
 532                 /* Send the READ command (opcode + addr) */
 533                 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 534                 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
 535                                         nvm->address_bits);
 536
 537                 /* Read the data.  For microwire, each word requires the
 538                  * overhead of setup and tear-down.
 539                  */
 540                 data[i] = e1000_shift_in_eec_bits(hw, 16);
 541                 e1000_standby_nvm(hw);
 542         }
 543
 544 release:
 545         nvm->ops.release(hw);
 546
 547         return ret_val;
 548 }
 549
 550 /**
 551  *  e1000_read_nvm_eerd - Reads EEPROM using EERD register
 552  *  @hw: pointer to the HW structure
 553  *  @offset: offset of word in the EEPROM to read
 554  *  @words: number of words to read
 555  *  @data: word read from the EEPROM
 556  *
 557  *  Reads a 16 bit word from the EEPROM using the EERD register.
 558  **/
 559 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 560 {
 561         struct e1000_nvm_info *nvm = &hw->nvm;
 562         u32 i, eerd = 0;
 563         s32 ret_val = E1000_SUCCESS;
 564
 565         DEBUGFUNC("e1000_read_nvm_eerd");
 566
 567         /* A check for invalid values:  offset too large, too many words,
 568          * too many words for the offset, and not enough words.
 569          */
 570         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 571             (words == 0)) {
 572                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 573                 return -E1000_ERR_NVM;
 574         }
 575
 576         for (i = 0; i < words; i++) {
 577                 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
 578                        E1000_NVM_RW_REG_START;
 579
 580                 E1000_WRITE_REG(hw, E1000_EERD, eerd);
 581                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
 582                 if (ret_val)
 583                         break;
 584
 585                 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
 586                            E1000_NVM_RW_REG_DATA);
 587         }
 588
 589         if (ret_val)
 590                 DEBUGOUT1("NVM read error: %d\n", ret_val);
 591
 592         return ret_val;
 593 }
 594
 595 /**
 596  *  e1000_write_nvm_spi - Write to EEPROM using SPI
 597  *  @hw: pointer to the HW structure
 598  *  @offset: offset within the EEPROM to be written to
 599  *  @words: number of words to write
 600  *  @data: 16 bit word(s) to be written to the EEPROM
 601  *
 602  *  Writes data to EEPROM at offset using SPI interface.
 603  *
 604  *  If e1000_update_nvm_checksum is not called after this function , the
 605  *  EEPROM will most likely contain an invalid checksum.
 606  **/
 607 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 608 {
 609         struct e1000_nvm_info *nvm = &hw->nvm;
 610         s32 ret_val = -E1000_ERR_NVM;
 611         u16 widx = 0;
 612
 613         DEBUGFUNC("e1000_write_nvm_spi");
 614
 615         /* A check for invalid values:  offset too large, too many words,
 616          * and not enough words.
 617          */
 618         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 619             (words == 0)) {
 620                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 621                 return -E1000_ERR_NVM;
 622         }
 623
 624         while (widx < words) {
 625                 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
 626
 627                 ret_val = nvm->ops.acquire(hw);
 628                 if (ret_val)
 629                         return ret_val;
 630
 631                 ret_val = e1000_ready_nvm_eeprom(hw);
 632                 if (ret_val) {
 633                         nvm->ops.release(hw);
 634                         return ret_val;
 635                 }
 636
 637                 e1000_standby_nvm(hw);
 638
 639                 /* Send the WRITE ENABLE command (8 bit opcode) */
 640                 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
 641                                          nvm->opcode_bits);
 642
 643                 e1000_standby_nvm(hw);
 644
 645                 /* Some SPI eeproms use the 8th address bit embedded in the
 646                  * opcode
 647                  */
 648                 if ((nvm->address_bits == 8) && (offset >= 128))
 649                         write_opcode |= NVM_A8_OPCODE_SPI;
 650
 651                 /* Send the Write command (8-bit opcode + addr) */
 652                 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
 653                 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
 654                                          nvm->address_bits);
 655
 656                 /* Loop to allow for up to whole page write of eeprom */
 657                 while (widx < words) {
 658                         u16 word_out = data[widx];
 659                         word_out = (word_out >> 8) | (word_out << 8);
 660                         e1000_shift_out_eec_bits(hw, word_out, 16);
 661                         widx++;
 662
 663                         if ((((offset + widx) * 2) % nvm->page_size) == 0) {
 664                                 e1000_standby_nvm(hw);
 665                                 break;
 666                         }
 667                 }
 668                 msec_delay(10);
 669                 nvm->ops.release(hw);
 670         }
 671
 672         return ret_val;
 673 }
 674
 675 /**
 676  *  e1000_write_nvm_microwire - Writes EEPROM using microwire
 677  *  @hw: pointer to the HW structure
 678  *  @offset: offset within the EEPROM to be written to
 679  *  @words: number of words to write
 680  *  @data: 16 bit word(s) to be written to the EEPROM
 681  *
 682  *  Writes data to EEPROM at offset using microwire interface.
 683  *
 684  *  If e1000_update_nvm_checksum is not called after this function , the
 685  *  EEPROM will most likely contain an invalid checksum.
 686  **/
 687 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 688                               u16 *data)
 689 {
 690         struct e1000_nvm_info *nvm = &hw->nvm;
 691         s32  ret_val;
 692         u32 eecd;
 693         u16 words_written = 0;
 694         u16 widx = 0;
 695
 696         DEBUGFUNC("e1000_write_nvm_microwire");
 697
 698         /* A check for invalid values:  offset too large, too many words,
 699          * and not enough words.
 700          */
 701         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 702             (words == 0)) {
 703                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 704                 return -E1000_ERR_NVM;
 705         }
 706
 707         ret_val = nvm->ops.acquire(hw);
 708         if (ret_val)
 709                 return ret_val;
 710
 711         ret_val = e1000_ready_nvm_eeprom(hw);
 712         if (ret_val)
 713                 goto release;
 714
 715         e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
 716                                  (u16)(nvm->opcode_bits + 2));
 717
 718         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 719
 720         e1000_standby_nvm(hw);
 721
 722         while (words_written < words) {
 723                 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
 724                                          nvm->opcode_bits);
 725
 726                 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
 727                                          nvm->address_bits);
 728
 729                 e1000_shift_out_eec_bits(hw, data[words_written], 16);
 730
 731                 e1000_standby_nvm(hw);
 732
 733                 for (widx = 0; widx < 200; widx++) {
 734                         eecd = E1000_READ_REG(hw, E1000_EECD);
 735                         if (eecd & E1000_EECD_DO)
 736                                 break;
 737                         usec_delay(50);
 738                 }
 739
 740                 if (widx == 200) {
 741                         DEBUGOUT("NVM Write did not complete\n");
 742                         ret_val = -E1000_ERR_NVM;
 743                         goto release;
 744                 }
 745
 746                 e1000_standby_nvm(hw);
 747
 748                 words_written++;
 749         }
 750
 751         e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
 752                                  (u16)(nvm->opcode_bits + 2));
 753
 754         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 755
 756 release:
 757         nvm->ops.release(hw);
 758
 759         return ret_val;
 760 }
 761
 762 /**
 763  *  e1000_read_pba_string_generic - Read device part number
 764  *  @hw: pointer to the HW structure
 765  *  @pba_num: pointer to device part number
 766  *  @pba_num_size: size of part number buffer
 767  *
 768  *  Reads the product board assembly (PBA) number from the EEPROM and stores
 769  *  the value in pba_num.
 770  **/
 771 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
 772                                   u32 pba_num_size)
 773 {
 774         s32 ret_val;
 775         u16 nvm_data;
 776         u16 pba_ptr;
 777         u16 offset;
 778         u16 length;
 779
 780         DEBUGFUNC("e1000_read_pba_string_generic");
 781
 782         if ((hw->mac.type >= e1000_i210) &&
 783             !e1000_get_flash_presence_i210(hw)) {
 784                 DEBUGOUT("Flashless no PBA string\n");
 785                 return -E1000_ERR_NVM_PBA_SECTION;
 786         }
 787
 788         if (pba_num == NULL) {
 789                 DEBUGOUT("PBA string buffer was null\n");
 790                 return -E1000_ERR_INVALID_ARGUMENT;
 791         }
 792
 793         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 794         if (ret_val) {
 795                 DEBUGOUT("NVM Read Error\n");
 796                 return ret_val;
 797         }
 798
 799         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 800         if (ret_val) {
 801                 DEBUGOUT("NVM Read Error\n");
 802                 return ret_val;
 803         }
 804
 805         /* if nvm_data is not ptr guard the PBA must be in legacy format which
 806          * means pba_ptr is actually our second data word for the PBA number
 807          * and we can decode it into an ascii string
 808          */
 809         if (nvm_data != NVM_PBA_PTR_GUARD) {
 810                 DEBUGOUT("NVM PBA number is not stored as string\n");
 811
 812                 /* make sure callers buffer is big enough to store the PBA */
 813                 if (pba_num_size < E1000_PBANUM_LENGTH) {
 814                         DEBUGOUT("PBA string buffer too small\n");
 815                         return E1000_ERR_NO_SPACE;
 816                 }
 817
 818                 /* extract hex string from data and pba_ptr */
 819                 pba_num[0] = (nvm_data >> 12) & 0xF;
 820                 pba_num[1] = (nvm_data >> 8) & 0xF;
 821                 pba_num[2] = (nvm_data >> 4) & 0xF;
 822                 pba_num[3] = nvm_data & 0xF;
 823                 pba_num[4] = (pba_ptr >> 12) & 0xF;
 824                 pba_num[5] = (pba_ptr >> 8) & 0xF;
 825                 pba_num[6] = '-';
 826                 pba_num[7] = 0;
 827                 pba_num[8] = (pba_ptr >> 4) & 0xF;
 828                 pba_num[9] = pba_ptr & 0xF;
 829
 830                 /* put a null character on the end of our string */
 831                 pba_num[10] = '\0';
 832
 833                 /* switch all the data but the '-' to hex char */
 834                 for (offset = 0; offset < 10; offset++) {
 835                         if (pba_num[offset] < 0xA)
 836                                 pba_num[offset] += '0';
 837                         else if (pba_num[offset] < 0x10)
 838                                 pba_num[offset] += 'A' - 0xA;
 839                 }
 840
 841                 return E1000_SUCCESS;
 842         }
 843
 844         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 845         if (ret_val) {
 846                 DEBUGOUT("NVM Read Error\n");
 847                 return ret_val;
 848         }
 849
 850         if (length == 0xFFFF || length == 0) {
 851                 DEBUGOUT("NVM PBA number section invalid length\n");
 852                 return -E1000_ERR_NVM_PBA_SECTION;
 853         }
 854         /* check if pba_num buffer is big enough */
 855         if (pba_num_size < (((u32)length * 2) - 1)) {
 856                 DEBUGOUT("PBA string buffer too small\n");
 857                 return -E1000_ERR_NO_SPACE;
 858         }
 859
 860         /* trim pba length from start of string */
 861         pba_ptr++;
 862         length--;
 863
 864         for (offset = 0; offset < length; offset++) {
 865                 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
 866                 if (ret_val) {
 867                         DEBUGOUT("NVM Read Error\n");
 868                         return ret_val;
 869                 }
 870                 pba_num[offset * 2] = (u8)(nvm_data >> 8);
 871                 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
 872         }
 873         pba_num[offset * 2] = '\0';
 874
 875         return E1000_SUCCESS;
 876 }
 877
 878 /**
 879  *  e1000_read_pba_length_generic - Read device part number length
 880  *  @hw: pointer to the HW structure
 881  *  @pba_num_size: size of part number buffer
 882  *
 883  *  Reads the product board assembly (PBA) number length from the EEPROM and
 884  *  stores the value in pba_num_size.
 885  **/
 886 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
 887 {
 888         s32 ret_val;
 889         u16 nvm_data;
 890         u16 pba_ptr;
 891         u16 length;
 892
 893         DEBUGFUNC("e1000_read_pba_length_generic");
 894
 895         if (pba_num_size == NULL) {
 896                 DEBUGOUT("PBA buffer size was null\n");
 897                 return -E1000_ERR_INVALID_ARGUMENT;
 898         }
 899
 900         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 901         if (ret_val) {
 902                 DEBUGOUT("NVM Read Error\n");
 903                 return ret_val;
 904         }
 905
 906         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 907         if (ret_val) {
 908                 DEBUGOUT("NVM Read Error\n");
 909                 return ret_val;
 910         }
 911
 912          /* if data is not ptr guard the PBA must be in legacy format */
 913         if (nvm_data != NVM_PBA_PTR_GUARD) {
 914                 *pba_num_size = E1000_PBANUM_LENGTH;
 915                 return E1000_SUCCESS;
 916         }
 917
 918         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 919         if (ret_val) {
 920                 DEBUGOUT("NVM Read Error\n");
 921                 return ret_val;
 922         }
 923
 924         if (length == 0xFFFF || length == 0) {
 925                 DEBUGOUT("NVM PBA number section invalid length\n");
 926                 return -E1000_ERR_NVM_PBA_SECTION;
 927         }
 928
 929         /* Convert from length in u16 values to u8 chars, add 1 for NULL,
 930          * and subtract 2 because length field is included in length.
 931          */
 932         *pba_num_size = ((u32)length * 2) - 1;
 933
 934         return E1000_SUCCESS;
 935 }
 936
 937 /**
 938  *  e1000_read_pba_num_generic - Read device part number
 939  *  @hw: pointer to the HW structure
 940  *  @pba_num: pointer to device part number
 941  *
 942  *  Reads the product board assembly (PBA) number from the EEPROM and stores
 943  *  the value in pba_num.
 944  **/
 945 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
 946 {
 947         s32 ret_val;
 948         u16 nvm_data;
 949
 950         DEBUGFUNC("e1000_read_pba_num_generic");
 951
 952         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 953         if (ret_val) {
 954                 DEBUGOUT("NVM Read Error\n");
 955                 return ret_val;
 956         } else if (nvm_data == NVM_PBA_PTR_GUARD) {
 957                 DEBUGOUT("NVM Not Supported\n");
 958                 return -E1000_NOT_IMPLEMENTED;
 959         }
 960         *pba_num = (u32)(nvm_data << 16);
 961
 962         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
 963         if (ret_val) {
 964                 DEBUGOUT("NVM Read Error\n");
 965                 return ret_val;
 966         }
 967         *pba_num |= nvm_data;
 968
 969         return E1000_SUCCESS;
 970 }
 971
 972 /**
 973  *  e1000_read_pba_raw
 974  *  @hw: pointer to the HW structure
 975  *  @eeprom_buf: optional pointer to EEPROM image
 976  *  @eeprom_buf_size: size of EEPROM image in words
 977  *  @max_pba_block_size: PBA block size limit
 978  *  @pba: pointer to output PBA structure
 979  *
 980  *  Reads PBA from EEPROM image when eeprom_buf is not NULL.
 981  *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.
 982  *
 983  **/
 984 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
 985                        u32 eeprom_buf_size, u16 max_pba_block_size,
 986                        struct e1000_pba *pba)
 987 {
 988         s32 ret_val;
 989         u16 pba_block_size;
 990
 991         if (pba == NULL)
 992                 return -E1000_ERR_PARAM;
 993
 994         if (eeprom_buf == NULL) {
 995                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
 996                                          &pba->word[0]);
 997                 if (ret_val)
 998                         return ret_val;
 999         } else {
1000                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1001                         pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1002                         pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1003                 } else {
1004                         return -E1000_ERR_PARAM;
1005                 }
1006         }
1007
1008         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1009                 if (pba->pba_block == NULL)
1010                         return -E1000_ERR_PARAM;
1011
1012                 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
1013                                                    eeprom_buf_size,
1014                                                    &pba_block_size);
1015                 if (ret_val)
1016                         return ret_val;
1017
1018                 if (pba_block_size > max_pba_block_size)
1019                         return -E1000_ERR_PARAM;
1020
1021                 if (eeprom_buf == NULL) {
1022                         ret_val = e1000_read_nvm(hw, pba->word[1],
1023                                                  pba_block_size,
1024                                                  pba->pba_block);
1025                         if (ret_val)
1026                                 return ret_val;
1027                 } else {
1028                         if (eeprom_buf_size > (u32)(pba->word[1] +
1029                                               pba_block_size)) {
1030                                 memcpy(pba->pba_block,
1031                                        &eeprom_buf[pba->word[1]],
1032                                        pba_block_size * sizeof(u16));
1033                         } else {
1034                                 return -E1000_ERR_PARAM;
1035                         }
1036                 }
1037         }
1038
1039         return E1000_SUCCESS;
1040 }
1041
1042 /**
1043  *  e1000_write_pba_raw
1044  *  @hw: pointer to the HW structure
1045  *  @eeprom_buf: optional pointer to EEPROM image
1046  *  @eeprom_buf_size: size of EEPROM image in words
1047  *  @pba: pointer to PBA structure
1048  *
1049  *  Writes PBA to EEPROM image when eeprom_buf is not NULL.
1050  *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1051  *
1052  **/
1053 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1054                         u32 eeprom_buf_size, struct e1000_pba *pba)
1055 {
1056         s32 ret_val;
1057
1058         if (pba == NULL)
1059                 return -E1000_ERR_PARAM;
1060
1061         if (eeprom_buf == NULL) {
1062                 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1063                                           &pba->word[0]);
1064                 if (ret_val)
1065                         return ret_val;
1066         } else {
1067                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1068                         eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1069                         eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1070                 } else {
1071                         return -E1000_ERR_PARAM;
1072                 }
1073         }
1074
1075         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1076                 if (pba->pba_block == NULL)
1077                         return -E1000_ERR_PARAM;
1078
1079                 if (eeprom_buf == NULL) {
1080                         ret_val = e1000_write_nvm(hw, pba->word[1],
1081                                                   pba->pba_block[0],
1082                                                   pba->pba_block);
1083                         if (ret_val)
1084                                 return ret_val;
1085                 } else {
1086                         if (eeprom_buf_size > (u32)(pba->word[1] +
1087                                               pba->pba_block[0])) {
1088                                 memcpy(&eeprom_buf[pba->word[1]],
1089                                        pba->pba_block,
1090                                        pba->pba_block[0] * sizeof(u16));
1091                         } else {
1092                                 return -E1000_ERR_PARAM;
1093                         }
1094                 }
1095         }
1096
1097         return E1000_SUCCESS;
1098 }
1099
1100 /**
1101  *  e1000_get_pba_block_size
1102  *  @hw: pointer to the HW structure
1103  *  @eeprom_buf: optional pointer to EEPROM image
1104  *  @eeprom_buf_size: size of EEPROM image in words
1105  *  @pba_data_size: pointer to output variable
1106  *
1107  *  Returns the size of the PBA block in words. Function operates on EEPROM
1108  *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1109  *  EEPROM device.
1110  *
1111  **/
1112 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1113                              u32 eeprom_buf_size, u16 *pba_block_size)
1114 {
1115         s32 ret_val;
1116         u16 pba_word[2];
1117         u16 length;
1118
1119         DEBUGFUNC("e1000_get_pba_block_size");
1120
1121         if (eeprom_buf == NULL) {
1122                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1123                 if (ret_val)
1124                         return ret_val;
1125         } else {
1126                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1127                         pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1128                         pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1129                 } else {
1130                         return -E1000_ERR_PARAM;
1131                 }
1132         }
1133
1134         if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1135                 if (eeprom_buf == NULL) {
1136                         ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1137                                                  &length);
1138                         if (ret_val)
1139                                 return ret_val;
1140                 } else {
1141                         if (eeprom_buf_size > pba_word[1])
1142                                 length = eeprom_buf[pba_word[1] + 0];
1143                         else
1144                                 return -E1000_ERR_PARAM;
1145                 }
1146
1147                 if (length == 0xFFFF || length == 0)
1148                         return -E1000_ERR_NVM_PBA_SECTION;
1149         } else {
1150                 /* PBA number in legacy format, there is no PBA Block. */
1151                 length = 0;
1152         }
1153
1154         if (pba_block_size != NULL)
1155                 *pba_block_size = length;
1156
1157         return E1000_SUCCESS;
1158 }
1159
1160 /**
1161  *  e1000_read_mac_addr_generic - Read device MAC address
1162  *  @hw: pointer to the HW structure
1163  *
1164  *  Reads the device MAC address from the EEPROM and stores the value.
1165  *  Since devices with two ports use the same EEPROM, we increment the
1166  *  last bit in the MAC address for the second port.
1167  **/
1168 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1169 {
1170         u32 rar_high;
1171         u32 rar_low;
1172         u16 i;
1173
1174         rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1175         rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1176
1177         for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1178                 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1179
1180         for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1181                 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1182
1183         for (i = 0; i < ETH_ADDR_LEN; i++)
1184                 hw->mac.addr[i] = hw->mac.perm_addr[i];
1185
1186         return E1000_SUCCESS;
1187 }
1188
1189 /**
1190  *  e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1191  *  @hw: pointer to the HW structure
1192  *
1193  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1194  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
1195  **/
1196 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1197 {
1198         s32 ret_val;
1199         u16 checksum = 0;
1200         u16 i, nvm_data;
1201
1202         DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1203
1204         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1205                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1206                 if (ret_val) {
1207                         DEBUGOUT("NVM Read Error\n");
1208                         return ret_val;
1209                 }
1210                 checksum += nvm_data;
1211         }
1212
1213         if (checksum != (u16) NVM_SUM) {
1214                 DEBUGOUT("NVM Checksum Invalid\n");
1215                 return -E1000_ERR_NVM;
1216         }
1217
1218         return E1000_SUCCESS;
1219 }
1220
1221 /**
1222  *  e1000_update_nvm_checksum_generic - Update EEPROM checksum
1223  *  @hw: pointer to the HW structure
1224  *
1225  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
1226  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
1227  *  value to the EEPROM.
1228  **/
1229 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1230 {
1231         s32 ret_val;
1232         u16 checksum = 0;
1233         u16 i, nvm_data;
1234
1235         DEBUGFUNC("e1000_update_nvm_checksum");
1236
1237         for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1238                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1239                 if (ret_val) {
1240                         DEBUGOUT("NVM Read Error while updating checksum.\n");
1241                         return ret_val;
1242                 }
1243                 checksum += nvm_data;
1244         }
1245         checksum = (u16) NVM_SUM - checksum;
1246         ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1247         if (ret_val)
1248                 DEBUGOUT("NVM Write Error while updating checksum.\n");
1249
1250         return ret_val;
1251 }
1252
1253 /**
1254  *  e1000_reload_nvm_generic - Reloads EEPROM
1255  *  @hw: pointer to the HW structure
1256  *
1257  *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1258  *  extended control register.
1259  **/
1260 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
1261 {
1262         u32 ctrl_ext;
1263
1264         DEBUGFUNC("e1000_reload_nvm_generic");
1265
1266         usec_delay(10);
1267         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1268         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1269         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1270         E1000_WRITE_FLUSH(hw);
1271 }
1272
1273 /**
1274  *  e1000_get_fw_version - Get firmware version information
1275  *  @hw: pointer to the HW structure
1276  *  @fw_vers: pointer to output version structure
1277  *
1278  *  unsupported/not present features return 0 in version structure
1279  **/
1280 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1281 {
1282         u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
1283         u8 q, hval, rem, result;
1284         u16 comb_verh, comb_verl, comb_offset;
1285
1286         memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1287
1288         /* basic eeprom version numbers, bits used vary by part and by tool
1289          * used to create the nvm images */
1290         /* Check which data format we have */
1291         switch (hw->mac.type) {
1292         case e1000_i211:
1293                 e1000_read_invm_version(hw, fw_vers);
1294                 return;
1295         case e1000_82575:
1296         case e1000_82576:
1297         case e1000_82580:
1298                 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1299                 /* Use this format, unless EETRACK ID exists,
1300                  * then use alternate format
1301                  */
1302                 if ((etrack_test &  NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
1303                         hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1304                         fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1305                                               >> NVM_MAJOR_SHIFT;
1306                         fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
1307                                               >> NVM_MINOR_SHIFT;
1308                         fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
1309                         goto etrack_id;
1310                 }
1311                 break;
1312         case e1000_i210:
1313                 if (!(e1000_get_flash_presence_i210(hw))) {
1314                         e1000_read_invm_version(hw, fw_vers);
1315                         return;
1316                 }
1317                 /* fall through */
1318         case e1000_i350:
1319                 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1320                 /* find combo image version */
1321                 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1322                 if ((comb_offset != 0x0) &&
1323                     (comb_offset != NVM_VER_INVALID)) {
1324
1325                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1326                                          + 1), 1, &comb_verh);
1327                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1328                                          1, &comb_verl);
1329
1330                         /* get Option Rom version if it exists and is valid */
1331                         if ((comb_verh && comb_verl) &&
1332                             ((comb_verh != NVM_VER_INVALID) &&
1333                              (comb_verl != NVM_VER_INVALID))) {
1334
1335                                 fw_vers->or_valid = TRUE;
1336                                 fw_vers->or_major =
1337                                         comb_verl >> NVM_COMB_VER_SHFT;
1338                                 fw_vers->or_build =
1339                                         (comb_verl << NVM_COMB_VER_SHFT)
1340                                         | (comb_verh >> NVM_COMB_VER_SHFT);
1341                                 fw_vers->or_patch =
1342                                         comb_verh & NVM_COMB_VER_MASK;
1343                         }
1344                 }
1345                 break;
1346         default:
1347                 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1348                 return;
1349         }
1350         hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1351         fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1352                               >> NVM_MAJOR_SHIFT;
1353
1354         /* check for old style version format in newer images*/
1355         if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
1356                 eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
1357         } else {
1358                 eeprom_verl = (fw_version & NVM_MINOR_MASK)
1359                                 >> NVM_MINOR_SHIFT;
1360         }
1361         /* Convert minor value to hex before assigning to output struct
1362          * Val to be converted will not be higher than 99, per tool output
1363          */
1364         q = eeprom_verl / NVM_HEX_CONV;
1365         hval = q * NVM_HEX_TENS;
1366         rem = eeprom_verl % NVM_HEX_CONV;
1367         result = hval + rem;
1368         fw_vers->eep_minor = result;
1369
1370 etrack_id:
1371         if ((etrack_test &  NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
1372                 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1373                 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1374                 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)
1375                         | eeprom_verl;
1376         } else if ((etrack_test & NVM_ETRACK_VALID) == 0) {
1377                 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh);
1378                 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl);
1379                 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) |
1380                                      eeprom_verl;
1381         }
1382 }
1383
1384