2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 #include <sys/resourcevar.h>
56 #include <sys/sfbuf.h>
57 #include <machine/md_var.h>
60 #include <drm/i915_drm.h>
62 #include "i915_trace.h"
63 #include "intel_drv.h"
64 #include <linux/shmem_fs.h>
65 #include <linux/slab.h>
66 #include <linux/swap.h>
67 #include <linux/pci.h>
69 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
70 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
71 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
73 bool map_and_fenceable,
75 static int i915_gem_phys_pwrite(struct drm_device *dev,
76 struct drm_i915_gem_object *obj,
77 struct drm_i915_gem_pwrite *args,
78 struct drm_file *file);
80 static void i915_gem_write_fence(struct drm_device *dev, int reg,
81 struct drm_i915_gem_object *obj);
82 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
83 struct drm_i915_fence_reg *fence,
86 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
87 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
89 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
92 i915_gem_release_mmap(obj);
94 /* As we do not have an associated fence register, we will force
95 * a tiling change if we ever need to acquire one.
97 obj->fence_dirty = false;
98 obj->fence_reg = I915_FENCE_REG_NONE;
101 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
102 static void i915_gem_lowmem(void *arg);
104 /* some bookkeeping */
105 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
108 dev_priv->mm.object_count++;
109 dev_priv->mm.object_memory += size;
112 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
115 dev_priv->mm.object_count--;
116 dev_priv->mm.object_memory -= size;
120 i915_gem_wait_for_error(struct i915_gpu_error *error)
124 #define EXIT_COND (!i915_reset_in_progress(error) || \
125 i915_terminally_wedged(error))
130 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
131 * userspace. If it takes that long something really bad is going on and
132 * we should simply try to bail out and fail as gracefully as possible.
134 ret = wait_event_interruptible_timeout(error->reset_queue,
138 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
140 } else if (ret < 0) {
148 int i915_mutex_lock_interruptible(struct drm_device *dev)
150 struct drm_i915_private *dev_priv = dev->dev_private;
153 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
157 ret = lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_SLEEPFAIL);
161 WARN_ON(i915_verify_lists(dev));
166 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
172 i915_gem_init_ioctl(struct drm_device *dev, void *data,
173 struct drm_file *file)
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct drm_i915_gem_init *args = data;
178 if (drm_core_check_feature(dev, DRIVER_MODESET))
181 if (args->gtt_start >= args->gtt_end ||
182 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
185 /* GEM with user mode setting was never supported on ilk and later. */
186 if (INTEL_INFO(dev)->gen >= 5)
189 mutex_lock(&dev->struct_mutex);
190 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
192 dev_priv->gtt.mappable_end = args->gtt_end;
193 mutex_unlock(&dev->struct_mutex);
199 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
200 struct drm_file *file)
202 struct drm_i915_private *dev_priv = dev->dev_private;
203 struct drm_i915_gem_get_aperture *args = data;
204 struct drm_i915_gem_object *obj;
208 mutex_lock(&dev->struct_mutex);
209 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
211 pinned += obj->gtt_space->size;
212 mutex_unlock(&dev->struct_mutex);
214 args->aper_size = dev_priv->gtt.total;
215 args->aper_available_size = args->aper_size - pinned;
220 void i915_gem_object_free(struct drm_i915_gem_object *obj)
226 i915_gem_create(struct drm_file *file,
227 struct drm_device *dev,
231 struct drm_i915_gem_object *obj;
235 size = roundup(size, PAGE_SIZE);
239 /* Allocate the new object */
240 obj = i915_gem_alloc_object(dev, size);
244 ret = drm_gem_handle_create(file, &obj->base, &handle);
246 drm_gem_object_release(&obj->base);
247 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
248 i915_gem_object_free(obj);
252 /* drop reference from allocate - handle holds it now */
253 drm_gem_object_unreference(&obj->base);
254 trace_i915_gem_object_create(obj);
261 i915_gem_dumb_create(struct drm_file *file,
262 struct drm_device *dev,
263 struct drm_mode_create_dumb *args)
266 /* have to work out size/pitch and return them */
267 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
268 args->size = args->pitch * args->height;
269 return i915_gem_create(file, dev,
270 args->size, &args->handle);
273 int i915_gem_dumb_destroy(struct drm_file *file,
274 struct drm_device *dev,
278 return drm_gem_handle_delete(file, handle);
282 * Creates a new mm object and returns a handle to it.
285 i915_gem_create_ioctl(struct drm_device *dev, void *data,
286 struct drm_file *file)
288 struct drm_i915_gem_create *args = data;
290 return i915_gem_create(file, dev,
291 args->size, &args->handle);
295 __copy_to_user_swizzled(char __user *cpu_vaddr,
296 const char *gpu_vaddr, int gpu_offset,
299 int ret, cpu_offset = 0;
302 int cacheline_end = ALIGN(gpu_offset + 1, 64);
303 int this_length = min(cacheline_end - gpu_offset, length);
304 int swizzled_gpu_offset = gpu_offset ^ 64;
306 ret = __copy_to_user(cpu_vaddr + cpu_offset,
307 gpu_vaddr + swizzled_gpu_offset,
312 cpu_offset += this_length;
313 gpu_offset += this_length;
314 length -= this_length;
321 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
322 const char __user *cpu_vaddr,
325 int ret, cpu_offset = 0;
328 int cacheline_end = ALIGN(gpu_offset + 1, 64);
329 int this_length = min(cacheline_end - gpu_offset, length);
330 int swizzled_gpu_offset = gpu_offset ^ 64;
332 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
333 cpu_vaddr + cpu_offset,
338 cpu_offset += this_length;
339 gpu_offset += this_length;
340 length -= this_length;
346 /* Per-page copy function for the shmem pread fastpath.
347 * Flushes invalid cachelines before reading the target if
348 * needs_clflush is set. */
350 shmem_pread_fast(struct vm_page *page, int shmem_page_offset, int page_length,
351 char __user *user_data,
352 bool page_do_bit17_swizzling, bool needs_clflush)
357 if (unlikely(page_do_bit17_swizzling))
360 vaddr = kmap_atomic(page);
362 drm_clflush_virt_range(vaddr + shmem_page_offset,
364 ret = __copy_to_user_inatomic(user_data,
365 vaddr + shmem_page_offset,
367 kunmap_atomic(vaddr);
369 return ret ? -EFAULT : 0;
373 shmem_clflush_swizzled_range(char *addr, unsigned long length,
376 if (unlikely(swizzled)) {
377 unsigned long start = (unsigned long) addr;
378 unsigned long end = (unsigned long) addr + length;
380 /* For swizzling simply ensure that we always flush both
381 * channels. Lame, but simple and it works. Swizzled
382 * pwrite/pread is far from a hotpath - current userspace
383 * doesn't use it at all. */
384 start = round_down(start, 128);
385 end = round_up(end, 128);
387 drm_clflush_virt_range((void *)start, end - start);
389 drm_clflush_virt_range(addr, length);
394 /* Only difference to the fast-path function is that this can handle bit17
395 * and uses non-atomic copy and kmap functions. */
397 shmem_pread_slow(struct vm_page *page, int shmem_page_offset, int page_length,
398 char __user *user_data,
399 bool page_do_bit17_swizzling, bool needs_clflush)
406 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
408 page_do_bit17_swizzling);
410 if (page_do_bit17_swizzling)
411 ret = __copy_to_user_swizzled(user_data,
412 vaddr, shmem_page_offset,
415 ret = __copy_to_user(user_data,
416 vaddr + shmem_page_offset,
420 return ret ? - EFAULT : 0;
423 static inline void vm_page_reference(vm_page_t m)
425 vm_page_flag_set(m, PG_REFERENCED);
429 i915_gem_shmem_pread(struct drm_device *dev,
430 struct drm_i915_gem_object *obj,
431 struct drm_i915_gem_pread *args,
432 struct drm_file *file)
434 char __user *user_data;
437 int shmem_page_offset, page_length, ret = 0;
438 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
439 int needs_clflush = 0;
442 user_data = (char __user *) (uintptr_t) args->data_ptr;
445 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
447 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
448 /* If we're not in the cpu read domain, set ourself into the gtt
449 * read domain and manually flush cachelines (if required). This
450 * optimizes for the case when the gpu will dirty the data
451 * anyway again before the next pread happens. */
452 if (obj->cache_level == I915_CACHE_NONE)
454 if (obj->gtt_space) {
455 ret = i915_gem_object_set_to_gtt_domain(obj, false);
461 ret = i915_gem_object_get_pages(obj);
465 i915_gem_object_pin_pages(obj);
467 offset = args->offset;
469 for (i = 0; i < (obj->base.size >> PAGE_SHIFT); i++) {
470 struct vm_page *page = obj->pages[i];
472 if (i < offset >> PAGE_SHIFT)
478 /* Operation in this page
480 * shmem_page_offset = offset within page in shmem file
481 * page_length = bytes to copy for this page
483 shmem_page_offset = offset_in_page(offset);
484 page_length = remain;
485 if ((shmem_page_offset + page_length) > PAGE_SIZE)
486 page_length = PAGE_SIZE - shmem_page_offset;
488 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
489 (VM_PAGE_TO_PHYS(page) & (1 << 17)) != 0;
491 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
492 user_data, page_do_bit17_swizzling,
497 mutex_unlock(&dev->struct_mutex);
501 ret = fault_in_multipages_writeable(user_data, remain);
502 /* Userspace is tricking us, but we've already clobbered
503 * its pages with the prefault and promised to write the
504 * data up to the first fault. Hence ignore any errors
505 * and just continue. */
511 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
512 user_data, page_do_bit17_swizzling,
515 mutex_lock(&dev->struct_mutex);
518 mark_page_accessed(page);
523 remain -= page_length;
524 user_data += page_length;
525 offset += page_length;
529 i915_gem_object_unpin_pages(obj);
535 * Reads data from the object referenced by handle.
537 * On error, the contents of *data are undefined.
540 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
541 struct drm_file *file)
543 struct drm_i915_gem_pread *args = data;
544 struct drm_i915_gem_object *obj;
550 ret = i915_mutex_lock_interruptible(dev);
554 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
555 if (&obj->base == NULL) {
560 /* Bounds check source. */
561 if (args->offset > obj->base.size ||
562 args->size > obj->base.size - args->offset) {
567 trace_i915_gem_object_pread(obj, args->offset, args->size);
569 ret = i915_gem_shmem_pread(dev, obj, args, file);
572 drm_gem_object_unreference(&obj->base);
574 mutex_unlock(&dev->struct_mutex);
579 /* This is the fast write path which cannot handle
580 * page faults in the source data
584 fast_user_write(struct io_mapping *mapping,
585 loff_t page_base, int page_offset,
586 char __user *user_data,
589 void __iomem *vaddr_atomic;
591 unsigned long unwritten;
593 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
594 /* We can use the cpu mem copy function because this is X86. */
595 vaddr = (void __force*)vaddr_atomic + page_offset;
596 unwritten = __copy_from_user_inatomic_nocache(vaddr,
598 io_mapping_unmap_atomic(vaddr_atomic);
603 * This is the fast pwrite path, where we copy the data directly from the
604 * user into the GTT, uncached.
607 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
608 struct drm_i915_gem_object *obj,
609 struct drm_i915_gem_pwrite *args,
610 struct drm_file *file)
612 drm_i915_private_t *dev_priv = dev->dev_private;
614 loff_t offset, page_base;
615 char __user *user_data;
616 int page_offset, page_length, ret;
618 ret = i915_gem_object_pin(obj, 0, true, true);
622 ret = i915_gem_object_set_to_gtt_domain(obj, true);
626 ret = i915_gem_object_put_fence(obj);
630 user_data = to_user_ptr(args->data_ptr);
633 offset = obj->gtt_offset + args->offset;
636 /* Operation in this page
638 * page_base = page offset within aperture
639 * page_offset = offset within page
640 * page_length = bytes to copy for this page
642 page_base = offset & PAGE_MASK;
643 page_offset = offset_in_page(offset);
644 page_length = remain;
645 if ((page_offset + remain) > PAGE_SIZE)
646 page_length = PAGE_SIZE - page_offset;
648 /* If we get a fault while copying data, then (presumably) our
649 * source page isn't available. Return the error and we'll
650 * retry in the slow path.
652 if (fast_user_write(dev_priv->gtt.mappable, page_base,
653 page_offset, user_data, page_length)) {
658 remain -= page_length;
659 user_data += page_length;
660 offset += page_length;
664 i915_gem_object_unpin(obj);
671 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
672 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
678 * Pass the unaligned physical address and size to pmap_mapdev_attr()
679 * so it can properly calculate whether an extra page needs to be
680 * mapped or not to cover the requested range. The function will
681 * add the page offset into the returned mkva for us.
683 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
684 offset, size, PAT_WRITE_COMBINING);
685 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
686 pmap_unmapdev(mkva, size);
691 /* Per-page copy function for the shmem pwrite fastpath.
692 * Flushes invalid cachelines before writing to the target if
693 * needs_clflush_before is set and flushes out any written cachelines after
694 * writing if needs_clflush is set. */
696 shmem_pwrite_fast(struct vm_page *page, int shmem_page_offset, int page_length,
697 char __user *user_data,
698 bool page_do_bit17_swizzling,
699 bool needs_clflush_before,
700 bool needs_clflush_after)
705 if (unlikely(page_do_bit17_swizzling))
708 vaddr = kmap_atomic(page);
709 if (needs_clflush_before)
710 drm_clflush_virt_range(vaddr + shmem_page_offset,
712 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
715 if (needs_clflush_after)
716 drm_clflush_virt_range(vaddr + shmem_page_offset,
718 kunmap_atomic(vaddr);
720 return ret ? -EFAULT : 0;
723 /* Only difference to the fast-path function is that this can handle bit17
724 * and uses non-atomic copy and kmap functions. */
726 shmem_pwrite_slow(struct vm_page *page, int shmem_page_offset, int page_length,
727 char __user *user_data,
728 bool page_do_bit17_swizzling,
729 bool needs_clflush_before,
730 bool needs_clflush_after)
736 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
737 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
739 page_do_bit17_swizzling);
740 if (page_do_bit17_swizzling)
741 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
745 ret = __copy_from_user(vaddr + shmem_page_offset,
748 if (needs_clflush_after)
749 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
751 page_do_bit17_swizzling);
754 return ret ? -EFAULT : 0;
759 i915_gem_shmem_pwrite(struct drm_device *dev,
760 struct drm_i915_gem_object *obj,
761 struct drm_i915_gem_pwrite *args,
762 struct drm_file *file)
769 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
771 do_bit17_swizzling = 0;
774 vm_obj = obj->base.vm_obj;
777 VM_OBJECT_LOCK(vm_obj);
778 vm_object_pip_add(vm_obj, 1);
779 while (args->size > 0) {
780 obj_pi = OFF_TO_IDX(args->offset);
781 obj_po = args->offset & PAGE_MASK;
783 m = shmem_read_mapping_page(vm_obj, obj_pi);
784 VM_OBJECT_UNLOCK(vm_obj);
786 sf = sf_buf_alloc(m);
787 mkva = sf_buf_kva(sf);
788 length = min(args->size, PAGE_SIZE - obj_po);
790 if (do_bit17_swizzling &&
791 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
792 cnt = roundup2(obj_po + 1, 64);
793 cnt = min(cnt - obj_po, length);
794 swizzled_po = obj_po ^ 64;
797 swizzled_po = obj_po;
799 ret = -copyin_nofault(
800 (void *)(uintptr_t)args->data_ptr,
801 (char *)mkva + swizzled_po, cnt);
804 args->data_ptr += cnt;
811 VM_OBJECT_LOCK(vm_obj);
813 vm_page_reference(m);
814 vm_page_busy_wait(m, FALSE, "i915gem");
815 vm_page_unwire(m, 1);
821 vm_object_pip_wakeup(vm_obj);
822 VM_OBJECT_UNLOCK(vm_obj);
828 * Writes data to the object referenced by handle.
830 * On error, the contents of the buffer that were to be modified are undefined.
833 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
834 struct drm_file *file)
836 struct drm_i915_gem_pwrite *args = data;
837 struct drm_i915_gem_object *obj;
839 vm_offset_t start, end;
845 start = trunc_page(args->data_ptr);
846 end = round_page(args->data_ptr + args->size);
847 npages = howmany(end - start, PAGE_SIZE);
848 ma = kmalloc(npages * sizeof(vm_page_t), M_DRM, M_WAITOK |
850 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
851 (vm_offset_t)args->data_ptr, args->size,
852 VM_PROT_READ, ma, npages);
858 ret = i915_mutex_lock_interruptible(dev);
862 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
863 if (&obj->base == NULL) {
868 /* Bounds check destination. */
869 if (args->offset > obj->base.size ||
870 args->size > obj->base.size - args->offset) {
875 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
878 ret = i915_gem_phys_pwrite(dev, obj, args, file);
879 } else if (obj->gtt_space &&
880 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
881 ret = i915_gem_object_pin(obj, 0, true, false);
884 ret = i915_gem_object_set_to_gtt_domain(obj, true);
887 ret = i915_gem_object_put_fence(obj);
890 ret = i915_gem_gtt_write(dev, obj, args->data_ptr, args->size,
893 i915_gem_object_unpin(obj);
895 ret = i915_gem_object_set_to_cpu_domain(obj, true);
898 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
901 drm_gem_object_unreference(&obj->base);
903 mutex_unlock(&dev->struct_mutex);
905 vm_page_unhold_pages(ma, npages);
912 i915_gem_check_wedge(struct i915_gpu_error *error,
915 if (i915_reset_in_progress(error)) {
916 /* Non-interruptible callers can't handle -EAGAIN, hence return
917 * -EIO unconditionally for these. */
921 /* Recovery complete, but the reset failed ... */
922 if (i915_terminally_wedged(error))
932 * Compare seqno against outstanding lazy request. Emit a request if they are
936 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
940 DRM_LOCK_ASSERT(ring->dev);
943 if (seqno == ring->outstanding_lazy_request)
944 ret = i915_add_request(ring, NULL);
950 * __wait_seqno - wait until execution of seqno has finished
951 * @ring: the ring expected to report seqno
953 * @reset_counter: reset sequence associated with the given seqno
954 * @interruptible: do an interruptible wait (normally yes)
955 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
957 * Note: It is of utmost importance that the passed in seqno and reset_counter
958 * values have been read by the caller in an smp safe manner. Where read-side
959 * locks are involved, it is sufficient to read the reset_counter before
960 * unlocking the lock that protects the seqno. For lockless tricks, the
961 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
964 * Returns 0 if the seqno was found within the alloted time. Else returns the
965 * errno with remaining time filled in timeout argument.
967 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
968 unsigned reset_counter,
969 bool interruptible, struct timespec *timeout)
971 drm_i915_private_t *dev_priv = ring->dev->dev_private;
972 struct timespec before, now, wait_time={1,0};
973 unsigned long timeout_jiffies;
975 bool wait_forever = true;
978 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
981 trace_i915_gem_request_wait_begin(ring, seqno);
983 if (timeout != NULL) {
984 wait_time = *timeout;
985 wait_forever = false;
988 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
990 if (WARN_ON(!ring->irq_get(ring)))
993 /* Record current time in case interrupted by signal, or wedged * */
994 getrawmonotonic(&before);
997 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
998 i915_reset_in_progress(&dev_priv->gpu_error) || \
999 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1002 end = wait_event_interruptible_timeout(ring->irq_queue,
1006 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1009 /* We need to check whether any gpu reset happened in between
1010 * the caller grabbing the seqno and now ... */
1011 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1014 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1016 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1019 } while (end == 0 && wait_forever);
1021 getrawmonotonic(&now);
1023 ring->irq_put(ring);
1024 trace_i915_gem_request_wait_end(ring, seqno);
1028 struct timespec sleep_time = timespec_sub(now, before);
1029 *timeout = timespec_sub(*timeout, sleep_time);
1030 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1031 set_normalized_timespec(timeout, 0, 0);
1036 case -EAGAIN: /* Wedged */
1037 case -ERESTARTSYS: /* Signal */
1039 case 0: /* Timeout */
1040 return -ETIMEDOUT; /* -ETIME on Linux */
1041 default: /* Completed */
1042 WARN_ON(end < 0); /* We're not aware of other errors */
1048 * Waits for a sequence number to be signaled, and cleans up the
1049 * request and object lists appropriately for that event.
1052 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1054 struct drm_device *dev = ring->dev;
1055 struct drm_i915_private *dev_priv = dev->dev_private;
1056 bool interruptible = dev_priv->mm.interruptible;
1059 DRM_LOCK_ASSERT(dev);
1062 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1066 ret = i915_gem_check_olr(ring, seqno);
1070 return __wait_seqno(ring, seqno,
1071 atomic_read(&dev_priv->gpu_error.reset_counter),
1072 interruptible, NULL);
1076 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1077 struct intel_ring_buffer *ring)
1079 i915_gem_retire_requests_ring(ring);
1081 /* Manually manage the write flush as we may have not yet
1082 * retired the buffer.
1084 * Note that the last_write_seqno is always the earlier of
1085 * the two (read/write) seqno, so if we haved successfully waited,
1086 * we know we have passed the last write.
1088 obj->last_write_seqno = 0;
1089 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1095 * Ensures that all rendering to the object has completed and the object is
1096 * safe to unbind from the GTT or access from the CPU.
1098 static __must_check int
1099 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1102 struct intel_ring_buffer *ring = obj->ring;
1106 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1110 ret = i915_wait_seqno(ring, seqno);
1114 return i915_gem_object_wait_rendering__tail(obj, ring);
1117 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1118 * as the object state may change during this call.
1120 static __must_check int
1121 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1124 struct drm_device *dev = obj->base.dev;
1125 struct drm_i915_private *dev_priv = dev->dev_private;
1126 struct intel_ring_buffer *ring = obj->ring;
1127 unsigned reset_counter;
1131 DRM_LOCK_ASSERT(dev);
1132 BUG_ON(!dev_priv->mm.interruptible);
1134 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1138 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1142 ret = i915_gem_check_olr(ring, seqno);
1146 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1147 mutex_unlock(&dev->struct_mutex);
1148 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1149 mutex_lock(&dev->struct_mutex);
1153 return i915_gem_object_wait_rendering__tail(obj, ring);
1157 * Called when user space prepares to use an object with the CPU, either
1158 * through the mmap ioctl's mapping or a GTT mapping.
1161 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1162 struct drm_file *file)
1164 struct drm_i915_gem_set_domain *args = data;
1165 struct drm_i915_gem_object *obj;
1166 uint32_t read_domains = args->read_domains;
1167 uint32_t write_domain = args->write_domain;
1170 /* Only handle setting domains to types used by the CPU. */
1171 if (write_domain & I915_GEM_GPU_DOMAINS)
1174 if (read_domains & I915_GEM_GPU_DOMAINS)
1177 /* Having something in the write domain implies it's in the read
1178 * domain, and only that read domain. Enforce that in the request.
1180 if (write_domain != 0 && read_domains != write_domain)
1183 ret = i915_mutex_lock_interruptible(dev);
1187 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1188 if (&obj->base == NULL) {
1193 /* Try to flush the object off the GPU without holding the lock.
1194 * We will repeat the flush holding the lock in the normal manner
1195 * to catch cases where we are gazumped.
1197 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1201 if (read_domains & I915_GEM_DOMAIN_GTT) {
1202 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1204 /* Silently promote "you're not bound, there was nothing to do"
1205 * to success, since the client was just asking us to
1206 * make sure everything was done.
1211 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1215 drm_gem_object_unreference(&obj->base);
1217 mutex_unlock(&dev->struct_mutex);
1222 * Called when user space has done writes to this buffer
1225 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1226 struct drm_file *file)
1228 struct drm_i915_gem_sw_finish *args = data;
1229 struct drm_i915_gem_object *obj;
1232 ret = i915_mutex_lock_interruptible(dev);
1235 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1236 if (&obj->base == NULL) {
1241 /* Pinned buffers may be scanout, so flush the cache */
1243 i915_gem_object_flush_cpu_write_domain(obj);
1245 drm_gem_object_unreference(&obj->base);
1247 mutex_unlock(&dev->struct_mutex);
1252 * Maps the contents of an object, returning the address it is mapped
1255 * While the mapping holds a reference on the contents of the object, it doesn't
1256 * imply a ref on the object itself.
1259 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1260 struct drm_file *file)
1262 struct drm_i915_gem_mmap *args = data;
1263 struct drm_gem_object *obj;
1264 struct proc *p = curproc;
1265 vm_map_t map = &p->p_vmspace->vm_map;
1270 obj = drm_gem_object_lookup(dev, file, args->handle);
1274 if (args->size == 0)
1277 size = round_page(args->size);
1278 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1284 vm_object_hold(obj->vm_obj);
1285 vm_object_reference_locked(obj->vm_obj);
1286 vm_object_drop(obj->vm_obj);
1287 rv = vm_map_find(map, obj->vm_obj, NULL,
1288 args->offset, &addr, args->size,
1289 PAGE_SIZE, /* align */
1291 VM_MAPTYPE_NORMAL, /* maptype */
1292 VM_PROT_READ | VM_PROT_WRITE, /* prot */
1293 VM_PROT_READ | VM_PROT_WRITE, /* max */
1294 MAP_SHARED /* cow */);
1295 if (rv != KERN_SUCCESS) {
1296 vm_object_deallocate(obj->vm_obj);
1297 error = -vm_mmap_to_errno(rv);
1299 args->addr_ptr = (uint64_t)addr;
1302 drm_gem_object_unreference(obj);
1309 * i915_gem_fault - fault a page into the GTT
1310 * vma: VMA in question
1313 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1314 * from userspace. The fault handler takes care of binding the object to
1315 * the GTT (if needed), allocating and programming a fence register (again,
1316 * only if needed based on whether the old reg is still valid or the object
1317 * is tiled) and inserting a new PTE into the faulting process.
1319 * Note that the faulting process may involve evicting existing objects
1320 * from the GTT and/or fence registers to make room. So performance may
1321 * suffer if the GTT working set is large or there are few fence registers
1325 i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1328 struct drm_gem_object *gem_obj;
1329 struct drm_i915_gem_object *obj;
1330 struct drm_device *dev;
1331 drm_i915_private_t *dev_priv;
1336 gem_obj = vm_obj->handle;
1337 obj = to_intel_bo(gem_obj);
1338 dev = obj->base.dev;
1339 dev_priv = dev->dev_private;
1341 write = (prot & VM_PROT_WRITE) != 0;
1345 vm_object_pip_add(vm_obj, 1);
1348 * Remove the placeholder page inserted by vm_fault() from the
1349 * object before dropping the object lock. If
1350 * i915_gem_release_mmap() is active in parallel on this gem
1351 * object, then it owns the drm device sx and might find the
1352 * placeholder already. Then, since the page is busy,
1353 * i915_gem_release_mmap() sleeps waiting for the busy state
1354 * of the page cleared. We will be not able to acquire drm
1355 * device lock until i915_gem_release_mmap() is able to make a
1358 if (*mres != NULL) {
1360 vm_page_remove(oldm);
1365 VM_OBJECT_UNLOCK(vm_obj);
1371 ret = i915_mutex_lock_interruptible(dev);
1377 mutex_lock(&dev->struct_mutex);
1380 * Since the object lock was dropped, other thread might have
1381 * faulted on the same GTT address and instantiated the
1382 * mapping for the page. Recheck.
1384 VM_OBJECT_LOCK(vm_obj);
1385 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1387 if ((m->flags & PG_BUSY) != 0) {
1388 mutex_unlock(&dev->struct_mutex);
1390 vm_page_sleep(m, "915pee");
1396 VM_OBJECT_UNLOCK(vm_obj);
1398 trace_i915_gem_object_fault(obj, page_offset, true, write);
1400 /* Access to snoopable pages through the GTT is incoherent. */
1401 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1406 /* Now bind it into the GTT if needed */
1407 if (!obj->map_and_fenceable) {
1408 ret = i915_gem_object_unbind(obj);
1414 if (!obj->gtt_space) {
1415 ret = i915_gem_object_bind_to_gtt(obj, 0, true, false);
1421 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1428 if (obj->tiling_mode == I915_TILING_NONE)
1429 ret = i915_gem_object_put_fence(obj);
1431 ret = i915_gem_object_get_fence(obj);
1437 if (i915_gem_object_is_inactive(obj))
1438 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1440 obj->fault_mappable = true;
1441 VM_OBJECT_LOCK(vm_obj);
1442 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
1449 KASSERT((m->flags & PG_FICTITIOUS) != 0,
1450 ("not fictitious %p", m));
1451 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1453 if ((m->flags & PG_BUSY) != 0) {
1454 mutex_unlock(&dev->struct_mutex);
1456 vm_page_sleep(m, "915pbs");
1460 m->valid = VM_PAGE_BITS_ALL;
1461 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1464 vm_page_busy_try(m, false);
1466 mutex_unlock(&dev->struct_mutex);
1470 vm_object_pip_wakeup(vm_obj);
1471 return (VM_PAGER_OK);
1474 mutex_unlock(&dev->struct_mutex);
1476 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1477 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1478 goto unlocked_vmobj;
1480 VM_OBJECT_LOCK(vm_obj);
1481 vm_object_pip_wakeup(vm_obj);
1482 return (VM_PAGER_ERROR);
1486 * i915_gem_release_mmap - remove physical page mappings
1487 * @obj: obj in question
1489 * Preserve the reservation of the mmapping with the DRM core code, but
1490 * relinquish ownership of the pages back to the system.
1492 * It is vital that we remove the page mapping if we have mapped a tiled
1493 * object through the GTT and then lose the fence register due to
1494 * resource pressure. Similarly if the object has been moved out of the
1495 * aperture, than pages mapped into userspace must be revoked. Removing the
1496 * mapping will then trigger a page fault on the next user access, allowing
1497 * fixup by i915_gem_fault().
1500 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1506 if (!obj->fault_mappable)
1509 devobj = cdev_pager_lookup(obj);
1510 if (devobj != NULL) {
1511 page_count = OFF_TO_IDX(obj->base.size);
1513 VM_OBJECT_LOCK(devobj);
1514 for (i = 0; i < page_count; i++) {
1515 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
1518 cdev_pager_free_page(devobj, m);
1520 VM_OBJECT_UNLOCK(devobj);
1521 vm_object_deallocate(devobj);
1524 obj->fault_mappable = false;
1528 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1532 if (INTEL_INFO(dev)->gen >= 4 ||
1533 tiling_mode == I915_TILING_NONE)
1536 /* Previous chips need a power-of-two fence region when tiling */
1537 if (INTEL_INFO(dev)->gen == 3)
1538 gtt_size = 1024*1024;
1540 gtt_size = 512*1024;
1542 while (gtt_size < size)
1549 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1550 * @obj: object to check
1552 * Return the required GTT alignment for an object, taking into account
1553 * potential fence register mapping.
1556 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1557 int tiling_mode, bool fenced)
1561 * Minimum alignment is 4k (GTT page size), but might be greater
1562 * if a fence register is needed for the object.
1564 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1565 tiling_mode == I915_TILING_NONE)
1569 * Previous chips need to be aligned to the size of the smallest
1570 * fence register that can contain the object.
1572 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1576 i915_gem_mmap_gtt(struct drm_file *file,
1577 struct drm_device *dev,
1581 struct drm_i915_private *dev_priv = dev->dev_private;
1582 struct drm_i915_gem_object *obj;
1585 ret = i915_mutex_lock_interruptible(dev);
1589 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1590 if (&obj->base == NULL) {
1595 if (obj->base.size > dev_priv->gtt.mappable_end) {
1600 if (obj->madv != I915_MADV_WILLNEED) {
1601 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1606 ret = drm_gem_create_mmap_offset(&obj->base);
1610 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1611 DRM_GEM_MAPPING_KEY;
1613 drm_gem_object_unreference(&obj->base);
1615 mutex_unlock(&dev->struct_mutex);
1620 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1622 * @data: GTT mapping ioctl data
1623 * @file: GEM object info
1625 * Simply returns the fake offset to userspace so it can mmap it.
1626 * The mmap call will end up in drm_gem_mmap(), which will set things
1627 * up so we can get faults in the handler above.
1629 * The fault handler will take care of binding the object into the GTT
1630 * (since it may have been evicted to make room for something), allocating
1631 * a fence register, and mapping the appropriate aperture address into
1635 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1636 struct drm_file *file)
1638 struct drm_i915_gem_mmap_gtt *args = data;
1640 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1643 /* Immediately discard the backing storage */
1645 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1649 vm_obj = obj->base.vm_obj;
1650 VM_OBJECT_LOCK(vm_obj);
1651 vm_object_page_remove(vm_obj, 0, 0, false);
1652 VM_OBJECT_UNLOCK(vm_obj);
1654 obj->madv = __I915_MADV_PURGED;
1658 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1660 return obj->madv == I915_MADV_DONTNEED;
1664 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1669 BUG_ON(obj->madv == __I915_MADV_PURGED);
1671 if (obj->tiling_mode != I915_TILING_NONE)
1672 i915_gem_object_save_bit_17_swizzle(obj);
1673 if (obj->madv == I915_MADV_DONTNEED)
1675 page_count = obj->base.size / PAGE_SIZE;
1676 VM_OBJECT_LOCK(obj->base.vm_obj);
1677 #if GEM_PARANOID_CHECK_GTT
1678 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
1680 for (i = 0; i < page_count; i++) {
1684 if (obj->madv == I915_MADV_WILLNEED)
1685 vm_page_reference(m);
1686 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
1687 vm_page_unwire(obj->pages[i], 1);
1688 vm_page_wakeup(obj->pages[i]);
1690 VM_OBJECT_UNLOCK(obj->base.vm_obj);
1692 drm_free(obj->pages, M_DRM);
1697 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1699 const struct drm_i915_gem_object_ops *ops = obj->ops;
1701 if (obj->pages == NULL)
1704 BUG_ON(obj->gtt_space);
1706 if (obj->pages_pin_count)
1709 /* ->put_pages might need to allocate memory for the bit17 swizzle
1710 * array, hence protect them from being reaped by removing them from gtt
1712 list_del(&obj->global_list);
1714 ops->put_pages(obj);
1717 if (i915_gem_object_is_purgeable(obj))
1718 i915_gem_object_truncate(obj);
1724 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1725 bool purgeable_only)
1727 struct drm_i915_gem_object *obj, *next;
1730 list_for_each_entry_safe(obj, next,
1731 &dev_priv->mm.unbound_list,
1734 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1735 i915_gem_object_put_pages(obj) == 0) {
1736 count += obj->base.size >> PAGE_SHIFT;
1737 if (count >= target)
1743 list_for_each_entry_safe(obj, next,
1744 &dev_priv->mm.inactive_list,
1747 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1748 i915_gem_object_unbind(obj) == 0 &&
1749 i915_gem_object_put_pages(obj) == 0) {
1750 count += obj->base.size >> PAGE_SHIFT;
1751 if (count >= target)
1761 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1763 return __i915_gem_shrink(dev_priv, target, true);
1767 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1769 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1770 struct drm_device *dev;
1772 int page_count, i, j;
1773 struct vm_page *page;
1775 dev = obj->base.dev;
1776 KASSERT(obj->pages == NULL, ("Obj already has pages"));
1777 page_count = obj->base.size / PAGE_SIZE;
1778 obj->pages = kmalloc(page_count * sizeof(vm_page_t), M_DRM,
1781 vm_obj = obj->base.vm_obj;
1782 VM_OBJECT_LOCK(vm_obj);
1784 for (i = 0; i < page_count; i++) {
1785 page = shmem_read_mapping_page(vm_obj, i);
1787 i915_gem_purge(dev_priv, page_count);
1791 obj->pages[i] = page;
1794 VM_OBJECT_UNLOCK(vm_obj);
1795 if (i915_gem_object_needs_bit17_swizzle(obj))
1796 i915_gem_object_do_bit_17_swizzle(obj);
1801 for (j = 0; j < i; j++) {
1802 page = obj->pages[j];
1803 vm_page_busy_wait(page, FALSE, "i915gem");
1804 vm_page_unwire(page, 0);
1805 vm_page_wakeup(page);
1807 VM_OBJECT_UNLOCK(vm_obj);
1808 drm_free(obj->pages, M_DRM);
1813 /* Ensure that the associated pages are gathered from the backing storage
1814 * and pinned into our object. i915_gem_object_get_pages() may be called
1815 * multiple times before they are released by a single call to
1816 * i915_gem_object_put_pages() - once the pages are no longer referenced
1817 * either as a result of memory pressure (reaping pages under the shrinker)
1818 * or as the object is itself released.
1821 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1823 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1824 const struct drm_i915_gem_object_ops *ops = obj->ops;
1830 if (obj->madv != I915_MADV_WILLNEED) {
1831 DRM_ERROR("Attempting to obtain a purgeable object\n");
1835 BUG_ON(obj->pages_pin_count);
1837 ret = ops->get_pages(obj);
1841 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1846 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1847 struct intel_ring_buffer *ring)
1849 struct drm_device *dev = obj->base.dev;
1850 struct drm_i915_private *dev_priv = dev->dev_private;
1851 u32 seqno = intel_ring_get_seqno(ring);
1853 BUG_ON(ring == NULL);
1854 if (obj->ring != ring && obj->last_write_seqno) {
1855 /* Keep the seqno relative to the current ring */
1856 obj->last_write_seqno = seqno;
1860 /* Add a reference if we're newly entering the active list. */
1862 drm_gem_object_reference(&obj->base);
1866 /* Move from whatever list we were on to the tail of execution. */
1867 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1868 list_move_tail(&obj->ring_list, &ring->active_list);
1870 obj->last_read_seqno = seqno;
1872 if (obj->fenced_gpu_access) {
1873 obj->last_fenced_seqno = seqno;
1875 /* Bump MRU to take account of the delayed flush */
1876 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1877 struct drm_i915_fence_reg *reg;
1879 reg = &dev_priv->fence_regs[obj->fence_reg];
1880 list_move_tail(®->lru_list,
1881 &dev_priv->mm.fence_list);
1887 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1889 struct drm_device *dev = obj->base.dev;
1890 struct drm_i915_private *dev_priv = dev->dev_private;
1892 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1893 BUG_ON(!obj->active);
1895 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1897 list_del_init(&obj->ring_list);
1900 obj->last_read_seqno = 0;
1901 obj->last_write_seqno = 0;
1902 obj->base.write_domain = 0;
1904 obj->last_fenced_seqno = 0;
1905 obj->fenced_gpu_access = false;
1908 drm_gem_object_unreference(&obj->base);
1910 WARN_ON(i915_verify_lists(dev));
1914 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 struct intel_ring_buffer *ring;
1920 /* Carefully retire all requests without writing to the rings */
1921 for_each_ring(ring, dev_priv, i) {
1922 ret = intel_ring_idle(ring);
1926 i915_gem_retire_requests(dev);
1928 /* Finally reset hw state */
1929 for_each_ring(ring, dev_priv, i) {
1930 intel_ring_init_seqno(ring, seqno);
1932 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1933 ring->sync_seqno[j] = 0;
1939 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1941 struct drm_i915_private *dev_priv = dev->dev_private;
1947 /* HWS page needs to be set less than what we
1948 * will inject to ring
1950 ret = i915_gem_init_seqno(dev, seqno - 1);
1954 /* Carefully set the last_seqno value so that wrap
1955 * detection still works
1957 dev_priv->next_seqno = seqno;
1958 dev_priv->last_seqno = seqno - 1;
1959 if (dev_priv->last_seqno == 0)
1960 dev_priv->last_seqno--;
1966 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1968 struct drm_i915_private *dev_priv = dev->dev_private;
1970 /* reserve 0 for non-seqno */
1971 if (dev_priv->next_seqno == 0) {
1972 int ret = i915_gem_init_seqno(dev, 0);
1976 dev_priv->next_seqno = 1;
1979 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
1983 int __i915_add_request(struct intel_ring_buffer *ring,
1984 struct drm_file *file,
1985 struct drm_i915_gem_object *obj,
1988 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1989 struct drm_i915_gem_request *request;
1990 u32 request_ring_position, request_start;
1994 request_start = intel_ring_get_tail(ring);
1996 * Emit any outstanding flushes - execbuf can fail to emit the flush
1997 * after having emitted the batchbuffer command. Hence we need to fix
1998 * things up similar to emitting the lazy request. The difference here
1999 * is that the flush _must_ happen before the next request, no matter
2002 ret = intel_ring_flush_all_caches(ring);
2006 request = kmalloc(sizeof(*request), M_DRM, M_WAITOK);
2007 if (request == NULL)
2011 /* Record the position of the start of the request so that
2012 * should we detect the updated seqno part-way through the
2013 * GPU processing the request, we never over-estimate the
2014 * position of the head.
2016 request_ring_position = intel_ring_get_tail(ring);
2018 ret = ring->add_request(ring);
2024 request->seqno = intel_ring_get_seqno(ring);
2025 request->ring = ring;
2026 request->head = request_start;
2027 request->tail = request_ring_position;
2028 request->ctx = ring->last_context;
2029 request->batch_obj = obj;
2031 /* Whilst this request exists, batch_obj will be on the
2032 * active_list, and so will hold the active reference. Only when this
2033 * request is retired will the the batch_obj be moved onto the
2034 * inactive_list and lose its active reference. Hence we do not need
2035 * to explicitly hold another reference here.
2039 i915_gem_context_reference(request->ctx);
2041 request->emitted_jiffies = jiffies;
2042 was_empty = list_empty(&ring->request_list);
2043 list_add_tail(&request->list, &ring->request_list);
2044 request->file_priv = NULL;
2047 struct drm_i915_file_private *file_priv = file->driver_priv;
2049 spin_lock(&file_priv->mm.lock);
2050 request->file_priv = file_priv;
2051 list_add_tail(&request->client_list,
2052 &file_priv->mm.request_list);
2053 spin_unlock(&file_priv->mm.lock);
2056 trace_i915_gem_request_add(ring, request->seqno);
2057 ring->outstanding_lazy_request = 0;
2059 if (!dev_priv->mm.suspended) {
2060 if (i915_enable_hangcheck) {
2061 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2062 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2065 queue_delayed_work(dev_priv->wq,
2066 &dev_priv->mm.retire_work,
2067 round_jiffies_up_relative(hz));
2068 intel_mark_busy(dev_priv->dev);
2073 *out_seqno = request->seqno;
2078 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2080 struct drm_i915_file_private *file_priv = request->file_priv;
2085 spin_lock(&file_priv->mm.lock);
2086 if (request->file_priv) {
2087 list_del(&request->client_list);
2088 request->file_priv = NULL;
2090 spin_unlock(&file_priv->mm.lock);
2093 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2095 if (acthd >= obj->gtt_offset &&
2096 acthd < obj->gtt_offset + obj->base.size)
2102 static bool i915_head_inside_request(const u32 acthd_unmasked,
2103 const u32 request_start,
2104 const u32 request_end)
2106 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2108 if (request_start < request_end) {
2109 if (acthd >= request_start && acthd < request_end)
2111 } else if (request_start > request_end) {
2112 if (acthd >= request_start || acthd < request_end)
2119 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2120 const u32 acthd, bool *inside)
2122 /* There is a possibility that unmasked head address
2123 * pointing inside the ring, matches the batch_obj address range.
2124 * However this is extremely unlikely.
2127 if (request->batch_obj) {
2128 if (i915_head_inside_object(acthd, request->batch_obj)) {
2134 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2142 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2143 struct drm_i915_gem_request *request,
2146 struct i915_ctx_hang_stats *hs = NULL;
2147 bool inside, guilty;
2149 /* Innocent until proven guilty */
2152 if (ring->hangcheck.action != wait &&
2153 i915_request_guilty(request, acthd, &inside)) {
2154 DRM_ERROR("%s hung %s bo (0x%x ctx %d) at 0x%x\n",
2156 inside ? "inside" : "flushing",
2157 request->batch_obj ?
2158 request->batch_obj->gtt_offset : 0,
2159 request->ctx ? request->ctx->id : 0,
2165 /* If contexts are disabled or this is the default context, use
2166 * file_priv->reset_state
2168 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2169 hs = &request->ctx->hang_stats;
2170 else if (request->file_priv)
2171 hs = &request->file_priv->hang_stats;
2177 hs->batch_pending++;
2181 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2183 list_del(&request->list);
2184 i915_gem_request_remove_from_client(request);
2187 i915_gem_context_unreference(request->ctx);
2192 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2193 struct intel_ring_buffer *ring)
2195 u32 completed_seqno;
2198 acthd = intel_ring_get_active_head(ring);
2199 completed_seqno = ring->get_seqno(ring, false);
2201 while (!list_empty(&ring->request_list)) {
2202 struct drm_i915_gem_request *request;
2204 request = list_first_entry(&ring->request_list,
2205 struct drm_i915_gem_request,
2208 if (request->seqno > completed_seqno)
2209 i915_set_reset_status(ring, request, acthd);
2211 i915_gem_free_request(request);
2214 while (!list_empty(&ring->active_list)) {
2215 struct drm_i915_gem_object *obj;
2217 obj = list_first_entry(&ring->active_list,
2218 struct drm_i915_gem_object,
2221 i915_gem_object_move_to_inactive(obj);
2225 void i915_gem_restore_fences(struct drm_device *dev)
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2230 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2231 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2234 * Commit delayed tiling changes if we have an object still
2235 * attached to the fence, otherwise just clear the fence.
2238 i915_gem_object_update_fence(reg->obj, reg,
2239 reg->obj->tiling_mode);
2241 i915_gem_write_fence(dev, i, NULL);
2246 void i915_gem_reset(struct drm_device *dev)
2248 struct drm_i915_private *dev_priv = dev->dev_private;
2249 struct drm_i915_gem_object *obj;
2250 struct intel_ring_buffer *ring;
2253 for_each_ring(ring, dev_priv, i)
2254 i915_gem_reset_ring_lists(dev_priv, ring);
2256 /* Move everything out of the GPU domains to ensure we do any
2257 * necessary invalidation upon reuse.
2259 list_for_each_entry(obj,
2260 &dev_priv->mm.inactive_list,
2263 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2266 i915_gem_restore_fences(dev);
2270 * This function clears the request list as sequence numbers are passed.
2273 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2277 if (list_empty(&ring->request_list))
2280 WARN_ON(i915_verify_lists(ring->dev));
2282 seqno = ring->get_seqno(ring, true);
2284 while (!list_empty(&ring->request_list)) {
2285 struct drm_i915_gem_request *request;
2287 request = list_first_entry(&ring->request_list,
2288 struct drm_i915_gem_request,
2291 if (!i915_seqno_passed(seqno, request->seqno))
2294 trace_i915_gem_request_retire(ring, request->seqno);
2295 /* We know the GPU must have read the request to have
2296 * sent us the seqno + interrupt, so use the position
2297 * of tail of the request to update the last known position
2300 ring->last_retired_head = request->tail;
2302 i915_gem_free_request(request);
2305 /* Move any buffers on the active list that are no longer referenced
2306 * by the ringbuffer to the flushing/inactive lists as appropriate.
2308 while (!list_empty(&ring->active_list)) {
2309 struct drm_i915_gem_object *obj;
2311 obj = list_first_entry(&ring->active_list,
2312 struct drm_i915_gem_object,
2315 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2318 i915_gem_object_move_to_inactive(obj);
2321 if (unlikely(ring->trace_irq_seqno &&
2322 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2323 ring->irq_put(ring);
2324 ring->trace_irq_seqno = 0;
2330 i915_gem_retire_requests(struct drm_device *dev)
2332 drm_i915_private_t *dev_priv = dev->dev_private;
2333 struct intel_ring_buffer *ring;
2336 for_each_ring(ring, dev_priv, i)
2337 i915_gem_retire_requests_ring(ring);
2341 i915_gem_retire_work_handler(struct work_struct *work)
2343 drm_i915_private_t *dev_priv;
2344 struct drm_device *dev;
2345 struct intel_ring_buffer *ring;
2349 dev_priv = container_of(work, drm_i915_private_t,
2350 mm.retire_work.work);
2351 dev = dev_priv->dev;
2353 /* Come back later if the device is busy... */
2354 if (lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_NOWAIT)) {
2355 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2356 round_jiffies_up_relative(hz));
2360 i915_gem_retire_requests(dev);
2362 /* Send a periodic flush down the ring so we don't hold onto GEM
2363 * objects indefinitely.
2366 for_each_ring(ring, dev_priv, i) {
2367 if (ring->gpu_caches_dirty)
2368 i915_add_request(ring, NULL);
2370 idle &= list_empty(&ring->request_list);
2373 if (!dev_priv->mm.suspended && !idle)
2374 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2375 round_jiffies_up_relative(hz));
2377 intel_mark_idle(dev);
2379 mutex_unlock(&dev->struct_mutex);
2382 * Ensures that an object will eventually get non-busy by flushing any required
2383 * write domains, emitting any outstanding lazy request and retiring and
2384 * completed requests.
2387 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2392 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2396 i915_gem_retire_requests_ring(obj->ring);
2403 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2404 * @DRM_IOCTL_ARGS: standard ioctl arguments
2406 * Returns 0 if successful, else an error is returned with the remaining time in
2407 * the timeout parameter.
2408 * -ETIME: object is still busy after timeout
2409 * -ERESTARTSYS: signal interrupted the wait
2410 * -ENONENT: object doesn't exist
2411 * Also possible, but rare:
2412 * -EAGAIN: GPU wedged
2414 * -ENODEV: Internal IRQ fail
2415 * -E?: The add request failed
2417 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2418 * non-zero timeout parameter the wait ioctl will wait for the given number of
2419 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2420 * without holding struct_mutex the object may become re-busied before this
2421 * function completes. A similar but shorter * race condition exists in the busy
2425 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2427 drm_i915_private_t *dev_priv = dev->dev_private;
2428 struct drm_i915_gem_wait *args = data;
2429 struct drm_i915_gem_object *obj;
2430 struct intel_ring_buffer *ring = NULL;
2431 struct timespec timeout_stack, *timeout = NULL;
2432 unsigned reset_counter;
2436 if (args->timeout_ns >= 0) {
2437 timeout_stack = ns_to_timespec(args->timeout_ns);
2438 timeout = &timeout_stack;
2441 ret = i915_mutex_lock_interruptible(dev);
2445 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2446 if (&obj->base == NULL) {
2447 mutex_unlock(&dev->struct_mutex);
2451 /* Need to make sure the object gets inactive eventually. */
2452 ret = i915_gem_object_flush_active(obj);
2457 seqno = obj->last_read_seqno;
2464 /* Do this after OLR check to make sure we make forward progress polling
2465 * on this IOCTL with a 0 timeout (like busy ioctl)
2467 if (!args->timeout_ns) {
2472 drm_gem_object_unreference(&obj->base);
2473 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2474 mutex_unlock(&dev->struct_mutex);
2476 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2478 args->timeout_ns = timespec_to_ns(timeout);
2482 drm_gem_object_unreference(&obj->base);
2483 mutex_unlock(&dev->struct_mutex);
2488 * i915_gem_object_sync - sync an object to a ring.
2490 * @obj: object which may be in use on another ring.
2491 * @to: ring we wish to use the object on. May be NULL.
2493 * This code is meant to abstract object synchronization with the GPU.
2494 * Calling with NULL implies synchronizing the object with the CPU
2495 * rather than a particular GPU ring.
2497 * Returns 0 if successful, else propagates up the lower layer error.
2500 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2501 struct intel_ring_buffer *to)
2503 struct intel_ring_buffer *from = obj->ring;
2507 if (from == NULL || to == from)
2510 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2511 return i915_gem_object_wait_rendering(obj, false);
2513 idx = intel_ring_sync_index(from, to);
2515 seqno = obj->last_read_seqno;
2516 if (seqno <= from->sync_seqno[idx])
2519 ret = i915_gem_check_olr(obj->ring, seqno);
2523 ret = to->sync_to(to, from, seqno);
2525 /* We use last_read_seqno because sync_to()
2526 * might have just caused seqno wrap under
2529 from->sync_seqno[idx] = obj->last_read_seqno;
2534 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2536 u32 old_write_domain, old_read_domains;
2538 /* Force a pagefault for domain tracking on next user access */
2539 i915_gem_release_mmap(obj);
2541 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2544 /* Wait for any direct GTT access to complete */
2547 old_read_domains = obj->base.read_domains;
2548 old_write_domain = obj->base.write_domain;
2550 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2551 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2553 trace_i915_gem_object_change_domain(obj,
2559 * Unbinds an object from the GTT aperture.
2562 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2564 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2567 if (obj->gtt_space == NULL)
2573 BUG_ON(obj->pages == NULL);
2575 ret = i915_gem_object_finish_gpu(obj);
2578 /* Continue on if we fail due to EIO, the GPU is hung so we
2579 * should be safe and we need to cleanup or else we might
2580 * cause memory corruption through use-after-free.
2583 i915_gem_object_finish_gtt(obj);
2585 /* Move the object to the CPU domain to ensure that
2586 * any possible CPU writes while it's not in the GTT
2587 * are flushed when we go to remap it.
2590 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2591 if (ret == -ERESTARTSYS)
2594 /* In the event of a disaster, abandon all caches and
2595 * hope for the best.
2597 i915_gem_clflush_object(obj);
2598 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2601 /* release the fence reg _after_ flushing */
2602 ret = i915_gem_object_put_fence(obj);
2606 trace_i915_gem_object_unbind(obj);
2608 if (obj->has_global_gtt_mapping)
2609 i915_gem_gtt_unbind_object(obj);
2610 if (obj->has_aliasing_ppgtt_mapping) {
2611 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2612 obj->has_aliasing_ppgtt_mapping = 0;
2614 i915_gem_gtt_finish_object(obj);
2616 i915_gem_object_put_pages_gtt(obj);
2618 list_del_init(&obj->global_list);
2619 list_del_init(&obj->mm_list);
2620 /* Avoid an unnecessary call to unbind on rebind. */
2621 obj->map_and_fenceable = true;
2623 drm_mm_put_block(obj->gtt_space);
2624 obj->gtt_space = NULL;
2625 obj->gtt_offset = 0;
2627 if (i915_gem_object_is_purgeable(obj))
2628 i915_gem_object_truncate(obj);
2633 int i915_gpu_idle(struct drm_device *dev)
2635 drm_i915_private_t *dev_priv = dev->dev_private;
2636 struct intel_ring_buffer *ring;
2639 /* Flush everything onto the inactive list. */
2640 for_each_ring(ring, dev_priv, i) {
2641 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2645 ret = intel_ring_idle(ring);
2653 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2654 struct drm_i915_gem_object *obj)
2656 drm_i915_private_t *dev_priv = dev->dev_private;
2658 int fence_pitch_shift;
2660 if (INTEL_INFO(dev)->gen >= 6) {
2661 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2662 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2664 fence_reg = FENCE_REG_965_0;
2665 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2668 fence_reg += reg * 8;
2670 /* To w/a incoherency with non-atomic 64-bit register updates,
2671 * we split the 64-bit update into two 32-bit writes. In order
2672 * for a partial fence not to be evaluated between writes, we
2673 * precede the update with write to turn off the fence register,
2674 * and only enable the fence as the last step.
2676 * For extra levels of paranoia, we make sure each step lands
2677 * before applying the next step.
2679 I915_WRITE(fence_reg, 0);
2680 POSTING_READ(fence_reg);
2683 u32 size = obj->gtt_space->size;
2686 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2688 val |= obj->gtt_offset & 0xfffff000;
2689 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2690 if (obj->tiling_mode == I915_TILING_Y)
2691 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2692 val |= I965_FENCE_REG_VALID;
2694 I915_WRITE(fence_reg + 4, val >> 32);
2695 POSTING_READ(fence_reg + 4);
2697 I915_WRITE(fence_reg + 0, val);
2698 POSTING_READ(fence_reg);
2700 I915_WRITE(fence_reg + 4, 0);
2701 POSTING_READ(fence_reg + 4);
2705 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2706 struct drm_i915_gem_object *obj)
2708 drm_i915_private_t *dev_priv = dev->dev_private;
2712 u32 size = obj->gtt_space->size;
2716 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2717 (size & -size) != size ||
2718 (obj->gtt_offset & (size - 1)),
2719 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2720 obj->gtt_offset, obj->map_and_fenceable, size);
2722 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2727 /* Note: pitch better be a power of two tile widths */
2728 pitch_val = obj->stride / tile_width;
2729 pitch_val = ffs(pitch_val) - 1;
2731 val = obj->gtt_offset;
2732 if (obj->tiling_mode == I915_TILING_Y)
2733 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2734 val |= I915_FENCE_SIZE_BITS(size);
2735 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2736 val |= I830_FENCE_REG_VALID;
2741 reg = FENCE_REG_830_0 + reg * 4;
2743 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2745 I915_WRITE(reg, val);
2749 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2750 struct drm_i915_gem_object *obj)
2752 drm_i915_private_t *dev_priv = dev->dev_private;
2756 u32 size = obj->gtt_space->size;
2759 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2760 (size & -size) != size ||
2761 (obj->gtt_offset & (size - 1)),
2762 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2763 obj->gtt_offset, size);
2765 pitch_val = obj->stride / 128;
2766 pitch_val = ffs(pitch_val) - 1;
2768 val = obj->gtt_offset;
2769 if (obj->tiling_mode == I915_TILING_Y)
2770 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2771 val |= I830_FENCE_SIZE_BITS(size);
2772 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2773 val |= I830_FENCE_REG_VALID;
2777 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2778 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2781 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2783 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2786 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2787 struct drm_i915_gem_object *obj)
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2791 /* Ensure that all CPU reads are completed before installing a fence
2792 * and all writes before removing the fence.
2794 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2797 WARN(obj && (!obj->stride || !obj->tiling_mode),
2798 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2799 obj->stride, obj->tiling_mode);
2801 switch (INTEL_INFO(dev)->gen) {
2805 case 4: i965_write_fence_reg(dev, reg, obj); break;
2806 case 3: i915_write_fence_reg(dev, reg, obj); break;
2807 case 2: i830_write_fence_reg(dev, reg, obj); break;
2811 /* And similarly be paranoid that no direct access to this region
2812 * is reordered to before the fence is installed.
2814 if (i915_gem_object_needs_mb(obj))
2818 static inline int fence_number(struct drm_i915_private *dev_priv,
2819 struct drm_i915_fence_reg *fence)
2821 return fence - dev_priv->fence_regs;
2824 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2825 struct drm_i915_fence_reg *fence,
2828 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2829 int reg = fence_number(dev_priv, fence);
2831 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2834 obj->fence_reg = reg;
2836 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2838 obj->fence_reg = I915_FENCE_REG_NONE;
2840 list_del_init(&fence->lru_list);
2842 obj->fence_dirty = false;
2846 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2848 if (obj->last_fenced_seqno) {
2849 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2853 obj->last_fenced_seqno = 0;
2856 obj->fenced_gpu_access = false;
2861 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2863 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2864 struct drm_i915_fence_reg *fence;
2867 ret = i915_gem_object_wait_fence(obj);
2871 if (obj->fence_reg == I915_FENCE_REG_NONE)
2874 fence = &dev_priv->fence_regs[obj->fence_reg];
2876 i915_gem_object_fence_lost(obj);
2877 i915_gem_object_update_fence(obj, fence, false);
2882 static struct drm_i915_fence_reg *
2883 i915_find_fence_reg(struct drm_device *dev)
2885 struct drm_i915_private *dev_priv = dev->dev_private;
2886 struct drm_i915_fence_reg *reg, *avail;
2889 /* First try to find a free reg */
2891 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2892 reg = &dev_priv->fence_regs[i];
2896 if (!reg->pin_count)
2903 /* None available, try to steal one or wait for a user to finish */
2904 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2915 * i915_gem_object_get_fence - set up fencing for an object
2916 * @obj: object to map through a fence reg
2918 * When mapping objects through the GTT, userspace wants to be able to write
2919 * to them without having to worry about swizzling if the object is tiled.
2920 * This function walks the fence regs looking for a free one for @obj,
2921 * stealing one if it can't find any.
2923 * It then sets up the reg based on the object's properties: address, pitch
2924 * and tiling format.
2926 * For an untiled surface, this removes any existing fence.
2929 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2931 struct drm_device *dev = obj->base.dev;
2932 struct drm_i915_private *dev_priv = dev->dev_private;
2933 bool enable = obj->tiling_mode != I915_TILING_NONE;
2934 struct drm_i915_fence_reg *reg;
2937 /* Have we updated the tiling parameters upon the object and so
2938 * will need to serialise the write to the associated fence register?
2940 if (obj->fence_dirty) {
2941 ret = i915_gem_object_wait_fence(obj);
2946 /* Just update our place in the LRU if our fence is getting reused. */
2947 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2948 reg = &dev_priv->fence_regs[obj->fence_reg];
2949 if (!obj->fence_dirty) {
2950 list_move_tail(®->lru_list,
2951 &dev_priv->mm.fence_list);
2954 } else if (enable) {
2955 reg = i915_find_fence_reg(dev);
2960 struct drm_i915_gem_object *old = reg->obj;
2962 ret = i915_gem_object_wait_fence(old);
2966 i915_gem_object_fence_lost(old);
2971 i915_gem_object_update_fence(obj, reg, enable);
2976 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2977 struct drm_mm_node *gtt_space,
2978 unsigned long cache_level)
2980 struct drm_mm_node *other;
2982 /* On non-LLC machines we have to be careful when putting differing
2983 * types of snoopable memory together to avoid the prefetcher
2984 * crossing memory domains and dying.
2989 if (gtt_space == NULL)
2992 if (list_empty(>t_space->node_list))
2995 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2996 if (other->allocated && !other->hole_follows && other->color != cache_level)
2999 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3000 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3006 static void i915_gem_verify_gtt(struct drm_device *dev)
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct drm_i915_gem_object *obj;
3013 list_for_each_entry(obj, &dev_priv->mm.global_list, global_list) {
3014 if (obj->gtt_space == NULL) {
3015 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3020 if (obj->cache_level != obj->gtt_space->color) {
3021 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3022 obj->gtt_space->start,
3023 obj->gtt_space->start + obj->gtt_space->size,
3025 obj->gtt_space->color);
3030 if (!i915_gem_valid_gtt_space(dev,
3032 obj->cache_level)) {
3033 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3034 obj->gtt_space->start,
3035 obj->gtt_space->start + obj->gtt_space->size,
3047 * Finds free space in the GTT aperture and binds the object there.
3050 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3052 bool map_and_fenceable,
3055 struct drm_device *dev = obj->base.dev;
3056 drm_i915_private_t *dev_priv = dev->dev_private;
3057 struct drm_mm_node *node;
3058 u32 size, fence_size, fence_alignment, unfenced_alignment;
3059 bool mappable, fenceable;
3060 size_t gtt_max = map_and_fenceable ?
3061 dev_priv->gtt.mappable_end : dev_priv->gtt.total;
3064 fence_size = i915_gem_get_gtt_size(dev,
3067 fence_alignment = i915_gem_get_gtt_alignment(dev,
3069 obj->tiling_mode, true);
3070 unfenced_alignment =
3071 i915_gem_get_gtt_alignment(dev,
3073 obj->tiling_mode, false);
3076 alignment = map_and_fenceable ? fence_alignment :
3078 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3079 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3083 size = map_and_fenceable ? fence_size : obj->base.size;
3085 /* If the object is bigger than the entire aperture, reject it early
3086 * before evicting everything in a vain attempt to find space.
3088 if (obj->base.size > gtt_max) {
3089 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3091 map_and_fenceable ? "mappable" : "total",
3097 if (map_and_fenceable)
3098 node = drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
3099 size, alignment, obj->cache_level,
3100 0, dev_priv->gtt.mappable_end,
3103 node = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
3104 size, alignment, obj->cache_level,
3107 if (map_and_fenceable)
3109 drm_mm_get_block_range_generic(node,
3110 size, alignment, obj->cache_level,
3111 0, dev_priv->gtt.mappable_end,
3115 drm_mm_get_block_generic(node,
3116 size, alignment, obj->cache_level,
3119 if (obj->gtt_space == NULL) {
3120 ret = i915_gem_evict_something(dev, size, alignment,
3131 * NOTE: i915_gem_object_get_pages_gtt() cannot
3132 * return ENOMEM, since we used VM_ALLOC_RETRY.
3134 ret = i915_gem_object_get_pages_gtt(obj);
3136 drm_mm_put_block(obj->gtt_space);
3137 obj->gtt_space = NULL;
3141 i915_gem_gtt_bind_object(obj, obj->cache_level);
3143 i915_gem_object_put_pages_gtt(obj);
3144 drm_mm_put_block(obj->gtt_space);
3145 obj->gtt_space = NULL;
3146 if (i915_gem_evict_everything(dev))
3151 list_add_tail(&obj->global_list, &dev_priv->mm.bound_list);
3152 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3154 obj->gtt_offset = obj->gtt_space->start;
3157 obj->gtt_space->size == fence_size &&
3158 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
3161 obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;
3163 obj->map_and_fenceable = mappable && fenceable;
3165 trace_i915_gem_object_bind(obj, map_and_fenceable);
3166 i915_gem_verify_gtt(dev);
3171 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3174 /* If we don't have a page list set up, then we're not pinned
3175 * to GPU, and we can ignore the cache flush because it'll happen
3176 * again at bind time.
3178 if (obj->pages == NULL)
3182 * Stolen memory is always coherent with the GPU as it is explicitly
3183 * marked as wc by the system, or the system is cache-coherent.
3188 /* If the GPU is snooping the contents of the CPU cache,
3189 * we do not need to manually clear the CPU cache lines. However,
3190 * the caches are only snooped when the render cache is
3191 * flushed/invalidated. As we always have to emit invalidations
3192 * and flushes when moving into and out of the RENDER domain, correct
3193 * snooping behaviour occurs naturally as the result of our domain
3196 if (obj->cache_level != I915_CACHE_NONE)
3199 trace_i915_gem_object_clflush(obj);
3201 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
3204 /** Flushes the GTT write domain for the object if it's dirty. */
3206 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3208 uint32_t old_write_domain;
3210 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3213 /* No actual flushing is required for the GTT write domain. Writes
3214 * to it immediately go to main memory as far as we know, so there's
3215 * no chipset flush. It also doesn't land in render cache.
3217 * However, we do have to enforce the order so that all writes through
3218 * the GTT land before any writes to the device, such as updates to
3223 old_write_domain = obj->base.write_domain;
3224 obj->base.write_domain = 0;
3226 trace_i915_gem_object_change_domain(obj,
3227 obj->base.read_domains,
3231 /** Flushes the CPU write domain for the object if it's dirty. */
3233 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3235 uint32_t old_write_domain;
3237 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3240 i915_gem_clflush_object(obj);
3241 i915_gem_chipset_flush(obj->base.dev);
3242 old_write_domain = obj->base.write_domain;
3243 obj->base.write_domain = 0;
3245 trace_i915_gem_object_change_domain(obj,
3246 obj->base.read_domains,
3251 * Moves a single object to the GTT read, and possibly write domain.
3253 * This function returns when the move is complete, including waiting on
3257 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3259 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3260 uint32_t old_write_domain, old_read_domains;
3263 /* Not valid to be called on unbound objects. */
3264 if (obj->gtt_space == NULL)
3267 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3270 ret = i915_gem_object_wait_rendering(obj, !write);
3274 i915_gem_object_flush_cpu_write_domain(obj);
3276 /* Serialise direct access to this object with the barriers for
3277 * coherent writes from the GPU, by effectively invalidating the
3278 * GTT domain upon first access.
3280 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3283 old_write_domain = obj->base.write_domain;
3284 old_read_domains = obj->base.read_domains;
3286 /* It should now be out of any other write domains, and we can update
3287 * the domain values for our changes.
3289 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3290 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3292 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3293 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3297 trace_i915_gem_object_change_domain(obj,
3301 /* And bump the LRU for this access */
3302 if (i915_gem_object_is_inactive(obj))
3303 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3308 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3309 enum i915_cache_level cache_level)
3311 struct drm_device *dev = obj->base.dev;
3312 drm_i915_private_t *dev_priv = dev->dev_private;
3315 if (obj->cache_level == cache_level)
3318 if (obj->pin_count) {
3319 DRM_DEBUG("can not change the cache level of pinned objects\n");
3323 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3324 ret = i915_gem_object_unbind(obj);
3329 if (obj->gtt_space) {
3330 ret = i915_gem_object_finish_gpu(obj);
3334 i915_gem_object_finish_gtt(obj);
3336 /* Before SandyBridge, you could not use tiling or fence
3337 * registers with snooped memory, so relinquish any fences
3338 * currently pointing to our region in the aperture.
3340 if (INTEL_INFO(dev)->gen < 6) {
3341 ret = i915_gem_object_put_fence(obj);
3346 if (obj->has_global_gtt_mapping)
3347 i915_gem_gtt_bind_object(obj, cache_level);
3348 if (obj->has_aliasing_ppgtt_mapping)
3349 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3352 obj->gtt_space->color = cache_level;
3355 if (cache_level == I915_CACHE_NONE) {
3356 u32 old_read_domains, old_write_domain;
3358 /* If we're coming from LLC cached, then we haven't
3359 * actually been tracking whether the data is in the
3360 * CPU cache or not, since we only allow one bit set
3361 * in obj->write_domain and have been skipping the clflushes.
3362 * Just set it to the CPU cache for now.
3364 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3365 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3367 old_read_domains = obj->base.read_domains;
3368 old_write_domain = obj->base.write_domain;
3370 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3371 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3373 trace_i915_gem_object_change_domain(obj,
3378 obj->cache_level = cache_level;
3379 i915_gem_verify_gtt(dev);
3383 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3384 struct drm_file *file)
3386 struct drm_i915_gem_caching *args = data;
3387 struct drm_i915_gem_object *obj;
3390 ret = i915_mutex_lock_interruptible(dev);
3394 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3395 if (&obj->base == NULL) {
3400 args->caching = obj->cache_level != I915_CACHE_NONE;
3402 drm_gem_object_unreference(&obj->base);
3404 mutex_unlock(&dev->struct_mutex);
3408 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3409 struct drm_file *file)
3411 struct drm_i915_gem_caching *args = data;
3412 struct drm_i915_gem_object *obj;
3413 enum i915_cache_level level;
3416 switch (args->caching) {
3417 case I915_CACHING_NONE:
3418 level = I915_CACHE_NONE;
3420 case I915_CACHING_CACHED:
3421 level = I915_CACHE_LLC;
3427 ret = i915_mutex_lock_interruptible(dev);
3431 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3432 if (&obj->base == NULL) {
3437 ret = i915_gem_object_set_cache_level(obj, level);
3439 drm_gem_object_unreference(&obj->base);
3441 mutex_unlock(&dev->struct_mutex);
3446 * Prepare buffer for display plane (scanout, cursors, etc).
3447 * Can be called from an uninterruptible phase (modesetting) and allows
3448 * any flushes to be pipelined (for pageflips).
3451 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3453 struct intel_ring_buffer *pipelined)
3455 u32 old_read_domains, old_write_domain;
3458 if (pipelined != obj->ring) {
3459 ret = i915_gem_object_sync(obj, pipelined);
3464 /* The display engine is not coherent with the LLC cache on gen6. As
3465 * a result, we make sure that the pinning that is about to occur is
3466 * done with uncached PTEs. This is lowest common denominator for all
3469 * However for gen6+, we could do better by using the GFDT bit instead
3470 * of uncaching, which would allow us to flush all the LLC-cached data
3471 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3473 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3477 /* As the user may map the buffer once pinned in the display plane
3478 * (e.g. libkms for the bootup splash), we have to ensure that we
3479 * always use map_and_fenceable for all scanout buffers.
3481 ret = i915_gem_object_pin(obj, alignment, true, false);
3485 i915_gem_object_flush_cpu_write_domain(obj);
3487 old_write_domain = obj->base.write_domain;
3488 old_read_domains = obj->base.read_domains;
3490 /* It should now be out of any other write domains, and we can update
3491 * the domain values for our changes.
3493 obj->base.write_domain = 0;
3494 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3496 trace_i915_gem_object_change_domain(obj,
3504 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3508 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3511 ret = i915_gem_object_wait_rendering(obj, false);
3515 /* Ensure that we invalidate the GPU's caches and TLBs. */
3516 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3521 * Moves a single object to the CPU read, and possibly write domain.
3523 * This function returns when the move is complete, including waiting on
3527 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3529 uint32_t old_write_domain, old_read_domains;
3532 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3535 ret = i915_gem_object_wait_rendering(obj, !write);
3539 i915_gem_object_flush_gtt_write_domain(obj);
3541 old_write_domain = obj->base.write_domain;
3542 old_read_domains = obj->base.read_domains;
3544 /* Flush the CPU cache if it's still invalid. */
3545 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3546 i915_gem_clflush_object(obj);
3548 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3551 /* It should now be out of any other write domains, and we can update
3552 * the domain values for our changes.
3554 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3556 /* If we're writing through the CPU, then the GPU read domains will
3557 * need to be invalidated at next use.
3560 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3561 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3564 trace_i915_gem_object_change_domain(obj,
3571 /* Throttle our rendering by waiting until the ring has completed our requests
3572 * emitted over 20 msec ago.
3574 * Note that if we were to use the current jiffies each time around the loop,
3575 * we wouldn't escape the function with any frames outstanding if the time to
3576 * render a frame was over 20ms.
3578 * This should get us reasonable parallelism between CPU and GPU but also
3579 * relatively low latency when blocking on a particular request to finish.
3582 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3584 struct drm_i915_private *dev_priv = dev->dev_private;
3585 struct drm_i915_file_private *file_priv = file->driver_priv;
3586 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3587 struct drm_i915_gem_request *request;
3588 struct intel_ring_buffer *ring = NULL;
3589 unsigned reset_counter;
3593 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3597 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3601 spin_lock(&file_priv->mm.lock);
3602 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3603 if (time_after_eq(request->emitted_jiffies, recent_enough))
3606 ring = request->ring;
3607 seqno = request->seqno;
3609 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3610 spin_unlock(&file_priv->mm.lock);
3615 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3617 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3623 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3625 bool map_and_fenceable,
3630 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3633 if (obj->gtt_space != NULL) {
3634 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3635 (map_and_fenceable && !obj->map_and_fenceable)) {
3636 WARN(obj->pin_count,
3637 "bo is already pinned with incorrect alignment:"
3638 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3639 " obj->map_and_fenceable=%d\n",
3640 obj->gtt_offset, alignment,
3642 obj->map_and_fenceable);
3643 ret = i915_gem_object_unbind(obj);
3649 if (obj->gtt_space == NULL) {
3650 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3652 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3658 if (!dev_priv->mm.aliasing_ppgtt)
3659 i915_gem_gtt_bind_object(obj, obj->cache_level);
3662 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3663 i915_gem_gtt_bind_object(obj, obj->cache_level);
3666 obj->pin_mappable |= map_and_fenceable;
3672 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3674 BUG_ON(obj->pin_count == 0);
3675 BUG_ON(obj->gtt_space == NULL);
3677 if (--obj->pin_count == 0)
3678 obj->pin_mappable = false;
3682 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3683 struct drm_file *file)
3685 struct drm_i915_gem_pin *args = data;
3686 struct drm_i915_gem_object *obj;
3689 ret = i915_mutex_lock_interruptible(dev);
3693 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3694 if (&obj->base == NULL) {
3699 if (obj->madv != I915_MADV_WILLNEED) {
3700 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3705 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3706 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3712 if (obj->user_pin_count == 0) {
3713 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3718 obj->user_pin_count++;
3719 obj->pin_filp = file;
3721 /* XXX - flush the CPU caches for pinned objects
3722 * as the X server doesn't manage domains yet
3724 i915_gem_object_flush_cpu_write_domain(obj);
3725 args->offset = obj->gtt_offset;
3727 drm_gem_object_unreference(&obj->base);
3729 mutex_unlock(&dev->struct_mutex);
3734 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3735 struct drm_file *file)
3737 struct drm_i915_gem_pin *args = data;
3738 struct drm_i915_gem_object *obj;
3741 ret = i915_mutex_lock_interruptible(dev);
3745 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3746 if (&obj->base == NULL) {
3751 if (obj->pin_filp != file) {
3752 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3757 obj->user_pin_count--;
3758 if (obj->user_pin_count == 0) {
3759 obj->pin_filp = NULL;
3760 i915_gem_object_unpin(obj);
3764 drm_gem_object_unreference(&obj->base);
3766 mutex_unlock(&dev->struct_mutex);
3771 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3772 struct drm_file *file)
3774 struct drm_i915_gem_busy *args = data;
3775 struct drm_i915_gem_object *obj;
3778 ret = i915_mutex_lock_interruptible(dev);
3782 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3783 if (&obj->base == NULL) {
3788 /* Count all active objects as busy, even if they are currently not used
3789 * by the gpu. Users of this interface expect objects to eventually
3790 * become non-busy without any further actions, therefore emit any
3791 * necessary flushes here.
3793 ret = i915_gem_object_flush_active(obj);
3795 args->busy = obj->active;
3797 args->busy |= intel_ring_flag(obj->ring) << 16;
3800 drm_gem_object_unreference(&obj->base);
3802 mutex_unlock(&dev->struct_mutex);
3807 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3808 struct drm_file *file_priv)
3810 return i915_gem_ring_throttle(dev, file_priv);
3814 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3815 struct drm_file *file_priv)
3817 struct drm_i915_gem_madvise *args = data;
3818 struct drm_i915_gem_object *obj;
3821 switch (args->madv) {
3822 case I915_MADV_DONTNEED:
3823 case I915_MADV_WILLNEED:
3829 ret = i915_mutex_lock_interruptible(dev);
3833 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3834 if (&obj->base == NULL) {
3839 if (obj->pin_count) {
3844 if (obj->madv != __I915_MADV_PURGED)
3845 obj->madv = args->madv;
3847 /* if the object is no longer attached, discard its backing storage */
3848 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3849 i915_gem_object_truncate(obj);
3851 args->retained = obj->madv != __I915_MADV_PURGED;
3854 drm_gem_object_unreference(&obj->base);
3856 mutex_unlock(&dev->struct_mutex);
3860 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3861 const struct drm_i915_gem_object_ops *ops)
3863 INIT_LIST_HEAD(&obj->mm_list);
3864 INIT_LIST_HEAD(&obj->global_list);
3865 INIT_LIST_HEAD(&obj->ring_list);
3866 INIT_LIST_HEAD(&obj->exec_list);
3870 obj->fence_reg = I915_FENCE_REG_NONE;
3871 obj->madv = I915_MADV_WILLNEED;
3872 /* Avoid an unnecessary call to unbind on the first bind. */
3873 obj->map_and_fenceable = true;
3875 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3878 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3879 .get_pages = i915_gem_object_get_pages_gtt,
3880 .put_pages = i915_gem_object_put_pages_gtt,
3883 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3886 struct drm_i915_gem_object *obj;
3888 struct address_space *mapping;
3892 obj = kmalloc(sizeof(*obj), M_DRM, M_WAITOK | M_ZERO);
3896 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3902 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3903 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3904 /* 965gm cannot relocate objects above 4GiB. */
3905 mask &= ~__GFP_HIGHMEM;
3906 mask |= __GFP_DMA32;
3909 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3910 mapping_set_gfp_mask(mapping, mask);
3913 i915_gem_object_init(obj, &i915_gem_object_ops);
3915 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3916 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3919 /* On some devices, we can have the GPU use the LLC (the CPU
3920 * cache) for about a 10% performance improvement
3921 * compared to uncached. Graphics requests other than
3922 * display scanout are coherent with the CPU in
3923 * accessing this cache. This means in this mode we
3924 * don't need to clflush on the CPU side, and on the
3925 * GPU side we only need to flush internal caches to
3926 * get data visible to the CPU.
3928 * However, we maintain the display planes as UC, and so
3929 * need to rebind when first used as such.
3931 obj->cache_level = I915_CACHE_LLC;
3933 obj->cache_level = I915_CACHE_NONE;
3938 int i915_gem_init_object(struct drm_gem_object *obj)
3945 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3947 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3948 struct drm_device *dev = obj->base.dev;
3949 drm_i915_private_t *dev_priv = dev->dev_private;
3951 trace_i915_gem_object_destroy(obj);
3954 i915_gem_detach_phys_object(dev, obj);
3957 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3958 bool was_interruptible;
3960 was_interruptible = dev_priv->mm.interruptible;
3961 dev_priv->mm.interruptible = false;
3963 WARN_ON(i915_gem_object_unbind(obj));
3965 dev_priv->mm.interruptible = was_interruptible;
3968 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3969 * before progressing. */
3971 i915_gem_object_unpin_pages(obj);
3973 if (WARN_ON(obj->pages_pin_count))
3974 obj->pages_pin_count = 0;
3975 i915_gem_object_put_pages(obj);
3976 drm_gem_free_mmap_offset(&obj->base);
3980 drm_gem_object_release(&obj->base);
3981 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3984 i915_gem_object_free(obj);
3988 i915_gem_idle(struct drm_device *dev)
3990 drm_i915_private_t *dev_priv = dev->dev_private;
3993 mutex_lock(&dev->struct_mutex);
3995 if (dev_priv->mm.suspended) {
3996 mutex_unlock(&dev->struct_mutex);
4000 ret = i915_gpu_idle(dev);
4002 mutex_unlock(&dev->struct_mutex);
4005 i915_gem_retire_requests(dev);
4007 /* Under UMS, be paranoid and evict. */
4008 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4009 i915_gem_evict_everything(dev);
4011 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4012 * We need to replace this with a semaphore, or something.
4013 * And not confound mm.suspended!
4015 dev_priv->mm.suspended = 1;
4016 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4018 i915_kernel_lost_context(dev);
4019 i915_gem_cleanup_ringbuffer(dev);
4021 mutex_unlock(&dev->struct_mutex);
4023 /* Cancel the retire work handler, which should be idle now. */
4024 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4029 void i915_gem_l3_remap(struct drm_device *dev)
4031 drm_i915_private_t *dev_priv = dev->dev_private;
4035 if (!HAS_L3_GPU_CACHE(dev))
4038 if (!dev_priv->l3_parity.remap_info)
4041 misccpctl = I915_READ(GEN7_MISCCPCTL);
4042 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4043 POSTING_READ(GEN7_MISCCPCTL);
4045 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4046 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4047 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4048 DRM_DEBUG("0x%x was already programmed to %x\n",
4049 GEN7_L3LOG_BASE + i, remap);
4050 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4051 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4052 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4055 /* Make sure all the writes land before disabling dop clock gating */
4056 POSTING_READ(GEN7_L3LOG_BASE);
4058 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4061 void i915_gem_init_swizzling(struct drm_device *dev)
4063 drm_i915_private_t *dev_priv = dev->dev_private;
4065 if (INTEL_INFO(dev)->gen < 5 ||
4066 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4069 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4070 DISP_TILE_SURFACE_SWIZZLING);
4075 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4077 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4078 else if (IS_GEN7(dev))
4079 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4085 intel_enable_blt(struct drm_device *dev)
4092 /* The blitter was dysfunctional on early prototypes */
4093 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
4094 if (IS_GEN6(dev) && revision < 8) {
4095 DRM_INFO("BLT not supported on this pre-production hardware;"
4096 " graphics performance will be degraded.\n");
4103 static int i915_gem_init_rings(struct drm_device *dev)
4105 struct drm_i915_private *dev_priv = dev->dev_private;
4108 ret = intel_init_render_ring_buffer(dev);
4113 ret = intel_init_bsd_ring_buffer(dev);
4115 goto cleanup_render_ring;
4118 if (intel_enable_blt(dev)) {
4119 ret = intel_init_blt_ring_buffer(dev);
4121 goto cleanup_bsd_ring;
4124 if (HAS_VEBOX(dev)) {
4125 ret = intel_init_vebox_ring_buffer(dev);
4127 goto cleanup_blt_ring;
4131 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4133 goto cleanup_vebox_ring;
4138 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4140 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4142 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4143 cleanup_render_ring:
4144 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4150 i915_gem_init_hw(struct drm_device *dev)
4152 drm_i915_private_t *dev_priv = dev->dev_private;
4156 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4160 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4161 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4163 if (HAS_PCH_NOP(dev)) {
4164 u32 temp = I915_READ(GEN7_MSG_CTL);
4165 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4166 I915_WRITE(GEN7_MSG_CTL, temp);
4169 i915_gem_l3_remap(dev);
4171 i915_gem_init_swizzling(dev);
4173 ret = i915_gem_init_rings(dev);
4178 * XXX: There was some w/a described somewhere suggesting loading
4179 * contexts before PPGTT.
4181 i915_gem_context_init(dev);
4182 if (dev_priv->mm.aliasing_ppgtt) {
4183 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4185 i915_gem_cleanup_aliasing_ppgtt(dev);
4186 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4193 int i915_gem_init(struct drm_device *dev)
4195 struct drm_i915_private *dev_priv = dev->dev_private;
4198 mutex_lock(&dev->struct_mutex);
4200 if (IS_VALLEYVIEW(dev)) {
4201 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4202 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4203 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4204 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4207 i915_gem_init_global_gtt(dev);
4209 ret = i915_gem_init_hw(dev);
4210 mutex_unlock(&dev->struct_mutex);
4212 i915_gem_cleanup_aliasing_ppgtt(dev);
4216 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4217 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4218 dev_priv->dri1.allow_batchbuffer = 1;
4223 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4225 drm_i915_private_t *dev_priv = dev->dev_private;
4226 struct intel_ring_buffer *ring;
4229 for_each_ring(ring, dev_priv, i)
4230 intel_cleanup_ring_buffer(ring);
4234 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4235 struct drm_file *file_priv)
4237 drm_i915_private_t *dev_priv = dev->dev_private;
4240 if (drm_core_check_feature(dev, DRIVER_MODESET))
4243 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4244 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4245 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4248 mutex_lock(&dev->struct_mutex);
4249 dev_priv->mm.suspended = 0;
4251 ret = i915_gem_init_hw(dev);
4253 mutex_unlock(&dev->struct_mutex);
4257 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
4258 mutex_unlock(&dev->struct_mutex);
4260 ret = drm_irq_install(dev);
4262 goto cleanup_ringbuffer;
4267 mutex_lock(&dev->struct_mutex);
4268 i915_gem_cleanup_ringbuffer(dev);
4269 dev_priv->mm.suspended = 1;
4270 mutex_unlock(&dev->struct_mutex);
4276 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4277 struct drm_file *file_priv)
4279 if (drm_core_check_feature(dev, DRIVER_MODESET))
4282 drm_irq_uninstall(dev);
4283 return i915_gem_idle(dev);
4287 i915_gem_lastclose(struct drm_device *dev)
4291 if (drm_core_check_feature(dev, DRIVER_MODESET))
4294 ret = i915_gem_idle(dev);
4296 DRM_ERROR("failed to idle hardware: %d\n", ret);
4300 init_ring_lists(struct intel_ring_buffer *ring)
4302 INIT_LIST_HEAD(&ring->active_list);
4303 INIT_LIST_HEAD(&ring->request_list);
4307 i915_gem_load(struct drm_device *dev)
4310 drm_i915_private_t *dev_priv = dev->dev_private;
4312 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4313 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4314 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4315 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4316 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4317 for (i = 0; i < I915_NUM_RINGS; i++)
4318 init_ring_lists(&dev_priv->ring[i]);
4319 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4320 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4321 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4322 i915_gem_retire_work_handler);
4323 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4325 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4327 I915_WRITE(MI_ARB_STATE,
4328 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4331 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4333 /* Old X drivers will take 0-2 for front, back, depth buffers */
4334 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4335 dev_priv->fence_reg_start = 3;
4337 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4338 dev_priv->num_fence_regs = 32;
4339 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4340 dev_priv->num_fence_regs = 16;
4342 dev_priv->num_fence_regs = 8;
4344 /* Initialize fence registers to zero */
4345 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4346 i915_gem_restore_fences(dev);
4348 i915_gem_detect_bit_6_swizzle(dev);
4349 init_waitqueue_head(&dev_priv->pending_flip_queue);
4351 dev_priv->mm.interruptible = true;
4354 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4355 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4356 register_shrinker(&dev_priv->mm.inactive_shrinker);
4358 dev_priv->mm.inactive_shrinker = EVENTHANDLER_REGISTER(vm_lowmem,
4359 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
4364 * Create a physically contiguous memory object for this object
4365 * e.g. for cursor + overlay regs
4367 static int i915_gem_init_phys_object(struct drm_device *dev,
4368 int id, int size, int align)
4370 drm_i915_private_t *dev_priv = dev->dev_private;
4371 struct drm_i915_gem_phys_object *phys_obj;
4374 if (dev_priv->mm.phys_objs[id - 1] || !size)
4377 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4383 phys_obj->handle = drm_pci_alloc(dev, size, align);
4384 if (!phys_obj->handle) {
4388 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
4389 size / PAGE_SIZE, PAT_WRITE_COMBINING);
4391 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4400 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4402 drm_i915_private_t *dev_priv = dev->dev_private;
4403 struct drm_i915_gem_phys_object *phys_obj;
4405 if (!dev_priv->mm.phys_objs[id - 1])
4408 phys_obj = dev_priv->mm.phys_objs[id - 1];
4409 if (phys_obj->cur_obj) {
4410 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4413 drm_pci_free(dev, phys_obj->handle);
4415 dev_priv->mm.phys_objs[id - 1] = NULL;
4418 void i915_gem_free_all_phys_object(struct drm_device *dev)
4422 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4423 i915_gem_free_phys_object(dev, i);
4426 void i915_gem_detach_phys_object(struct drm_device *dev,
4427 struct drm_i915_gem_object *obj)
4429 struct vm_object *mapping = obj->base.vm_obj;
4436 vaddr = obj->phys_obj->handle->vaddr;
4438 page_count = obj->base.size / PAGE_SIZE;
4439 VM_OBJECT_LOCK(obj->base.vm_obj);
4440 for (i = 0; i < page_count; i++) {
4441 struct vm_page *page = shmem_read_mapping_page(mapping, i);
4442 if (!IS_ERR(page)) {
4443 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4444 char *dst = kmap_atomic(page);
4445 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4448 drm_clflush_pages(&page, 1);
4451 set_page_dirty(page);
4452 mark_page_accessed(page);
4453 page_cache_release(page);
4455 VM_OBJECT_LOCK(obj->base.vm_obj);
4456 vm_page_reference(page);
4457 vm_page_dirty(page);
4458 vm_page_busy_wait(page, FALSE, "i915gem");
4459 vm_page_unwire(page, 0);
4460 vm_page_wakeup(page);
4463 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4464 intel_gtt_chipset_flush();
4466 obj->phys_obj->cur_obj = NULL;
4467 obj->phys_obj = NULL;
4471 i915_gem_attach_phys_object(struct drm_device *dev,
4472 struct drm_i915_gem_object *obj,
4476 struct vm_object *mapping = obj->base.vm_obj;
4477 drm_i915_private_t *dev_priv = dev->dev_private;
4482 if (id > I915_MAX_PHYS_OBJECT)
4485 if (obj->phys_obj) {
4486 if (obj->phys_obj->id == id)
4488 i915_gem_detach_phys_object(dev, obj);
4491 /* create a new object */
4492 if (!dev_priv->mm.phys_objs[id - 1]) {
4493 ret = i915_gem_init_phys_object(dev, id,
4494 obj->base.size, align);
4496 DRM_ERROR("failed to init phys object %d size: %zu\n",
4497 id, obj->base.size);
4502 /* bind to the object */
4503 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4504 obj->phys_obj->cur_obj = obj;
4506 page_count = obj->base.size / PAGE_SIZE;
4508 VM_OBJECT_LOCK(obj->base.vm_obj);
4509 for (i = 0; i < page_count; i++) {
4510 struct vm_page *page;
4513 page = shmem_read_mapping_page(mapping, i);
4514 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4516 return PTR_ERR(page);
4518 src = kmap_atomic(page);
4519 dst = (char*)obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4520 memcpy(dst, src, PAGE_SIZE);
4524 mark_page_accessed(page);
4525 page_cache_release(page);
4527 VM_OBJECT_LOCK(obj->base.vm_obj);
4528 vm_page_reference(page);
4529 vm_page_busy_wait(page, FALSE, "i915gem");
4530 vm_page_unwire(page, 0);
4531 vm_page_wakeup(page);
4533 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4539 i915_gem_phys_pwrite(struct drm_device *dev,
4540 struct drm_i915_gem_object *obj,
4541 struct drm_i915_gem_pwrite *args,
4542 struct drm_file *file_priv)
4544 void *vaddr = (char *)obj->phys_obj->handle->vaddr + args->offset;
4545 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4547 if (copyin_nofault(user_data, vaddr, args->size) != 0) {
4548 unsigned long unwritten;
4550 /* The physical object once assigned is fixed for the lifetime
4551 * of the obj, so we can safely drop the lock and continue
4554 mutex_unlock(&dev->struct_mutex);
4555 unwritten = copy_from_user(vaddr, user_data, args->size);
4556 mutex_lock(&dev->struct_mutex);
4561 i915_gem_chipset_flush(dev);
4565 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4567 struct drm_i915_file_private *file_priv = file->driver_priv;
4569 /* Clean up our request list when the client is going away, so that
4570 * later retire_requests won't dereference our soon-to-be-gone
4573 spin_lock(&file_priv->mm.lock);
4574 while (!list_empty(&file_priv->mm.request_list)) {
4575 struct drm_i915_gem_request *request;
4577 request = list_first_entry(&file_priv->mm.request_list,
4578 struct drm_i915_gem_request,
4580 list_del(&request->client_list);
4581 request->file_priv = NULL;
4583 spin_unlock(&file_priv->mm.lock);
4587 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
4588 vm_ooffset_t foff, struct ucred *cred, u_short *color)
4591 *color = 0; /* XXXKIB */
4596 i915_gem_pager_dtor(void *handle)
4598 struct drm_gem_object *obj;
4599 struct drm_device *dev;
4604 mutex_lock(&dev->struct_mutex);
4605 drm_gem_free_mmap_offset(obj);
4606 i915_gem_release_mmap(to_intel_bo(obj));
4607 drm_gem_object_unreference(obj);
4608 mutex_unlock(&dev->struct_mutex);
4611 #define GEM_PARANOID_CHECK_GTT 0
4612 #if GEM_PARANOID_CHECK_GTT
4614 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
4617 struct drm_i915_private *dev_priv;
4619 unsigned long start, end;
4623 dev_priv = dev->dev_private;
4624 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
4625 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
4626 for (i = start; i < end; i++) {
4627 pa = intel_gtt_read_pte_paddr(i);
4628 for (j = 0; j < page_count; j++) {
4629 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
4630 panic("Page %p in GTT pte index %d pte %x",
4631 ma[i], i, intel_gtt_read_pte(i));
4635 obj->fence_dirty = false;
4640 i915_gpu_is_active(struct drm_device *dev)
4642 drm_i915_private_t *dev_priv = dev->dev_private;
4644 return !list_empty(&dev_priv->mm.active_list);
4648 i915_gem_lowmem(void *arg)
4650 struct drm_device *dev;
4651 struct drm_i915_private *dev_priv;
4652 struct drm_i915_gem_object *obj, *next;
4653 int cnt, cnt_fail, cnt_total;
4656 dev_priv = dev->dev_private;
4658 if (lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_NOWAIT))
4662 /* first scan for clean buffers */
4663 i915_gem_retire_requests(dev);
4665 cnt_total = cnt_fail = cnt = 0;
4667 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4669 if (i915_gem_object_is_purgeable(obj)) {
4670 if (i915_gem_object_unbind(obj) != 0)
4676 /* second pass, evict/count anything still on the inactive list */
4677 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4679 if (i915_gem_object_unbind(obj) == 0)
4685 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
4687 * We are desperate for pages, so as a last resort, wait
4688 * for the GPU to finish and discard whatever we can.
4689 * This has a dramatic impact to reduce the number of
4690 * OOM-killer events whilst running the GPU aggressively.
4692 if (i915_gpu_idle(dev) == 0)
4695 mutex_unlock(&dev->struct_mutex);