2 * Core definitions and data structures shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
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13 * without modification.
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17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
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40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#92 $
42 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.h,v 1.3.2.6 2003/06/10 03:26:07 gibbs Exp $
43 * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx.h,v 1.2 2003/06/17 04:28:21 dillon Exp $
49 /* Register Definitions */
50 #include "aic79xx_reg.h"
52 /************************* Forward Declarations *******************************/
53 struct ahd_platform_data;
54 struct scb_platform_data;
56 /****************************** Useful Macros *********************************/
58 #define MAX(a,b) (((a) > (b)) ? (a) : (b))
62 #define MIN(a,b) (((a) < (b)) ? (a) : (b))
72 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
74 #define ALL_CHANNELS '\0'
75 #define ALL_TARGETS_MASK 0xFFFF
76 #define INITIATOR_WILDCARD (~0)
77 #define SCB_LIST_NULL 0xFF00
78 #define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL))
79 #define QOUTFIFO_ENTRY_VALID 0x8000
80 #define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000))
81 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
83 #define SCSIID_TARGET(ahd, scsiid) \
84 (((scsiid) & TID) >> TID_SHIFT)
85 #define SCSIID_OUR_ID(scsiid) \
87 #define SCSIID_CHANNEL(ahd, scsiid) ('A')
88 #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
89 #define SCB_GET_OUR_ID(scb) \
90 SCSIID_OUR_ID((scb)->hscb->scsiid)
91 #define SCB_GET_TARGET(ahd, scb) \
92 SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
93 #define SCB_GET_CHANNEL(ahd, scb) \
94 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
95 #define SCB_GET_LUN(scb) \
97 #define SCB_GET_TARGET_OFFSET(ahd, scb) \
98 SCB_GET_TARGET(ahd, scb)
99 #define SCB_GET_TARGET_MASK(ahd, scb) \
100 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
102 #define SCB_IS_SILENT(scb) \
103 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
104 && (((scb)->flags & SCB_SILENT) != 0))
106 #define SCB_IS_SILENT(scb) \
107 (((scb)->flags & SCB_SILENT) != 0)
110 * TCLs have the following format: TTTTLLLLLLLL
112 #define TCL_TARGET_OFFSET(tcl) \
113 ((((tcl) >> 4) & TID) >> 4)
114 #define TCL_LUN(tcl) \
115 (tcl & (AHD_NUM_LUNS - 1))
116 #define BUILD_TCL(scsiid, lun) \
117 ((lun) | (((scsiid) & TID) << 4))
118 #define BUILD_TCL_RAW(target, channel, lun) \
119 ((lun) | ((target) << 8))
121 #define SCB_GET_TAG(scb) \
122 ahd_le16toh(scb->hscb->tag)
124 #ifndef AHD_TARGET_MODE
125 #undef AHD_TMODE_ENABLE
126 #define AHD_TMODE_ENABLE 0
129 #define AHD_BUILD_COL_IDX(target, lun) \
130 (((lun) << 4) | target)
132 #define AHD_GET_SCB_COL_IDX(ahd, scb) \
133 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
135 #define AHD_SET_SCB_COL_IDX(scb, col_idx) \
137 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \
138 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \
141 #define AHD_COPY_SCB_COL_IDX(dst, src) \
143 dst->hscb->scsiid = src->hscb->scsiid; \
144 dst->hscb->lun = src->hscb->lun; \
147 #define AHD_NEVER_COL_IDX 0xFFFF
149 /**************************** Driver Constants ********************************/
151 * The maximum number of supported targets.
153 #define AHD_NUM_TARGETS 16
156 * The maximum number of supported luns.
157 * The identify message only supports 64 luns in non-packetized transfers.
158 * You can have 2^64 luns when information unit transfers are enabled,
159 * but until we see a need to support that many, we support 256.
161 #define AHD_NUM_LUNS_NONPKT 64
162 #define AHD_NUM_LUNS 256
165 * The maximum transfer per S/G segment.
167 #define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
170 * The maximum amount of SCB storage in hardware on a controller.
171 * This value represents an upper bound. Due to software design,
172 * we may not be able to use this number.
174 #define AHD_SCB_MAX 512
177 * The maximum number of concurrent transactions supported per driver instance.
178 * Sequencer Control Blocks (SCBs) store per-transaction information.
180 #define AHD_MAX_QUEUE AHD_SCB_MAX
183 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2
184 * in size and accommodate as many transactions as can be queued concurrently.
186 #define AHD_QIN_SIZE AHD_MAX_QUEUE
187 #define AHD_QOUT_SIZE AHD_MAX_QUEUE
189 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
191 * The maximum amount of SCB storage we allocate in host memory.
193 #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
196 * Ring Buffer of incoming target commands.
197 * We allocate 256 to simplify the logic in the sequencer
198 * by using the natural wrap point of an 8bit counter.
200 #define AHD_TMODE_CMDS 256
202 /* Reset line assertion time in us */
203 #define AHD_BUSRESET_DELAY 25
205 /******************* Chip Characteristics/Operating Settings *****************/
208 * The chip order is from least sophisticated to most sophisticated.
212 AHD_CHIPID_MASK = 0x00FF,
213 AHD_AIC7901 = 0x0001,
214 AHD_AIC7902 = 0x0002,
215 AHD_AIC7901A = 0x0003,
216 AHD_PCI = 0x0100, /* Bus type PCI */
217 AHD_PCIX = 0x0200, /* Bus type PCIX */
218 AHD_BUS_MASK = 0x0F00
222 * Features available in each chip type.
225 AHD_FENONE = 0x00000,
226 AHD_WIDE = 0x00001,/* Wide Channel */
227 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */
228 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */
229 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */
230 AHD_RTI = 0x04000,/* Retained Training Support */
231 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */
232 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */
233 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/
234 AHD_AIC7901_FE = AHD_FENONE,
235 AHD_AIC7902_FE = AHD_MULTI_FUNC
239 * Bugs in the silicon that we work around in software.
242 AHD_BUGNONE = 0x0000,
244 * Rev A hardware fails to update LAST/CURR/NEXTSCB
245 * correctly in certain packetized selection cases.
247 AHD_SENT_SCB_UPDATE_BUG = 0x0001,
248 /* The wrong SCB is accessed to check the abort pending bit. */
249 AHD_ABORT_LQI_BUG = 0x0002,
250 /* Packetized bitbucket crosses packet boundaries. */
251 AHD_PKT_BITBUCKET_BUG = 0x0004,
252 /* The selection timer runs twice as long as its setting. */
253 AHD_LONG_SETIMO_BUG = 0x0008,
254 /* The Non-LQ CRC error status is delayed until phase change. */
255 AHD_NLQICRC_DELAYED_BUG = 0x0010,
256 /* The chip must be reset for all outgoing bus resets. */
257 AHD_SCSIRST_BUG = 0x0020,
258 /* Some PCIX fields must be saved and restored across chip reset. */
259 AHD_PCIX_CHIPRST_BUG = 0x0040,
260 /* MMAPIO is not functional in PCI-X mode. */
261 AHD_PCIX_MMAPIO_BUG = 0x0080,
262 /* Reads to SCBRAM fail to reset the discard timer. */
263 AHD_PCIX_SCBRAM_RD_BUG = 0x0100,
264 /* Bug workarounds that can be disabled on non-PCIX busses. */
265 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG
266 | AHD_PCIX_MMAPIO_BUG
267 | AHD_PCIX_SCBRAM_RD_BUG,
269 * LQOSTOP0 status set even for forced selections with ATN
270 * to perform non-packetized message delivery.
272 AHD_LQO_ATNO_BUG = 0x0200,
273 /* FIFO auto-flush does not always trigger. */
274 AHD_AUTOFLUSH_BUG = 0x0400,
275 /* The CLRLQO registers are not self-clearing. */
276 AHD_CLRLQO_AUTOCLR_BUG = 0x0800,
277 /* The PACKETIZED status bit refers to the previous connection. */
278 AHD_PKTIZED_STATUS_BUG = 0x1000,
279 /* "Short Luns" are not placed into outgoing LQ packets correctly. */
280 AHD_PKT_LUN_BUG = 0x2000,
282 * Only the FIFO allocated to the non-packetized connection may
283 * be in use during a non-packetzied connection.
285 AHD_NONPACKFIFO_BUG = 0x4000,
287 * Writing to a DFF SCBPTR register may fail if concurent with
288 * a hardware write to the other DFF SCBPTR register. This is
289 * not currently a concern in our sequencer since all chips with
290 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
291 * occur in non-packetized connections.
293 AHD_MDFF_WSCBPTR_BUG = 0x8000,
294 /* SGHADDR updates are slow. */
295 AHD_REG_SLOW_SETTLE_BUG = 0x10000,
297 * Changing the MODE_PTR coincident with an interrupt that
298 * switches to a different mode will cause the interrupt to
299 * be in the mode written outside of interrupt context.
301 AHD_SET_MODE_BUG = 0x20000,
302 /* Non-packetized busfree revision does not work. */
303 AHD_BUSFREEREV_BUG = 0x40000,
305 * Paced transfers are indicated with a non-standard PPR
306 * option bit in the neg table, 160MHz is indicated by
307 * sync factor 0x7, and the offset if off by a factor of 2.
309 AHD_PACED_NEGTABLE_BUG = 0x80000,
310 /* LQOOVERRUN false positives. */
311 AHD_LQOOVERRUN_BUG = 0x100000,
313 * Controller write to INTSTAT will lose to a host
316 AHD_INTCOLLISION_BUG = 0x200000,
318 * The GEM318 violates the SCSI spec by not waiting
319 * the mandated bus settle delay between phase changes
320 * in some situations. Some aic79xx chip revs. are more
321 * strict in this regard and will treat REQ assertions
322 * that fall within the bus settle delay window as
323 * glitches. This flag tells the firmware to tolerate
324 * early REQ assertions.
326 AHD_EARLY_REQ_BUG = 0x400000,
328 * The LED does not stay on long enough in packetized modes.
330 AHD_FAINT_LED_BUG = 0x800000
334 * Configuration specific settings.
335 * The driver determines these settings by probing the
336 * chip/controller's configuration.
340 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */
341 AHD_USEDEFAULTS = 0x00004,/*
342 * For cards without an seeprom
343 * or a BIOS to initialize the chip's
344 * SRAM, we use the default target
347 AHD_SEQUENCER_DEBUG = 0x00008,
348 AHD_RESET_BUS_A = 0x00010,
349 AHD_EXTENDED_TRANS_A = 0x00020,
350 AHD_TERM_ENB_A = 0x00040,
351 AHD_SPCHK_ENB_A = 0x00080,
352 AHD_STPWLEVEL_A = 0x00100,
353 AHD_INITIATORROLE = 0x00200,/*
354 * Allow initiator operations on
357 AHD_TARGETROLE = 0x00400,/*
358 * Allow target operations on this
361 AHD_RESOURCE_SHORTAGE = 0x00800,
362 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */
363 AHD_INT50_SPEEDFLEX = 0x02000,/*
364 * Internal 50pin connector
365 * sits behind an aic3860
367 AHD_BIOS_ENABLED = 0x04000,
368 AHD_ALL_INTERRUPTS = 0x08000,
369 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */
370 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */
371 AHD_CURRENT_SENSING = 0x40000,
372 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */
373 AHD_HP_BOARD = 0x100000,
374 AHD_RESET_POLL_ACTIVE = 0x200000,
375 AHD_UPDATE_PEND_CMDS = 0x400000,
376 AHD_RUNNING_QOUTFIFO = 0x800000
379 /************************* Hardware SCB Definition ***************************/
382 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
383 * consists of a "hardware SCB" mirroring the fields available on the card
384 * and additional information the kernel stores for each transaction.
386 * To minimize space utilization, a portion of the hardware scb stores
387 * different data during different portions of a SCSI transaction.
388 * As initialized by the host driver for the initiator role, this area
389 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
390 * the cdb has been presented to the target, this area serves to store
391 * residual transfer information and the SCSI status byte.
392 * For the target role, the contents of this area do not change, but
393 * still serve a different purpose than for the initiator role. See
394 * struct target_data for details.
398 * Status information embedded in the shared poriton of
399 * an SCB after passing the cdb to the target. The kernel
400 * driver will only read this data for transactions that
401 * complete abnormally.
403 struct initiator_status {
404 uint32_t residual_datacnt; /* Residual in the current S/G seg */
405 uint32_t residual_sgptr; /* The next S/G for this transfer */
406 uint8_t scsi_status; /* Standard SCSI status byte */
409 struct target_status {
410 uint32_t residual_datacnt; /* Residual in the current S/G seg */
411 uint32_t residual_sgptr; /* The next S/G for this transfer */
412 uint8_t scsi_status; /* SCSI status to give to initiator */
413 uint8_t target_phases; /* Bitmap of phases to execute */
414 uint8_t data_phase; /* Data-In or Data-Out */
415 uint8_t initiator_tag; /* Initiator's transaction tag */
419 * Initiator mode SCB shared data area.
420 * If the embedded CDB is 12 bytes or less, we embed
421 * the sense buffer address in the SCB. This allows
422 * us to retrieve sense information without interrupting
423 * the host in packetized mode.
425 typedef uint32_t sense_addr_t;
426 #define MAX_CDB_LEN 16
427 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
428 union initiator_data {
433 uint8_t cdb[MAX_CDB_LEN];
435 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
436 sense_addr_t sense_addr;
441 * Target mode version of the shared data SCB segment.
445 uint8_t scsi_status; /* SCSI status to give to initiator */
446 uint8_t target_phases; /* Bitmap of phases to execute */
447 uint8_t data_phase; /* Data-In or Data-Out */
448 uint8_t initiator_tag; /* Initiator's transaction tag */
451 struct hardware_scb {
453 union initiator_data idata;
454 struct target_data tdata;
455 struct initiator_status istatus;
456 struct target_status tstatus;
459 * A word about residuals.
460 * The scb is presented to the sequencer with the dataptr and datacnt
461 * fields initialized to the contents of the first S/G element to
462 * transfer. The sgptr field is initialized to the bus address for
463 * the S/G element that follows the first in the in core S/G array
464 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
465 * S/G entry for this transfer (single S/G element transfer with the
466 * first elements address and length preloaded in the dataptr/datacnt
467 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
468 * The SG_FULL_RESID flag ensures that the residual will be correctly
469 * noted even if no data transfers occur. Once the data phase is entered,
470 * the residual sgptr and datacnt are loaded from the sgptr and the
471 * datacnt fields. After each S/G element's dataptr and length are
472 * loaded into the hardware, the residual sgptr is advanced. After
473 * each S/G element is expired, its datacnt field is checked to see
474 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
475 * residual sg ptr and the transfer is considered complete. If the
476 * sequencer determines that there is a residual in the tranfer, or
477 * there is non-zero status, it will set the SG_STATUS_VALID flag in
478 * sgptr and dma the scb back into host memory. To sumarize:
481 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
482 * or residual_sgptr does not have SG_LIST_NULL set.
484 * o We are transfering the last segment if residual_datacnt has
485 * the SG_LAST_SEG flag set.
488 * o A residual can only have occurred if a completed scb has the
489 * SG_STATUS_VALID flag set. Inspection of the SCSI status field,
490 * the residual_datacnt, and the residual_sgptr field will tell
493 * o residual_sgptr and sgptr refer to the "next" sg entry
494 * and so may point beyond the last valid sg entry for the
497 #define SG_PTR_MASK 0xFFFFFFF8
498 /*16*/ uint16_t tag; /* Reused by Sequencer. */
499 /*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */
500 /*19*/ uint8_t scsiid; /*
502 * Our Id (bits 0-3) Their ID (bits 4-7)
505 /*21*/ uint8_t task_attribute;
506 /*22*/ uint8_t cdb_len;
507 /*23*/ uint8_t task_management;
508 /*24*/ uint64_t dataptr;
509 /*32*/ uint32_t datacnt; /* Byte 3 is spare. */
510 /*36*/ uint32_t sgptr;
511 /*40*/ uint32_t hscb_busaddr;
512 /*44*/ uint32_t next_hscb_busaddr;
513 /********** Long lun field only downloaded for full 8 byte lun support ********/
514 /*48*/ uint8_t pkt_long_lun[8];
515 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
516 /*56*/ uint8_t spare[8];
519 /************************ Kernel SCB Definitions ******************************/
521 * Some fields of the SCB are OS dependent. Here we collect the
522 * definitions for elements that all OS platforms need to include
523 * in there SCB definition.
527 * Definition of a scatter/gather element as transfered to the controller.
528 * The aic7xxx chips only support a 24bit length. We use the top byte of
529 * the length to store additional address bits and a flag to indicate
530 * that a given segment terminates the transfer. This gives us an
531 * addressable range of 512GB on machines with 64bit PCI or with chips
532 * that can support dual address cycles on 32bit PCI busses.
537 #define AHD_DMA_LAST_SEG 0x80000000
538 #define AHD_SG_HIGH_ADDR_MASK 0x7F000000
539 #define AHD_SG_LEN_MASK 0x00FFFFFF
542 struct ahd_dma64_seg {
552 SLIST_ENTRY(map_node) links;
556 * The current state of this SCB.
559 SCB_FLAG_NONE = 0x00000,
560 SCB_TRANSMISSION_ERROR = 0x00001,/*
561 * We detected a parity or CRC
562 * error that has effected the
563 * payload of the command. This
564 * flag is checked when normal
565 * status is returned to catch
566 * the case of a target not
567 * responding to our attempt
568 * to report the error.
570 SCB_OTHERTCL_TIMEOUT = 0x00002,/*
571 * Another device was active
572 * during the first timeout for
573 * this SCB so we gave ourselves
574 * an additional timeout period
575 * in case it was hogging the
578 SCB_DEVICE_RESET = 0x00004,
580 SCB_CDB32_PTR = 0x00010,
581 SCB_RECOVERY_SCB = 0x00020,
582 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */
583 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */
585 SCB_ACTIVE = 0x00200,
586 SCB_TARGET_IMMEDIATE = 0x00400,
587 SCB_PACKETIZED = 0x00800,
588 SCB_EXPECT_PPR_BUSFREE = 0x01000,
589 SCB_PKT_SENSE = 0x02000,
590 SCB_CMDPHASE_ABORT = 0x04000,
591 SCB_ON_COL_LIST = 0x08000,
592 SCB_SILENT = 0x10000 /*
593 * Be quiet about transmission type
594 * errors. They are expected and we
595 * don't want to upset the user. This
596 * flag is typically used during DV.
601 struct hardware_scb *hscb;
603 SLIST_ENTRY(scb) sle;
605 TAILQ_ENTRY(scb) tqe;
608 SLIST_ENTRY(scb) sle;
610 TAILQ_ENTRY(scb) tqe;
612 #define pending_links links2.le
613 #define collision_links links2.le
616 struct ahd_softc *ahd_softc;
621 struct scb_platform_data *platform_data;
622 struct map_node *hscb_map;
623 struct map_node *sg_map;
624 struct map_node *sense_map;
627 bus_addr_t sg_list_busaddr;
628 bus_addr_t sense_busaddr;
629 u_int sg_count;/* How full ahd_dma_seg is */
630 #define AHD_MAX_LQ_CRC_ERRORS 5
631 u_int crc_retry_count;
634 TAILQ_HEAD(scb_tailq, scb);
635 LIST_HEAD(scb_list, scb);
639 * TAILQ of lists of free SCBs grouped by device
642 struct scb_tailq free_scbs;
645 * Per-device lists of SCBs whose tag ID would collide
646 * with an already active tag on the device.
648 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
651 * SCBs that will not collide with any active device.
653 struct scb_list any_dev_free_scb_list;
656 * Mapping from tag to SCB.
658 struct scb *scbindex[AHD_SCB_MAX];
661 * "Bus" addresses of our data structures.
663 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
664 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
665 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */
666 SLIST_HEAD(, map_node) hscb_maps;
667 SLIST_HEAD(, map_node) sg_maps;
668 SLIST_HEAD(, map_node) sense_maps;
669 int scbs_left; /* unallocated scbs in head map_node */
670 int sgs_left; /* unallocated sgs in head map_node */
671 int sense_left; /* unallocated sense in head map_node */
673 uint16_t maxhscbs; /* Number of SCBs on the card */
674 uint8_t init_level; /*
675 * How far we've initialized
680 /************************ Target Mode Definitions *****************************/
683 * Connection desciptor for select-in requests in target mode.
686 uint8_t scsiid; /* Our ID and the initiator's ID */
687 uint8_t identify; /* Identify message */
688 uint8_t bytes[22]; /*
689 * Bytes contains any additional message
690 * bytes terminated by 0xFF. The remainder
691 * is the cdb to execute.
693 uint8_t cmd_valid; /*
694 * When a command is complete, the firmware
695 * will set cmd_valid to all bits set.
696 * After the host has seen the command,
697 * the bits are cleared. This allows us
698 * to just peek at host memory to determine
699 * if more work is complete. cmd_valid is on
700 * an 8 byte boundary to simplify setting
701 * it on aic7880 hardware which only has
702 * limited direct access to the DMA FIFO.
708 * Number of events we can buffer up if we run out
709 * of immediate notify ccbs.
711 #define AHD_TMODE_EVENT_BUFFER_SIZE 8
712 struct ahd_tmode_event {
713 uint8_t initiator_id;
714 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
715 #define EVENT_TYPE_BUS_RESET 0xFF
720 * Per enabled lun target mode state.
721 * As this state is directly influenced by the host OS'es target mode
722 * environment, we let the OS module define it. Forward declare the
723 * structure here so we can store arrays of them, etc. in OS neutral
726 #ifdef AHD_TARGET_MODE
727 struct ahd_tmode_lstate {
728 struct cam_path *path;
729 struct ccb_hdr_slist accept_tios;
730 struct ccb_hdr_slist immed_notifies;
731 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
736 struct ahd_tmode_lstate;
739 /******************** Transfer Negotiation Datastructures *********************/
740 #define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */
741 #define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
742 #define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */
743 #define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */
744 #define AHD_PERIOD_10MHz 0x19
746 #define AHD_WIDTH_UNKNOWN 0xFF
747 #define AHD_PERIOD_UNKNOWN 0xFF
748 #define AHD_OFFSET_UNKNOWN 0xFF
749 #define AHD_PPR_OPTS_UNKNOWN 0xFF
752 * Transfer Negotiation Information.
754 struct ahd_transinfo {
755 uint8_t protocol_version; /* SCSI Revision level */
756 uint8_t transport_version; /* SPI Revision level */
757 uint8_t width; /* Bus width */
758 uint8_t period; /* Sync rate factor */
759 uint8_t offset; /* Sync offset */
760 uint8_t ppr_options; /* Parallel Protocol Request options */
764 * Per-initiator current, goal and user transfer negotiation information. */
765 struct ahd_initiator_tinfo {
766 struct ahd_transinfo curr;
767 struct ahd_transinfo goal;
768 struct ahd_transinfo user;
772 * Per enabled target ID state.
773 * Pointers to lun target state as well as sync/wide negotiation information
774 * for each initiator<->target mapping. For the initiator role we pretend
775 * that we are the target and the targets are the initiators since the
776 * negotiation is the same regardless of role.
778 struct ahd_tmode_tstate {
779 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS];
780 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS];
783 * Per initiator state bitmasks.
785 uint16_t auto_negotiate;/* Auto Negotiation Required */
786 uint16_t discenable; /* Disconnection allowed */
787 uint16_t tagenable; /* Tagged Queuing allowed */
791 * Points of interest along the negotiated transfer scale.
793 #define AHD_SYNCRATE_160 0x8
794 #define AHD_SYNCRATE_PACED 0x8
795 #define AHD_SYNCRATE_DT 0x9
796 #define AHD_SYNCRATE_ULTRA2 0xa
797 #define AHD_SYNCRATE_ULTRA 0xc
798 #define AHD_SYNCRATE_FAST 0x19
799 #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST
800 #define AHD_SYNCRATE_SYNC 0x32
801 #define AHD_SYNCRATE_MIN 0x60
802 #define AHD_SYNCRATE_ASYNC 0xFF
803 #define AHD_SYNCRATE_MAX AHD_SYNCRATE_160
805 /* Safe and valid period for async negotiations. */
806 #define AHD_ASYNC_XFER_PERIOD 0x44
809 * In RevA, the synctable uses a 120MHz rate for the period
810 * factor 8 and 160MHz for the period factor 7. The 120MHz
811 * rate never made it into the official SCSI spec, so we must
812 * compensate when setting the negotiation table for Rev A
815 #define AHD_SYNCRATE_REVA_120 0x8
816 #define AHD_SYNCRATE_REVA_160 0x7
818 /***************************** Lookup Tables **********************************/
820 * Phase -> name and message out response
821 * to parity errors in each phase table.
823 struct ahd_phase_table_entry {
825 uint8_t mesg_out; /* Message response to parity errors */
829 /************************** Serial EEPROM Format ******************************/
831 struct seeprom_config {
833 * Per SCSI ID Configuration Flags
835 uint16_t device_flags[16]; /* words 0-15 */
836 #define CFXFER 0x003F /* synchronous transfer rate */
837 #define CFXFER_ASYNC 0x3F
838 #define CFQAS 0x0040 /* Negotiate QAS */
839 #define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */
840 #define CFSTART 0x0100 /* send start unit SCSI command */
841 #define CFINCBIOS 0x0200 /* include in BIOS scan */
842 #define CFDISC 0x0400 /* enable disconnection */
843 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
844 #define CFWIDEB 0x1000 /* wide bus device */
845 #define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */
850 uint16_t bios_control; /* word 16 */
851 #define CFSUPREM 0x0001 /* support all removeable drives */
852 #define CFSUPREMB 0x0002 /* support removeable boot drives */
853 #define CFBIOSSTATE 0x000C /* BIOS Action State */
854 #define CFBS_DISABLED 0x00
855 #define CFBS_ENABLED 0x04
856 #define CFBS_DISABLED_SCAN 0x08
857 #define CFENABLEDV 0x0010 /* Perform Domain Validation */
858 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
859 #define CFSPARITY 0x0040 /* SCSI parity */
860 #define CFEXTEND 0x0080 /* extended translation enabled */
861 #define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */
862 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
863 #define CFMSG_VERBOSE 0x0000
864 #define CFMSG_SILENT 0x0200
865 #define CFMSG_DIAG 0x0400
866 #define CFRESETB 0x0800 /* reset SCSI bus at boot */
870 * Host Adapter Control Bits
872 uint16_t adapter_control; /* word 17 */
873 #define CFAUTOTERM 0x0001 /* Perform Auto termination */
874 #define CFSTERM 0x0002 /* SCSI low byte termination */
875 #define CFWSTERM 0x0004 /* SCSI high byte termination */
876 #define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/
877 #define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */
878 #define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */
879 #define CFSTPWLEVEL 0x0040 /* Termination level control */
880 #define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */
881 #define CFTERM_MENU 0x0100 /* BIOS displays termination menu */
882 #define CFCLUSTERENB 0x8000 /* Cluster Enable */
885 * Bus Release Time, Host Adapter ID
887 uint16_t brtime_id; /* word 18 */
888 #define CFSCSIID 0x000f /* host adapter SCSI ID */
890 #define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */
895 uint16_t max_targets; /* word 19 */
896 #define CFMAXTARG 0x00ff /* maximum targets */
897 #define CFBOOTLUN 0x0f00 /* Lun to boot from */
898 #define CFBOOTID 0xf000 /* Target to boot from */
899 uint16_t res_1[10]; /* words 20-29 */
900 uint16_t signature; /* BIOS Signature */
901 #define CFSIGNATURE 0x400
902 uint16_t checksum; /* word 31 */
906 * Vital Product Data used during POST and by the BIOS.
910 #define VPDMASTERBIOS 0x0001
911 #define VPDBOOTHOST 0x0002
912 uint8_t reserved_1[21];
913 uint8_t resource_type;
914 uint8_t resource_len[2];
915 uint8_t resource_data[8];
918 uint8_t vpd_keyword[2];
921 uint8_t device_flags;
922 uint8_t termnation_menus[2];
923 uint8_t fifo_threshold;
925 uint8_t vpd_checksum;
926 uint16_t default_target_flags;
927 uint16_t default_bios_flags;
928 uint16_t default_ctrl_flags;
936 uint8_t reserved_3[4];
939 /****************************** Flexport Logic ********************************/
940 #define FLXADDR_TERMCTL 0x0
941 #define FLX_TERMCTL_ENSECHIGH 0x8
942 #define FLX_TERMCTL_ENSECLOW 0x4
943 #define FLX_TERMCTL_ENPRIHIGH 0x2
944 #define FLX_TERMCTL_ENPRILOW 0x1
945 #define FLXADDR_ROMSTAT_CURSENSECTL 0x1
946 #define FLX_ROMSTAT_SEECFG 0xF0
947 #define FLX_ROMSTAT_EECFG 0x0F
948 #define FLX_ROMSTAT_SEE_93C66 0x00
949 #define FLX_ROMSTAT_SEE_NONE 0xF0
950 #define FLX_ROMSTAT_EE_512x8 0x0
951 #define FLX_ROMSTAT_EE_1MBx8 0x1
952 #define FLX_ROMSTAT_EE_2MBx8 0x2
953 #define FLX_ROMSTAT_EE_4MBx8 0x3
954 #define FLX_ROMSTAT_EE_16MBx8 0x4
955 #define CURSENSE_ENB 0x1
956 #define FLXADDR_FLEXSTAT 0x2
957 #define FLX_FSTAT_BUSY 0x1
958 #define FLXADDR_CURRENT_STAT 0x4
959 #define FLX_CSTAT_SEC_HIGH 0xC0
960 #define FLX_CSTAT_SEC_LOW 0x30
961 #define FLX_CSTAT_PRI_HIGH 0x0C
962 #define FLX_CSTAT_PRI_LOW 0x03
963 #define FLX_CSTAT_MASK 0x03
964 #define FLX_CSTAT_SHIFT 2
965 #define FLX_CSTAT_OKAY 0x0
966 #define FLX_CSTAT_OVER 0x1
967 #define FLX_CSTAT_UNDER 0x2
968 #define FLX_CSTAT_INVALID 0x3
970 int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
971 u_int start_addr, u_int count, int bstream);
973 int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
974 u_int start_addr, u_int count);
975 int ahd_wait_seeprom(struct ahd_softc *ahd);
976 int ahd_verify_vpd_cksum(struct vpd_config *vpd);
977 int ahd_verify_cksum(struct seeprom_config *sc);
978 int ahd_acquire_seeprom(struct ahd_softc *ahd);
979 void ahd_release_seeprom(struct ahd_softc *ahd);
981 /**************************** Message Buffer *********************************/
983 MSG_FLAG_NONE = 0x00,
984 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01,
985 MSG_FLAG_IU_REQ_CHANGED = 0x02,
986 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04,
987 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08,
988 MSG_FLAG_PACKETIZED = 0x10
992 MSG_TYPE_NONE = 0x00,
993 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
994 MSG_TYPE_INITIATOR_MSGIN = 0x02,
995 MSG_TYPE_TARGET_MSGOUT = 0x03,
996 MSG_TYPE_TARGET_MSGIN = 0x04
1001 MSGLOOP_MSGCOMPLETE,
1005 /*********************** Software Configuration Structure *********************/
1006 struct ahd_suspend_channel_state {
1016 struct ahd_suspend_state {
1017 struct ahd_suspend_channel_state channel[2];
1020 uint8_t dspcistatus;
1022 uint8_t crccontrol1;
1024 /* Host and sequencer SCB counts */
1026 uint8_t *scratch_ram;
1030 typedef void (*ahd_bus_intr_t)(struct ahd_softc *);
1041 #define AHD_MK_MSK(x) (0x01 << (x))
1042 #define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0)
1043 #define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1)
1044 #define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN)
1045 #define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI)
1046 #define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG)
1047 #define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN)
1048 #define AHD_MODE_ANY_MSK (~0)
1050 typedef uint8_t ahd_mode_state;
1052 typedef void ahd_callback_t (void *);
1055 bus_space_tag_t tags[2];
1056 bus_space_handle_t bshs[2];
1058 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
1060 struct scb_data scb_data;
1062 struct hardware_scb *next_queued_hscb;
1065 * SCBs that have been sent to the controller
1067 LIST_HEAD(, scb) pending_scbs;
1070 * Current register window mode information.
1076 * Saved register window mode information
1077 * used for restore on next unpause.
1079 ahd_mode saved_dst_mode;
1080 ahd_mode saved_src_mode;
1083 * Platform specific data.
1085 struct ahd_platform_data *platform_data;
1088 * Platform specific device information.
1090 ahd_dev_softc_t dev_softc;
1093 * Bus specific device information.
1095 ahd_bus_intr_t bus_intr;
1098 * Target mode related state kept on a per enabled lun basis.
1099 * Targets that are not enabled will have null entries.
1100 * As an initiator, we keep one target entry for our initiator
1101 * ID to store our sync/wide transfer settings.
1103 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS];
1106 * The black hole device responsible for handling requests for
1107 * disabled luns on enabled targets.
1109 struct ahd_tmode_lstate *black_hole;
1112 * Device instance currently on the bus awaiting a continue TIO
1113 * for a command that was not given the disconnect priveledge.
1115 struct ahd_tmode_lstate *pending_device;
1118 * Timer handles for timer driven callbacks.
1120 ahd_timer_t reset_timer;
1121 ahd_timer_t stat_timer;
1126 #define AHD_STAT_UPDATE_US 250000 /* 250ms */
1127 #define AHD_STAT_BUCKETS 4
1128 u_int cmdcmplt_bucket;
1129 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS];
1130 uint32_t cmdcmplt_total;
1133 * Card characteristics
1136 ahd_feature features;
1139 struct seeprom_config *seep_config;
1141 /* Values to store in the SEQCTL register for pause and unpause */
1145 /* Command Queues */
1146 uint16_t qoutfifonext;
1147 uint16_t qoutfifonext_valid_tag;
1148 uint16_t qinfifonext;
1149 uint16_t qinfifo[AHD_SCB_MAX];
1152 /* Critical Section Data */
1153 struct cs *critical_sections;
1154 u_int num_critical_sections;
1156 /* Buffer for handling packetized bitbucket. */
1157 uint8_t *overrun_buf;
1159 /* Links for chaining softcs */
1160 TAILQ_ENTRY(ahd_softc) links;
1162 /* Channel Names ('A', 'B', etc.) */
1165 /* Initiator Bus ID */
1169 * Target incoming command FIFO.
1171 struct target_cmd *targetcmds;
1172 uint8_t tqinfifonext;
1175 * Cached verson of the hs_mailbox so we can avoid
1176 * pausing the sequencer during mailbox updates.
1181 * Incoming and outgoing message handling.
1183 uint8_t send_msg_perror;
1184 ahd_msg_flags msg_flags;
1185 ahd_msg_type msg_type;
1186 uint8_t msgout_buf[12];/* Message we are sending */
1187 uint8_t msgin_buf[12];/* Message we are receiving */
1188 u_int msgout_len; /* Length of message to send */
1189 u_int msgout_index; /* Current index in msgout */
1190 u_int msgin_index; /* Current index in msgin */
1193 * Mapping information for data structures shared
1194 * between the sequencer and kernel.
1196 bus_dma_tag_t parent_dmat;
1197 bus_dma_tag_t shared_data_dmat;
1198 bus_dmamap_t shared_data_dmamap;
1199 bus_addr_t shared_data_busaddr;
1201 /* Information saved through suspend/resume cycles */
1202 struct ahd_suspend_state suspend_state;
1204 /* Number of enabled target mode device on this card */
1207 /* Initialization level of this data structure */
1210 /* PCI cacheline size. */
1211 u_int pci_cachesize;
1213 /* IO Cell Parameters */
1214 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
1217 uint16_t *saved_stack;
1219 /* Per-Unit descriptive information */
1220 const char *description;
1221 const char *bus_description;
1225 /* Selection Timer settings */
1229 * Interrupt coalescing settings.
1231 #define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/
1232 #define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10
1233 #define AHD_INT_COALESCING_MAXCMDS_MAX 127
1234 #define AHD_INT_COALESCING_MINCMDS_DEFAULT 5
1235 #define AHD_INT_COALESCING_MINCMDS_MAX 127
1236 #define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000
1237 #define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000
1238 u_int int_coalescing_timer;
1239 u_int int_coalescing_maxcmds;
1240 u_int int_coalescing_mincmds;
1241 u_int int_coalescing_threshold;
1242 u_int int_coalescing_stop_threshold;
1244 uint16_t user_discenable;/* Disconnection allowed */
1245 uint16_t user_tagenable;/* Tagged Queuing allowed */
1248 TAILQ_HEAD(ahd_softc_tailq, ahd_softc);
1249 extern struct ahd_softc_tailq ahd_tailq;
1251 /*************************** IO Cell Configuration ****************************/
1252 #define AHD_PRECOMP_SLEW_INDEX \
1253 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0)
1255 #define AHD_AMPLITUDE_INDEX \
1256 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0)
1258 #define AHD_SET_SLEWRATE(ahd, new_slew) \
1260 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \
1261 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1262 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \
1265 #define AHD_SET_PRECOMP(ahd, new_pcomp) \
1267 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \
1268 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1269 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \
1272 #define AHD_SET_AMPLITUDE(ahd, new_amp) \
1274 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \
1275 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \
1276 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \
1279 /************************ Active Device Information ***************************/
1286 struct ahd_devinfo {
1289 uint16_t target_mask;
1294 * Only guaranteed to be correct if not
1295 * in the busfree state.
1299 /****************************** PCI Structures ********************************/
1300 #define AHD_PCI_IOADDR0 PCIR_MAPS /* I/O BAR*/
1301 #define AHD_PCI_MEMADDR (PCIR_MAPS + 4) /* Memory BAR */
1302 #define AHD_PCI_IOADDR1 (PCIR_MAPS + 12)/* Second I/O BAR */
1304 typedef int (ahd_device_setup_t)(struct ahd_softc *);
1306 struct ahd_pci_identity {
1310 ahd_device_setup_t *setup;
1312 extern struct ahd_pci_identity ahd_pci_ident_table [];
1313 extern const u_int ahd_num_pci_devs;
1315 /***************************** VL/EISA Declarations ***************************/
1316 struct aic7770_identity {
1320 ahd_device_setup_t *setup;
1322 extern struct aic7770_identity aic7770_ident_table [];
1323 extern const int ahd_num_aic7770_devs;
1325 #define AHD_EISA_SLOT_OFFSET 0xc00
1326 #define AHD_EISA_IOSIZE 0x100
1328 /*************************** Function Declarations ****************************/
1329 /******************************************************************************/
1330 void ahd_reset_cmds_pending(struct ahd_softc *ahd);
1331 u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl);
1332 void ahd_busy_tcl(struct ahd_softc *ahd,
1333 u_int tcl, u_int busyid);
1334 static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl);
1335 static __inline void
1336 ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl)
1338 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL);
1341 /***************************** PCI Front End *********************************/
1342 struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t);
1343 int ahd_pci_config(struct ahd_softc *,
1344 struct ahd_pci_identity *);
1345 int ahd_pci_test_register_access(struct ahd_softc *);
1347 /************************** SCB and SCB queue management **********************/
1348 int ahd_probe_scbs(struct ahd_softc *);
1349 void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd,
1351 int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb,
1352 int target, char channel, int lun,
1353 u_int tag, role_t role);
1355 /****************************** Initialization ********************************/
1356 struct ahd_softc *ahd_alloc(void *platform_arg, char *name);
1357 int ahd_softc_init(struct ahd_softc *);
1358 void ahd_controller_info(struct ahd_softc *ahd, char *buf);
1359 int ahd_init(struct ahd_softc *ahd);
1360 int ahd_default_config(struct ahd_softc *ahd);
1361 int ahd_parse_vpddata(struct ahd_softc *ahd,
1362 struct vpd_config *vpd);
1363 int ahd_parse_cfgdata(struct ahd_softc *ahd,
1364 struct seeprom_config *sc);
1365 void ahd_intr_enable(struct ahd_softc *ahd, int enable);
1366 void ahd_update_coalescing_values(struct ahd_softc *ahd,
1370 void ahd_enable_coalescing(struct ahd_softc *ahd,
1372 void ahd_pause_and_flushwork(struct ahd_softc *ahd);
1373 int ahd_suspend(struct ahd_softc *ahd);
1374 int ahd_resume(struct ahd_softc *ahd);
1375 void ahd_softc_insert(struct ahd_softc *);
1376 struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd);
1377 void ahd_set_unit(struct ahd_softc *, int);
1378 void ahd_set_name(struct ahd_softc *, char *);
1379 struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx);
1380 void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb);
1381 void ahd_alloc_scbs(struct ahd_softc *ahd);
1382 void ahd_free(struct ahd_softc *ahd);
1383 int ahd_reset(struct ahd_softc *ahd, int reinit);
1384 void ahd_shutdown(void *arg);
1385 int ahd_write_flexport(struct ahd_softc *ahd,
1386 u_int addr, u_int value);
1387 int ahd_read_flexport(struct ahd_softc *ahd, u_int addr,
1389 int ahd_wait_flexport(struct ahd_softc *ahd);
1391 /*************************** Interrupt Services *******************************/
1392 void ahd_pci_intr(struct ahd_softc *ahd);
1393 void ahd_clear_intstat(struct ahd_softc *ahd);
1394 void ahd_flush_qoutfifo(struct ahd_softc *ahd);
1395 void ahd_run_qoutfifo(struct ahd_softc *ahd);
1396 #ifdef AHD_TARGET_MODE
1397 void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused);
1399 void ahd_handle_hwerrint(struct ahd_softc *ahd);
1400 void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat);
1401 void ahd_handle_scsiint(struct ahd_softc *ahd,
1403 void ahd_clear_critical_section(struct ahd_softc *ahd);
1405 /***************************** Error Recovery *********************************/
1411 } ahd_search_action;
1412 int ahd_search_qinfifo(struct ahd_softc *ahd, int target,
1413 char channel, int lun, u_int tag,
1414 role_t role, uint32_t status,
1415 ahd_search_action action);
1416 int ahd_search_disc_list(struct ahd_softc *ahd, int target,
1417 char channel, int lun, u_int tag,
1418 int stop_on_first, int remove,
1420 void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb);
1421 int ahd_reset_channel(struct ahd_softc *ahd, char channel,
1422 int initiate_reset);
1423 int ahd_abort_scbs(struct ahd_softc *ahd, int target,
1424 char channel, int lun, u_int tag,
1425 role_t role, uint32_t status);
1426 void ahd_restart(struct ahd_softc *ahd);
1427 void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo);
1428 void ahd_handle_scb_status(struct ahd_softc *ahd,
1430 void ahd_handle_scsi_status(struct ahd_softc *ahd,
1432 void ahd_calc_residual(struct ahd_softc *ahd,
1434 /*************************** Utility Functions ********************************/
1435 struct ahd_phase_table_entry*
1436 ahd_lookup_phase_entry(int phase);
1437 void ahd_compile_devinfo(struct ahd_devinfo *devinfo,
1438 u_int our_id, u_int target,
1439 u_int lun, char channel,
1441 /************************** Transfer Negotiation ******************************/
1442 void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
1443 u_int *ppr_options, u_int maxsync);
1444 void ahd_validate_offset(struct ahd_softc *ahd,
1445 struct ahd_initiator_tinfo *tinfo,
1446 u_int period, u_int *offset,
1447 int wide, role_t role);
1448 void ahd_validate_width(struct ahd_softc *ahd,
1449 struct ahd_initiator_tinfo *tinfo,
1453 * Negotiation types. These are used to qualify if we should renegotiate
1454 * even if our goal and current transport parameters are identical.
1457 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1458 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1459 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */
1461 int ahd_update_neg_request(struct ahd_softc*,
1462 struct ahd_devinfo*,
1463 struct ahd_tmode_tstate*,
1464 struct ahd_initiator_tinfo*,
1466 void ahd_set_width(struct ahd_softc *ahd,
1467 struct ahd_devinfo *devinfo,
1468 u_int width, u_int type, int paused);
1469 void ahd_set_syncrate(struct ahd_softc *ahd,
1470 struct ahd_devinfo *devinfo,
1471 u_int period, u_int offset,
1473 u_int type, int paused);
1480 void ahd_set_tags(struct ahd_softc *ahd,
1481 struct ahd_devinfo *devinfo,
1484 /**************************** Target Mode *************************************/
1485 #ifdef AHD_TARGET_MODE
1486 void ahd_send_lstate_events(struct ahd_softc *,
1487 struct ahd_tmode_lstate *);
1488 void ahd_handle_en_lun(struct ahd_softc *ahd,
1489 struct cam_sim *sim, union ccb *ccb);
1490 cam_status ahd_find_tmode_devs(struct ahd_softc *ahd,
1491 struct cam_sim *sim, union ccb *ccb,
1492 struct ahd_tmode_tstate **tstate,
1493 struct ahd_tmode_lstate **lstate,
1494 int notfound_failure);
1495 #ifndef AHD_TMODE_ENABLE
1496 #define AHD_TMODE_ENABLE 0
1499 /******************************* Debug ***************************************/
1501 extern uint32_t ahd_debug;
1502 #define AHD_SHOW_MISC 0x00001
1503 #define AHD_SHOW_SENSE 0x00002
1504 #define AHD_SHOW_RECOVERY 0x00004
1505 #define AHD_DUMP_SEEPROM 0x00008
1506 #define AHD_SHOW_TERMCTL 0x00010
1507 #define AHD_SHOW_MEMORY 0x00020
1508 #define AHD_SHOW_MESSAGES 0x00040
1509 #define AHD_SHOW_MODEPTR 0x00080
1510 #define AHD_SHOW_SELTO 0x00100
1511 #define AHD_SHOW_FIFOS 0x00200
1512 #define AHD_SHOW_QFULL 0x00400
1513 #define AHD_SHOW_DV 0x00800
1514 #define AHD_SHOW_MASKED_ERRORS 0x01000
1515 #define AHD_SHOW_QUEUE 0x02000
1516 #define AHD_SHOW_TQIN 0x04000
1517 #define AHD_SHOW_SG 0x08000
1518 #define AHD_SHOW_INT_COALESCING 0x10000
1519 #define AHD_DEBUG_SEQUENCER 0x20000
1521 void ahd_print_scb(struct scb *scb);
1522 void ahd_print_devinfo(struct ahd_softc *ahd,
1523 struct ahd_devinfo *devinfo);
1524 void ahd_dump_sglist(struct scb *scb);
1525 void ahd_dump_all_cards_state(void);
1526 void ahd_dump_card_state(struct ahd_softc *ahd);
1527 int ahd_print_register(ahd_reg_parse_entry_t *table,
1534 void ahd_dump_scbs(struct ahd_softc *ahd);
1535 #endif /* _AIC79XX_H_ */