sys/dev/disk/aic7xxx/aic7xxx_pci.c

   1 /*
   2  * Product specific probe and attach routines for:
   3  *      3940, 2940, aic7895, aic7890, aic7880,
   4  *      aic7870, aic7860 and aic7850 SCSI controllers
   5  *
   6  * Copyright (c) 1994-2001 Justin T. Gibbs.
   7  * Copyright (c) 2000-2001 Adaptec Inc.
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions, and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17  *    substantially similar to the "NO WARRANTY" disclaimer below
  18  *    ("Disclaimer") and any redistribution must be conditioned upon
  19  *    including a substantially similar Disclaimer requirement for further
  20  *    binary redistribution.
  21  * 3. Neither the names of the above-listed copyright holders nor the names
  22  *    of any contributors may be used to endorse or promote products derived
  23  *    from this software without specific prior written permission.
  24  *
  25  * Alternatively, this software may be distributed under the terms of the
  26  * GNU General Public License ("GPL") version 2 as published by the Free
  27  * Software Foundation.
  28  *
  29  * NO WARRANTY
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  34  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  35  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  36  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  37  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  38  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  39  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  40  * POSSIBILITY OF SUCH DAMAGES.
  41  *
  42  * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#69 $
  43  *
  44  * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.2.2.17 2003/06/10 03:26:09 gibbs Exp $
  45  * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx_pci.c,v 1.5 2006/09/05 16:50:50 dillon Exp $
  46  */
  47
  48 #ifdef __linux__
  49 #include "aic7xxx_osm.h"
  50 #include "aic7xxx_inline.h"
  51 #include "aic7xxx_93cx6.h"
  52 #else
  53 #include "aic7xxx_osm.h"
  54 #include "aic7xxx_inline.h"
  55 #include "aic7xxx_93cx6.h"
  56 #endif
  57
  58 #ifdef AHC_PCI_CONFIG
  59
  60 #define AHC_PCI_IOADDR  PCIR_MAPS       /* I/O Address */
  61 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
  62
  63 static __inline uint64_t
  64 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
  65 {
  66         uint64_t id;
  67
  68         id = subvendor
  69            | (subdevice << 16)
  70            | ((uint64_t)vendor << 32)
  71            | ((uint64_t)device << 48);
  72
  73         return (id);
  74 }
  75
  76 #define ID_ALL_MASK                     0xFFFFFFFFFFFFFFFFull
  77 #define ID_DEV_VENDOR_MASK              0xFFFFFFFF00000000ull
  78 #define ID_9005_GENERIC_MASK            0xFFF0FFFF00000000ull
  79 #define ID_9005_SISL_MASK               0x000FFFFF00000000ull
  80 #define ID_9005_SISL_ID                 0x0005900500000000ull
  81 #define ID_AIC7850                      0x5078900400000000ull
  82 #define ID_AHA_2902_04_10_15_20C_30C    0x5078900478509004ull
  83 #define ID_AIC7855                      0x5578900400000000ull
  84 #define ID_AIC7859                      0x3860900400000000ull
  85 #define ID_AHA_2930CU                   0x3860900438699004ull
  86 #define ID_AIC7860                      0x6078900400000000ull
  87 #define ID_AIC7860C                     0x6078900478609004ull
  88 #define ID_AHA_1480A                    0x6075900400000000ull
  89 #define ID_AHA_2940AU_0                 0x6178900400000000ull
  90 #define ID_AHA_2940AU_1                 0x6178900478619004ull
  91 #define ID_AHA_2940AU_CN                0x2178900478219004ull
  92 #define ID_AHA_2930C_VAR                0x6038900438689004ull
  93
  94 #define ID_AIC7870                      0x7078900400000000ull
  95 #define ID_AHA_2940                     0x7178900400000000ull
  96 #define ID_AHA_3940                     0x7278900400000000ull
  97 #define ID_AHA_398X                     0x7378900400000000ull
  98 #define ID_AHA_2944                     0x7478900400000000ull
  99 #define ID_AHA_3944                     0x7578900400000000ull
 100 #define ID_AHA_4944                     0x7678900400000000ull
 101
 102 #define ID_AIC7880                      0x8078900400000000ull
 103 #define ID_AIC7880_B                    0x8078900478809004ull
 104 #define ID_AHA_2940U                    0x8178900400000000ull
 105 #define ID_AHA_3940U                    0x8278900400000000ull
 106 #define ID_AHA_2944U                    0x8478900400000000ull
 107 #define ID_AHA_3944U                    0x8578900400000000ull
 108 #define ID_AHA_398XU                    0x8378900400000000ull
 109 #define ID_AHA_4944U                    0x8678900400000000ull
 110 #define ID_AHA_2940UB                   0x8178900478819004ull
 111 #define ID_AHA_2930U                    0x8878900478889004ull
 112 #define ID_AHA_2940U_PRO                0x8778900478879004ull
 113 #define ID_AHA_2940U_CN                 0x0078900478009004ull
 114
 115 #define ID_AIC7895                      0x7895900478959004ull
 116 #define ID_AIC7895_ARO                  0x7890900478939004ull
 117 #define ID_AIC7895_ARO_MASK             0xFFF0FFFFFFFFFFFFull
 118 #define ID_AHA_2940U_DUAL               0x7895900478919004ull
 119 #define ID_AHA_3940AU                   0x7895900478929004ull
 120 #define ID_AHA_3944AU                   0x7895900478949004ull
 121
 122 #define ID_AIC7890                      0x001F9005000F9005ull
 123 #define ID_AIC7890_ARO                  0x00139005000F9005ull
 124 #define ID_AAA_131U2                    0x0013900500039005ull
 125 #define ID_AHA_2930U2                   0x0011900501819005ull
 126 #define ID_AHA_2940U2B                  0x00109005A1009005ull
 127 #define ID_AHA_2940U2_OEM               0x0010900521809005ull
 128 #define ID_AHA_2940U2                   0x00109005A1809005ull
 129 #define ID_AHA_2950U2B                  0x00109005E1009005ull
 130
 131 #define ID_AIC7892                      0x008F9005FFFF9005ull
 132 #define ID_AIC7892_ARO                  0x00839005FFFF9005ull
 133 #define ID_AHA_29160                    0x00809005E2A09005ull
 134 #define ID_AHA_29160_CPQ                0x00809005E2A00E11ull
 135 #define ID_AHA_29160N                   0x0080900562A09005ull
 136 #define ID_AHA_29160C                   0x0080900562209005ull
 137 #define ID_AHA_29160B                   0x00809005E2209005ull
 138 #define ID_AHA_19160B                   0x0081900562A19005ull
 139
 140 #define ID_AIC7896                      0x005F9005FFFF9005ull
 141 #define ID_AIC7896_ARO                  0x00539005FFFF9005ull
 142 #define ID_AHA_3950U2B_0                0x00509005FFFF9005ull
 143 #define ID_AHA_3950U2B_1                0x00509005F5009005ull
 144 #define ID_AHA_3950U2D_0                0x00519005FFFF9005ull
 145 #define ID_AHA_3950U2D_1                0x00519005B5009005ull
 146
 147 #define ID_AIC7899                      0x00CF9005FFFF9005ull
 148 #define ID_AIC7899_ARO                  0x00C39005FFFF9005ull
 149 #define ID_AHA_3960D                    0x00C09005F6209005ull
 150 #define ID_AHA_3960D_CPQ                0x00C09005F6200E11ull
 151
 152 #define ID_AIC7810                      0x1078900400000000ull
 153 #define ID_AIC7815                      0x7815900400000000ull
 154
 155 #define DEVID_9005_TYPE(id) ((id) & 0xF)
 156 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
 157 #define         DEVID_9005_TYPE_AAA             0x3     /* RAID Card */
 158 #define         DEVID_9005_TYPE_SISL            0x5     /* Container ROMB */
 159 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
 160
 161 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
 162 #define         DEVID_9005_MAXRATE_U160         0x0
 163 #define         DEVID_9005_MAXRATE_ULTRA2       0x1
 164 #define         DEVID_9005_MAXRATE_ULTRA        0x2
 165 #define         DEVID_9005_MAXRATE_FAST         0x3
 166
 167 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
 168
 169 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
 170 #define         DEVID_9005_CLASS_SPI            0x0     /* Parallel SCSI */
 171
 172 #define SUBID_9005_TYPE(id) ((id) & 0xF)
 173 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
 174 #define         SUBID_9005_TYPE_CARD            0x0     /* Standard Card */
 175 #define         SUBID_9005_TYPE_LCCARD          0x1     /* Low Cost Card */
 176 #define         SUBID_9005_TYPE_RAID            0x3     /* Combined with Raid */
 177
 178 #define SUBID_9005_TYPE_KNOWN(id)                       \
 179           ((((id) & 0xF) == SUBID_9005_TYPE_MB)         \
 180         || (((id) & 0xF) == SUBID_9005_TYPE_CARD)       \
 181         || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD)     \
 182         || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
 183
 184 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
 185 #define         SUBID_9005_MAXRATE_ULTRA2       0x0
 186 #define         SUBID_9005_MAXRATE_ULTRA        0x1
 187 #define         SUBID_9005_MAXRATE_U160         0x2
 188 #define         SUBID_9005_MAXRATE_RESERVED     0x3
 189
 190 #define SUBID_9005_SEEPTYPE(id)                                         \
 191         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 192          ? ((id) & 0xC0) >> 6                                           \
 193          : ((id) & 0x300) >> 8)
 194 #define         SUBID_9005_SEEPTYPE_NONE        0x0
 195 #define         SUBID_9005_SEEPTYPE_1K          0x1
 196 #define         SUBID_9005_SEEPTYPE_2K_4K       0x2
 197 #define         SUBID_9005_SEEPTYPE_RESERVED    0x3
 198 #define SUBID_9005_AUTOTERM(id)                                         \
 199         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 200          ? (((id) & 0x400) >> 10) == 0                                  \
 201          : (((id) & 0x40) >> 6) == 0)
 202
 203 #define SUBID_9005_NUMCHAN(id)                                          \
 204         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 205          ? ((id) & 0x300) >> 8                                          \
 206          : ((id) & 0xC00) >> 10)
 207
 208 #define SUBID_9005_LEGACYCONN(id)                                       \
 209         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 210          ? 0                                                            \
 211          : ((id) & 0x80) >> 7)
 212
 213 #define SUBID_9005_MFUNCENB(id)                                         \
 214         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 215          ? ((id) & 0x800) >> 11                                         \
 216          : ((id) & 0x1000) >> 12)
 217 /*
 218  * Informational only. Should use chip register to be
 219  * certain, but may be use in identification strings.
 220  */
 221 #define SUBID_9005_CARD_SCSIWIDTH_MASK  0x2000
 222 #define SUBID_9005_CARD_PCIWIDTH_MASK   0x4000
 223 #define SUBID_9005_CARD_SEDIFF_MASK     0x8000
 224
 225 static ahc_device_setup_t ahc_aic785X_setup;
 226 static ahc_device_setup_t ahc_aic7860_setup;
 227 static ahc_device_setup_t ahc_apa1480_setup;
 228 static ahc_device_setup_t ahc_aic7870_setup;
 229 static ahc_device_setup_t ahc_aha394X_setup;
 230 static ahc_device_setup_t ahc_aha494X_setup;
 231 static ahc_device_setup_t ahc_aha398X_setup;
 232 static ahc_device_setup_t ahc_aic7880_setup;
 233 static ahc_device_setup_t ahc_aha2940Pro_setup;
 234 static ahc_device_setup_t ahc_aha394XU_setup;
 235 static ahc_device_setup_t ahc_aha398XU_setup;
 236 static ahc_device_setup_t ahc_aic7890_setup;
 237 static ahc_device_setup_t ahc_aic7892_setup;
 238 static ahc_device_setup_t ahc_aic7895_setup;
 239 static ahc_device_setup_t ahc_aic7896_setup;
 240 static ahc_device_setup_t ahc_aic7899_setup;
 241 static ahc_device_setup_t ahc_aha29160C_setup;
 242 static ahc_device_setup_t ahc_raid_setup;
 243 static ahc_device_setup_t ahc_aha394XX_setup;
 244 static ahc_device_setup_t ahc_aha494XX_setup;
 245 static ahc_device_setup_t ahc_aha398XX_setup;
 246
 247 struct ahc_pci_identity ahc_pci_ident_table [] =
 248 {
 249         /* aic7850 based controllers */
 250         {
 251                 ID_AHA_2902_04_10_15_20C_30C,
 252                 ID_ALL_MASK,
 253                 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
 254                 ahc_aic785X_setup
 255         },
 256         /* aic7860 based controllers */
 257         {
 258                 ID_AHA_2930CU,
 259                 ID_ALL_MASK,
 260                 "Adaptec 2930CU SCSI adapter",
 261                 ahc_aic7860_setup
 262         },
 263         {
 264                 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
 265                 ID_DEV_VENDOR_MASK,
 266                 "Adaptec 1480A Ultra SCSI adapter",
 267                 ahc_apa1480_setup
 268         },
 269         {
 270                 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
 271                 ID_DEV_VENDOR_MASK,
 272                 "Adaptec 2940A Ultra SCSI adapter",
 273                 ahc_aic7860_setup
 274         },
 275         {
 276                 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
 277                 ID_DEV_VENDOR_MASK,
 278                 "Adaptec 2940A/CN Ultra SCSI adapter",
 279                 ahc_aic7860_setup
 280         },
 281         {
 282                 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
 283                 ID_DEV_VENDOR_MASK,
 284                 "Adaptec 2930C Ultra SCSI adapter (VAR)",
 285                 ahc_aic7860_setup
 286         },
 287         /* aic7870 based controllers */
 288         {
 289                 ID_AHA_2940,
 290                 ID_ALL_MASK,
 291                 "Adaptec 2940 SCSI adapter",
 292                 ahc_aic7870_setup
 293         },
 294         {
 295                 ID_AHA_3940,
 296                 ID_ALL_MASK,
 297                 "Adaptec 3940 SCSI adapter",
 298                 ahc_aha394X_setup
 299         },
 300         {
 301                 ID_AHA_398X,
 302                 ID_ALL_MASK,
 303                 "Adaptec 398X SCSI RAID adapter",
 304                 ahc_aha398X_setup
 305         },
 306         {
 307                 ID_AHA_2944,
 308                 ID_ALL_MASK,
 309                 "Adaptec 2944 SCSI adapter",
 310                 ahc_aic7870_setup
 311         },
 312         {
 313                 ID_AHA_3944,
 314                 ID_ALL_MASK,
 315                 "Adaptec 3944 SCSI adapter",
 316                 ahc_aha394X_setup
 317         },
 318         {
 319                 ID_AHA_4944,
 320                 ID_ALL_MASK,
 321                 "Adaptec 4944 SCSI adapter",
 322                 ahc_aha494X_setup
 323         },
 324         /* aic7880 based controllers */
 325         {
 326                 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
 327                 ID_DEV_VENDOR_MASK,
 328                 "Adaptec 2940 Ultra SCSI adapter",
 329                 ahc_aic7880_setup
 330         },
 331         {
 332                 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
 333                 ID_DEV_VENDOR_MASK,
 334                 "Adaptec 3940 Ultra SCSI adapter",
 335                 ahc_aha394XU_setup
 336         },
 337         {
 338                 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
 339                 ID_DEV_VENDOR_MASK,
 340                 "Adaptec 2944 Ultra SCSI adapter",
 341                 ahc_aic7880_setup
 342         },
 343         {
 344                 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
 345                 ID_DEV_VENDOR_MASK,
 346                 "Adaptec 3944 Ultra SCSI adapter",
 347                 ahc_aha394XU_setup
 348         },
 349         {
 350                 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
 351                 ID_DEV_VENDOR_MASK,
 352                 "Adaptec 398X Ultra SCSI RAID adapter",
 353                 ahc_aha398XU_setup
 354         },
 355         {
 356                 /*
 357                  * XXX Don't know the slot numbers
 358                  * so we can't identify channels
 359                  */
 360                 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
 361                 ID_DEV_VENDOR_MASK,
 362                 "Adaptec 4944 Ultra SCSI adapter",
 363                 ahc_aic7880_setup
 364         },
 365         {
 366                 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
 367                 ID_DEV_VENDOR_MASK,
 368                 "Adaptec 2930 Ultra SCSI adapter",
 369                 ahc_aic7880_setup
 370         },
 371         {
 372                 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
 373                 ID_DEV_VENDOR_MASK,
 374                 "Adaptec 2940 Pro Ultra SCSI adapter",
 375                 ahc_aha2940Pro_setup
 376         },
 377         {
 378                 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
 379                 ID_DEV_VENDOR_MASK,
 380                 "Adaptec 2940/CN Ultra SCSI adapter",
 381                 ahc_aic7880_setup
 382         },
 383         /* Ignore all SISL (AAC on MB) based controllers. */
 384         {
 385                 ID_9005_SISL_ID,
 386                 ID_9005_SISL_MASK,
 387                 NULL,
 388                 NULL
 389         },
 390         /* aic7890 based controllers */
 391         {
 392                 ID_AHA_2930U2,
 393                 ID_ALL_MASK,
 394                 "Adaptec 2930 Ultra2 SCSI adapter",
 395                 ahc_aic7890_setup
 396         },
 397         {
 398                 ID_AHA_2940U2B,
 399                 ID_ALL_MASK,
 400                 "Adaptec 2940B Ultra2 SCSI adapter",
 401                 ahc_aic7890_setup
 402         },
 403         {
 404                 ID_AHA_2940U2_OEM,
 405                 ID_ALL_MASK,
 406                 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
 407                 ahc_aic7890_setup
 408         },
 409         {
 410                 ID_AHA_2940U2,
 411                 ID_ALL_MASK,
 412                 "Adaptec 2940 Ultra2 SCSI adapter",
 413                 ahc_aic7890_setup
 414         },
 415         {
 416                 ID_AHA_2950U2B,
 417                 ID_ALL_MASK,
 418                 "Adaptec 2950 Ultra2 SCSI adapter",
 419                 ahc_aic7890_setup
 420         },
 421         {
 422                 ID_AIC7890_ARO,
 423                 ID_ALL_MASK,
 424                 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
 425                 ahc_aic7890_setup
 426         },
 427         {
 428                 ID_AAA_131U2,
 429                 ID_ALL_MASK,
 430                 "Adaptec AAA-131 Ultra2 RAID adapter",
 431                 ahc_aic7890_setup
 432         },
 433         /* aic7892 based controllers */
 434         {
 435                 ID_AHA_29160,
 436                 ID_ALL_MASK,
 437                 "Adaptec 29160 Ultra160 SCSI adapter",
 438                 ahc_aic7892_setup
 439         },
 440         {
 441                 ID_AHA_29160_CPQ,
 442                 ID_ALL_MASK,
 443                 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
 444                 ahc_aic7892_setup
 445         },
 446         {
 447                 ID_AHA_29160N,
 448                 ID_ALL_MASK,
 449                 "Adaptec 29160N Ultra160 SCSI adapter",
 450                 ahc_aic7892_setup
 451         },
 452         {
 453                 ID_AHA_29160C,
 454                 ID_ALL_MASK,
 455                 "Adaptec 29160C Ultra160 SCSI adapter",
 456                 ahc_aha29160C_setup
 457         },
 458         {
 459                 ID_AHA_29160B,
 460                 ID_ALL_MASK,
 461                 "Adaptec 29160B Ultra160 SCSI adapter",
 462                 ahc_aic7892_setup
 463         },
 464         {
 465                 ID_AHA_19160B,
 466                 ID_ALL_MASK,
 467                 "Adaptec 19160B Ultra160 SCSI adapter",
 468                 ahc_aic7892_setup
 469         },
 470         {
 471                 ID_AIC7892_ARO,
 472                 ID_ALL_MASK,
 473                 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
 474                 ahc_aic7892_setup
 475         },
 476         /* aic7895 based controllers */
 477         {
 478                 ID_AHA_2940U_DUAL,
 479                 ID_ALL_MASK,
 480                 "Adaptec 2940/DUAL Ultra SCSI adapter",
 481                 ahc_aic7895_setup
 482         },
 483         {
 484                 ID_AHA_3940AU,
 485                 ID_ALL_MASK,
 486                 "Adaptec 3940A Ultra SCSI adapter",
 487                 ahc_aic7895_setup
 488         },
 489         {
 490                 ID_AHA_3944AU,
 491                 ID_ALL_MASK,
 492                 "Adaptec 3944A Ultra SCSI adapter",
 493                 ahc_aic7895_setup
 494         },
 495         {
 496                 ID_AIC7895_ARO,
 497                 ID_AIC7895_ARO_MASK,
 498                 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
 499                 ahc_aic7895_setup
 500         },
 501         /* aic7896/97 based controllers */
 502         {
 503                 ID_AHA_3950U2B_0,
 504                 ID_ALL_MASK,
 505                 "Adaptec 3950B Ultra2 SCSI adapter",
 506                 ahc_aic7896_setup
 507         },
 508         {
 509                 ID_AHA_3950U2B_1,
 510                 ID_ALL_MASK,
 511                 "Adaptec 3950B Ultra2 SCSI adapter",
 512                 ahc_aic7896_setup
 513         },
 514         {
 515                 ID_AHA_3950U2D_0,
 516                 ID_ALL_MASK,
 517                 "Adaptec 3950D Ultra2 SCSI adapter",
 518                 ahc_aic7896_setup
 519         },
 520         {
 521                 ID_AHA_3950U2D_1,
 522                 ID_ALL_MASK,
 523                 "Adaptec 3950D Ultra2 SCSI adapter",
 524                 ahc_aic7896_setup
 525         },
 526         {
 527                 ID_AIC7896_ARO,
 528                 ID_ALL_MASK,
 529                 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
 530                 ahc_aic7896_setup
 531         },
 532         /* aic7899 based controllers */
 533         {
 534                 ID_AHA_3960D,
 535                 ID_ALL_MASK,
 536                 "Adaptec 3960D Ultra160 SCSI adapter",
 537                 ahc_aic7899_setup
 538         },
 539         {
 540                 ID_AHA_3960D_CPQ,
 541                 ID_ALL_MASK,
 542                 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
 543                 ahc_aic7899_setup
 544         },
 545         {
 546                 ID_AIC7899_ARO,
 547                 ID_ALL_MASK,
 548                 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
 549                 ahc_aic7899_setup
 550         },
 551         /* Generic chip probes for devices we don't know 'exactly' */
 552         {
 553                 ID_AIC7850 & ID_DEV_VENDOR_MASK,
 554                 ID_DEV_VENDOR_MASK,
 555                 "Adaptec aic7850 SCSI adapter",
 556                 ahc_aic785X_setup
 557         },
 558         {
 559                 ID_AIC7855 & ID_DEV_VENDOR_MASK,
 560                 ID_DEV_VENDOR_MASK,
 561                 "Adaptec aic7855 SCSI adapter",
 562                 ahc_aic785X_setup
 563         },
 564         {
 565                 ID_AIC7859 & ID_DEV_VENDOR_MASK,
 566                 ID_DEV_VENDOR_MASK,
 567                 "Adaptec aic7859 SCSI adapter",
 568                 ahc_aic7860_setup
 569         },
 570         {
 571                 ID_AIC7860 & ID_DEV_VENDOR_MASK,
 572                 ID_DEV_VENDOR_MASK,
 573                 "Adaptec aic7860 Ultra SCSI adapter",
 574                 ahc_aic7860_setup
 575         },
 576         {
 577                 ID_AIC7870 & ID_DEV_VENDOR_MASK,
 578                 ID_DEV_VENDOR_MASK,
 579                 "Adaptec aic7870 SCSI adapter",
 580                 ahc_aic7870_setup
 581         },
 582         {
 583                 ID_AIC7880 & ID_DEV_VENDOR_MASK,
 584                 ID_DEV_VENDOR_MASK,
 585                 "Adaptec aic7880 Ultra SCSI adapter",
 586                 ahc_aic7880_setup
 587         },
 588         {
 589                 ID_AIC7890 & ID_9005_GENERIC_MASK,
 590                 ID_9005_GENERIC_MASK,
 591                 "Adaptec aic7890/91 Ultra2 SCSI adapter",
 592                 ahc_aic7890_setup
 593         },
 594         {
 595                 ID_AIC7892 & ID_9005_GENERIC_MASK,
 596                 ID_9005_GENERIC_MASK,
 597                 "Adaptec aic7892 Ultra160 SCSI adapter",
 598                 ahc_aic7892_setup
 599         },
 600         {
 601                 ID_AIC7895 & ID_DEV_VENDOR_MASK,
 602                 ID_DEV_VENDOR_MASK,
 603                 "Adaptec aic7895 Ultra SCSI adapter",
 604                 ahc_aic7895_setup
 605         },
 606         {
 607                 ID_AIC7896 & ID_9005_GENERIC_MASK,
 608                 ID_9005_GENERIC_MASK,
 609                 "Adaptec aic7896/97 Ultra2 SCSI adapter",
 610                 ahc_aic7896_setup
 611         },
 612         {
 613                 ID_AIC7899 & ID_9005_GENERIC_MASK,
 614                 ID_9005_GENERIC_MASK,
 615                 "Adaptec aic7899 Ultra160 SCSI adapter",
 616                 ahc_aic7899_setup
 617         },
 618         {
 619                 ID_AIC7810 & ID_DEV_VENDOR_MASK,
 620                 ID_DEV_VENDOR_MASK,
 621                 "Adaptec aic7810 RAID memory controller",
 622                 ahc_raid_setup
 623         },
 624         {
 625                 ID_AIC7815 & ID_DEV_VENDOR_MASK,
 626                 ID_DEV_VENDOR_MASK,
 627                 "Adaptec aic7815 RAID memory controller",
 628                 ahc_raid_setup
 629         }
 630 };
 631
 632 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
 633
 634 #define AHC_394X_SLOT_CHANNEL_A 4
 635 #define AHC_394X_SLOT_CHANNEL_B 5
 636
 637 #define AHC_398X_SLOT_CHANNEL_A 4
 638 #define AHC_398X_SLOT_CHANNEL_B 8
 639 #define AHC_398X_SLOT_CHANNEL_C 12
 640
 641 #define AHC_494X_SLOT_CHANNEL_A 4
 642 #define AHC_494X_SLOT_CHANNEL_B 5
 643 #define AHC_494X_SLOT_CHANNEL_C 6
 644 #define AHC_494X_SLOT_CHANNEL_D 7
 645
 646 #define DEVCONFIG               0x40
 647 #define         PCIERRGENDIS    0x80000000ul
 648 #define         SCBSIZE32       0x00010000ul    /* aic789X only */
 649 #define         REXTVALID       0x00001000ul    /* ultra cards only */
 650 #define         MPORTMODE       0x00000400ul    /* aic7870+ only */
 651 #define         RAMPSM          0x00000200ul    /* aic7870+ only */
 652 #define         VOLSENSE        0x00000100ul
 653 #define         PCI64BIT        0x00000080ul    /* 64Bit PCI bus (Ultra2 Only)*/
 654 #define         SCBRAMSEL       0x00000080ul
 655 #define         MRDCEN          0x00000040ul
 656 #define         EXTSCBTIME      0x00000020ul    /* aic7870 only */
 657 #define         EXTSCBPEN       0x00000010ul    /* aic7870 only */
 658 #define         BERREN          0x00000008ul
 659 #define         DACEN           0x00000004ul
 660 #define         STPWLEVEL       0x00000002ul
 661 #define         DIFACTNEGEN     0x00000001ul    /* aic7870 only */
 662
 663 #define CSIZE_LATTIME           0x0c
 664 #define         CACHESIZE       0x0000003ful    /* only 5 bits */
 665 #define         LATTIME         0x0000ff00ul
 666
 667 /* PCI STATUS definitions */
 668 #define DPE     0x80
 669 #define SSE     0x40
 670 #define RMA     0x20
 671 #define RTA     0x10
 672 #define STA     0x08
 673 #define DPR     0x01
 674
 675 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
 676                                      uint16_t subvendor, uint16_t subdevice);
 677 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
 678 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
 679                                   int pcheck, int fast, int large);
 680 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
 681 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
 682 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
 683                                  struct seeprom_config *sc);
 684 static void configure_termination(struct ahc_softc *ahc,
 685                                   struct seeprom_descriptor *sd,
 686                                   u_int adapter_control,
 687                                   u_int *sxfrctl1);
 688
 689 static void ahc_new_term_detect(struct ahc_softc *ahc,
 690                                 int *enableSEC_low,
 691                                 int *enableSEC_high,
 692                                 int *enablePRI_low,
 693                                 int *enablePRI_high,
 694                                 int *eeprom_present);
 695 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
 696                                  int *internal68_present,
 697                                  int *externalcable_present,
 698                                  int *eeprom_present);
 699 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
 700                                  int *externalcable_present,
 701                                  int *eeprom_present);
 702 static void    write_brdctl(struct ahc_softc *ahc, uint8_t value);
 703 static uint8_t read_brdctl(struct ahc_softc *ahc);
 704 static void ahc_pci_intr(struct ahc_softc *ahc);
 705 static int  ahc_pci_chip_init(struct ahc_softc *ahc);
 706 static int  ahc_pci_suspend(struct ahc_softc *ahc);
 707 static int  ahc_pci_resume(struct ahc_softc *ahc);
 708
 709 static int
 710 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
 711                           uint16_t subdevice, uint16_t subvendor)
 712 {
 713         int result;
 714
 715         /* Default to invalid. */
 716         result = 0;
 717         if (vendor == 0x9005
 718          && subvendor == 0x9005
 719          && subdevice != device
 720          && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
 721
 722                 switch (SUBID_9005_TYPE(subdevice)) {
 723                 case SUBID_9005_TYPE_MB:
 724                         break;
 725                 case SUBID_9005_TYPE_CARD:
 726                 case SUBID_9005_TYPE_LCCARD:
 727                         /*
 728                          * Currently only trust Adaptec cards to
 729                          * get the sub device info correct.
 730                          */
 731                         if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
 732                                 result = 1;
 733                         break;
 734                 case SUBID_9005_TYPE_RAID:
 735                         break;
 736                 default:
 737                         break;
 738                 }
 739         }
 740         return (result);
 741 }
 742
 743 struct ahc_pci_identity *
 744 ahc_find_pci_device(ahc_dev_softc_t pci)
 745 {
 746         uint64_t  full_id;
 747         uint16_t  device;
 748         uint16_t  vendor;
 749         uint16_t  subdevice;
 750         uint16_t  subvendor;
 751         struct    ahc_pci_identity *entry;
 752         u_int     i;
 753
 754         vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
 755         device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
 756         subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
 757         subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
 758         full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
 759
 760         /*
 761          * If the second function is not hooked up, ignore it.
 762          * Unfortunately, not all MB vendors implement the
 763          * subdevice ID as per the Adaptec spec, so do our best
 764          * to sanity check it prior to accepting the subdevice
 765          * ID as valid.
 766          */
 767         if (ahc_get_pci_function(pci) > 0
 768          && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
 769          && SUBID_9005_MFUNCENB(subdevice) == 0)
 770                 return (NULL);
 771
 772         for (i = 0; i < ahc_num_pci_devs; i++) {
 773                 entry = &ahc_pci_ident_table[i];
 774                 if (entry->full_id == (full_id & entry->id_mask)) {
 775                         /* Honor exclusion entries. */
 776                         if (entry->name == NULL)
 777                                 return (NULL);
 778                         return (entry);
 779                 }
 780         }
 781         return (NULL);
 782 }
 783
 784 int
 785 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
 786 {
 787         u_long   l;
 788         u_int    command;
 789         u_int    our_id;
 790         u_int    sxfrctl1;
 791         u_int    scsiseq;
 792         u_int    dscommand0;
 793         uint32_t devconfig;
 794         int      error;
 795         uint8_t  sblkctl;
 796
 797         our_id = 0;
 798         error = entry->setup(ahc);
 799         if (error != 0)
 800                 return (error);
 801         ahc->chip |= AHC_PCI;
 802         ahc->description = entry->name;
 803
 804         ahc_power_state_change(ahc, AHC_POWER_STATE_D0);
 805
 806         error = ahc_pci_map_registers(ahc);
 807         if (error != 0)
 808                 return (error);
 809
 810         /*
 811          * Before we continue probing the card, ensure that
 812          * its interrupts are *disabled*.  We don't want
 813          * a misstep to hang the machine in an interrupt
 814          * storm.
 815          */
 816         ahc_intr_enable(ahc, FALSE);
 817
 818         devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
 819
 820         /*
 821          * If we need to support high memory, enable dual
 822          * address cycles.  This bit must be set to enable
 823          * high address bit generation even if we are on a
 824          * 64bit bus (PCI64BIT set in devconfig).
 825          */
 826         if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
 827
 828                 if (bootverbose)
 829                         printf("%s: Enabling 39Bit Addressing\n",
 830                                ahc_name(ahc));
 831                 devconfig |= DACEN;
 832         }
 833
 834         /* Ensure that pci error generation, a test feature, is disabled. */
 835         devconfig |= PCIERRGENDIS;
 836
 837         ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
 838
 839         /* Ensure busmastering is enabled */
 840         command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
 841         command |= PCIM_CMD_BUSMASTEREN;
 842
 843         ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
 844
 845         /* On all PCI adapters, we allow SCB paging */
 846         ahc->flags |= AHC_PAGESCBS;
 847
 848         error = ahc_softc_init(ahc);
 849         if (error != 0)
 850                 return (error);
 851
 852         /*
 853          * Disable PCI parity error checking.  Users typically
 854          * do this to work around broken PCI chipsets that get
 855          * the parity timing wrong and thus generate lots of spurious
 856          * errors.  The chip only allows us to disable *all* parity
 857          * error reporting when doing this, so CIO bus, scb ram, and
 858          * scratch ram parity errors will be ignored too.
 859          */
 860         if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
 861                 ahc->seqctl |= FAILDIS;
 862
 863         ahc->bus_intr = ahc_pci_intr;
 864         ahc->bus_chip_init = ahc_pci_chip_init;
 865         ahc->bus_suspend = ahc_pci_suspend;
 866         ahc->bus_resume = ahc_pci_resume;
 867
 868         /* Remeber how the card was setup in case there is no SEEPROM */
 869         if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
 870                 ahc_pause(ahc);
 871                 if ((ahc->features & AHC_ULTRA2) != 0)
 872                         our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
 873                 else
 874                         our_id = ahc_inb(ahc, SCSIID) & OID;
 875                 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
 876                 scsiseq = ahc_inb(ahc, SCSISEQ);
 877         } else {
 878                 sxfrctl1 = STPWEN;
 879                 our_id = 7;
 880                 scsiseq = 0;
 881         }
 882
 883         error = ahc_reset(ahc, /*reinit*/FALSE);
 884         if (error != 0)
 885                 return (ENXIO);
 886
 887         if ((ahc->features & AHC_DT) != 0) {
 888                 u_int sfunct;
 889
 890                 /* Perform ALT-Mode Setup */
 891                 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
 892                 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
 893                 ahc_outb(ahc, OPTIONMODE,
 894                          OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
 895                 ahc_outb(ahc, SFUNCT, sfunct);
 896
 897                 /* Normal mode setup */
 898                 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
 899                                           |TARGCRCENDEN);
 900         }
 901
 902         dscommand0 = ahc_inb(ahc, DSCOMMAND0);
 903         dscommand0 |= MPARCKEN|CACHETHEN;
 904         if ((ahc->features & AHC_ULTRA2) != 0) {
 905
 906                 /*
 907                  * DPARCKEN doesn't work correctly on
 908                  * some MBs so don't use it.
 909                  */
 910                 dscommand0 &= ~DPARCKEN;
 911         }
 912
 913         /*
 914          * Handle chips that must have cache line
 915          * streaming (dis/en)abled.
 916          */
 917         if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
 918                 dscommand0 |= CACHETHEN;
 919
 920         if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
 921                 dscommand0 &= ~CACHETHEN;
 922
 923         ahc_outb(ahc, DSCOMMAND0, dscommand0);
 924
 925         ahc->pci_cachesize =
 926             ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
 927                                 /*bytes*/1) & CACHESIZE;
 928         ahc->pci_cachesize *= 4;
 929
 930         if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
 931          && ahc->pci_cachesize == 4) {
 932
 933                 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
 934                                      0, /*bytes*/1);
 935                 ahc->pci_cachesize = 0;
 936         }
 937
 938         /*
 939          * We cannot perform ULTRA speeds without the presense
 940          * of the external precision resistor.
 941          */
 942         if ((ahc->features & AHC_ULTRA) != 0) {
 943                 uint32_t devconfig;
 944
 945                 devconfig = ahc_pci_read_config(ahc->dev_softc,
 946                                                 DEVCONFIG, /*bytes*/4);
 947                 if ((devconfig & REXTVALID) == 0)
 948                         ahc->features &= ~AHC_ULTRA;
 949         }
 950
 951         /* See if we have a SEEPROM and perform auto-term */
 952         check_extport(ahc, &sxfrctl1);
 953
 954         /*
 955          * Take the LED out of diagnostic mode
 956          */
 957         sblkctl = ahc_inb(ahc, SBLKCTL);
 958         ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
 959
 960         if ((ahc->features & AHC_ULTRA2) != 0) {
 961                 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
 962         } else {
 963                 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
 964         }
 965
 966         if (ahc->flags & AHC_USEDEFAULTS) {
 967                 /*
 968                  * PCI Adapter default setup
 969                  * Should only be used if the adapter does not have
 970                  * a SEEPROM.
 971                  */
 972                 /* See if someone else set us up already */
 973                 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
 974                  && scsiseq != 0) {
 975                         printf("%s: Using left over BIOS settings\n",
 976                                 ahc_name(ahc));
 977                         ahc->flags &= ~AHC_USEDEFAULTS;
 978                         ahc->flags |= AHC_BIOS_ENABLED;
 979                 } else {
 980                         /*
 981                          * Assume only one connector and always turn
 982                          * on termination.
 983                          */
 984                         our_id = 0x07;
 985                         sxfrctl1 = STPWEN;
 986                 }
 987                 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
 988
 989                 ahc->our_id = our_id;
 990         }
 991
 992         /*
 993          * Take a look to see if we have external SRAM.
 994          * We currently do not attempt to use SRAM that is
 995          * shared among multiple controllers.
 996          */
 997         ahc_probe_ext_scbram(ahc);
 998
 999         /*
1000          * Record our termination setting for the
1001          * generic initialization routine.
1002          */
1003         if ((sxfrctl1 & STPWEN) != 0)
1004                 ahc->flags |= AHC_TERM_ENB_A;
1005
1006         /*
1007          * Save chip register configuration data for chip resets
1008          * that occur during runtime and resume events.
1009          */
1010         ahc->bus_softc.pci_softc.devconfig =
1011             ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1012         ahc->bus_softc.pci_softc.command =
1013             ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
1014         ahc->bus_softc.pci_softc.csize_lattime =
1015             ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
1016         ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1017         ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1018         if ((ahc->features & AHC_DT) != 0) {
1019                 u_int sfunct;
1020
1021                 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1022                 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1023                 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1024                 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1025                 ahc_outb(ahc, SFUNCT, sfunct);
1026                 ahc->bus_softc.pci_softc.crccontrol1 =
1027                     ahc_inb(ahc, CRCCONTROL1);
1028         }
1029         if ((ahc->features & AHC_MULTI_FUNC) != 0)
1030                 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1031
1032         if ((ahc->features & AHC_ULTRA2) != 0)
1033                 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1034
1035         /* Core initialization */
1036         error = ahc_init(ahc);
1037         if (error != 0)
1038                 return (error);
1039
1040         /*
1041          * Allow interrupts now that we are completely setup.
1042          */
1043         error = ahc_pci_map_int(ahc);
1044         if (error != 0)
1045                 return (error);
1046
1047         ahc_list_lock(&l);
1048         /*
1049          * Link this softc in with all other ahc instances.
1050          */
1051         ahc_softc_insert(ahc);
1052         ahc_list_unlock(&l);
1053         return (0);
1054 }
1055
1056 /*
1057  * Test for the presense of external sram in an
1058  * "unshared" configuration.
1059  */
1060 static int
1061 ahc_ext_scbram_present(struct ahc_softc *ahc)
1062 {
1063         u_int chip;
1064         int ramps;
1065         int single_user;
1066         uint32_t devconfig;
1067
1068         chip = ahc->chip & AHC_CHIPID_MASK;
1069         devconfig = ahc_pci_read_config(ahc->dev_softc,
1070                                         DEVCONFIG, /*bytes*/4);
1071         single_user = (devconfig & MPORTMODE) != 0;
1072
1073         if ((ahc->features & AHC_ULTRA2) != 0)
1074                 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1075         else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1076                 /*
1077                  * External SCBRAM arbitration is flakey
1078                  * on these chips.  Unfortunately this means
1079                  * we don't use the extra SCB ram space on the
1080                  * 3940AUW.
1081                  */
1082                 ramps = 0;
1083         else if (chip >= AHC_AIC7870)
1084                 ramps = (devconfig & RAMPSM) != 0;
1085         else
1086                 ramps = 0;
1087
1088         if (ramps && single_user)
1089                 return (1);
1090         return (0);
1091 }
1092
1093 /*
1094  * Enable external scbram.
1095  */
1096 static void
1097 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1098                   int fast, int large)
1099 {
1100         uint32_t devconfig;
1101
1102         if (ahc->features & AHC_MULTI_FUNC) {
1103                 /*
1104                  * Set the SCB Base addr (highest address bit)
1105                  * depending on which channel we are.
1106                  */
1107                 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc));
1108         }
1109
1110         ahc->flags &= ~AHC_LSCBS_ENABLED;
1111         if (large)
1112                 ahc->flags |= AHC_LSCBS_ENABLED;
1113         devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1114         if ((ahc->features & AHC_ULTRA2) != 0) {
1115                 u_int dscommand0;
1116
1117                 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1118                 if (enable)
1119                         dscommand0 &= ~INTSCBRAMSEL;
1120                 else
1121                         dscommand0 |= INTSCBRAMSEL;
1122                 if (large)
1123                         dscommand0 &= ~USCBSIZE32;
1124                 else
1125                         dscommand0 |= USCBSIZE32;
1126                 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1127         } else {
1128                 if (fast)
1129                         devconfig &= ~EXTSCBTIME;
1130                 else
1131                         devconfig |= EXTSCBTIME;
1132                 if (enable)
1133                         devconfig &= ~SCBRAMSEL;
1134                 else
1135                         devconfig |= SCBRAMSEL;
1136                 if (large)
1137                         devconfig &= ~SCBSIZE32;
1138                 else
1139                         devconfig |= SCBSIZE32;
1140         }
1141         if (pcheck)
1142                 devconfig |= EXTSCBPEN;
1143         else
1144                 devconfig &= ~EXTSCBPEN;
1145
1146         ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1147 }
1148
1149 /*
1150  * Take a look to see if we have external SRAM.
1151  * We currently do not attempt to use SRAM that is
1152  * shared among multiple controllers.
1153  */
1154 static void
1155 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1156 {
1157         int num_scbs;
1158         int test_num_scbs;
1159         int enable;
1160         int pcheck;
1161         int fast;
1162         int large;
1163
1164         enable = FALSE;
1165         pcheck = FALSE;
1166         fast = FALSE;
1167         large = FALSE;
1168         num_scbs = 0;
1169
1170         if (ahc_ext_scbram_present(ahc) == 0)
1171                 goto done;
1172
1173         /*
1174          * Probe for the best parameters to use.
1175          */
1176         ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1177         num_scbs = ahc_probe_scbs(ahc);
1178         if (num_scbs == 0) {
1179                 /* The SRAM wasn't really present. */
1180                 goto done;
1181         }
1182         enable = TRUE;
1183
1184         /*
1185          * Clear any outstanding parity error
1186          * and ensure that parity error reporting
1187          * is enabled.
1188          */
1189         ahc_outb(ahc, SEQCTL, 0);
1190         ahc_outb(ahc, CLRINT, CLRPARERR);
1191         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1192
1193         /* Now see if we can do parity */
1194         ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1195         num_scbs = ahc_probe_scbs(ahc);
1196         if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1197          || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1198                 pcheck = TRUE;
1199
1200         /* Clear any resulting parity error */
1201         ahc_outb(ahc, CLRINT, CLRPARERR);
1202         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1203
1204         /* Now see if we can do fast timing */
1205         ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1206         test_num_scbs = ahc_probe_scbs(ahc);
1207         if (test_num_scbs == num_scbs
1208          && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1209           || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1210                 fast = TRUE;
1211
1212         /*
1213          * See if we can use large SCBs and still maintain
1214          * the same overall count of SCBs.
1215          */
1216         if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1217                 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1218                 test_num_scbs = ahc_probe_scbs(ahc);
1219                 if (test_num_scbs >= num_scbs) {
1220                         large = TRUE;
1221                         num_scbs = test_num_scbs;
1222                         if (num_scbs >= 64) {
1223                                 /*
1224                                  * We have enough space to move the
1225                                  * "busy targets table" into SCB space
1226                                  * and make it qualify all the way to the
1227                                  * lun level.
1228                                  */
1229                                 ahc->flags |= AHC_SCB_BTT;
1230                         }
1231                 }
1232         }
1233 done:
1234         /*
1235          * Disable parity error reporting until we
1236          * can load instruction ram.
1237          */
1238         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1239         /* Clear any latched parity error */
1240         ahc_outb(ahc, CLRINT, CLRPARERR);
1241         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1242         if (bootverbose && enable) {
1243                 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1244                        ahc_name(ahc), fast ? "fast" : "slow",
1245                        pcheck ? ", parity checking enabled" : "",
1246                        large ? 64 : 32);
1247         }
1248         ahc_scbram_config(ahc, enable, pcheck, fast, large);
1249 }
1250
1251 /*
1252  * Perform some simple tests that should catch situations where
1253  * our registers are invalidly mapped.
1254  */
1255 int
1256 ahc_pci_test_register_access(struct ahc_softc *ahc)
1257 {
1258         int      error;
1259         u_int    status1;
1260         uint32_t cmd;
1261         uint8_t  hcntrl;
1262
1263         error = EIO;
1264
1265         /*
1266          * Enable PCI error interrupt status, but suppress NMIs
1267          * generated by SERR raised due to target aborts.
1268          */
1269         cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1270         ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1271                              cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1272
1273         /*
1274          * First a simple test to see if any
1275          * registers can be read.  Reading
1276          * HCNTRL has no side effects and has
1277          * at least one bit that is guaranteed to
1278          * be zero so it is a good register to
1279          * use for this test.
1280          */
1281         hcntrl = ahc_inb(ahc, HCNTRL);
1282         if (hcntrl == 0xFF)
1283                 goto fail;
1284
1285         /*
1286          * Next create a situation where write combining
1287          * or read prefetching could be initiated by the
1288          * CPU or host bridge.  Our device does not support
1289          * either, so look for data corruption and/or flagged
1290          * PCI errors.
1291          */
1292         ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1293         while (ahc_is_paused(ahc) == 0)
1294                 ;
1295
1296         /* Clear any PCI errors that occurred before our driver attached. */
1297         status1 = ahc_pci_read_config(ahc->dev_softc,
1298                                       PCIR_STATUS + 1, /*bytes*/1);
1299         ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1300                              status1, /*bytes*/1);
1301         ahc_outb(ahc, CLRINT, CLRPARERR);
1302
1303         ahc_outb(ahc, SEQCTL, PERRORDIS);
1304         ahc_outb(ahc, SCBPTR, 0);
1305         ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1306         if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1307                 goto fail;
1308
1309         status1 = ahc_pci_read_config(ahc->dev_softc,
1310                                       PCIR_STATUS + 1, /*bytes*/1);
1311         if ((status1 & STA) != 0)
1312                 goto fail;
1313
1314         error = 0;
1315
1316 fail:
1317         /* Silently clear any latched errors. */
1318         status1 = ahc_pci_read_config(ahc->dev_softc,
1319                                       PCIR_STATUS + 1, /*bytes*/1);
1320         ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1321                              status1, /*bytes*/1);
1322         ahc_outb(ahc, CLRINT, CLRPARERR);
1323         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1324         ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1325         return (error);
1326 }
1327
1328 /*
1329  * Check the external port logic for a serial eeprom
1330  * and termination/cable detection contrls.
1331  */
1332 static void
1333 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1334 {
1335         struct  seeprom_descriptor sd;
1336         struct  seeprom_config *sc;
1337         int     have_seeprom;
1338         int     have_autoterm;
1339
1340         sd.sd_ahc = ahc;
1341         sd.sd_control_offset = SEECTL;
1342         sd.sd_status_offset = SEECTL;
1343         sd.sd_dataout_offset = SEECTL;
1344         sc = ahc->seep_config;
1345
1346         /*
1347          * For some multi-channel devices, the c46 is simply too
1348          * small to work.  For the other controller types, we can
1349          * get our information from either SEEPROM type.  Set the
1350          * type to start our probe with accordingly.
1351          */
1352         if (ahc->flags & AHC_LARGE_SEEPROM)
1353                 sd.sd_chip = C56_66;
1354         else
1355                 sd.sd_chip = C46;
1356
1357         sd.sd_MS = SEEMS;
1358         sd.sd_RDY = SEERDY;
1359         sd.sd_CS = SEECS;
1360         sd.sd_CK = SEECK;
1361         sd.sd_DO = SEEDO;
1362         sd.sd_DI = SEEDI;
1363
1364         have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1365         if (have_seeprom) {
1366
1367                 if (bootverbose)
1368                         printf("%s: Reading SEEPROM...", ahc_name(ahc));
1369
1370                 for (;;) {
1371                         u_int start_addr;
1372
1373                         start_addr = 32 * (ahc->channel - 'A');
1374
1375                         have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1376                                                         start_addr,
1377                                                         sizeof(*sc)/2);
1378
1379                         if (have_seeprom)
1380                                 have_seeprom = ahc_verify_cksum(sc);
1381
1382                         if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1383                                 if (bootverbose) {
1384                                         if (have_seeprom == 0)
1385                                                 printf ("checksum error\n");
1386                                         else
1387                                                 printf ("done.\n");
1388                                 }
1389                                 break;
1390                         }
1391                         sd.sd_chip = C56_66;
1392                 }
1393                 ahc_release_seeprom(&sd);
1394         }
1395
1396         if (!have_seeprom) {
1397                 /*
1398                  * Pull scratch ram settings and treat them as
1399                  * if they are the contents of an seeprom if
1400                  * the 'ADPT' signature is found in SCB2.
1401                  * We manually compose the data as 16bit values
1402                  * to avoid endian issues.
1403                  */
1404                 ahc_outb(ahc, SCBPTR, 2);
1405                 if (ahc_inb(ahc, SCB_BASE) == 'A'
1406                  && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1407                  && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1408                  && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1409                         uint16_t *sc_data;
1410                         int       i;
1411
1412                         sc_data = (uint16_t *)sc;
1413                         for (i = 0; i < 32; i++, sc_data++) {
1414                                 int     j;
1415
1416                                 j = i * 2;
1417                                 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1418                                          | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1419                         }
1420                         have_seeprom = ahc_verify_cksum(sc);
1421                         if (have_seeprom)
1422                                 ahc->flags |= AHC_SCB_CONFIG_USED;
1423                 }
1424                 /*
1425                  * Clear any SCB parity errors in case this data and
1426                  * its associated parity was not initialized by the BIOS
1427                  */
1428                 ahc_outb(ahc, CLRINT, CLRPARERR);
1429                 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1430         }
1431
1432         if (!have_seeprom) {
1433                 if (bootverbose)
1434                         printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1435                 ahc->flags |= AHC_USEDEFAULTS;
1436                 kfree(ahc->seep_config, M_DEVBUF);
1437                 ahc->seep_config = NULL;
1438                 sc = NULL;
1439         } else {
1440                 ahc_parse_pci_eeprom(ahc, sc);
1441         }
1442
1443         /*
1444          * Cards that have the external logic necessary to talk to
1445          * a SEEPROM, are almost certain to have the remaining logic
1446          * necessary for auto-termination control.  This assumption
1447          * hasn't failed yet...
1448          */
1449         have_autoterm = have_seeprom;
1450
1451         /*
1452          * Some low-cost chips have SEEPROM and auto-term control built
1453          * in, instead of using a GAL.  They can tell us directly
1454          * if the termination logic is enabled.
1455          */
1456         if ((ahc->features & AHC_SPIOCAP) != 0) {
1457                 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1458                         have_autoterm = FALSE;
1459         }
1460
1461         if (have_autoterm) {
1462                 ahc->flags |= AHC_HAS_TERM_LOGIC;
1463                 ahc_acquire_seeprom(ahc, &sd);
1464                 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1465                 ahc_release_seeprom(&sd);
1466         } else if (have_seeprom) {
1467                 *sxfrctl1 &= ~STPWEN;
1468                 if ((sc->adapter_control & CFSTERM) != 0)
1469                         *sxfrctl1 |= STPWEN;
1470                 if (bootverbose)
1471                         printf("%s: Low byte termination %sabled\n",
1472                                ahc_name(ahc),
1473                                (*sxfrctl1 & STPWEN) ? "en" : "dis");
1474         }
1475 }
1476
1477 static void
1478 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1479 {
1480         /*
1481          * Put the data we've collected down into SRAM
1482          * where ahc_init will find it.
1483          */
1484         int      i;
1485         int      max_targ = sc->max_targets & CFMAXTARG;
1486         u_int    scsi_conf;
1487         uint16_t discenable;
1488         uint16_t ultraenb;
1489
1490         discenable = 0;
1491         ultraenb = 0;
1492         if ((sc->adapter_control & CFULTRAEN) != 0) {
1493                 /*
1494                  * Determine if this adapter has a "newstyle"
1495                  * SEEPROM format.
1496                  */
1497                 for (i = 0; i < max_targ; i++) {
1498                         if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1499                                 ahc->flags |= AHC_NEWEEPROM_FMT;
1500                                 break;
1501                         }
1502                 }
1503         }
1504
1505         for (i = 0; i < max_targ; i++) {
1506                 u_int     scsirate;
1507                 uint16_t target_mask;
1508
1509                 target_mask = 0x01 << i;
1510                 if (sc->device_flags[i] & CFDISC)
1511                         discenable |= target_mask;
1512                 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1513                         if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1514                                 ultraenb |= target_mask;
1515                 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1516                         ultraenb |= target_mask;
1517                 }
1518                 if ((sc->device_flags[i] & CFXFER) == 0x04
1519                  && (ultraenb & target_mask) != 0) {
1520                         /* Treat 10MHz as a non-ultra speed */
1521                         sc->device_flags[i] &= ~CFXFER;
1522                         ultraenb &= ~target_mask;
1523                 }
1524                 if ((ahc->features & AHC_ULTRA2) != 0) {
1525                         u_int offset;
1526
1527                         if (sc->device_flags[i] & CFSYNCH)
1528                                 offset = MAX_OFFSET_ULTRA2;
1529                         else
1530                                 offset = 0;
1531                         ahc_outb(ahc, TARG_OFFSET + i, offset);
1532
1533                         /*
1534                          * The ultra enable bits contain the
1535                          * high bit of the ultra2 sync rate
1536                          * field.
1537                          */
1538                         scsirate = (sc->device_flags[i] & CFXFER)
1539                                  | ((ultraenb & target_mask) ? 0x8 : 0x0);
1540                         if (sc->device_flags[i] & CFWIDEB)
1541                                 scsirate |= WIDEXFER;
1542                 } else {
1543                         scsirate = (sc->device_flags[i] & CFXFER) << 4;
1544                         if (sc->device_flags[i] & CFSYNCH)
1545                                 scsirate |= SOFS;
1546                         if (sc->device_flags[i] & CFWIDEB)
1547                                 scsirate |= WIDEXFER;
1548                 }
1549                 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1550         }
1551         ahc->our_id = sc->brtime_id & CFSCSIID;
1552
1553         scsi_conf = (ahc->our_id & 0x7);
1554         if (sc->adapter_control & CFSPARITY)
1555                 scsi_conf |= ENSPCHK;
1556         if (sc->adapter_control & CFRESETB)
1557                 scsi_conf |= RESET_SCSI;
1558
1559         ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1560
1561         if (sc->bios_control & CFEXTEND)
1562                 ahc->flags |= AHC_EXTENDED_TRANS_A;
1563
1564         if (sc->bios_control & CFBIOSEN)
1565                 ahc->flags |= AHC_BIOS_ENABLED;
1566         if (ahc->features & AHC_ULTRA
1567          && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1568                 /* Should we enable Ultra mode? */
1569                 if (!(sc->adapter_control & CFULTRAEN))
1570                         /* Treat us as a non-ultra card */
1571                         ultraenb = 0;
1572         }
1573
1574         if (sc->signature == CFSIGNATURE
1575          || sc->signature == CFSIGNATURE2) {
1576                 uint32_t devconfig;
1577
1578                 /* Honor the STPWLEVEL settings */
1579                 devconfig = ahc_pci_read_config(ahc->dev_softc,
1580                                                 DEVCONFIG, /*bytes*/4);
1581                 devconfig &= ~STPWLEVEL;
1582                 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1583                         devconfig |= STPWLEVEL;
1584                 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
1585                                      devconfig, /*bytes*/4);
1586         }
1587         /* Set SCSICONF info */
1588         ahc_outb(ahc, SCSICONF, scsi_conf);
1589         ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1590         ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1591         ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1592         ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1593 }
1594
1595 static void
1596 configure_termination(struct ahc_softc *ahc,
1597                       struct seeprom_descriptor *sd,
1598                       u_int adapter_control,
1599                       u_int *sxfrctl1)
1600 {
1601         uint8_t brddat;
1602
1603         brddat = 0;
1604
1605         /*
1606          * Update the settings in sxfrctl1 to match the
1607          * termination settings
1608          */
1609         *sxfrctl1 = 0;
1610
1611         /*
1612          * SEECS must be on for the GALS to latch
1613          * the data properly.  Be sure to leave MS
1614          * on or we will release the seeprom.
1615          */
1616         SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1617         if ((adapter_control & CFAUTOTERM) != 0
1618          || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1619                 int internal50_present;
1620                 int internal68_present;
1621                 int externalcable_present;
1622                 int eeprom_present;
1623                 int enableSEC_low;
1624                 int enableSEC_high;
1625                 int enablePRI_low;
1626                 int enablePRI_high;
1627                 int sum;
1628
1629                 enableSEC_low = 0;
1630                 enableSEC_high = 0;
1631                 enablePRI_low = 0;
1632                 enablePRI_high = 0;
1633                 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1634                         ahc_new_term_detect(ahc, &enableSEC_low,
1635                                             &enableSEC_high,
1636                                             &enablePRI_low,
1637                                             &enablePRI_high,
1638                                             &eeprom_present);
1639                         if ((adapter_control & CFSEAUTOTERM) == 0) {
1640                                 if (bootverbose)
1641                                         printf("%s: Manual SE Termination\n",
1642                                                ahc_name(ahc));
1643                                 enableSEC_low = (adapter_control & CFSELOWTERM);
1644                                 enableSEC_high =
1645                                     (adapter_control & CFSEHIGHTERM);
1646                         }
1647                         if ((adapter_control & CFAUTOTERM) == 0) {
1648                                 if (bootverbose)
1649                                         printf("%s: Manual LVD Termination\n",
1650                                                ahc_name(ahc));
1651                                 enablePRI_low = (adapter_control & CFSTERM);
1652                                 enablePRI_high = (adapter_control & CFWSTERM);
1653                         }
1654                         /* Make the table calculations below happy */
1655                         internal50_present = 0;
1656                         internal68_present = 1;
1657                         externalcable_present = 1;
1658                 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1659                         aic785X_cable_detect(ahc, &internal50_present,
1660                                              &externalcable_present,
1661                                              &eeprom_present);
1662                         /* Can never support a wide connector. */
1663                         internal68_present = 0;
1664                 } else {
1665                         aic787X_cable_detect(ahc, &internal50_present,
1666                                              &internal68_present,
1667                                              &externalcable_present,
1668                                              &eeprom_present);
1669                 }
1670
1671                 if ((ahc->features & AHC_WIDE) == 0)
1672                         internal68_present = 0;
1673
1674                 if (bootverbose
1675                  && (ahc->features & AHC_ULTRA2) == 0) {
1676                         printf("%s: internal 50 cable %s present",
1677                                ahc_name(ahc),
1678                                internal50_present ? "is":"not");
1679
1680                         if ((ahc->features & AHC_WIDE) != 0)
1681                                 printf(", internal 68 cable %s present",
1682                                        internal68_present ? "is":"not");
1683                         printf("\n%s: external cable %s present\n",
1684                                ahc_name(ahc),
1685                                externalcable_present ? "is":"not");
1686                 }
1687                 if (bootverbose)
1688                         printf("%s: BIOS eeprom %s present\n",
1689                                ahc_name(ahc), eeprom_present ? "is" : "not");
1690
1691                 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1692                         /*
1693                          * The 50 pin connector is a separate bus,
1694                          * so force it to always be terminated.
1695                          * In the future, perform current sensing
1696                          * to determine if we are in the middle of
1697                          * a properly terminated bus.
1698                          */
1699                         internal50_present = 0;
1700                 }
1701
1702                 /*
1703                  * Now set the termination based on what
1704                  * we found.
1705                  * Flash Enable = BRDDAT7
1706                  * Secondary High Term Enable = BRDDAT6
1707                  * Secondary Low Term Enable = BRDDAT5 (7890)
1708                  * Primary High Term Enable = BRDDAT4 (7890)
1709                  */
1710                 if ((ahc->features & AHC_ULTRA2) == 0
1711                  && (internal50_present != 0)
1712                  && (internal68_present != 0)
1713                  && (externalcable_present != 0)) {
1714                         printf("%s: Illegal cable configuration!!. "
1715                                "Only two connectors on the "
1716                                "adapter may be used at a "
1717                                "time!\n", ahc_name(ahc));
1718
1719                         /*
1720                          * Pretend there are no cables in the hope
1721                          * that having all of the termination on
1722                          * gives us a more stable bus.
1723                          */
1724                         internal50_present = 0;
1725                         internal68_present = 0;
1726                         externalcable_present = 0;
1727                 }
1728
1729                 if ((ahc->features & AHC_WIDE) != 0
1730                  && ((externalcable_present == 0)
1731                   || (internal68_present == 0)
1732                   || (enableSEC_high != 0))) {
1733                         brddat |= BRDDAT6;
1734                         if (bootverbose) {
1735                                 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1736                                         printf("%s: 68 pin termination "
1737                                                "Enabled\n", ahc_name(ahc));
1738                                 else
1739                                         printf("%s: %sHigh byte termination "
1740                                                "Enabled\n", ahc_name(ahc),
1741                                                enableSEC_high ? "Secondary "
1742                                                               : "");
1743                         }
1744                 }
1745
1746                 sum = internal50_present + internal68_present
1747                     + externalcable_present;
1748                 if (sum < 2 || (enableSEC_low != 0)) {
1749                         if ((ahc->features & AHC_ULTRA2) != 0)
1750                                 brddat |= BRDDAT5;
1751                         else
1752                                 *sxfrctl1 |= STPWEN;
1753                         if (bootverbose) {
1754                                 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1755                                         printf("%s: 50 pin termination "
1756                                                "Enabled\n", ahc_name(ahc));
1757                                 else
1758                                         printf("%s: %sLow byte termination "
1759                                                "Enabled\n", ahc_name(ahc),
1760                                                enableSEC_low ? "Secondary "
1761                                                              : "");
1762                         }
1763                 }
1764
1765                 if (enablePRI_low != 0) {
1766                         *sxfrctl1 |= STPWEN;
1767                         if (bootverbose)
1768                                 printf("%s: Primary Low Byte termination "
1769                                        "Enabled\n", ahc_name(ahc));
1770                 }
1771
1772                 /*
1773                  * Setup STPWEN before setting up the rest of
1774                  * the termination per the tech note on the U160 cards.
1775                  */
1776                 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1777
1778                 if (enablePRI_high != 0) {
1779                         brddat |= BRDDAT4;
1780                         if (bootverbose)
1781                                 printf("%s: Primary High Byte "
1782                                        "termination Enabled\n",
1783                                        ahc_name(ahc));
1784                 }
1785
1786                 write_brdctl(ahc, brddat);
1787
1788         } else {
1789                 if ((adapter_control & CFSTERM) != 0) {
1790                         *sxfrctl1 |= STPWEN;
1791
1792                         if (bootverbose)
1793                                 printf("%s: %sLow byte termination Enabled\n",
1794                                        ahc_name(ahc),
1795                                        (ahc->features & AHC_ULTRA2) ? "Primary "
1796                                                                     : "");
1797                 }
1798
1799                 if ((adapter_control & CFWSTERM) != 0
1800                  && (ahc->features & AHC_WIDE) != 0) {
1801                         brddat |= BRDDAT6;
1802                         if (bootverbose)
1803                                 printf("%s: %sHigh byte termination Enabled\n",
1804                                        ahc_name(ahc),
1805                                        (ahc->features & AHC_ULTRA2)
1806                                      ? "Secondary " : "");
1807                 }
1808
1809                 /*
1810                  * Setup STPWEN before setting up the rest of
1811                  * the termination per the tech note on the U160 cards.
1812                  */
1813                 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1814
1815                 if ((ahc->features & AHC_WIDE) != 0)
1816                         write_brdctl(ahc, brddat);
1817         }
1818         SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1819 }
1820
1821 static void
1822 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1823                     int *enableSEC_high, int *enablePRI_low,
1824                     int *enablePRI_high, int *eeprom_present)
1825 {
1826         uint8_t brdctl;
1827
1828         /*
1829          * BRDDAT7 = Eeprom
1830          * BRDDAT6 = Enable Secondary High Byte termination
1831          * BRDDAT5 = Enable Secondary Low Byte termination
1832          * BRDDAT4 = Enable Primary high byte termination
1833          * BRDDAT3 = Enable Primary low byte termination
1834          */
1835         brdctl = read_brdctl(ahc);
1836         *eeprom_present = brdctl & BRDDAT7;
1837         *enableSEC_high = (brdctl & BRDDAT6);
1838         *enableSEC_low = (brdctl & BRDDAT5);
1839         *enablePRI_high = (brdctl & BRDDAT4);
1840         *enablePRI_low = (brdctl & BRDDAT3);
1841 }
1842
1843 static void
1844 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1845                      int *internal68_present, int *externalcable_present,
1846                      int *eeprom_present)
1847 {
1848         uint8_t brdctl;
1849
1850         /*
1851          * First read the status of our cables.
1852          * Set the rom bank to 0 since the
1853          * bank setting serves as a multiplexor
1854          * for the cable detection logic.
1855          * BRDDAT5 controls the bank switch.
1856          */
1857         write_brdctl(ahc, 0);
1858
1859         /*
1860          * Now read the state of the internal
1861          * connectors.  BRDDAT6 is INT50 and
1862          * BRDDAT7 is INT68.
1863          */
1864         brdctl = read_brdctl(ahc);
1865         *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1866         *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1867
1868         /*
1869          * Set the rom bank to 1 and determine
1870          * the other signals.
1871          */
1872         write_brdctl(ahc, BRDDAT5);
1873
1874         /*
1875          * Now read the state of the external
1876          * connectors.  BRDDAT6 is EXT68 and
1877          * BRDDAT7 is EPROMPS.
1878          */
1879         brdctl = read_brdctl(ahc);
1880         *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1881         *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1882 }
1883
1884 static void
1885 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1886                      int *externalcable_present, int *eeprom_present)
1887 {
1888         uint8_t brdctl;
1889         uint8_t spiocap;
1890
1891         spiocap = ahc_inb(ahc, SPIOCAP);
1892         spiocap &= ~SOFTCMDEN;
1893         spiocap |= EXT_BRDCTL;
1894         ahc_outb(ahc, SPIOCAP, spiocap);
1895         ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1896         ahc_flush_device_writes(ahc);
1897         ahc_delay(500);
1898         ahc_outb(ahc, BRDCTL, 0);
1899         ahc_flush_device_writes(ahc);
1900         ahc_delay(500);
1901         brdctl = ahc_inb(ahc, BRDCTL);
1902         *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1903         *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1904         *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1905 }
1906
1907 int
1908 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1909 {
1910         int wait;
1911
1912         if ((ahc->features & AHC_SPIOCAP) != 0
1913          && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1914                 return (0);
1915
1916         /*
1917          * Request access of the memory port.  When access is
1918          * granted, SEERDY will go high.  We use a 1 second
1919          * timeout which should be near 1 second more than
1920          * is needed.  Reason: after the chip reset, there
1921          * should be no contention.
1922          */
1923         SEEPROM_OUTB(sd, sd->sd_MS);
1924         wait = 1000;  /* 1 second timeout in msec */
1925         while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1926                 ahc_delay(1000);  /* delay 1 msec */
1927         }
1928         if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1929                 SEEPROM_OUTB(sd, 0);
1930                 return (0);
1931         }
1932         return(1);
1933 }
1934
1935 void
1936 ahc_release_seeprom(struct seeprom_descriptor *sd)
1937 {
1938         /* Release access to the memory port and the serial EEPROM. */
1939         SEEPROM_OUTB(sd, 0);
1940 }
1941
1942 static void
1943 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1944 {
1945         uint8_t brdctl;
1946
1947         if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1948                 brdctl = BRDSTB;
1949                 if (ahc->channel == 'B')
1950                         brdctl |= BRDCS;
1951         } else if ((ahc->features & AHC_ULTRA2) != 0) {
1952                 brdctl = 0;
1953         } else {
1954                 brdctl = BRDSTB|BRDCS;
1955         }
1956         ahc_outb(ahc, BRDCTL, brdctl);
1957         ahc_flush_device_writes(ahc);
1958         brdctl |= value;
1959         ahc_outb(ahc, BRDCTL, brdctl);
1960         ahc_flush_device_writes(ahc);
1961         if ((ahc->features & AHC_ULTRA2) != 0)
1962                 brdctl |= BRDSTB_ULTRA2;
1963         else
1964                 brdctl &= ~BRDSTB;
1965         ahc_outb(ahc, BRDCTL, brdctl);
1966         ahc_flush_device_writes(ahc);
1967         if ((ahc->features & AHC_ULTRA2) != 0)
1968                 brdctl = 0;
1969         else
1970                 brdctl &= ~BRDCS;
1971         ahc_outb(ahc, BRDCTL, brdctl);
1972 }
1973
1974 static uint8_t
1975 read_brdctl(struct ahc_softc *ahc)
1976 {
1977         uint8_t brdctl;
1978         uint8_t value;
1979
1980         if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1981                 brdctl = BRDRW;
1982                 if (ahc->channel == 'B')
1983                         brdctl |= BRDCS;
1984         } else if ((ahc->features & AHC_ULTRA2) != 0) {
1985                 brdctl = BRDRW_ULTRA2;
1986         } else {
1987                 brdctl = BRDRW|BRDCS;
1988         }
1989         ahc_outb(ahc, BRDCTL, brdctl);
1990         ahc_flush_device_writes(ahc);
1991         value = ahc_inb(ahc, BRDCTL);
1992         ahc_outb(ahc, BRDCTL, 0);
1993         return (value);
1994 }
1995
1996 static void
1997 ahc_pci_intr(struct ahc_softc *ahc)
1998 {
1999         u_int error;
2000         u_int status1;
2001
2002         error = ahc_inb(ahc, ERROR);
2003         if ((error & PCIERRSTAT) == 0)
2004                 return;
2005
2006         status1 = ahc_pci_read_config(ahc->dev_softc,
2007                                       PCIR_STATUS + 1, /*bytes*/1);
2008
2009         printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
2010               ahc_name(ahc),
2011               ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
2012
2013         if (status1 & DPE) {
2014                 ahc->pci_target_perr_count++;
2015                 printf("%s: Data Parity Error Detected during address "
2016                        "or write data phase\n", ahc_name(ahc));
2017         }
2018         if (status1 & SSE) {
2019                 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
2020         }
2021         if (status1 & RMA) {
2022                 printf("%s: Received a Master Abort\n", ahc_name(ahc));
2023         }
2024         if (status1 & RTA) {
2025                 printf("%s: Received a Target Abort\n", ahc_name(ahc));
2026         }
2027         if (status1 & STA) {
2028                 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
2029         }
2030         if (status1 & DPR) {
2031                 printf("%s: Data Parity Error has been reported via PERR#\n",
2032                        ahc_name(ahc));
2033         }
2034
2035         /* Clear latched errors. */
2036         ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
2037                              status1, /*bytes*/1);
2038
2039         if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
2040                 printf("%s: Latched PCIERR interrupt with "
2041                        "no status bits set\n", ahc_name(ahc));
2042         } else {
2043                 ahc_outb(ahc, CLRINT, CLRPARERR);
2044         }
2045
2046         if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) {
2047                 printf(
2048 "%s: WARNING WARNING WARNING WARNING\n"
2049 "%s: Too many PCI parity errors observed as a target.\n"
2050 "%s: Some device on this bus is generating bad parity.\n"
2051 "%s: This is an error *observed by*, not *generated by*, this controller.\n"
2052 "%s: PCI parity error checking has been disabled.\n"
2053 "%s: WARNING WARNING WARNING WARNING\n",
2054                        ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2055                        ahc_name(ahc), ahc_name(ahc), ahc_name(ahc));
2056                 ahc->seqctl |= FAILDIS;
2057                 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2058         }
2059         ahc_unpause(ahc);
2060 }
2061
2062 static int
2063 ahc_pci_chip_init(struct ahc_softc *ahc)
2064 {
2065         ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2066         ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2067         if ((ahc->features & AHC_DT) != 0) {
2068                 u_int sfunct;
2069
2070                 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2071                 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2072                 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2073                 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2074                 ahc_outb(ahc, SFUNCT, sfunct);
2075                 ahc_outb(ahc, CRCCONTROL1,
2076                          ahc->bus_softc.pci_softc.crccontrol1);
2077         }
2078         if ((ahc->features & AHC_MULTI_FUNC) != 0)
2079                 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2080
2081         if ((ahc->features & AHC_ULTRA2) != 0)
2082                 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2083
2084         return (ahc_chip_init(ahc));
2085 }
2086
2087 static int
2088 ahc_pci_suspend(struct ahc_softc *ahc)
2089 {
2090         return (ahc_suspend(ahc));
2091 }
2092
2093 static int
2094 ahc_pci_resume(struct ahc_softc *ahc)
2095 {
2096
2097         ahc_power_state_change(ahc, AHC_POWER_STATE_D0);
2098
2099         /*
2100          * We assume that the OS has restored our register
2101          * mappings, etc.  Just update the config space registers
2102          * that the OS doesn't know about and rely on our chip
2103          * reset handler to handle the rest.
2104          */
2105         ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4,
2106                              ahc->bus_softc.pci_softc.devconfig);
2107         ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1,
2108                              ahc->bus_softc.pci_softc.command);
2109         ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1,
2110                              ahc->bus_softc.pci_softc.csize_lattime);
2111         if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2112                 struct  seeprom_descriptor sd;
2113                 u_int   sxfrctl1;
2114
2115                 sd.sd_ahc = ahc;
2116                 sd.sd_control_offset = SEECTL;
2117                 sd.sd_status_offset = SEECTL;
2118                 sd.sd_dataout_offset = SEECTL;
2119
2120                 ahc_acquire_seeprom(ahc, &sd);
2121                 configure_termination(ahc, &sd,
2122                                       ahc->seep_config->adapter_control,
2123                                       &sxfrctl1);
2124                 ahc_release_seeprom(&sd);
2125         }
2126         return (ahc_resume(ahc));
2127 }
2128
2129 static int
2130 ahc_aic785X_setup(struct ahc_softc *ahc)
2131 {
2132         ahc_dev_softc_t pci;
2133         uint8_t rev;
2134
2135         pci = ahc->dev_softc;
2136         ahc->channel = 'A';
2137         ahc->chip = AHC_AIC7850;
2138         ahc->features = AHC_AIC7850_FE;
2139         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2140         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2141         if (rev >= 1)
2142                 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2143         ahc->instruction_ram_size = 512;
2144         return (0);
2145 }
2146
2147 static int
2148 ahc_aic7860_setup(struct ahc_softc *ahc)
2149 {
2150         ahc_dev_softc_t pci;
2151         uint8_t rev;
2152
2153         pci = ahc->dev_softc;
2154         ahc->channel = 'A';
2155         ahc->chip = AHC_AIC7860;
2156         ahc->features = AHC_AIC7860_FE;
2157         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2158         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2159         if (rev >= 1)
2160                 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2161         ahc->instruction_ram_size = 512;
2162         return (0);
2163 }
2164
2165 static int
2166 ahc_apa1480_setup(struct ahc_softc *ahc)
2167 {
2168         int error;
2169
2170         error = ahc_aic7860_setup(ahc);
2171         if (error != 0)
2172                 return (error);
2173         ahc->features |= AHC_REMOVABLE;
2174         return (0);
2175 }
2176
2177 static int
2178 ahc_aic7870_setup(struct ahc_softc *ahc)
2179 {
2180
2181         ahc->channel = 'A';
2182         ahc->chip = AHC_AIC7870;
2183         ahc->features = AHC_AIC7870_FE;
2184         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2185         ahc->instruction_ram_size = 512;
2186         return (0);
2187 }
2188
2189 static int
2190 ahc_aha394X_setup(struct ahc_softc *ahc)
2191 {
2192         int error;
2193
2194         error = ahc_aic7870_setup(ahc);
2195         if (error == 0)
2196                 error = ahc_aha394XX_setup(ahc);
2197         return (error);
2198 }
2199
2200 static int
2201 ahc_aha398X_setup(struct ahc_softc *ahc)
2202 {
2203         int error;
2204
2205         error = ahc_aic7870_setup(ahc);
2206         if (error == 0)
2207                 error = ahc_aha398XX_setup(ahc);
2208         return (error);
2209 }
2210
2211 static int
2212 ahc_aha494X_setup(struct ahc_softc *ahc)
2213 {
2214         int error;
2215
2216         error = ahc_aic7870_setup(ahc);
2217         if (error == 0)
2218                 error = ahc_aha494XX_setup(ahc);
2219         return (error);
2220 }
2221
2222 static int
2223 ahc_aic7880_setup(struct ahc_softc *ahc)
2224 {
2225         ahc_dev_softc_t pci;
2226         uint8_t rev;
2227
2228         pci = ahc->dev_softc;
2229         ahc->channel = 'A';
2230         ahc->chip = AHC_AIC7880;
2231         ahc->features = AHC_AIC7880_FE;
2232         ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2233         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2234         if (rev >= 1) {
2235                 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2236         } else {
2237                 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2238         }
2239         ahc->instruction_ram_size = 512;
2240         return (0);
2241 }
2242
2243 static int
2244 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2245 {
2246
2247         ahc->flags |= AHC_INT50_SPEEDFLEX;
2248         return (ahc_aic7880_setup(ahc));
2249 }
2250
2251 static int
2252 ahc_aha394XU_setup(struct ahc_softc *ahc)
2253 {
2254         int error;
2255
2256         error = ahc_aic7880_setup(ahc);
2257         if (error == 0)
2258                 error = ahc_aha394XX_setup(ahc);
2259         return (error);
2260 }
2261
2262 static int
2263 ahc_aha398XU_setup(struct ahc_softc *ahc)
2264 {
2265         int error;
2266
2267         error = ahc_aic7880_setup(ahc);
2268         if (error == 0)
2269                 error = ahc_aha398XX_setup(ahc);
2270         return (error);
2271 }
2272
2273 static int
2274 ahc_aic7890_setup(struct ahc_softc *ahc)
2275 {
2276         ahc_dev_softc_t pci;
2277         uint8_t rev;
2278
2279         pci = ahc->dev_softc;
2280         ahc->channel = 'A';
2281         ahc->chip = AHC_AIC7890;
2282         ahc->features = AHC_AIC7890_FE;
2283         ahc->flags |= AHC_NEWEEPROM_FMT;
2284         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2285         if (rev == 0)
2286                 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2287         ahc->instruction_ram_size = 768;
2288         return (0);
2289 }
2290
2291 static int
2292 ahc_aic7892_setup(struct ahc_softc *ahc)
2293 {
2294
2295         ahc->channel = 'A';
2296         ahc->chip = AHC_AIC7892;
2297         ahc->features = AHC_AIC7892_FE;
2298         ahc->flags |= AHC_NEWEEPROM_FMT;
2299         ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2300         ahc->instruction_ram_size = 1024;
2301         return (0);
2302 }
2303
2304 static int
2305 ahc_aic7895_setup(struct ahc_softc *ahc)
2306 {
2307         ahc_dev_softc_t pci;
2308         uint8_t rev;
2309
2310         pci = ahc->dev_softc;
2311         ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2312         /*
2313          * The 'C' revision of the aic7895 has a few additional features.
2314          */
2315         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2316         if (rev >= 4) {
2317                 ahc->chip = AHC_AIC7895C;
2318                 ahc->features = AHC_AIC7895C_FE;
2319         } else  {
2320                 u_int command;
2321
2322                 ahc->chip = AHC_AIC7895;
2323                 ahc->features = AHC_AIC7895_FE;
2324
2325                 /*
2326                  * The BIOS disables the use of MWI transactions
2327                  * since it does not have the MWI bug work around
2328                  * we have.  Disabling MWI reduces performance, so
2329                  * turn it on again.
2330                  */
2331                 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2332                 command |= PCIM_CMD_MWRICEN;
2333                 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2334                 ahc->bugs |= AHC_PCI_MWI_BUG;
2335         }
2336         /*
2337          * XXX Does CACHETHEN really not work???  What about PCI retry?
2338          * on C level chips.  Need to test, but for now, play it safe.
2339          */
2340         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2341                   |  AHC_CACHETHEN_BUG;
2342
2343 #if 0
2344         uint32_t devconfig;
2345
2346         /*
2347          * Cachesize must also be zero due to stray DAC
2348          * problem when sitting behind some bridges.
2349          */
2350         ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2351         devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2352         devconfig |= MRDCEN;
2353         ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2354 #endif
2355         ahc->flags |= AHC_NEWEEPROM_FMT;
2356         ahc->instruction_ram_size = 512;
2357         return (0);
2358 }
2359
2360 static int
2361 ahc_aic7896_setup(struct ahc_softc *ahc)
2362 {
2363         ahc_dev_softc_t pci;
2364
2365         pci = ahc->dev_softc;
2366         ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2367         ahc->chip = AHC_AIC7896;
2368         ahc->features = AHC_AIC7896_FE;
2369         ahc->flags |= AHC_NEWEEPROM_FMT;
2370         ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2371         ahc->instruction_ram_size = 768;
2372         return (0);
2373 }
2374
2375 static int
2376 ahc_aic7899_setup(struct ahc_softc *ahc)
2377 {
2378         ahc_dev_softc_t pci;
2379
2380         pci = ahc->dev_softc;
2381         ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2382         ahc->chip = AHC_AIC7899;
2383         ahc->features = AHC_AIC7899_FE;
2384         ahc->flags |= AHC_NEWEEPROM_FMT;
2385         ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2386         ahc->instruction_ram_size = 1024;
2387         return (0);
2388 }
2389
2390 static int
2391 ahc_aha29160C_setup(struct ahc_softc *ahc)
2392 {
2393         int error;
2394
2395         error = ahc_aic7899_setup(ahc);
2396         if (error != 0)
2397                 return (error);
2398         ahc->features |= AHC_REMOVABLE;
2399         return (0);
2400 }
2401
2402 static int
2403 ahc_raid_setup(struct ahc_softc *ahc)
2404 {
2405         printf("RAID functionality unsupported\n");
2406         return (ENXIO);
2407 }
2408
2409 static int
2410 ahc_aha394XX_setup(struct ahc_softc *ahc)
2411 {
2412         ahc_dev_softc_t pci;
2413
2414         pci = ahc->dev_softc;
2415         switch (ahc_get_pci_slot(pci)) {
2416         case AHC_394X_SLOT_CHANNEL_A:
2417                 ahc->channel = 'A';
2418                 break;
2419         case AHC_394X_SLOT_CHANNEL_B:
2420                 ahc->channel = 'B';
2421                 break;
2422         default:
2423                 printf("adapter at unexpected slot %d\n"
2424                        "unable to map to a channel\n",
2425                        ahc_get_pci_slot(pci));
2426                 ahc->channel = 'A';
2427         }
2428         return (0);
2429 }
2430
2431 static int
2432 ahc_aha398XX_setup(struct ahc_softc *ahc)
2433 {
2434         ahc_dev_softc_t pci;
2435
2436         pci = ahc->dev_softc;
2437         switch (ahc_get_pci_slot(pci)) {
2438         case AHC_398X_SLOT_CHANNEL_A:
2439                 ahc->channel = 'A';
2440                 break;
2441         case AHC_398X_SLOT_CHANNEL_B:
2442                 ahc->channel = 'B';
2443                 break;
2444         case AHC_398X_SLOT_CHANNEL_C:
2445                 ahc->channel = 'C';
2446                 break;
2447         default:
2448                 printf("adapter at unexpected slot %d\n"
2449                        "unable to map to a channel\n",
2450                        ahc_get_pci_slot(pci));
2451                 ahc->channel = 'A';
2452                 break;
2453         }
2454         ahc->flags |= AHC_LARGE_SEEPROM;
2455         return (0);
2456 }
2457
2458 static int
2459 ahc_aha494XX_setup(struct ahc_softc *ahc)
2460 {
2461         ahc_dev_softc_t pci;
2462
2463         pci = ahc->dev_softc;
2464         switch (ahc_get_pci_slot(pci)) {
2465         case AHC_494X_SLOT_CHANNEL_A:
2466                 ahc->channel = 'A';
2467                 break;
2468         case AHC_494X_SLOT_CHANNEL_B:
2469                 ahc->channel = 'B';
2470                 break;
2471         case AHC_494X_SLOT_CHANNEL_C:
2472                 ahc->channel = 'C';
2473                 break;
2474         case AHC_494X_SLOT_CHANNEL_D:
2475                 ahc->channel = 'D';
2476                 break;
2477         default:
2478                 printf("adapter at unexpected slot %d\n"
2479                        "unable to map to a channel\n",
2480                        ahc_get_pci_slot(pci));
2481                 ahc->channel = 'A';
2482         }
2483         ahc->flags |= AHC_LARGE_SEEPROM;
2484         return (0);
2485 }
2486
2487 #endif