2 * Copyright (c) 2004-2006
3 * Damien Bergamini <damien.bergamini@free.fr>.
4 * Copyright (c) 2004, 2005
5 * Andrew Atrens <atrens@nortelnetworks.com>.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice unmodified, this list of conditions, and the following
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/iwi/if_iwireg.h,v 1.2.2.2 2006/01/29 13:54:19 damien Exp $
32 * $DragonFly: src/sys/dev/netif/iwi/if_iwireg.h,v 1.2 2006/05/18 13:51:45 sephe Exp $
35 #define IWI_CMD_RING_COUNT 16
36 #define IWI_TX_RING_COUNT 64
37 #define IWI_RX_RING_COUNT 32
39 #define IWI_TX_DESC_SIZE (sizeof (struct iwi_tx_desc))
40 #define IWI_CMD_DESC_SIZE (sizeof (struct iwi_cmd_desc))
42 #define IWI_CSR_INTR 0x0008
43 #define IWI_CSR_INTR_MASK 0x000c
44 #define IWI_CSR_INDIRECT_ADDR 0x0010
45 #define IWI_CSR_INDIRECT_DATA 0x0014
46 #define IWI_CSR_AUTOINC_ADDR 0x0018
47 #define IWI_CSR_AUTOINC_DATA 0x001c
48 #define IWI_CSR_RST 0x0020
49 #define IWI_CSR_CTL 0x0024
50 #define IWI_CSR_IO 0x0030
51 #define IWI_CSR_CMD_BASE 0x0200
52 #define IWI_CSR_CMD_SIZE 0x0204
53 #define IWI_CSR_TX1_BASE 0x0208
54 #define IWI_CSR_TX1_SIZE 0x020c
55 #define IWI_CSR_TX2_BASE 0x0210
56 #define IWI_CSR_TX2_SIZE 0x0214
57 #define IWI_CSR_TX3_BASE 0x0218
58 #define IWI_CSR_TX3_SIZE 0x021c
59 #define IWI_CSR_TX4_BASE 0x0220
60 #define IWI_CSR_TX4_SIZE 0x0224
61 #define IWI_CSR_CMD_RIDX 0x0280
62 #define IWI_CSR_TX1_RIDX 0x0284
63 #define IWI_CSR_TX2_RIDX 0x0288
64 #define IWI_CSR_TX3_RIDX 0x028c
65 #define IWI_CSR_TX4_RIDX 0x0290
66 #define IWI_CSR_RX_RIDX 0x02a0
67 #define IWI_CSR_RX_BASE 0x0500
68 #define IWI_CSR_TABLE0_SIZE 0x0700
69 #define IWI_CSR_TABLE0_BASE 0x0704
70 #define IWI_CSR_NODE_BASE 0x0c0c
71 #define IWI_CSR_CMD_WIDX 0x0f80
72 #define IWI_CSR_TX1_WIDX 0x0f84
73 #define IWI_CSR_TX2_WIDX 0x0f88
74 #define IWI_CSR_TX3_WIDX 0x0f8c
75 #define IWI_CSR_TX4_WIDX 0x0f90
76 #define IWI_CSR_RX_WIDX 0x0fa0
77 #define IWI_CSR_READ_INT 0x0ff4
80 #define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE
82 /* flags for IWI_CSR_INTR */
83 #define IWI_INTR_RX_DONE 0x00000002
84 #define IWI_INTR_CMD_DONE 0x00000800
85 #define IWI_INTR_TX1_DONE 0x00001000
86 #define IWI_INTR_TX2_DONE 0x00002000
87 #define IWI_INTR_TX3_DONE 0x00004000
88 #define IWI_INTR_TX4_DONE 0x00008000
89 #define IWI_INTR_FW_INITED 0x01000000
90 #define IWI_INTR_RADIO_OFF 0x04000000
91 #define IWI_INTR_FATAL_ERROR 0x40000000
92 #define IWI_INTR_PARITY_ERROR 0x80000000
94 #define IWI_INTR_MASK \
95 (IWI_INTR_RX_DONE | IWI_INTR_CMD_DONE | IWI_INTR_TX1_DONE | \
96 IWI_INTR_TX2_DONE | IWI_INTR_TX3_DONE | IWI_INTR_TX4_DONE | \
97 IWI_INTR_FW_INITED | IWI_INTR_RADIO_OFF | \
98 IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR)
100 /* flags for IWI_CSR_RST */
101 #define IWI_RST_PRINCETON_RESET 0x00000001
102 #define IWI_RST_SOFT_RESET 0x00000080
103 #define IWI_RST_MASTER_DISABLED 0x00000100
104 #define IWI_RST_STOP_MASTER 0x00000200
106 /* flags for IWI_CSR_CTL */
107 #define IWI_CTL_CLOCK_READY 0x00000001
108 #define IWI_CTL_ALLOW_STANDBY 0x00000002
109 #define IWI_CTL_INIT 0x00000004
111 /* flags for IWI_CSR_IO */
112 #define IWI_IO_RADIO_ENABLED 0x00010000
114 /* flags for IWI_CSR_READ_INT */
115 #define IWI_READ_INT_INIT_HOST 0x20000000
117 /* constants for command blocks */
118 #define IWI_CB_DEFAULT_CTL 0x8cea0000
119 #define IWI_CB_MAXDATALEN 8191
121 /* supported rates */
122 #define IWI_RATE_DS1 10
123 #define IWI_RATE_DS2 20
124 #define IWI_RATE_DS5 55
125 #define IWI_RATE_DS11 110
126 #define IWI_RATE_OFDM6 13
127 #define IWI_RATE_OFDM9 15
128 #define IWI_RATE_OFDM12 5
129 #define IWI_RATE_OFDM18 7
130 #define IWI_RATE_OFDM24 9
131 #define IWI_RATE_OFDM36 11
132 #define IWI_RATE_OFDM48 1
133 #define IWI_RATE_OFDM54 3
137 #define IWI_HDR_TYPE_DATA 0
138 #define IWI_HDR_TYPE_COMMAND 1
139 #define IWI_HDR_TYPE_NOTIF 3
140 #define IWI_HDR_TYPE_FRAME 9
144 #define IWI_HDR_FLAG_IRQ 0x04
150 uint32_t reserved[2];
152 #define IWI_NOTIF_TYPE_ASSOCIATION 10
153 #define IWI_NOTIF_TYPE_AUTHENTICATION 11
154 #define IWI_NOTIF_TYPE_SCAN_CHANNEL 12
155 #define IWI_NOTIF_TYPE_SCAN_COMPLETE 13
156 #define IWI_NOTIF_TYPE_BEACON 17
157 #define IWI_NOTIF_TYPE_CALIBRATION 20
158 #define IWI_NOTIF_TYPE_NOISE 25
164 /* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */
165 struct iwi_notif_authentication {
167 #define IWI_DEAUTHENTICATED 0
168 #define IWI_AUTHENTICATED 9
171 /* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */
172 struct iwi_notif_association {
174 #define IWI_DEASSOCIATED 0
175 #define IWI_ASSOCIATED 12
177 struct ieee80211_frame frame;
183 /* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */
184 struct iwi_notif_scan_channel {
186 uint8_t reserved[47];
189 /* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */
190 struct iwi_notif_scan_complete {
197 /* received frame header */
199 uint32_t reserved1[2];
210 uint8_t reserved2[2];
214 /* header for transmission */
219 uint8_t reserved2[3];
221 #define IWI_DATA_CMD_TX 0x0b
227 #define IWI_DATA_FLAG_SHPREAMBLE 0x04
228 #define IWI_DATA_FLAG_NO_WEP 0x20
229 #define IWI_DATA_FLAG_NEED_ACK 0x80
232 #define IWI_DATA_XFLAG_QOS 0x10
235 uint8_t wepkey[IEEE80211_KEYBUF_SIZE];
238 uint8_t reserved3[10];
239 struct ieee80211_qosframe_addr4 wh;
243 #define IWI_MAX_NSEG 6
245 uint32_t seg_addr[IWI_MAX_NSEG];
246 uint16_t seg_len[IWI_MAX_NSEG];
250 struct iwi_cmd_desc {
253 #define IWI_CMD_ENABLE 2
254 #define IWI_CMD_SET_CONFIG 6
255 #define IWI_CMD_SET_ESSID 8
256 #define IWI_CMD_SET_MAC_ADDRESS 11
257 #define IWI_CMD_SET_RTS_THRESHOLD 15
258 #define IWI_CMD_SET_FRAG_THRESHOLD 16
259 #define IWI_CMD_SET_POWER_MODE 17
260 #define IWI_CMD_SET_WEP_KEY 18
261 #define IWI_CMD_ASSOCIATE 21
262 #define IWI_CMD_SET_RATES 22
263 #define IWI_CMD_ABORT_SCAN 23
264 #define IWI_CMD_SET_WME_PARAMS 25
265 #define IWI_CMD_SCAN 26
266 #define IWI_CMD_SET_OPTIE 31
267 #define IWI_CMD_DISABLE 33
268 #define IWI_CMD_SET_IV 34
269 #define IWI_CMD_SET_TX_POWER 35
270 #define IWI_CMD_SET_SENSITIVITY 42
271 #define IWI_CMD_SET_WMEIE 84
278 /* node information (IBSS) */
279 struct iwi_ibssnode {
280 uint8_t bssid[IEEE80211_ADDR_LEN];
284 /* constants for 'mode' fields */
285 #define IWI_MODE_11A 0
286 #define IWI_MODE_11B 1
287 #define IWI_MODE_11G 2
289 /* possible values for command IWI_CMD_SET_POWER_MODE */
290 #define IWI_POWER_MODE_CAM 0
292 /* structure for command IWI_CMD_SET_RATES */
297 #define IWI_RATESET_TYPE_NEGOTIATED 0
298 #define IWI_RATESET_TYPE_SUPPORTED 1
304 /* structure for command IWI_CMD_SET_TX_POWER */
311 #define IWI_TXPOWER_MAX 20
312 #define IWI_TXPOWER_RATIO (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX)
316 /* structure for command IWI_CMD_ASSOCIATE */
317 struct iwi_associate {
320 #define IWI_AUTH_OPEN 0
321 #define IWI_AUTH_SHARED 1
322 #define IWI_AUTH_NONE 3
327 #define IWI_POLICY_WME 1
328 #define IWI_POLICY_WPA 2
332 uint8_t bssid[IEEE80211_ADDR_LEN];
337 uint8_t dst[IEEE80211_ADDR_LEN];
342 /* structure for command IWI_CMD_SCAN */
345 uint8_t channels[54];
346 #define IWI_CHAN_5GHZ (0 << 6)
347 #define IWI_CHAN_2GHZ (1 << 6)
350 #define IWI_SCAN_TYPE_PASSIVE 0x11
351 #define IWI_SCAN_TYPE_DIRECTED 0x22
352 #define IWI_SCAN_TYPE_BROADCAST 0x33
353 #define IWI_SCAN_TYPE_BDIRECTED 0x44
357 uint16_t passive; /* dwell time */
358 uint16_t directed; /* dwell time */
359 uint16_t broadcast; /* dwell time */
360 uint16_t bdirected; /* dwell time */
363 /* structure for command IWI_CMD_SET_CONFIG */
364 struct iwi_configuration {
365 uint8_t bluetooth_coexistence;
367 uint8_t answer_pbreq;
368 uint8_t allow_invalid_frames;
369 uint8_t multicast_enabled;
370 uint8_t drop_unicast_unencrypted;
371 uint8_t disable_unicast_decryption;
372 uint8_t drop_multicast_unencrypted;
373 uint8_t disable_multicast_decryption;
376 uint8_t use_protection;
377 uint8_t protection_ctsonly;
378 uint8_t enable_multicast_filtering;
379 uint8_t bluetooth_threshold;
381 uint8_t allow_beacon_and_probe_resp;
383 uint8_t noise_reported;
387 /* structure for command IWI_CMD_SET_WEP_KEY */
390 #define IWI_WEP_KEY_CMD_SETKEY 0x08
395 uint8_t key[IEEE80211_KEYBUF_SIZE];
398 /* structure for command IWI_CMD_SET_WME_PARAMS */
399 struct iwi_wme_params {
400 uint16_t cwmin[WME_NUM_AC];
401 uint16_t cwmax[WME_NUM_AC];
402 uint8_t aifsn[WME_NUM_AC];
403 uint8_t acm[WME_NUM_AC];
404 uint16_t burst[WME_NUM_AC];
407 #define IWI_MEM_EVENT_CTL 0x00300004
408 #define IWI_MEM_EEPROM_CTL 0x00300040
410 /* possible flags for register IWI_MEM_EVENT */
411 #define IWI_LED_ASSOC (1 << 5)
412 #define IWI_LED_MASK 0xd9fffffb
414 #define IWI_EEPROM_MAC 0x21
416 #define IWI_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
418 #define IWI_EEPROM_C (1 << 0) /* Serial Clock */
419 #define IWI_EEPROM_S (1 << 1) /* Chip Select */
420 #define IWI_EEPROM_D (1 << 2) /* Serial data input */
421 #define IWI_EEPROM_Q (1 << 4) /* Serial data output */
423 #define IWI_EEPROM_SHIFT_D 2
424 #define IWI_EEPROM_SHIFT_Q 4
427 * control and status registers access macros
429 #define CSR_READ_1(sc, reg) \
430 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
432 #define CSR_READ_2(sc, reg) \
433 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
435 #define CSR_READ_4(sc, reg) \
436 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
438 #define CSR_READ_REGION_4(sc, offset, datap, count) \
439 bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \
442 #define CSR_WRITE_1(sc, reg, val) \
443 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
445 #define CSR_WRITE_2(sc, reg, val) \
446 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
448 #define CSR_WRITE_4(sc, reg, val) \
449 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
451 #define CSR_WRITE_REGION_1(sc, offset, datap, count) \
452 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \
456 * indirect memory space access macros
458 #define MEM_READ_1(sc, addr) \
459 (CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)), \
460 CSR_READ_1((sc), IWI_CSR_INDIRECT_DATA))
462 #define MEM_READ_4(sc, addr) \
463 (CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)), \
464 CSR_READ_4((sc), IWI_CSR_INDIRECT_DATA))
466 #define MEM_WRITE_1(sc, addr, val) do { \
467 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
468 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \
469 } while (/* CONSTCOND */0)
471 #define MEM_WRITE_2(sc, addr, val) do { \
472 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
473 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
474 } while (/* CONSTCOND */0)
476 #define MEM_WRITE_4(sc, addr, val) do { \
477 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
478 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \
479 } while (/* CONSTCOND */0)
481 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \
482 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
483 CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len)); \
484 } while (/* CONSTCOND */0)
487 * EEPROM access macro
489 #define IWI_EEPROM_CTL(sc, val) do { \
490 MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \
491 DELAY(IWI_EEPROM_DELAY); \
492 } while (/* CONSTCOND */0)