2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.16 2004/03/22 10:22:26 joerg Exp $
39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Engineer, Wind River Systems
46 * The Broadcom BCM5700 is based on technology originally developed by
47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
51 * frames, highly configurable RX filtering, and 16 RX and TX queues
52 * (which, along with RX filter rules, can be used for QOS applications).
53 * Other features, such as TCP segmentation, may be available as part
54 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
55 * firmware images can be stored in hardware and need not be compiled
58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
61 * The BCM5701 is a single-chip solution incorporating both the BCM5700
62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
63 * does not support external SSRAM.
65 * Broadcom also produces a variation of the BCM5700 under the "Altima"
66 * brand name, which is functionally similar but lacks PCI-X support.
68 * Without external SSRAM, you can only have at most 4 TX rings,
69 * and the use of the mini RX ring is disabled. This seems to imply
70 * that these features are simply not available on the BCM5701. As a
71 * result, this driver does not implement any support for the mini RX
75 #include <sys/param.h>
76 #include <sys/systm.h>
77 #include <sys/sockio.h>
79 #include <sys/malloc.h>
80 #include <sys/kernel.h>
81 #include <sys/socket.h>
82 #include <sys/queue.h>
85 #include <net/if_arp.h>
86 #include <net/ethernet.h>
87 #include <net/if_dl.h>
88 #include <net/if_media.h>
92 #include <net/if_types.h>
93 #include <net/vlan/if_vlan_var.h>
95 #include <netinet/in_systm.h>
96 #include <netinet/in.h>
97 #include <netinet/ip.h>
99 #include <vm/vm.h> /* for vtophys */
100 #include <vm/pmap.h> /* for vtophys */
101 #include <machine/clock.h> /* for DELAY */
102 #include <machine/bus_memio.h>
103 #include <machine/bus.h>
104 #include <machine/resource.h>
106 #include <sys/rman.h>
108 #include <dev/netif/mii_layer/mii.h>
109 #include <dev/netif/mii_layer/miivar.h>
110 #include <dev/netif/mii_layer/miidevs.h>
111 #include <dev/netif/mii_layer/brgphyreg.h>
113 #include <bus/pci/pcidevs.h>
114 #include <bus/pci/pcireg.h>
115 #include <bus/pci/pcivar.h>
117 #include "if_bgereg.h"
119 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
121 /* "controller miibus0" required. See GENERIC if you get errors here. */
122 #include "miibus_if.h"
125 * Various supported device vendors/types and their names. Note: the
126 * spec seems to indicate that the hardware still has Alteon's vendor
127 * ID burned into it, though it will always be overriden by the vendor
128 * ID in the EEPROM. Just to be safe, we cover all possibilities.
130 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */
132 static struct bge_type bge_devs[] = {
133 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
134 "Broadcom BCM5700 Gigabit Ethernet" },
135 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
136 "Broadcom BCM5701 Gigabit Ethernet" },
137 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
138 "Broadcom BCM5700 Gigabit Ethernet" },
139 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
140 "Broadcom BCM5701 Gigabit Ethernet" },
141 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
142 "Broadcom BCM5702X Gigabit Ethernet" },
143 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5702X,
144 "Broadcom BCM5702X Gigabit Ethernet" },
145 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
146 "Broadcom BCM5703X Gigabit Ethernet" },
147 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5703X,
148 "Broadcom BCM5703X Gigabit Ethernet" },
149 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
150 "Broadcom BCM5704C Dual Gigabit Ethernet" },
151 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
152 "Broadcom BCM5704S Dual Gigabit Ethernet" },
153 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
154 "Broadcom BCM5705 Gigabit Ethernet" },
155 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
156 "Broadcom BCM5705M Gigabit Ethernet" },
157 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705_ALT,
158 "Broadcom BCM5705M Gigabit Ethernet" },
159 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
160 "Broadcom BCM5782 Gigabit Ethernet" },
161 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5788,
162 "Broadcom BCM5788 Gigabit Ethernet" },
163 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
164 "Broadcom BCM5901 Fast Ethernet" },
165 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
166 "Broadcom BCM5901A2 Fast Ethernet" },
167 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
168 "SysKonnect Gigabit Ethernet" },
169 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
170 "Altima AC1000 Gigabit Ethernet" },
171 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
172 "Altima AC1002 Gigabit Ethernet" },
173 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
174 "Altima AC9100 Gigabit Ethernet" },
178 static int bge_probe (device_t);
179 static int bge_attach (device_t);
180 static int bge_detach (device_t);
181 static void bge_release_resources
182 (struct bge_softc *);
183 static void bge_txeof (struct bge_softc *);
184 static void bge_rxeof (struct bge_softc *);
186 static void bge_tick (void *);
187 static void bge_stats_update (struct bge_softc *);
188 static void bge_stats_update_regs
189 (struct bge_softc *);
190 static int bge_encap (struct bge_softc *, struct mbuf *,
193 static void bge_intr (void *);
194 static void bge_start (struct ifnet *);
195 static int bge_ioctl (struct ifnet *, u_long, caddr_t);
196 static void bge_init (void *);
197 static void bge_stop (struct bge_softc *);
198 static void bge_watchdog (struct ifnet *);
199 static void bge_shutdown (device_t);
200 static int bge_ifmedia_upd (struct ifnet *);
201 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
203 static u_int8_t bge_eeprom_getbyte (struct bge_softc *,
205 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int);
207 static u_int32_t bge_crc (caddr_t);
208 static void bge_setmulti (struct bge_softc *);
210 static void bge_handle_events (struct bge_softc *);
211 static int bge_alloc_jumbo_mem (struct bge_softc *);
212 static void bge_free_jumbo_mem (struct bge_softc *);
213 static void *bge_jalloc (struct bge_softc *);
214 static void bge_jfree (caddr_t, u_int);
215 static void bge_jref (caddr_t, u_int);
216 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *);
217 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *);
218 static int bge_init_rx_ring_std (struct bge_softc *);
219 static void bge_free_rx_ring_std (struct bge_softc *);
220 static int bge_init_rx_ring_jumbo (struct bge_softc *);
221 static void bge_free_rx_ring_jumbo (struct bge_softc *);
222 static void bge_free_tx_ring (struct bge_softc *);
223 static int bge_init_tx_ring (struct bge_softc *);
225 static int bge_chipinit (struct bge_softc *);
226 static int bge_blockinit (struct bge_softc *);
229 static u_int8_t bge_vpd_readbyte (struct bge_softc *, int);
230 static void bge_vpd_read_res (struct bge_softc *,
231 struct vpd_res *, int);
232 static void bge_vpd_read (struct bge_softc *);
235 static u_int32_t bge_readmem_ind
236 (struct bge_softc *, int);
237 static void bge_writemem_ind (struct bge_softc *, int, int);
239 static u_int32_t bge_readreg_ind
240 (struct bge_softc *, int);
242 static void bge_writereg_ind (struct bge_softc *, int, int);
244 static int bge_miibus_readreg (device_t, int, int);
245 static int bge_miibus_writereg (device_t, int, int, int);
246 static void bge_miibus_statchg (device_t);
248 static void bge_reset (struct bge_softc *);
250 static device_method_t bge_methods[] = {
251 /* Device interface */
252 DEVMETHOD(device_probe, bge_probe),
253 DEVMETHOD(device_attach, bge_attach),
254 DEVMETHOD(device_detach, bge_detach),
255 DEVMETHOD(device_shutdown, bge_shutdown),
258 DEVMETHOD(bus_print_child, bus_generic_print_child),
259 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
262 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
263 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
264 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
269 static driver_t bge_driver = {
272 sizeof(struct bge_softc)
275 static devclass_t bge_devclass;
277 DECLARE_DUMMY_MODULE(if_bge);
278 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
279 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
282 bge_readmem_ind(sc, off)
283 struct bge_softc *sc;
290 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
291 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
295 bge_writemem_ind(sc, off, val)
296 struct bge_softc *sc;
303 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
304 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
311 bge_readreg_ind(sc, off)
312 struct bge_softc *sc;
319 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
320 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
325 bge_writereg_ind(sc, off, val)
326 struct bge_softc *sc;
333 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
334 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
341 bge_vpd_readbyte(sc, addr)
342 struct bge_softc *sc;
350 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
351 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
353 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
357 if (i == BGE_TIMEOUT) {
358 printf("bge%d: VPD read timed out\n", sc->bge_unit);
362 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
364 return((val >> ((addr % 4) * 8)) & 0xFF);
368 bge_vpd_read_res(sc, res, addr)
369 struct bge_softc *sc;
376 ptr = (u_int8_t *)res;
377 for (i = 0; i < sizeof(struct vpd_res); i++)
378 ptr[i] = bge_vpd_readbyte(sc, i + addr);
385 struct bge_softc *sc;
390 if (sc->bge_vpd_prodname != NULL)
391 free(sc->bge_vpd_prodname, M_DEVBUF);
392 if (sc->bge_vpd_readonly != NULL)
393 free(sc->bge_vpd_readonly, M_DEVBUF);
394 sc->bge_vpd_prodname = NULL;
395 sc->bge_vpd_readonly = NULL;
397 bge_vpd_read_res(sc, &res, pos);
399 if (res.vr_id != VPD_RES_ID) {
400 printf("bge%d: bad VPD resource id: expected %x got %x\n",
401 sc->bge_unit, VPD_RES_ID, res.vr_id);
406 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
407 for (i = 0; i < res.vr_len; i++)
408 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
409 sc->bge_vpd_prodname[i] = '\0';
412 bge_vpd_read_res(sc, &res, pos);
414 if (res.vr_id != VPD_RES_READ) {
415 printf("bge%d: bad VPD resource id: expected %x got %x\n",
416 sc->bge_unit, VPD_RES_READ, res.vr_id);
421 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
422 for (i = 0; i < res.vr_len + 1; i++)
423 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
430 * Read a byte of data stored in the EEPROM at address 'addr.' The
431 * BCM570x supports both the traditional bitbang interface and an
432 * auto access interface for reading the EEPROM. We use the auto
436 bge_eeprom_getbyte(sc, addr, dest)
437 struct bge_softc *sc;
445 * Enable use of auto EEPROM access so we can avoid
446 * having to use the bitbang method.
448 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
450 /* Reset the EEPROM, load the clock period. */
451 CSR_WRITE_4(sc, BGE_EE_ADDR,
452 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
455 /* Issue the read EEPROM command. */
456 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
458 /* Wait for completion */
459 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
461 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
465 if (i == BGE_TIMEOUT) {
466 printf("bge%d: eeprom read timed out\n", sc->bge_unit);
471 byte = CSR_READ_4(sc, BGE_EE_DATA);
473 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
479 * Read a sequence of bytes from the EEPROM.
482 bge_read_eeprom(sc, dest, off, cnt)
483 struct bge_softc *sc;
491 for (i = 0; i < cnt; i++) {
492 err = bge_eeprom_getbyte(sc, off + i, &byte);
502 bge_miibus_readreg(dev, phy, reg)
506 struct bge_softc *sc;
508 u_int32_t val, autopoll;
511 sc = device_get_softc(dev);
512 ifp = &sc->arpcom.ac_if;
515 * Broadcom's own driver always assumes the internal
516 * PHY is at GMII address 1. On some chips, the PHY responds
517 * to accesses at all addresses, which could cause us to
518 * bogusly attach the PHY 32 times at probe type. Always
519 * restricting the lookup to address 1 is simpler than
520 * trying to figure out which chips revisions should be
526 /* Reading with autopolling on may trigger PCI errors */
527 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
528 if (autopoll & BGE_MIMODE_AUTOPOLL) {
529 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
533 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
534 BGE_MIPHY(phy)|BGE_MIREG(reg));
536 for (i = 0; i < BGE_TIMEOUT; i++) {
537 val = CSR_READ_4(sc, BGE_MI_COMM);
538 if (!(val & BGE_MICOMM_BUSY))
542 if (i == BGE_TIMEOUT) {
543 printf("bge%d: PHY read timed out\n", sc->bge_unit);
548 val = CSR_READ_4(sc, BGE_MI_COMM);
551 if (autopoll & BGE_MIMODE_AUTOPOLL) {
552 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
556 if (val & BGE_MICOMM_READFAIL)
559 return(val & 0xFFFF);
563 bge_miibus_writereg(dev, phy, reg, val)
567 struct bge_softc *sc;
571 sc = device_get_softc(dev);
573 /* Reading with autopolling on may trigger PCI errors */
574 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
575 if (autopoll & BGE_MIMODE_AUTOPOLL) {
576 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
580 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
581 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
583 for (i = 0; i < BGE_TIMEOUT; i++) {
584 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
588 if (autopoll & BGE_MIMODE_AUTOPOLL) {
589 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
593 if (i == BGE_TIMEOUT) {
594 printf("bge%d: PHY read timed out\n", sc->bge_unit);
602 bge_miibus_statchg(dev)
605 struct bge_softc *sc;
606 struct mii_data *mii;
608 sc = device_get_softc(dev);
609 mii = device_get_softc(sc->bge_miibus);
611 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
612 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) {
613 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
615 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
618 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
619 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
621 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
628 * Handle events that have triggered interrupts.
631 bge_handle_events(sc)
632 struct bge_softc *sc;
639 * Memory management for jumbo frames.
643 bge_alloc_jumbo_mem(sc)
644 struct bge_softc *sc;
648 struct bge_jpool_entry *entry;
650 /* Grab a big chunk o' storage. */
651 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
652 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
654 if (sc->bge_cdata.bge_jumbo_buf == NULL) {
655 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit);
659 SLIST_INIT(&sc->bge_jfree_listhead);
660 SLIST_INIT(&sc->bge_jinuse_listhead);
663 * Now divide it up into 9K pieces and save the addresses
664 * in an array. Note that we play an evil trick here by using
665 * the first few bytes in the buffer to hold the the address
666 * of the softc structure for this interface. This is because
667 * bge_jfree() needs it, but it is called by the mbuf management
668 * code which will not pass it to us explicitly.
670 ptr = sc->bge_cdata.bge_jumbo_buf;
671 for (i = 0; i < BGE_JSLOTS; i++) {
673 aptr = (u_int64_t **)ptr;
674 aptr[0] = (u_int64_t *)sc;
675 ptr += sizeof(u_int64_t);
676 sc->bge_cdata.bge_jslots[i].bge_buf = ptr;
677 sc->bge_cdata.bge_jslots[i].bge_inuse = 0;
678 ptr += (BGE_JLEN - sizeof(u_int64_t));
679 entry = malloc(sizeof(struct bge_jpool_entry),
682 contigfree(sc->bge_cdata.bge_jumbo_buf,
684 sc->bge_cdata.bge_jumbo_buf = NULL;
685 printf("bge%d: no memory for jumbo "
686 "buffer queue!\n", sc->bge_unit);
690 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
691 entry, jpool_entries);
698 bge_free_jumbo_mem(sc)
699 struct bge_softc *sc;
702 struct bge_jpool_entry *entry;
704 for (i = 0; i < BGE_JSLOTS; i++) {
705 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
706 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
707 free(entry, M_DEVBUF);
710 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
716 * Allocate a jumbo buffer.
720 struct bge_softc *sc;
722 struct bge_jpool_entry *entry;
724 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
727 printf("bge%d: no free jumbo buffers\n", sc->bge_unit);
731 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
732 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
733 sc->bge_cdata.bge_jslots[entry->slot].bge_inuse = 1;
734 return(sc->bge_cdata.bge_jslots[entry->slot].bge_buf);
738 * Adjust usage count on a jumbo buffer.
745 struct bge_softc *sc;
749 /* Extract the softc struct pointer. */
750 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
751 sc = (struct bge_softc *)(aptr[0]);
754 panic("bge_jref: can't find softc pointer!");
756 if (size != BGE_JUMBO_FRAMELEN)
757 panic("bge_jref: adjusting refcount of buf of wrong size!");
759 /* calculate the slot this buffer belongs to */
761 i = ((vm_offset_t)aptr
762 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
764 if ((i < 0) || (i >= BGE_JSLOTS))
765 panic("bge_jref: asked to reference buffer "
766 "that we don't manage!");
767 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0)
768 panic("bge_jref: buffer already free!");
770 sc->bge_cdata.bge_jslots[i].bge_inuse++;
776 * Release a jumbo buffer.
783 struct bge_softc *sc;
786 struct bge_jpool_entry *entry;
788 /* Extract the softc struct pointer. */
789 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
790 sc = (struct bge_softc *)(aptr[0]);
793 panic("bge_jfree: can't find softc pointer!");
795 if (size != BGE_JUMBO_FRAMELEN)
796 panic("bge_jfree: freeing buffer of wrong size!");
798 /* calculate the slot this buffer belongs to */
800 i = ((vm_offset_t)aptr
801 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
803 if ((i < 0) || (i >= BGE_JSLOTS))
804 panic("bge_jfree: asked to free buffer that we don't manage!");
805 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0)
806 panic("bge_jfree: buffer already free!");
808 sc->bge_cdata.bge_jslots[i].bge_inuse--;
809 if(sc->bge_cdata.bge_jslots[i].bge_inuse == 0) {
810 entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
812 panic("bge_jfree: buffer not in use!");
814 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead,
816 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
817 entry, jpool_entries);
826 * Intialize a standard receive ring descriptor.
829 bge_newbuf_std(sc, i, m)
830 struct bge_softc *sc;
834 struct mbuf *m_new = NULL;
838 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
843 MCLGET(m_new, M_DONTWAIT);
844 if (!(m_new->m_flags & M_EXT)) {
848 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
851 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
852 m_new->m_data = m_new->m_ext.ext_buf;
855 if (!sc->bge_rx_alignment_bug)
856 m_adj(m_new, ETHER_ALIGN);
857 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
858 r = &sc->bge_rdata->bge_rx_std_ring[i];
859 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
860 r->bge_flags = BGE_RXBDFLAG_END;
861 r->bge_len = m_new->m_len;
868 * Initialize a jumbo receive ring descriptor. This allocates
869 * a jumbo buffer from the pool managed internally by the driver.
872 bge_newbuf_jumbo(sc, i, m)
873 struct bge_softc *sc;
877 struct mbuf *m_new = NULL;
883 /* Allocate the mbuf. */
884 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
889 /* Allocate the jumbo buffer */
890 buf = bge_jalloc(sc);
893 printf("bge%d: jumbo allocation failed "
894 "-- packet dropped!\n", sc->bge_unit);
898 /* Attach the buffer to the mbuf. */
899 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
900 m_new->m_flags |= M_EXT;
901 m_new->m_len = m_new->m_pkthdr.len =
902 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
903 m_new->m_ext.ext_free = bge_jfree;
904 m_new->m_ext.ext_ref = bge_jref;
907 m_new->m_data = m_new->m_ext.ext_buf;
908 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
911 if (!sc->bge_rx_alignment_bug)
912 m_adj(m_new, ETHER_ALIGN);
913 /* Set up the descriptor. */
914 r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
915 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
916 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
917 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
918 r->bge_len = m_new->m_len;
925 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
926 * that's 1MB or memory, which is a lot. For now, we fill only the first
927 * 256 ring entries and hope that our CPU is fast enough to keep up with
931 bge_init_rx_ring_std(sc)
932 struct bge_softc *sc;
936 for (i = 0; i < BGE_SSLOTS; i++) {
937 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
942 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
948 bge_free_rx_ring_std(sc)
949 struct bge_softc *sc;
953 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
954 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
955 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
956 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
958 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i],
959 sizeof(struct bge_rx_bd));
966 bge_init_rx_ring_jumbo(sc)
967 struct bge_softc *sc;
972 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
973 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
977 sc->bge_jumbo = i - 1;
979 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
980 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
981 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
983 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
989 bge_free_rx_ring_jumbo(sc)
990 struct bge_softc *sc;
994 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
995 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
996 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
997 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
999 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i],
1000 sizeof(struct bge_rx_bd));
1007 bge_free_tx_ring(sc)
1008 struct bge_softc *sc;
1012 if (sc->bge_rdata->bge_tx_ring == NULL)
1015 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1016 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1017 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1018 sc->bge_cdata.bge_tx_chain[i] = NULL;
1020 bzero((char *)&sc->bge_rdata->bge_tx_ring[i],
1021 sizeof(struct bge_tx_bd));
1028 bge_init_tx_ring(sc)
1029 struct bge_softc *sc;
1032 sc->bge_tx_saved_considx = 0;
1034 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1035 /* 5700 b2 errata */
1036 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1037 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1039 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1040 /* 5700 b2 errata */
1041 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1042 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1047 #define BGE_POLY 0xEDB88320
1053 u_int32_t idx, bit, data, crc;
1055 /* Compute CRC for the address value. */
1056 crc = 0xFFFFFFFF; /* initial value */
1058 for (idx = 0; idx < 6; idx++) {
1059 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1060 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0);
1068 struct bge_softc *sc;
1071 struct ifmultiaddr *ifma;
1072 u_int32_t hashes[4] = { 0, 0, 0, 0 };
1075 ifp = &sc->arpcom.ac_if;
1077 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1078 for (i = 0; i < 4; i++)
1079 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1083 /* First, zot all the existing filters. */
1084 for (i = 0; i < 4; i++)
1085 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1087 /* Now program new ones. */
1088 for (ifma = ifp->if_multiaddrs.lh_first;
1089 ifma != NULL; ifma = ifma->ifma_link.le_next) {
1090 if (ifma->ifma_addr->sa_family != AF_LINK)
1092 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1093 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1096 for (i = 0; i < 4; i++)
1097 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1103 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1104 * self-test results.
1108 struct bge_softc *sc;
1111 u_int32_t dma_rw_ctl;
1113 /* Set endianness before we access any non-PCI registers. */
1114 #if BYTE_ORDER == BIG_ENDIAN
1115 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1116 BGE_BIGENDIAN_INIT, 4);
1118 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1119 BGE_LITTLEENDIAN_INIT, 4);
1123 * Check the 'ROM failed' bit on the RX CPU to see if
1124 * self-tests passed.
1126 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1127 printf("bge%d: RX CPU self-diagnostics failed!\n",
1132 /* Clear the MAC control register */
1133 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1136 * Clear the MAC statistics block in the NIC's
1139 for (i = BGE_STATS_BLOCK;
1140 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
1141 BGE_MEMWIN_WRITE(sc, i, 0);
1143 for (i = BGE_STATUS_BLOCK;
1144 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
1145 BGE_MEMWIN_WRITE(sc, i, 0);
1147 /* Set up the PCI DMA control register. */
1148 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1149 BGE_PCISTATE_PCI_BUSMODE) {
1150 /* Conventional PCI bus */
1151 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1152 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1153 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1158 * The 5704 uses a different encoding of read/write
1161 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1162 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1163 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1164 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1166 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1167 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1168 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1172 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1173 * for hardware bugs.
1175 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1176 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1179 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1180 if (tmp == 0x6 || tmp == 0x7)
1181 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1185 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1186 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1187 sc->bge_asicrev == BGE_ASICREV_BCM5705)
1188 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1189 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1192 * Set up general mode register.
1194 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1195 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1196 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1197 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1200 * Disable memory write invalidate. Apparently it is not supported
1201 * properly by these devices.
1203 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1205 #ifdef __brokenalpha__
1207 * Must insure that we do not cross an 8K (bytes) boundary
1208 * for DMA reads. Our highest limit is 1K bytes. This is a
1209 * restriction on some ALPHA platforms with early revision
1210 * 21174 PCI chipsets, such as the AlphaPC 164lx
1212 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1213 BGE_PCI_READ_BNDRY_1024BYTES, 4);
1216 /* Set the timer prescaler (always 66Mhz) */
1217 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1224 struct bge_softc *sc;
1226 struct bge_rcb *rcb;
1227 volatile struct bge_rcb *vrcb;
1231 * Initialize the memory window pointer register so that
1232 * we can access the first 32K of internal NIC RAM. This will
1233 * allow us to set up the TX send ring RCBs and the RX return
1234 * ring RCBs, plus other things which live in NIC memory.
1236 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1238 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1240 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1241 /* Configure mbuf memory pool */
1242 if (sc->bge_extram) {
1243 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1245 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1246 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1248 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1250 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1252 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1253 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1255 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1258 /* Configure DMA resource pool */
1259 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1260 BGE_DMA_DESCRIPTORS);
1261 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1264 /* Configure mbuf pool watermarks */
1265 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
1266 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1267 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1269 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1270 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1272 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1274 /* Configure DMA resource watermarks */
1275 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1276 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1278 /* Enable buffer manager */
1279 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1280 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1281 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1283 /* Poll for buffer manager start indication */
1284 for (i = 0; i < BGE_TIMEOUT; i++) {
1285 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1290 if (i == BGE_TIMEOUT) {
1291 printf("bge%d: buffer manager failed to start\n",
1297 /* Enable flow-through queues */
1298 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1299 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1301 /* Wait until queue initialization is complete */
1302 for (i = 0; i < BGE_TIMEOUT; i++) {
1303 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1308 if (i == BGE_TIMEOUT) {
1309 printf("bge%d: flow-through queue init failed\n",
1314 /* Initialize the standard RX ring control block */
1315 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1316 BGE_HOSTADDR(rcb->bge_hostaddr,
1317 vtophys(&sc->bge_rdata->bge_rx_std_ring));
1318 if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
1319 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1321 rcb->bge_maxlen_flags =
1322 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1324 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1326 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1327 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1328 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1329 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1330 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1333 * Initialize the jumbo RX ring control block
1334 * We set the 'ring disabled' bit in the flags
1335 * field until we're actually ready to start
1336 * using this ring (i.e. once we set the MTU
1337 * high enough to require it).
1339 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1340 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1341 BGE_HOSTADDR(rcb->bge_hostaddr,
1342 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring));
1343 rcb->bge_maxlen_flags =
1344 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1345 BGE_RCB_FLAG_RING_DISABLED);
1347 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1349 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1350 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1351 rcb->bge_hostaddr.bge_addr_hi);
1352 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1353 rcb->bge_hostaddr.bge_addr_lo);
1354 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1355 rcb->bge_maxlen_flags);
1356 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1358 /* Set up dummy disabled mini ring RCB */
1359 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1360 rcb->bge_maxlen_flags =
1361 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1362 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1363 rcb->bge_maxlen_flags);
1367 * Set the BD ring replentish thresholds. The recommended
1368 * values are 1/8th the number of descriptors allocated to
1371 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1372 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1375 * Disable all unused send rings by setting the 'ring disabled'
1376 * bit in the flags field of all the TX send ring control blocks.
1377 * These are located in NIC memory.
1379 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1381 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1382 vrcb->bge_maxlen_flags =
1383 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1384 vrcb->bge_nicaddr = 0;
1388 /* Configure TX RCB 0 (we use only the first ring) */
1389 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1391 vrcb->bge_hostaddr.bge_addr_hi = 0;
1392 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring));
1393 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1394 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1395 vrcb->bge_maxlen_flags =
1396 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1398 /* Disable all unused RX return rings */
1399 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1400 BGE_RX_RETURN_RING_RCB);
1401 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1402 vrcb->bge_hostaddr.bge_addr_hi = 0;
1403 vrcb->bge_hostaddr.bge_addr_lo = 0;
1404 vrcb->bge_maxlen_flags =
1405 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1406 BGE_RCB_FLAG_RING_DISABLED);
1407 vrcb->bge_nicaddr = 0;
1408 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1409 (i * (sizeof(u_int64_t))), 0);
1413 /* Initialize RX ring indexes */
1414 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1415 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1416 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1419 * Set up RX return ring 0
1420 * Note that the NIC address for RX return rings is 0x00000000.
1421 * The return rings live entirely within the host, so the
1422 * nicaddr field in the RCB isn't used.
1424 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1425 BGE_RX_RETURN_RING_RCB);
1426 vrcb->bge_hostaddr.bge_addr_hi = 0;
1427 BGE_HOSTADDR(vrcb->bge_hostaddr,
1428 vtophys(&sc->bge_rdata->bge_rx_return_ring));
1429 vrcb->bge_nicaddr = 0x00000000;
1430 vrcb->bge_maxlen_flags =
1431 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
1433 /* Set random backoff seed for TX */
1434 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1435 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1436 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1437 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1438 BGE_TX_BACKOFF_SEED_MASK);
1440 /* Set inter-packet gap */
1441 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1444 * Specify which ring to use for packets that don't match
1447 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1450 * Configure number of RX lists. One interrupt distribution
1451 * list, sixteen active lists, one bad frames class.
1453 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1455 /* Inialize RX list placement stats mask. */
1456 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1457 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1459 /* Disable host coalescing until we get it set up */
1460 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1462 /* Poll to make sure it's shut down. */
1463 for (i = 0; i < BGE_TIMEOUT; i++) {
1464 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1469 if (i == BGE_TIMEOUT) {
1470 printf("bge%d: host coalescing engine failed to idle\n",
1475 /* Set up host coalescing defaults */
1476 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1477 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1478 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1479 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1480 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1481 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1482 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1484 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1485 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1487 /* Set up address of statistics block */
1488 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1489 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1490 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1491 vtophys(&sc->bge_rdata->bge_info.bge_stats));
1493 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1494 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1495 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1498 /* Set up address of status block */
1499 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1500 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1501 vtophys(&sc->bge_rdata->bge_status_block));
1503 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1504 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1506 /* Turn on host coalescing state machine */
1507 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1509 /* Turn on RX BD completion state machine and enable attentions */
1510 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1511 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1513 /* Turn on RX list placement state machine */
1514 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1516 /* Turn on RX list selector state machine. */
1517 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1518 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1520 /* Turn on DMA, clear stats */
1521 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1522 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1523 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1524 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1525 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1527 /* Set misc. local control, enable interrupts on attentions */
1528 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1531 /* Assert GPIO pins for PHY reset */
1532 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1533 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1534 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1535 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1538 /* Turn on DMA completion state machine */
1539 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1540 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1542 /* Turn on write DMA state machine */
1543 CSR_WRITE_4(sc, BGE_WDMA_MODE,
1544 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1546 /* Turn on read DMA state machine */
1547 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1548 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1550 /* Turn on RX data completion state machine */
1551 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1553 /* Turn on RX BD initiator state machine */
1554 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1556 /* Turn on RX data and RX BD initiator state machine */
1557 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1559 /* Turn on Mbuf cluster free state machine */
1560 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1561 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1563 /* Turn on send BD completion state machine */
1564 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1566 /* Turn on send data completion state machine */
1567 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1569 /* Turn on send data initiator state machine */
1570 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1572 /* Turn on send BD initiator state machine */
1573 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1575 /* Turn on send BD selector state machine */
1576 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1578 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1579 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1580 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1582 /* ack/clear link change events */
1583 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1584 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1585 BGE_MACSTAT_LINK_CHANGED);
1587 /* Enable PHY auto polling (for MII/GMII only) */
1589 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1591 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1592 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1593 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1594 BGE_EVTENB_MI_INTERRUPT);
1597 /* Enable link state change attentions. */
1598 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1604 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1605 * against our list and return its name if we find a match. Note
1606 * that since the Broadcom controller contains VPD support, we
1607 * can get the device name string from the controller itself instead
1608 * of the compiled-in string. This is a little slow, but it guarantees
1609 * we'll always announce the right product name.
1616 struct bge_softc *sc;
1621 sc = device_get_softc(dev);
1622 bzero(sc, sizeof(struct bge_softc));
1623 sc->bge_unit = device_get_unit(dev);
1626 while(t->bge_name != NULL) {
1627 if ((pci_get_vendor(dev) == t->bge_vid) &&
1628 (pci_get_device(dev) == t->bge_did)) {
1631 device_set_desc(dev, sc->bge_vpd_prodname);
1633 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
1634 if (descbuf == NULL)
1636 snprintf(descbuf, BGE_DEVDESC_MAX,
1637 "%s, ASIC rev. %#04x", t->bge_name,
1638 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1639 device_set_desc_copy(dev, descbuf);
1640 if (pci_get_subvendor(dev) == DELL_VENDORID)
1641 sc->bge_no_3_led = 1;
1642 free(descbuf, M_TEMP);
1658 struct bge_softc *sc;
1659 u_int32_t hwcfg = 0;
1660 u_int32_t mac_addr = 0;
1661 int unit, error = 0, rid;
1662 uint8_t ether_addr[ETHER_ADDR_LEN];
1666 sc = device_get_softc(dev);
1667 unit = device_get_unit(dev);
1669 sc->bge_unit = unit;
1672 * Map control/status registers.
1674 command = pci_read_config(dev, PCIR_COMMAND, 4);
1675 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1676 pci_write_config(dev, PCIR_COMMAND, command, 4);
1677 command = pci_read_config(dev, PCIR_COMMAND, 4);
1679 if (!(command & PCIM_CMD_MEMEN)) {
1680 printf("bge%d: failed to enable memory mapping!\n", unit);
1686 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1687 0, ~0, 1, RF_ACTIVE);
1689 if (sc->bge_res == NULL) {
1690 printf ("bge%d: couldn't map memory\n", unit);
1695 sc->bge_btag = rman_get_bustag(sc->bge_res);
1696 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1697 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1700 * XXX FIXME: rman_get_virtual() on the alpha is currently
1701 * broken and returns a physical address instead of a kernel
1702 * virtual address. Consequently, we need to do a little
1703 * extra mangling of the vhandle on the alpha. This should
1704 * eventually be fixed! The whole idea here is to get rid
1705 * of platform dependencies.
1708 if (pci_cvt_to_bwx(sc->bge_vhandle))
1709 sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle);
1711 sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle);
1712 sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle);
1715 /* Allocate interrupt */
1718 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1719 RF_SHAREABLE | RF_ACTIVE);
1721 if (sc->bge_irq == NULL) {
1722 printf("bge%d: couldn't map interrupt\n", unit);
1727 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET,
1728 bge_intr, sc, &sc->bge_intrhand);
1731 bge_release_resources(sc);
1732 printf("bge%d: couldn't set up irq\n", unit);
1736 sc->bge_unit = unit;
1738 /* Try to reset the chip. */
1741 if (bge_chipinit(sc)) {
1742 printf("bge%d: chip initialization failed\n", sc->bge_unit);
1743 bge_release_resources(sc);
1749 * Get station address from the EEPROM.
1751 mac_addr = bge_readmem_ind(sc, 0x0c14);
1752 if ((mac_addr >> 16) == 0x484b) {
1753 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1754 ether_addr[1] = (uint8_t)mac_addr;
1755 mac_addr = bge_readmem_ind(sc, 0x0c18);
1756 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1757 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1758 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1759 ether_addr[5] = (uint8_t)mac_addr;
1760 } else if (bge_read_eeprom(sc, ether_addr,
1761 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1762 printf("bge%d: failed to read station address\n", unit);
1763 bge_release_resources(sc);
1769 * A Broadcom chip was detected. Inform the world.
1771 printf("bge%d: Ethernet address: %6D\n", unit,
1772 sc->arpcom.ac_enaddr, ":");
1774 /* Allocate the general information block and ring buffers. */
1775 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1776 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1778 if (sc->bge_rdata == NULL) {
1779 bge_release_resources(sc);
1781 printf("bge%d: no memory for list buffers!\n", sc->bge_unit);
1785 bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1787 /* Save ASIC rev. */
1790 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1791 BGE_PCIMISCCTL_ASICREV;
1792 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1793 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1796 * Try to allocate memory for jumbo buffers.
1797 * The 5705 does not appear to support jumbo frames.
1799 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1800 if (bge_alloc_jumbo_mem(sc)) {
1801 printf("bge%d: jumbo buffer allocation "
1802 "failed\n", sc->bge_unit);
1803 bge_release_resources(sc);
1809 /* Set default tuneable values. */
1810 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1811 sc->bge_rx_coal_ticks = 150;
1812 sc->bge_tx_coal_ticks = 150;
1813 sc->bge_rx_max_coal_bds = 64;
1814 sc->bge_tx_max_coal_bds = 128;
1816 /* 5705 limits RX return ring to 512 entries. */
1817 if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
1818 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1820 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1822 /* Set up ifnet structure */
1823 ifp = &sc->arpcom.ac_if;
1825 if_initname(ifp, "bge", sc->bge_unit);
1826 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1827 ifp->if_ioctl = bge_ioctl;
1828 ifp->if_output = ether_output;
1829 ifp->if_start = bge_start;
1830 ifp->if_watchdog = bge_watchdog;
1831 ifp->if_init = bge_init;
1832 ifp->if_mtu = ETHERMTU;
1833 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1;
1834 ifp->if_hwassist = BGE_CSUM_FEATURES;
1835 ifp->if_capabilities = IFCAP_HWCSUM;
1836 ifp->if_capenable = ifp->if_capabilities;
1839 * Figure out what sort of media we have by checking the
1840 * hardware config word in the first 32k of NIC internal memory,
1841 * or fall back to examining the EEPROM if necessary.
1842 * Note: on some BCM5700 cards, this value appears to be unset.
1843 * If that's the case, we have to rely on identifying the NIC
1844 * by its PCI subsystem ID, as we do below for the SysKonnect
1847 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1848 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1850 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1851 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1852 hwcfg = ntohl(hwcfg);
1855 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1858 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1859 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
1860 PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1864 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1865 bge_ifmedia_upd, bge_ifmedia_sts);
1866 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1867 ifmedia_add(&sc->bge_ifmedia,
1868 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1869 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1870 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1873 * Do transceiver setup.
1875 if (mii_phy_probe(dev, &sc->bge_miibus,
1876 bge_ifmedia_upd, bge_ifmedia_sts)) {
1877 printf("bge%d: MII without any PHY!\n", sc->bge_unit);
1878 bge_release_resources(sc);
1879 bge_free_jumbo_mem(sc);
1886 * When using the BCM5701 in PCI-X mode, data corruption has
1887 * been observed in the first few bytes of some received packets.
1888 * Aligning the packet buffer in memory eliminates the corruption.
1889 * Unfortunately, this misaligns the packet payloads. On platforms
1890 * which do not support unaligned accesses, we will realign the
1891 * payloads by copying the received packets.
1893 switch (sc->bge_chipid) {
1894 case BGE_CHIPID_BCM5701_A0:
1895 case BGE_CHIPID_BCM5701_B0:
1896 case BGE_CHIPID_BCM5701_B2:
1897 case BGE_CHIPID_BCM5701_B5:
1898 /* If in PCI-X mode, work around the alignment bug. */
1899 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1900 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1901 BGE_PCISTATE_PCI_BUSSPEED)
1902 sc->bge_rx_alignment_bug = 1;
1907 * Call MI attach routine.
1909 ether_ifattach(ifp, ether_addr);
1910 callout_handle_init(&sc->bge_stat_ch);
1922 struct bge_softc *sc;
1928 sc = device_get_softc(dev);
1929 ifp = &sc->arpcom.ac_if;
1931 ether_ifdetach(ifp);
1936 ifmedia_removeall(&sc->bge_ifmedia);
1938 bus_generic_detach(dev);
1939 device_delete_child(dev, sc->bge_miibus);
1942 bge_release_resources(sc);
1943 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1944 bge_free_jumbo_mem(sc);
1952 bge_release_resources(sc)
1953 struct bge_softc *sc;
1959 if (sc->bge_vpd_prodname != NULL)
1960 free(sc->bge_vpd_prodname, M_DEVBUF);
1962 if (sc->bge_vpd_readonly != NULL)
1963 free(sc->bge_vpd_readonly, M_DEVBUF);
1965 if (sc->bge_intrhand != NULL)
1966 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1968 if (sc->bge_irq != NULL)
1969 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1971 if (sc->bge_res != NULL)
1972 bus_release_resource(dev, SYS_RES_MEMORY,
1973 BGE_PCI_BAR0, sc->bge_res);
1975 if (sc->bge_rdata != NULL)
1976 contigfree(sc->bge_rdata,
1977 sizeof(struct bge_ring_data), M_DEVBUF);
1984 struct bge_softc *sc;
1987 u_int32_t cachesize, command, pcistate;
1992 /* Save some important PCI state. */
1993 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1994 command = pci_read_config(dev, BGE_PCI_CMD, 4);
1995 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1997 pci_write_config(dev, BGE_PCI_MISC_CTL,
1998 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1999 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2001 /* Issue global reset */
2002 bge_writereg_ind(sc, BGE_MISC_CFG,
2003 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1));
2007 /* Reset some of the PCI state that got zapped by reset */
2008 pci_write_config(dev, BGE_PCI_MISC_CTL,
2009 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2010 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2011 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2012 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2013 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
2016 * Prevent PXE restart: write a magic number to the
2017 * general communications memory at 0xB50.
2019 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2021 * Poll the value location we just wrote until
2022 * we see the 1's complement of the magic number.
2023 * This indicates that the firmware initialization
2026 for (i = 0; i < BGE_TIMEOUT; i++) {
2027 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2028 if (val == ~BGE_MAGIC_NUMBER)
2033 if (i == BGE_TIMEOUT) {
2034 printf("bge%d: firmware handshake timed out\n", sc->bge_unit);
2039 * XXX Wait for the value of the PCISTATE register to
2040 * return to its original pre-reset state. This is a
2041 * fairly good indicator of reset completion. If we don't
2042 * wait for the reset to fully complete, trying to read
2043 * from the device's non-PCI registers may yield garbage
2046 for (i = 0; i < BGE_TIMEOUT; i++) {
2047 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2052 /* Enable memory arbiter. */
2053 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2054 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2056 /* Fix up byte swapping */
2057 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
2058 BGE_MODECTL_BYTESWAP_DATA);
2060 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2068 * Frame reception handling. This is called if there's a frame
2069 * on the receive return list.
2071 * Note: we have to be able to handle two possibilities here:
2072 * 1) the frame is from the jumbo recieve ring
2073 * 2) the frame is from the standard receive ring
2078 struct bge_softc *sc;
2081 int stdcnt = 0, jumbocnt = 0;
2083 ifp = &sc->arpcom.ac_if;
2085 while(sc->bge_rx_saved_considx !=
2086 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
2087 struct bge_rx_bd *cur_rx;
2089 struct ether_header *eh;
2090 struct mbuf *m = NULL;
2091 u_int16_t vlan_tag = 0;
2095 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
2097 rxidx = cur_rx->bge_idx;
2098 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2100 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2102 vlan_tag = cur_rx->bge_vlan_tag;
2105 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2106 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2107 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2108 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2110 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2112 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2115 if (bge_newbuf_jumbo(sc,
2116 sc->bge_jumbo, NULL) == ENOBUFS) {
2118 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2122 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2123 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2124 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2126 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2128 bge_newbuf_std(sc, sc->bge_std, m);
2131 if (bge_newbuf_std(sc, sc->bge_std,
2134 bge_newbuf_std(sc, sc->bge_std, m);
2142 * The i386 allows unaligned accesses, but for other
2143 * platforms we must make sure the payload is aligned.
2145 if (sc->bge_rx_alignment_bug) {
2146 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2148 m->m_data += ETHER_ALIGN;
2151 eh = mtod(m, struct ether_header *);
2152 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2153 m->m_pkthdr.rcvif = ifp;
2155 /* Remove header from mbuf and pass it on. */
2156 m_adj(m, sizeof(struct ether_header));
2158 #if 0 /* currently broken for some packets, possibly related to TCP options */
2159 if (ifp->if_hwassist) {
2160 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2161 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2162 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2163 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2164 m->m_pkthdr.csum_data =
2165 cur_rx->bge_tcp_udp_csum;
2166 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2172 * If we received a packet with a vlan tag, pass it
2173 * to vlan_input() instead of ether_input().
2176 VLAN_INPUT_TAG(eh, m, vlan_tag);
2177 have_tag = vlan_tag = 0;
2181 ether_input(ifp, eh, m);
2184 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2186 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2188 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2195 struct bge_softc *sc;
2197 struct bge_tx_bd *cur_tx = NULL;
2200 ifp = &sc->arpcom.ac_if;
2203 * Go through our tx ring and free mbufs for those
2204 * frames that have been sent.
2206 while (sc->bge_tx_saved_considx !=
2207 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
2210 idx = sc->bge_tx_saved_considx;
2211 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
2212 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2214 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2215 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2216 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2219 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2224 ifp->if_flags &= ~IFF_OACTIVE;
2233 struct bge_softc *sc;
2238 ifp = &sc->arpcom.ac_if;
2241 /* Avoid this for now -- checking this register is expensive. */
2242 /* Make sure this is really our interrupt. */
2243 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2246 /* Ack interrupt and stop others from occuring. */
2247 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2250 * Process link state changes.
2251 * Grrr. The link status word in the status block does
2252 * not work correctly on the BCM5700 rev AX and BX chips,
2253 * according to all available information. Hence, we have
2254 * to enable MII interrupts in order to properly obtain
2255 * async link changes. Unfortunately, this also means that
2256 * we have to read the MAC status register to detect link
2257 * changes, thereby adding an additional register access to
2258 * the interrupt handler.
2261 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2262 status = CSR_READ_4(sc, BGE_MAC_STS);
2263 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2265 untimeout(bge_tick, sc, sc->bge_stat_ch);
2267 /* Clear the interrupt */
2268 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2269 BGE_EVTENB_MI_INTERRUPT);
2270 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2271 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2275 if ((sc->bge_rdata->bge_status_block.bge_status &
2276 BGE_STATFLAG_UPDATED) &&
2277 (sc->bge_rdata->bge_status_block.bge_status &
2278 BGE_STATFLAG_LINKSTATE_CHANGED)) {
2279 sc->bge_rdata->bge_status_block.bge_status &=
2280 ~(BGE_STATFLAG_UPDATED|
2281 BGE_STATFLAG_LINKSTATE_CHANGED);
2283 * Sometimes PCS encoding errors are detected in
2284 * TBI mode (on fiber NICs), and for some reason
2285 * the chip will signal them as link changes.
2286 * If we get a link change event, but the 'PCS
2287 * encoding error' bit in the MAC status register
2288 * is set, don't bother doing a link check.
2289 * This avoids spurious "gigabit link up" messages
2290 * that sometimes appear on fiber NICs during
2291 * periods of heavy traffic. (There should be no
2292 * effect on copper NICs.)
2294 status = CSR_READ_4(sc, BGE_MAC_STS);
2295 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR|
2296 BGE_MACSTAT_MI_COMPLETE))) {
2298 untimeout(bge_tick, sc, sc->bge_stat_ch);
2302 untimeout(bge_tick, sc, sc->bge_stat_ch);
2304 /* Clear the interrupt */
2305 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2306 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2307 BGE_MACSTAT_LINK_CHANGED);
2309 /* Force flush the status block cached by PCI bridge */
2310 CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2314 if (ifp->if_flags & IFF_RUNNING) {
2315 /* Check RX return ring producer/consumer */
2318 /* Check TX ring producer/consumer */
2322 bge_handle_events(sc);
2324 /* Re-enable interrupts. */
2325 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2327 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
2337 struct bge_softc *sc;
2338 struct mii_data *mii = NULL;
2339 struct ifmedia *ifm = NULL;
2344 ifp = &sc->arpcom.ac_if;
2348 if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
2349 bge_stats_update_regs(sc);
2351 bge_stats_update(sc);
2352 sc->bge_stat_ch = timeout(bge_tick, sc, hz);
2359 ifm = &sc->bge_ifmedia;
2360 if (CSR_READ_4(sc, BGE_MAC_STS) &
2361 BGE_MACSTAT_TBI_PCS_SYNCHED) {
2363 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2364 printf("bge%d: gigabit link up\n", sc->bge_unit);
2365 if (ifp->if_snd.ifq_head != NULL)
2372 mii = device_get_softc(sc->bge_miibus);
2375 if (!sc->bge_link) {
2377 if (mii->mii_media_status & IFM_ACTIVE &&
2378 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2380 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX ||
2381 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2382 printf("bge%d: gigabit link up\n",
2384 if (ifp->if_snd.ifq_head != NULL)
2395 bge_stats_update_regs(sc)
2396 struct bge_softc *sc;
2399 struct bge_mac_stats_regs stats;
2403 ifp = &sc->arpcom.ac_if;
2405 s = (u_int32_t *)&stats;
2406 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2407 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2411 ifp->if_collisions +=
2412 (stats.dot3StatsSingleCollisionFrames +
2413 stats.dot3StatsMultipleCollisionFrames +
2414 stats.dot3StatsExcessiveCollisions +
2415 stats.dot3StatsLateCollisions) -
2422 bge_stats_update(sc)
2423 struct bge_softc *sc;
2426 struct bge_stats *stats;
2428 ifp = &sc->arpcom.ac_if;
2430 stats = (struct bge_stats *)(sc->bge_vhandle +
2431 BGE_MEMWIN_START + BGE_STATS_BLOCK);
2433 ifp->if_collisions +=
2434 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
2435 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
2436 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
2437 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
2441 ifp->if_collisions +=
2442 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2443 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2444 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2445 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2453 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2454 * pointers to descriptors.
2457 bge_encap(sc, m_head, txidx)
2458 struct bge_softc *sc;
2459 struct mbuf *m_head;
2462 struct bge_tx_bd *f = NULL;
2464 u_int32_t frag, cur, cnt = 0;
2465 u_int16_t csum_flags = 0;
2466 struct ifvlan *ifv = NULL;
2468 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2469 m_head->m_pkthdr.rcvif != NULL &&
2470 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2471 ifv = m_head->m_pkthdr.rcvif->if_softc;
2474 cur = frag = *txidx;
2476 if (m_head->m_pkthdr.csum_flags) {
2477 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2478 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2479 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2480 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2481 if (m_head->m_flags & M_LASTFRAG)
2482 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2483 else if (m_head->m_flags & M_FRAG)
2484 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2487 * Start packing the mbufs in this chain into
2488 * the fragment pointers. Stop when we run out
2489 * of fragments or hit the end of the mbuf chain.
2491 for (m = m_head; m != NULL; m = m->m_next) {
2492 if (m->m_len != 0) {
2493 f = &sc->bge_rdata->bge_tx_ring[frag];
2494 if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2496 BGE_HOSTADDR(f->bge_addr,
2497 vtophys(mtod(m, vm_offset_t)));
2498 f->bge_len = m->m_len;
2499 f->bge_flags = csum_flags;
2501 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2502 f->bge_vlan_tag = ifv->ifv_tag;
2504 f->bge_vlan_tag = 0;
2507 * Sanity check: avoid coming within 16 descriptors
2508 * of the end of the ring.
2510 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2513 BGE_INC(frag, BGE_TX_RING_CNT);
2521 if (frag == sc->bge_tx_saved_considx)
2524 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2525 sc->bge_cdata.bge_tx_chain[cur] = m_head;
2526 sc->bge_txcnt += cnt;
2534 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2535 * to the mbuf data regions directly in the transmit descriptors.
2541 struct bge_softc *sc;
2542 struct mbuf *m_head = NULL;
2543 u_int32_t prodidx = 0;
2547 if (!sc->bge_link && ifp->if_snd.ifq_len < 10)
2550 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2552 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2553 IF_DEQUEUE(&ifp->if_snd, m_head);
2559 * safety overkill. If this is a fragmented packet chain
2560 * with delayed TCP/UDP checksums, then only encapsulate
2561 * it if we have enough descriptors to handle the entire
2563 * (paranoia -- may not actually be needed)
2565 if (m_head->m_flags & M_FIRSTFRAG &&
2566 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2567 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2568 m_head->m_pkthdr.csum_data + 16) {
2569 IF_PREPEND(&ifp->if_snd, m_head);
2570 ifp->if_flags |= IFF_OACTIVE;
2576 * Pack the data into the transmit ring. If we
2577 * don't have room, set the OACTIVE flag and wait
2578 * for the NIC to drain the ring.
2580 if (bge_encap(sc, m_head, &prodidx)) {
2581 IF_PREPEND(&ifp->if_snd, m_head);
2582 ifp->if_flags |= IFF_OACTIVE;
2587 * If there's a BPF listener, bounce a copy of this frame
2591 bpf_mtap(ifp, m_head);
2595 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2596 /* 5700 b2 errata */
2597 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2598 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2601 * Set a timeout in case the chip goes out to lunch.
2612 struct bge_softc *sc = xsc;
2619 ifp = &sc->arpcom.ac_if;
2621 if (ifp->if_flags & IFF_RUNNING) {
2626 /* Cancel pending I/O and flush buffers. */
2632 * Init the various state machines, ring
2633 * control blocks and firmware.
2635 if (bge_blockinit(sc)) {
2636 printf("bge%d: initialization failure\n", sc->bge_unit);
2641 ifp = &sc->arpcom.ac_if;
2644 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2645 ETHER_HDR_LEN + ETHER_CRC_LEN);
2647 /* Load our MAC address. */
2648 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2649 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2650 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2652 /* Enable or disable promiscuous mode as needed. */
2653 if (ifp->if_flags & IFF_PROMISC) {
2654 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2656 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2659 /* Program multicast filter. */
2663 bge_init_rx_ring_std(sc);
2666 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2667 * memory to insure that the chip has in fact read the first
2668 * entry of the ring.
2670 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2672 for (i = 0; i < 10; i++) {
2674 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2675 if (v == (MCLBYTES - ETHER_ALIGN))
2679 printf ("bge%d: 5705 A0 chip failed to load RX ring\n",
2683 /* Init jumbo RX ring. */
2684 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2685 bge_init_rx_ring_jumbo(sc);
2687 /* Init our RX return ring index */
2688 sc->bge_rx_saved_considx = 0;
2691 bge_init_tx_ring(sc);
2693 /* Turn on transmitter */
2694 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2696 /* Turn on receiver */
2697 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2699 /* Tell firmware we're alive. */
2700 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2702 /* Enable host interrupts. */
2703 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2704 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2705 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2707 bge_ifmedia_upd(ifp);
2709 ifp->if_flags |= IFF_RUNNING;
2710 ifp->if_flags &= ~IFF_OACTIVE;
2714 sc->bge_stat_ch = timeout(bge_tick, sc, hz);
2720 * Set media options.
2723 bge_ifmedia_upd(ifp)
2726 struct bge_softc *sc;
2727 struct mii_data *mii;
2728 struct ifmedia *ifm;
2731 ifm = &sc->bge_ifmedia;
2733 /* If this is a 1000baseX NIC, enable the TBI port. */
2735 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2737 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2741 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2742 BGE_CLRBIT(sc, BGE_MAC_MODE,
2743 BGE_MACMODE_HALF_DUPLEX);
2745 BGE_SETBIT(sc, BGE_MAC_MODE,
2746 BGE_MACMODE_HALF_DUPLEX);
2755 mii = device_get_softc(sc->bge_miibus);
2757 if (mii->mii_instance) {
2758 struct mii_softc *miisc;
2759 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
2760 miisc = LIST_NEXT(miisc, mii_list))
2761 mii_phy_reset(miisc);
2769 * Report current media status.
2772 bge_ifmedia_sts(ifp, ifmr)
2774 struct ifmediareq *ifmr;
2776 struct bge_softc *sc;
2777 struct mii_data *mii;
2782 ifmr->ifm_status = IFM_AVALID;
2783 ifmr->ifm_active = IFM_ETHER;
2784 if (CSR_READ_4(sc, BGE_MAC_STS) &
2785 BGE_MACSTAT_TBI_PCS_SYNCHED)
2786 ifmr->ifm_status |= IFM_ACTIVE;
2787 ifmr->ifm_active |= IFM_1000_SX;
2788 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2789 ifmr->ifm_active |= IFM_HDX;
2791 ifmr->ifm_active |= IFM_FDX;
2795 mii = device_get_softc(sc->bge_miibus);
2797 ifmr->ifm_active = mii->mii_media_active;
2798 ifmr->ifm_status = mii->mii_media_status;
2804 bge_ioctl(ifp, command, data)
2809 struct bge_softc *sc = ifp->if_softc;
2810 struct ifreq *ifr = (struct ifreq *) data;
2811 int s, mask, error = 0;
2812 struct mii_data *mii;
2819 error = ether_ioctl(ifp, command, data);
2822 /* Disallow jumbo frames on 5705. */
2823 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2824 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
2827 ifp->if_mtu = ifr->ifr_mtu;
2828 ifp->if_flags &= ~IFF_RUNNING;
2833 if (ifp->if_flags & IFF_UP) {
2835 * If only the state of the PROMISC flag changed,
2836 * then just use the 'set promisc mode' command
2837 * instead of reinitializing the entire NIC. Doing
2838 * a full re-init means reloading the firmware and
2839 * waiting for it to start up, which may take a
2842 if (ifp->if_flags & IFF_RUNNING &&
2843 ifp->if_flags & IFF_PROMISC &&
2844 !(sc->bge_if_flags & IFF_PROMISC)) {
2845 BGE_SETBIT(sc, BGE_RX_MODE,
2846 BGE_RXMODE_RX_PROMISC);
2847 } else if (ifp->if_flags & IFF_RUNNING &&
2848 !(ifp->if_flags & IFF_PROMISC) &&
2849 sc->bge_if_flags & IFF_PROMISC) {
2850 BGE_CLRBIT(sc, BGE_RX_MODE,
2851 BGE_RXMODE_RX_PROMISC);
2855 if (ifp->if_flags & IFF_RUNNING) {
2859 sc->bge_if_flags = ifp->if_flags;
2864 if (ifp->if_flags & IFF_RUNNING) {
2872 error = ifmedia_ioctl(ifp, ifr,
2873 &sc->bge_ifmedia, command);
2875 mii = device_get_softc(sc->bge_miibus);
2876 error = ifmedia_ioctl(ifp, ifr,
2877 &mii->mii_media, command);
2881 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2882 if (mask & IFCAP_HWCSUM) {
2883 if (IFCAP_HWCSUM & ifp->if_capenable)
2884 ifp->if_capenable &= ~IFCAP_HWCSUM;
2886 ifp->if_capenable |= IFCAP_HWCSUM;
2904 struct bge_softc *sc;
2908 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit);
2910 ifp->if_flags &= ~IFF_RUNNING;
2919 * Stop the adapter and free any mbufs allocated to the
2924 struct bge_softc *sc;
2927 struct ifmedia_entry *ifm;
2928 struct mii_data *mii = NULL;
2931 ifp = &sc->arpcom.ac_if;
2934 mii = device_get_softc(sc->bge_miibus);
2936 untimeout(bge_tick, sc, sc->bge_stat_ch);
2939 * Disable all of the receiver blocks
2941 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2942 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2943 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2944 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2945 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2946 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2947 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2948 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2951 * Disable all of the transmit blocks
2953 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2954 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2955 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2956 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2957 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
2958 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2959 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2960 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2963 * Shut down all of the memory managers and related
2966 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2967 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
2968 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2969 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2970 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2971 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2972 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
2973 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2974 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2977 /* Disable host interrupts. */
2978 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2979 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2982 * Tell firmware we're shutting down.
2984 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2986 /* Free the RX lists. */
2987 bge_free_rx_ring_std(sc);
2989 /* Free jumbo RX list. */
2990 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2991 bge_free_rx_ring_jumbo(sc);
2993 /* Free TX buffers. */
2994 bge_free_tx_ring(sc);
2997 * Isolate/power down the PHY, but leave the media selection
2998 * unchanged so that things will be put back to normal when
2999 * we bring the interface back up.
3002 itmp = ifp->if_flags;
3003 ifp->if_flags |= IFF_UP;
3004 ifm = mii->mii_media.ifm_cur;
3005 mtmp = ifm->ifm_media;
3006 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3008 ifm->ifm_media = mtmp;
3009 ifp->if_flags = itmp;
3014 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3016 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3022 * Stop all chip I/O so that the kernel's probe routines don't
3023 * get confused by errant DMAs when rebooting.
3029 struct bge_softc *sc;
3031 sc = device_get_softc(dev);