bca94b2856c1f69c22c739213bffa64ae2e01518
[dragonfly.git] / sys / dev / disk / aic7xxx / aic7xxx.c
1 /*
2  * Core routines and tables shareable across OS platforms.
3  *
4  * Copyright (c) 1994-2002 Justin T. Gibbs.
5  * Copyright (c) 2000-2002 Adaptec Inc.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions, and the following disclaimer,
13  *    without modification.
14  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15  *    substantially similar to the "NO WARRANTY" disclaimer below
16  *    ("Disclaimer") and any redistribution must be conditioned upon
17  *    including a substantially similar Disclaimer requirement for further
18  *    binary redistribution.
19  * 3. Neither the names of the above-listed copyright holders nor the names
20  *    of any contributors may be used to endorse or promote products derived
21  *    from this software without specific prior written permission.
22  *
23  * Alternatively, this software may be distributed under the terms of the
24  * GNU General Public License ("GPL") version 2 as published by the Free
25  * Software Foundation.
26  *
27  * NO WARRANTY
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  * POSSIBILITY OF SUCH DAMAGES.
39  *
40  * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
41  *
42  * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.103 2004/10/19 20:48:05 gibbs Exp $
43  * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx.c,v 1.20 2007/07/06 05:45:52 pavalos Exp $
44  */
45
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
49
50 /****************************** Softc Data ************************************/
51 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
52
53 /***************************** Lookup Tables **********************************/
54 char *ahc_chip_names[] =
55 {
56         "NONE",
57         "aic7770",
58         "aic7850",
59         "aic7855",
60         "aic7859",
61         "aic7860",
62         "aic7870",
63         "aic7880",
64         "aic7895",
65         "aic7895C",
66         "aic7890/91",
67         "aic7896/97",
68         "aic7892",
69         "aic7899"
70 };
71 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names);
72
73 /*
74  * Hardware error codes.
75  */
76 struct ahc_hard_error_entry {
77         uint8_t error;
78         char *errmesg;
79 };
80
81 static struct ahc_hard_error_entry ahc_hard_errors[] = {
82         { ILLHADDR,     "Illegal Host Access" },
83         { ILLSADDR,     "Illegal Sequencer Address referenced" },
84         { ILLOPCODE,    "Illegal Opcode in sequencer program" },
85         { SQPARERR,     "Sequencer Parity Error" },
86         { DPARERR,      "Data-path Parity Error" },
87         { MPARERR,      "Scratch or SCB Memory Parity Error" },
88         { PCIERRSTAT,   "PCI Error detected" },
89         { CIOPARERR,    "CIOBUS Parity Error" },
90 };
91 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
92
93 static struct ahc_phase_table_entry ahc_phase_table[] =
94 {
95         { P_DATAOUT,    MSG_NOOP,               "in Data-out phase"     },
96         { P_DATAIN,     MSG_INITIATOR_DET_ERR,  "in Data-in phase"      },
97         { P_DATAOUT_DT, MSG_NOOP,               "in DT Data-out phase"  },
98         { P_DATAIN_DT,  MSG_INITIATOR_DET_ERR,  "in DT Data-in phase"   },
99         { P_COMMAND,    MSG_NOOP,               "in Command phase"      },
100         { P_MESGOUT,    MSG_NOOP,               "in Message-out phase"  },
101         { P_STATUS,     MSG_INITIATOR_DET_ERR,  "in Status phase"       },
102         { P_MESGIN,     MSG_PARITY_ERROR,       "in Message-in phase"   },
103         { P_BUSFREE,    MSG_NOOP,               "while idle"            },
104         { 0,            MSG_NOOP,               "in unknown phase"      }
105 };
106
107 /*
108  * In most cases we only wish to itterate over real phases, so
109  * exclude the last element from the count.
110  */
111 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
112
113 /*
114  * Valid SCSIRATE values.  (p. 3-17)
115  * Provides a mapping of tranfer periods in ns to the proper value to
116  * stick in the scsixfer reg.
117  */
118 static struct ahc_syncrate ahc_syncrates[] =
119 {
120       /* ultra2    fast/ultra  period     rate */
121         { 0x42,      0x000,      9,      "80.0" },
122         { 0x03,      0x000,     10,      "40.0" },
123         { 0x04,      0x000,     11,      "33.0" },
124         { 0x05,      0x100,     12,      "20.0" },
125         { 0x06,      0x110,     15,      "16.0" },
126         { 0x07,      0x120,     18,      "13.4" },
127         { 0x08,      0x000,     25,      "10.0" },
128         { 0x19,      0x010,     31,      "8.0"  },
129         { 0x1a,      0x020,     37,      "6.67" },
130         { 0x1b,      0x030,     43,      "5.7"  },
131         { 0x1c,      0x040,     50,      "5.0"  },
132         { 0x00,      0x050,     56,      "4.4"  },
133         { 0x00,      0x060,     62,      "4.0"  },
134         { 0x00,      0x070,     68,      "3.6"  },
135         { 0x00,      0x000,      0,      NULL   }
136 };
137
138 /* Our Sequencer Program */
139 #include "aic7xxx_seq.h"
140
141 /**************************** Function Declarations ***************************/
142 static void             ahc_force_renegotiation(struct ahc_softc *ahc,
143                                                 struct ahc_devinfo *devinfo);
144 static struct ahc_tmode_tstate*
145                         ahc_alloc_tstate(struct ahc_softc *ahc,
146                                          u_int scsi_id, char channel);
147 #ifdef AHC_TARGET_MODE
148 static void             ahc_free_tstate(struct ahc_softc *ahc,
149                                         u_int scsi_id, char channel, int force);
150 #endif
151 static struct ahc_syncrate*
152                         ahc_devlimited_syncrate(struct ahc_softc *ahc,
153                                                 struct ahc_initiator_tinfo *,
154                                                 u_int *period,
155                                                 u_int *ppr_options,
156                                                 role_t role);
157 static void             ahc_update_pending_scbs(struct ahc_softc *ahc);
158 static void             ahc_fetch_devinfo(struct ahc_softc *ahc,
159                                           struct ahc_devinfo *devinfo);
160 static void             ahc_scb_devinfo(struct ahc_softc *ahc,
161                                         struct ahc_devinfo *devinfo,
162                                         struct scb *scb);
163 static void             ahc_assert_atn(struct ahc_softc *ahc);
164 static void             ahc_setup_initiator_msgout(struct ahc_softc *ahc,
165                                                    struct ahc_devinfo *devinfo,
166                                                    struct scb *scb);
167 static void             ahc_build_transfer_msg(struct ahc_softc *ahc,
168                                                struct ahc_devinfo *devinfo);
169 static void             ahc_construct_sdtr(struct ahc_softc *ahc,
170                                            struct ahc_devinfo *devinfo,
171                                            u_int period, u_int offset);
172 static void             ahc_construct_wdtr(struct ahc_softc *ahc,
173                                            struct ahc_devinfo *devinfo,
174                                            u_int bus_width);
175 static void             ahc_construct_ppr(struct ahc_softc *ahc,
176                                           struct ahc_devinfo *devinfo,
177                                           u_int period, u_int offset,
178                                           u_int bus_width, u_int ppr_options);
179 static void             ahc_clear_msg_state(struct ahc_softc *ahc);
180 static void             ahc_handle_proto_violation(struct ahc_softc *ahc);
181 static void             ahc_handle_message_phase(struct ahc_softc *ahc);
182 typedef enum {
183         AHCMSG_1B,
184         AHCMSG_2B,
185         AHCMSG_EXT
186 } ahc_msgtype;
187 static int              ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
188                                      u_int msgval, int full);
189 static int              ahc_parse_msg(struct ahc_softc *ahc,
190                                       struct ahc_devinfo *devinfo);
191 static int              ahc_handle_msg_reject(struct ahc_softc *ahc,
192                                               struct ahc_devinfo *devinfo);
193 static void             ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
194                                                 struct ahc_devinfo *devinfo);
195 static void             ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
196 static void             ahc_handle_devreset(struct ahc_softc *ahc,
197                                             struct ahc_devinfo *devinfo,
198                                             cam_status status, char *message,
199                                             int verbose_level);
200 #ifdef AHC_TARGET_MODE
201 static void             ahc_setup_target_msgin(struct ahc_softc *ahc,
202                                                struct ahc_devinfo *devinfo,
203                                                struct scb *scb);
204 #endif
205
206 static bus_dmamap_callback_t    ahc_dmamap_cb; 
207 static void                     ahc_build_free_scb_list(struct ahc_softc *ahc);
208 static int                      ahc_init_scbdata(struct ahc_softc *ahc);
209 static void                     ahc_fini_scbdata(struct ahc_softc *ahc);
210 static void             ahc_qinfifo_requeue(struct ahc_softc *ahc,
211                                             struct scb *prev_scb,
212                                             struct scb *scb);
213 static int              ahc_qinfifo_count(struct ahc_softc *ahc);
214 static u_int            ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
215                                                    u_int prev, u_int scbptr);
216 static void             ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
217 static u_int            ahc_rem_wscb(struct ahc_softc *ahc,
218                                      u_int scbpos, u_int prev);
219 static void             ahc_reset_current_bus(struct ahc_softc *ahc);
220 #ifdef AHC_DUMP_SEQ
221 static void             ahc_dumpseq(struct ahc_softc *ahc);
222 #endif
223 static int              ahc_loadseq(struct ahc_softc *ahc);
224 static int              ahc_check_patch(struct ahc_softc *ahc,
225                                         struct patch **start_patch,
226                                         u_int start_instr, u_int *skip_addr);
227 static void             ahc_download_instr(struct ahc_softc *ahc,
228                                            u_int instrptr, uint8_t *dconsts);
229 static int              ahc_other_scb_timeout(struct ahc_softc *ahc,
230                                               struct scb *scb,
231                                               struct scb *other_scb);
232 #ifdef AHC_TARGET_MODE
233 static void             ahc_queue_lstate_event(struct ahc_softc *ahc,
234                                                struct ahc_tmode_lstate *lstate,
235                                                u_int initiator_id,
236                                                u_int event_type,
237                                                u_int event_arg);
238 static void             ahc_update_scsiid(struct ahc_softc *ahc,
239                                           u_int targid_mask);
240 static int              ahc_handle_target_cmd(struct ahc_softc *ahc,
241                                               struct target_cmd *cmd);
242 #endif
243 /************************* Sequencer Execution Control ************************/
244 /*
245  * Restart the sequencer program from address zero
246  */
247 void
248 ahc_restart(struct ahc_softc *ahc)
249 {
250
251         ahc_pause(ahc);
252
253         /* No more pending messages. */
254         ahc_clear_msg_state(ahc);
255
256         ahc_outb(ahc, SCSISIGO, 0);             /* De-assert BSY */
257         ahc_outb(ahc, MSG_OUT, MSG_NOOP);       /* No message to send */
258         ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
259         ahc_outb(ahc, LASTPHASE, P_BUSFREE);
260         ahc_outb(ahc, SAVED_SCSIID, 0xFF);
261         ahc_outb(ahc, SAVED_LUN, 0xFF);
262
263         /*
264          * Ensure that the sequencer's idea of TQINPOS
265          * matches our own.  The sequencer increments TQINPOS
266          * only after it sees a DMA complete and a reset could
267          * occur before the increment leaving the kernel to believe
268          * the command arrived but the sequencer to not.
269          */
270         ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
271
272         /* Always allow reselection */
273         ahc_outb(ahc, SCSISEQ,
274                  ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
275         if ((ahc->features & AHC_CMD_CHAN) != 0) {
276                 /* Ensure that no DMA operations are in progress */
277                 ahc_outb(ahc, CCSCBCNT, 0);
278                 ahc_outb(ahc, CCSGCTL, 0);
279                 ahc_outb(ahc, CCSCBCTL, 0);
280         }
281         /*
282          * If we were in the process of DMA'ing SCB data into
283          * an SCB, replace that SCB on the free list.  This prevents
284          * an SCB leak.
285          */
286         if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
287                 ahc_add_curscb_to_free_list(ahc);
288                 ahc_outb(ahc, SEQ_FLAGS2,
289                          ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
290         }
291
292         /*
293          * Clear any pending sequencer interrupt.  It is no
294          * longer relevant since we're resetting the Program
295          * Counter.
296          */
297         ahc_outb(ahc, CLRINT, CLRSEQINT);
298
299         ahc_outb(ahc, MWI_RESIDUAL, 0);
300         ahc_outb(ahc, SEQCTL, ahc->seqctl);
301         ahc_outb(ahc, SEQADDR0, 0);
302         ahc_outb(ahc, SEQADDR1, 0);
303
304         ahc_unpause(ahc);
305 }
306
307 /************************* Input/Output Queues ********************************/
308 void
309 ahc_run_qoutfifo(struct ahc_softc *ahc)
310 {
311         struct scb *scb;
312         u_int  scb_index;
313
314         ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
315         while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
316
317                 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
318                 if ((ahc->qoutfifonext & 0x03) == 0x03) {
319                         u_int modnext;
320
321                         /*
322                          * Clear 32bits of QOUTFIFO at a time
323                          * so that we don't clobber an incoming
324                          * byte DMA to the array on architectures
325                          * that only support 32bit load and store
326                          * operations.
327                          */
328                         modnext = ahc->qoutfifonext & ~0x3;
329                         *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
330                         aic_dmamap_sync(ahc, ahc->shared_data_dmat,
331                                         ahc->shared_data_dmamap,
332                                         /*offset*/modnext, /*len*/4,
333                                         BUS_DMASYNC_PREREAD);
334                 }
335                 ahc->qoutfifonext++;
336
337                 scb = ahc_lookup_scb(ahc, scb_index);
338                 if (scb == NULL) {
339                         kprintf("%s: WARNING no command for scb %d "
340                                "(cmdcmplt)\nQOUTPOS = %d\n",
341                                ahc_name(ahc), scb_index,
342                                (ahc->qoutfifonext - 1) & 0xFF);
343                         continue;
344                 }
345
346                 /*
347                  * Save off the residual
348                  * if there is one.
349                  */
350                 ahc_update_residual(ahc, scb);
351                 ahc_done(ahc, scb);
352         }
353 }
354
355 void
356 ahc_run_untagged_queues(struct ahc_softc *ahc)
357 {
358         int i;
359
360         for (i = 0; i < 16; i++)
361                 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
362 }
363
364 void
365 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
366 {
367         struct scb *scb;
368
369         if (ahc->untagged_queue_lock != 0)
370                 return;
371
372         if ((scb = TAILQ_FIRST(queue)) != NULL
373          && (scb->flags & SCB_ACTIVE) == 0) {
374                 scb->flags |= SCB_ACTIVE;
375                 /*
376                  * Timers are disabled while recovery is in progress.
377                  */
378                 aic_scb_timer_start(scb);
379                 ahc_queue_scb(ahc, scb);
380         }
381 }
382
383 /************************* Interrupt Handling *********************************/
384 void
385 ahc_handle_brkadrint(struct ahc_softc *ahc)
386 {
387         /*
388          * We upset the sequencer :-(
389          * Lookup the error message
390          */
391         int i;
392         int error;
393
394         error = ahc_inb(ahc, ERROR);
395         for (i = 0; error != 1 && i < num_errors; i++)
396                 error >>= 1;
397         kprintf("%s: brkadrint, %s at seqaddr = 0x%x\n",
398                ahc_name(ahc), ahc_hard_errors[i].errmesg,
399                ahc_inb(ahc, SEQADDR0) |
400                (ahc_inb(ahc, SEQADDR1) << 8));
401
402         ahc_dump_card_state(ahc);
403
404         /* Tell everyone that this HBA is no longer available */
405         ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
406                        CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
407                        CAM_NO_HBA);
408
409         /* Disable all interrupt sources by resetting the controller */
410         ahc_shutdown(ahc);
411 }
412
413 void
414 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
415 {
416         struct scb *scb;
417         struct ahc_devinfo devinfo;
418         
419         ahc_fetch_devinfo(ahc, &devinfo);
420
421         /*
422          * Clear the upper byte that holds SEQINT status
423          * codes and clear the SEQINT bit. We will unpause
424          * the sequencer, if appropriate, after servicing
425          * the request.
426          */
427         ahc_outb(ahc, CLRINT, CLRSEQINT);
428         switch (intstat & SEQINT_MASK) {
429         case BAD_STATUS:
430         {
431                 u_int  scb_index;
432                 struct hardware_scb *hscb;
433
434                 /*
435                  * Set the default return value to 0 (don't
436                  * send sense).  The sense code will change
437                  * this if needed.
438                  */
439                 ahc_outb(ahc, RETURN_1, 0);
440
441                 /*
442                  * The sequencer will notify us when a command
443                  * has an error that would be of interest to
444                  * the kernel.  This allows us to leave the sequencer
445                  * running in the common case of command completes
446                  * without error.  The sequencer will already have
447                  * dma'd the SCB back up to us, so we can reference
448                  * the in kernel copy directly.
449                  */
450                 scb_index = ahc_inb(ahc, SCB_TAG);
451                 scb = ahc_lookup_scb(ahc, scb_index);
452                 if (scb == NULL) {
453                         ahc_print_devinfo(ahc, &devinfo);
454                         kprintf("ahc_intr - referenced scb "
455                                "not valid during seqint 0x%x scb(%d)\n",
456                                intstat, scb_index);
457                         ahc_dump_card_state(ahc);
458                         panic("for safety");
459                         goto unpause;
460                 }
461
462                 hscb = scb->hscb; 
463
464                 /* Don't want to clobber the original sense code */
465                 if ((scb->flags & SCB_SENSE) != 0) {
466                         /*
467                          * Clear the SCB_SENSE Flag and have
468                          * the sequencer do a normal command
469                          * complete.
470                          */
471                         scb->flags &= ~SCB_SENSE;
472                         aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
473                         break;
474                 }
475                 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
476                 /* Freeze the queue until the client sees the error. */
477                 ahc_freeze_devq(ahc, scb);
478                 aic_freeze_scb(scb);
479                 aic_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
480                 switch (hscb->shared_data.status.scsi_status) {
481                 case SCSI_STATUS_OK:
482                         kprintf("%s: Interrupted for staus of 0???\n",
483                                ahc_name(ahc));
484                         break;
485                 case SCSI_STATUS_CMD_TERMINATED:
486                 case SCSI_STATUS_CHECK_COND:
487                 {
488                         struct ahc_dma_seg *sg;
489                         struct scsi_sense *sc;
490                         struct ahc_initiator_tinfo *targ_info;
491                         struct ahc_tmode_tstate *tstate;
492                         struct ahc_transinfo *tinfo;
493 #ifdef AHC_DEBUG
494                         if (ahc_debug & AHC_SHOW_SENSE) {
495                                 ahc_print_path(ahc, scb);
496                                 kprintf("SCB %d: requests Check Status\n",
497                                        scb->hscb->tag);
498                         }
499 #endif
500
501                         if (aic_perform_autosense(scb) == 0)
502                                 break;
503
504                         targ_info = ahc_fetch_transinfo(ahc,
505                                                         devinfo.channel,
506                                                         devinfo.our_scsiid,
507                                                         devinfo.target,
508                                                         &tstate);
509                         tinfo = &targ_info->curr;
510                         sg = scb->sg_list;
511                         sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 
512                         /*
513                          * Save off the residual if there is one.
514                          */
515                         ahc_update_residual(ahc, scb);
516 #ifdef AHC_DEBUG
517                         if (ahc_debug & AHC_SHOW_SENSE) {
518                                 ahc_print_path(ahc, scb);
519                                 kprintf("Sending Sense\n");
520                         }
521 #endif
522                         sg->addr = ahc_get_sense_bufaddr(ahc, scb);
523                         sg->len = aic_get_sense_bufsize(ahc, scb);
524                         sg->len |= AHC_DMA_LAST_SEG;
525
526                         /* Fixup byte order */
527                         sg->addr = aic_htole32(sg->addr);
528                         sg->len = aic_htole32(sg->len);
529
530                         sc->opcode = REQUEST_SENSE;
531                         sc->byte2 = 0;
532                         if (tinfo->protocol_version <= SCSI_REV_2
533                          && SCB_GET_LUN(scb) < 8)
534                                 sc->byte2 = SCB_GET_LUN(scb) << 5;
535                         sc->unused[0] = 0;
536                         sc->unused[1] = 0;
537                         sc->length = sg->len;
538                         sc->control = 0;
539
540                         /*
541                          * We can't allow the target to disconnect.
542                          * This will be an untagged transaction and
543                          * having the target disconnect will make this
544                          * transaction indestinguishable from outstanding
545                          * tagged transactions.
546                          */
547                         hscb->control = 0;
548
549                         /*
550                          * This request sense could be because the
551                          * the device lost power or in some other
552                          * way has lost our transfer negotiations.
553                          * Renegotiate if appropriate.  Unit attention
554                          * errors will be reported before any data
555                          * phases occur.
556                          */
557                         if (aic_get_residual(scb) 
558                          == aic_get_transfer_length(scb)) {
559                                 ahc_update_neg_request(ahc, &devinfo,
560                                                        tstate, targ_info,
561                                                        AHC_NEG_IF_NON_ASYNC);
562                         }
563                         if (tstate->auto_negotiate & devinfo.target_mask) {
564                                 hscb->control |= MK_MESSAGE;
565                                 scb->flags &= ~SCB_NEGOTIATE;
566                                 scb->flags |= SCB_AUTO_NEGOTIATE;
567                         }
568                         hscb->cdb_len = sizeof(*sc);
569                         hscb->dataptr = sg->addr; 
570                         hscb->datacnt = sg->len;
571                         hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
572                         hscb->sgptr = aic_htole32(hscb->sgptr);
573                         scb->sg_count = 1;
574                         scb->flags |= SCB_SENSE;
575                         ahc_qinfifo_requeue_tail(ahc, scb);
576                         ahc_outb(ahc, RETURN_1, SEND_SENSE);
577                         /*
578                          * Ensure we have enough time to actually
579                          * retrieve the sense, but only schedule
580                          * the timer if we are not in recovery or
581                          * this is a recovery SCB that is allowed
582                          * to have an active timer.
583                          */
584                         if (ahc->scb_data->recovery_scbs == 0
585                          || (scb->flags & SCB_RECOVERY_SCB) != 0)
586                                 aic_scb_timer_reset(scb, 5 * 1000000);
587                         break;
588                 }
589                 default:
590                         break;
591                 }
592                 break;
593         }
594         case NO_MATCH:
595         {
596                 /* Ensure we don't leave the selection hardware on */
597                 ahc_outb(ahc, SCSISEQ,
598                          ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
599
600                 kprintf("%s:%c:%d: no active SCB for reconnecting "
601                        "target - issuing BUS DEVICE RESET\n",
602                        ahc_name(ahc), devinfo.channel, devinfo.target);
603                 kprintf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
604                        "ARG_1 == 0x%x ACCUM = 0x%x\n",
605                        ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
606                        ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
607                 kprintf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
608                        "SINDEX == 0x%x\n",
609                        ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
610                        ahc_index_busy_tcl(ahc,
611                             BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
612                                       ahc_inb(ahc, SAVED_LUN))),
613                        ahc_inb(ahc, SINDEX));
614                 kprintf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
615                        "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
616                        ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
617                        ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
618                        ahc_inb(ahc, SCB_CONTROL));
619                 kprintf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
620                        ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
621                 kprintf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
622                 kprintf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
623                 ahc_dump_card_state(ahc);
624                 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
625                 ahc->msgout_len = 1;
626                 ahc->msgout_index = 0;
627                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
628                 ahc_outb(ahc, MSG_OUT, HOST_MSG);
629                 ahc_assert_atn(ahc);
630                 break;
631         }
632         case SEND_REJECT: 
633         {
634                 u_int rejbyte = ahc_inb(ahc, ACCUM);
635                 kprintf("%s:%c:%d: Warning - unknown message received from "
636                        "target (0x%x).  Rejecting\n", 
637                        ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
638                 break; 
639         }
640         case PROTO_VIOLATION:
641         {
642                 ahc_handle_proto_violation(ahc);
643                 break;
644         }
645         case IGN_WIDE_RES:
646                 ahc_handle_ign_wide_residue(ahc, &devinfo);
647                 break;
648         case PDATA_REINIT:
649                 ahc_reinitialize_dataptrs(ahc);
650                 break;
651         case BAD_PHASE:
652         {
653                 u_int lastphase;
654
655                 lastphase = ahc_inb(ahc, LASTPHASE);
656                 kprintf("%s:%c:%d: unknown scsi bus phase %x, "
657                        "lastphase = 0x%x.  Attempting to continue\n",
658                        ahc_name(ahc), devinfo.channel, devinfo.target,
659                        lastphase, ahc_inb(ahc, SCSISIGI));
660                 break;
661         }
662         case MISSED_BUSFREE:
663         {
664                 u_int lastphase;
665
666                 lastphase = ahc_inb(ahc, LASTPHASE);
667                 kprintf("%s:%c:%d: Missed busfree. "
668                        "Lastphase = 0x%x, Curphase = 0x%x\n",
669                        ahc_name(ahc), devinfo.channel, devinfo.target,
670                        lastphase, ahc_inb(ahc, SCSISIGI));
671                 ahc_restart(ahc);
672                 return;
673         }
674         case HOST_MSG_LOOP:
675         {
676                 /*
677                  * The sequencer has encountered a message phase
678                  * that requires host assistance for completion.
679                  * While handling the message phase(s), we will be
680                  * notified by the sequencer after each byte is
681                  * transfered so we can track bus phase changes.
682                  *
683                  * If this is the first time we've seen a HOST_MSG_LOOP
684                  * interrupt, initialize the state of the host message
685                  * loop.
686                  */
687                 if (ahc->msg_type == MSG_TYPE_NONE) {
688                         struct scb *scb;
689                         u_int scb_index;
690                         u_int bus_phase;
691
692                         bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
693                         if (bus_phase != P_MESGIN
694                          && bus_phase != P_MESGOUT) {
695                                 kprintf("ahc_intr: HOST_MSG_LOOP bad "
696                                        "phase 0x%x\n",
697                                       bus_phase);
698                                 /*
699                                  * Probably transitioned to bus free before
700                                  * we got here.  Just punt the message.
701                                  */
702                                 ahc_clear_intstat(ahc);
703                                 ahc_restart(ahc);
704                                 return;
705                         }
706
707                         scb_index = ahc_inb(ahc, SCB_TAG);
708                         scb = ahc_lookup_scb(ahc, scb_index);
709                         if (devinfo.role == ROLE_INITIATOR) {
710                                 if (scb == NULL)
711                                         panic("HOST_MSG_LOOP with "
712                                               "invalid SCB %x\n", scb_index);
713
714                                 if (bus_phase == P_MESGOUT)
715                                         ahc_setup_initiator_msgout(ahc,
716                                                                    &devinfo,
717                                                                    scb);
718                                 else {
719                                         ahc->msg_type =
720                                             MSG_TYPE_INITIATOR_MSGIN;
721                                         ahc->msgin_index = 0;
722                                 }
723                         }
724 #ifdef AHC_TARGET_MODE
725                         else {
726                                 if (bus_phase == P_MESGOUT) {
727                                         ahc->msg_type =
728                                             MSG_TYPE_TARGET_MSGOUT;
729                                         ahc->msgin_index = 0;
730                                 }
731                                 else 
732                                         ahc_setup_target_msgin(ahc,
733                                                                &devinfo,
734                                                                scb);
735                         }
736 #endif
737                 }
738
739                 ahc_handle_message_phase(ahc);
740                 break;
741         }
742         case PERR_DETECTED:
743         {
744                 /*
745                  * If we've cleared the parity error interrupt
746                  * but the sequencer still believes that SCSIPERR
747                  * is true, it must be that the parity error is
748                  * for the currently presented byte on the bus,
749                  * and we are not in a phase (data-in) where we will
750                  * eventually ack this byte.  Ack the byte and
751                  * throw it away in the hope that the target will
752                  * take us to message out to deliver the appropriate
753                  * error message.
754                  */
755                 if ((intstat & SCSIINT) == 0
756                  && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
757
758                         if ((ahc->features & AHC_DT) == 0) {
759                                 u_int curphase;
760
761                                 /*
762                                  * The hardware will only let you ack bytes
763                                  * if the expected phase in SCSISIGO matches
764                                  * the current phase.  Make sure this is
765                                  * currently the case.
766                                  */
767                                 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
768                                 ahc_outb(ahc, LASTPHASE, curphase);
769                                 ahc_outb(ahc, SCSISIGO, curphase);
770                         }
771                         if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
772                                 int wait;
773
774                                 /*
775                                  * In a data phase.  Faster to bitbucket
776                                  * the data than to individually ack each
777                                  * byte.  This is also the only strategy
778                                  * that will work with AUTOACK enabled.
779                                  */
780                                 ahc_outb(ahc, SXFRCTL1,
781                                          ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
782                                 wait = 5000;
783                                 while (--wait != 0) {
784                                         if ((ahc_inb(ahc, SCSISIGI)
785                                           & (CDI|MSGI)) != 0)
786                                                 break;
787                                         aic_delay(100);
788                                 }
789                                 ahc_outb(ahc, SXFRCTL1,
790                                          ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
791                                 if (wait == 0) {
792                                         struct  scb *scb;
793                                         u_int   scb_index;
794
795                                         ahc_print_devinfo(ahc, &devinfo);
796                                         kprintf("Unable to clear parity error.  "
797                                                "Resetting bus.\n");
798                                         scb_index = ahc_inb(ahc, SCB_TAG);
799                                         scb = ahc_lookup_scb(ahc, scb_index);
800                                         if (scb != NULL)
801                                                 aic_set_transaction_status(scb,
802                                                     CAM_UNCOR_PARITY);
803                                         ahc_reset_channel(ahc, devinfo.channel, 
804                                                           /*init reset*/TRUE);
805                                 }
806                         } else {
807                                 ahc_inb(ahc, SCSIDATL);
808                         }
809                 }
810                 break;
811         }
812         case DATA_OVERRUN:
813         {
814                 /*
815                  * When the sequencer detects an overrun, it
816                  * places the controller in "BITBUCKET" mode
817                  * and allows the target to complete its transfer.
818                  * Unfortunately, none of the counters get updated
819                  * when the controller is in this mode, so we have
820                  * no way of knowing how large the overrun was.
821                  */
822                 u_int scbindex = ahc_inb(ahc, SCB_TAG);
823                 u_int lastphase = ahc_inb(ahc, LASTPHASE);
824                 u_int i;
825
826                 scb = ahc_lookup_scb(ahc, scbindex);
827                 for (i = 0; i < num_phases; i++) {
828                         if (lastphase == ahc_phase_table[i].phase)
829                                 break;
830                 }
831                 ahc_print_path(ahc, scb);
832                 kprintf("data overrun detected %s."
833                        "  Tag == 0x%x.\n",
834                        ahc_phase_table[i].phasemsg,
835                        scb->hscb->tag);
836                 ahc_print_path(ahc, scb);
837                 kprintf("%s seen Data Phase.  Length = %ld.  NumSGs = %d.\n",
838                        ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
839                        aic_get_transfer_length(scb), scb->sg_count);
840                 if (scb->sg_count > 0) {
841                         for (i = 0; i < scb->sg_count; i++) {
842
843                                 kprintf("sg[%d] - Addr 0x%x%x : Length %d\n",
844                                        i,
845                                        (aic_le32toh(scb->sg_list[i].len) >> 24
846                                         & SG_HIGH_ADDR_BITS),
847                                        aic_le32toh(scb->sg_list[i].addr),
848                                        aic_le32toh(scb->sg_list[i].len)
849                                        & AHC_SG_LEN_MASK);
850                         }
851                 }
852                 /*
853                  * Set this and it will take effect when the
854                  * target does a command complete.
855                  */
856                 ahc_freeze_devq(ahc, scb);
857                 if ((scb->flags & SCB_SENSE) == 0) {
858                         aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
859                 } else {
860                         scb->flags &= ~SCB_SENSE;
861                         aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
862                 }
863                 aic_freeze_scb(scb);
864
865                 if ((ahc->features & AHC_ULTRA2) != 0) {
866                         /*
867                          * Clear the channel in case we return
868                          * to data phase later.
869                          */
870                         ahc_outb(ahc, SXFRCTL0,
871                                  ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
872                         ahc_outb(ahc, SXFRCTL0,
873                                  ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
874                 }
875                 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
876                         u_int dscommand1;
877
878                         /* Ensure HHADDR is 0 for future DMA operations. */
879                         dscommand1 = ahc_inb(ahc, DSCOMMAND1);
880                         ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
881                         ahc_outb(ahc, HADDR, 0);
882                         ahc_outb(ahc, DSCOMMAND1, dscommand1);
883                 }
884                 break;
885         }
886         case MKMSG_FAILED:
887         {
888                 u_int scbindex;
889
890                 kprintf("%s:%c:%d:%d: Attempt to issue message failed\n",
891                        ahc_name(ahc), devinfo.channel, devinfo.target,
892                        devinfo.lun);
893                 scbindex = ahc_inb(ahc, SCB_TAG);
894                 scb = ahc_lookup_scb(ahc, scbindex);
895                 if (scb != NULL
896                  && (scb->flags & SCB_RECOVERY_SCB) != 0)
897                         /*
898                          * Ensure that we didn't put a second instance of this
899                          * SCB into the QINFIFO.
900                          */
901                         ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
902                                            SCB_GET_CHANNEL(ahc, scb),
903                                            SCB_GET_LUN(scb), scb->hscb->tag,
904                                            ROLE_INITIATOR, /*status*/0,
905                                            SEARCH_REMOVE);
906                 break;
907         }
908         case NO_FREE_SCB:
909         {
910                 kprintf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
911                 ahc_dump_card_state(ahc);
912                 panic("for safety");
913                 break;
914         }
915         case SCB_MISMATCH:
916         {
917                 u_int scbptr;
918
919                 scbptr = ahc_inb(ahc, SCBPTR);
920                 kprintf("Bogus TAG after DMA.  SCBPTR %d, tag %d, our tag %d\n",
921                        scbptr, ahc_inb(ahc, ARG_1),
922                        ahc->scb_data->hscbs[scbptr].tag);
923                 ahc_dump_card_state(ahc);
924                 panic("for saftey");
925                 break;
926         }
927         case OUT_OF_RANGE:
928         {
929                 kprintf("%s: BTT calculation out of range\n", ahc_name(ahc));
930                 kprintf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
931                        "ARG_1 == 0x%x ACCUM = 0x%x\n",
932                        ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
933                        ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
934                 kprintf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
935                        "SINDEX == 0x%x\n, A == 0x%x\n",
936                        ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
937                        ahc_index_busy_tcl(ahc,
938                             BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
939                                       ahc_inb(ahc, SAVED_LUN))),
940                        ahc_inb(ahc, SINDEX),
941                        ahc_inb(ahc, ACCUM));
942                 kprintf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
943                        "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
944                        ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
945                        ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
946                        ahc_inb(ahc, SCB_CONTROL));
947                 kprintf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
948                        ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
949                 ahc_dump_card_state(ahc);
950                 panic("for safety");
951                 break;
952         }
953         default:
954                 kprintf("ahc_intr: seqint, "
955                        "intstat == 0x%x, scsisigi = 0x%x\n",
956                        intstat, ahc_inb(ahc, SCSISIGI));
957                 break;
958         }
959 unpause:
960         /*
961          *  The sequencer is paused immediately on
962          *  a SEQINT, so we should restart it when
963          *  we're done.
964          */
965         ahc_unpause(ahc);
966 }
967
968 void
969 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
970 {
971         u_int   scb_index;
972         u_int   status0;
973         u_int   status;
974         struct  scb *scb;
975         char    cur_channel;
976         char    intr_channel;
977
978         if ((ahc->features & AHC_TWIN) != 0
979          && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
980                 cur_channel = 'B';
981         else
982                 cur_channel = 'A';
983         intr_channel = cur_channel;
984
985         if ((ahc->features & AHC_ULTRA2) != 0)
986                 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
987         else
988                 status0 = 0;
989         status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
990         if (status == 0 && status0 == 0) {
991                 if ((ahc->features & AHC_TWIN) != 0) {
992                         /* Try the other channel */
993                         ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
994                         status = ahc_inb(ahc, SSTAT1)
995                                & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
996                         intr_channel = (cur_channel == 'A') ? 'B' : 'A';
997                 }
998                 if (status == 0) {
999                         kprintf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1000                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1001                         ahc_unpause(ahc);
1002                         return;
1003                 }
1004         }
1005
1006         /* Make sure the sequencer is in a safe location. */
1007         ahc_clear_critical_section(ahc);
1008
1009         scb_index = ahc_inb(ahc, SCB_TAG);
1010         scb = ahc_lookup_scb(ahc, scb_index);
1011         if (scb != NULL
1012          && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1013                 scb = NULL;
1014
1015         if ((ahc->features & AHC_ULTRA2) != 0
1016          && (status0 & IOERR) != 0) {
1017                 int now_lvd;
1018
1019                 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1020                 kprintf("%s: Transceiver State Has Changed to %s mode\n",
1021                        ahc_name(ahc), now_lvd ? "LVD" : "SE");
1022                 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1023                 /*
1024                  * When transitioning to SE mode, the reset line
1025                  * glitches, triggering an arbitration bug in some
1026                  * Ultra2 controllers.  This bug is cleared when we
1027                  * assert the reset line.  Since a reset glitch has
1028                  * already occurred with this transition and a
1029                  * transceiver state change is handled just like
1030                  * a bus reset anyway, asserting the reset line
1031                  * ourselves is safe.
1032                  */
1033                 ahc_reset_channel(ahc, intr_channel,
1034                                  /*Initiate Reset*/now_lvd == 0);
1035         } else if ((status & SCSIRSTI) != 0) {
1036                 kprintf("%s: Someone reset channel %c\n",
1037                         ahc_name(ahc), intr_channel);
1038                 if (intr_channel != cur_channel)
1039                         ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1040                 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1041         } else if ((status & SCSIPERR) != 0) {
1042                 /*
1043                  * Determine the bus phase and queue an appropriate message.
1044                  * SCSIPERR is latched true as soon as a parity error
1045                  * occurs.  If the sequencer acked the transfer that
1046                  * caused the parity error and the currently presented
1047                  * transfer on the bus has correct parity, SCSIPERR will
1048                  * be cleared by CLRSCSIPERR.  Use this to determine if
1049                  * we should look at the last phase the sequencer recorded,
1050                  * or the current phase presented on the bus.
1051                  */
1052                 struct  ahc_devinfo devinfo;
1053                 u_int   mesg_out;
1054                 u_int   curphase;
1055                 u_int   errorphase;
1056                 u_int   lastphase;
1057                 u_int   scsirate;
1058                 u_int   i;
1059                 u_int   sstat2;
1060                 int     silent;
1061
1062                 lastphase = ahc_inb(ahc, LASTPHASE);
1063                 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1064                 sstat2 = ahc_inb(ahc, SSTAT2);
1065                 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1066                 /*
1067                  * For all phases save DATA, the sequencer won't
1068                  * automatically ack a byte that has a parity error
1069                  * in it.  So the only way that the current phase
1070                  * could be 'data-in' is if the parity error is for
1071                  * an already acked byte in the data phase.  During
1072                  * synchronous data-in transfers, we may actually
1073                  * ack bytes before latching the current phase in
1074                  * LASTPHASE, leading to the discrepancy between
1075                  * curphase and lastphase.
1076                  */
1077                 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1078                  || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1079                         errorphase = curphase;
1080                 else
1081                         errorphase = lastphase;
1082
1083                 for (i = 0; i < num_phases; i++) {
1084                         if (errorphase == ahc_phase_table[i].phase)
1085                                 break;
1086                 }
1087                 mesg_out = ahc_phase_table[i].mesg_out;
1088                 silent = FALSE;
1089                 if (scb != NULL) {
1090                         if (SCB_IS_SILENT(scb))
1091                                 silent = TRUE;
1092                         else
1093                                 ahc_print_path(ahc, scb);
1094                         scb->flags |= SCB_TRANSMISSION_ERROR;
1095                 } else
1096                         kprintf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1097                                SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1098                 scsirate = ahc_inb(ahc, SCSIRATE);
1099                 if (silent == FALSE) {
1100                         kprintf("parity error detected %s. "
1101                                "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1102                                ahc_phase_table[i].phasemsg,
1103                                ahc_inw(ahc, SEQADDR0),
1104                                scsirate);
1105                         if ((ahc->features & AHC_DT) != 0) {
1106                                 if ((sstat2 & CRCVALERR) != 0)
1107                                         kprintf("\tCRC Value Mismatch\n");
1108                                 if ((sstat2 & CRCENDERR) != 0)
1109                                         kprintf("\tNo terminal CRC packet "
1110                                                "received\n");
1111                                 if ((sstat2 & CRCREQERR) != 0)
1112                                         kprintf("\tIllegal CRC packet "
1113                                                "request\n");
1114                                 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1115                                         kprintf("\tUnexpected %sDT Data Phase\n",
1116                                                (scsirate & SINGLE_EDGE)
1117                                              ? "" : "non-");
1118                         }
1119                 }
1120
1121                 if ((ahc->features & AHC_DT) != 0
1122                  && (sstat2 & DUAL_EDGE_ERR) != 0) {
1123                         /*
1124                          * This error applies regardless of
1125                          * data direction, so ignore the value
1126                          * in the phase table.
1127                          */
1128                         mesg_out = MSG_INITIATOR_DET_ERR;
1129                 }
1130
1131                 /*
1132                  * We've set the hardware to assert ATN if we   
1133                  * get a parity error on "in" phases, so all we  
1134                  * need to do is stuff the message buffer with
1135                  * the appropriate message.  "In" phases have set
1136                  * mesg_out to something other than MSG_NOP.
1137                  */
1138                 if (mesg_out != MSG_NOOP) {
1139                         if (ahc->msg_type != MSG_TYPE_NONE)
1140                                 ahc->send_msg_perror = TRUE;
1141                         else
1142                                 ahc_outb(ahc, MSG_OUT, mesg_out);
1143                 }
1144                 /*
1145                  * Force a renegotiation with this target just in
1146                  * case we are out of sync for some external reason
1147                  * unknown (or unreported) by the target.
1148                  */
1149                 ahc_fetch_devinfo(ahc, &devinfo);
1150                 ahc_force_renegotiation(ahc, &devinfo);
1151
1152                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1153                 ahc_unpause(ahc);
1154         } else if ((status & SELTO) != 0) {
1155                 u_int   scbptr;
1156
1157                 /* Stop the selection */
1158                 ahc_outb(ahc, SCSISEQ, 0);
1159
1160                 /* No more pending messages */
1161                 ahc_clear_msg_state(ahc);
1162
1163                 /* Clear interrupt state */
1164                 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1165                 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1166
1167                 /*
1168                  * Although the driver does not care about the
1169                  * 'Selection in Progress' status bit, the busy
1170                  * LED does.  SELINGO is only cleared by a successful
1171                  * selection, so we must manually clear it to insure
1172                  * the LED turns off just in case no future successful
1173                  * selections occur (e.g. no devices on the bus).
1174                  */
1175                 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1176
1177                 scbptr = ahc_inb(ahc, WAITING_SCBH);
1178                 ahc_outb(ahc, SCBPTR, scbptr);
1179                 scb_index = ahc_inb(ahc, SCB_TAG);
1180
1181                 scb = ahc_lookup_scb(ahc, scb_index);
1182                 if (scb == NULL) {
1183                         kprintf("%s: ahc_intr - referenced scb not "
1184                                "valid during SELTO scb(%d, %d)\n",
1185                                ahc_name(ahc), scbptr, scb_index);
1186                         ahc_dump_card_state(ahc);
1187                 } else {
1188                         struct ahc_devinfo devinfo;
1189 #ifdef AHC_DEBUG
1190                         if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1191                                 ahc_print_path(ahc, scb);
1192                                 kprintf("Saw Selection Timeout for SCB 0x%x\n",
1193                                        scb_index);
1194                         }
1195 #endif
1196                         ahc_scb_devinfo(ahc, &devinfo, scb);
1197                         aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1198                         ahc_freeze_devq(ahc, scb);
1199
1200                         /*
1201                          * Cancel any pending transactions on the device
1202                          * now that it seems to be missing.  This will
1203                          * also revert us to async/narrow transfers until
1204                          * we can renegotiate with the device.
1205                          */
1206                         ahc_handle_devreset(ahc, &devinfo,
1207                                             CAM_SEL_TIMEOUT,
1208                                             "Selection Timeout",
1209                                             /*verbose_level*/1);
1210                 }
1211                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1212                 ahc_restart(ahc);
1213         } else if ((status & BUSFREE) != 0
1214                 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1215                 struct  ahc_devinfo devinfo;
1216                 u_int   lastphase;
1217                 u_int   saved_scsiid;
1218                 u_int   saved_lun;
1219                 u_int   target;
1220                 u_int   initiator_role_id;
1221                 char    channel;
1222                 int     printerror;
1223
1224                 /*
1225                  * Clear our selection hardware as soon as possible.
1226                  * We may have an entry in the waiting Q for this target,
1227                  * that is affected by this busfree and we don't want to
1228                  * go about selecting the target while we handle the event.
1229                  */
1230                 ahc_outb(ahc, SCSISEQ,
1231                          ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1232
1233                 /*
1234                  * Disable busfree interrupts and clear the busfree
1235                  * interrupt status.  We do this here so that several
1236                  * bus transactions occur prior to clearing the SCSIINT
1237                  * latch.  It can take a bit for the clearing to take effect.
1238                  */
1239                 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1240                 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1241
1242                 /*
1243                  * Look at what phase we were last in.
1244                  * If its message out, chances are pretty good
1245                  * that the busfree was in response to one of
1246                  * our abort requests.
1247                  */
1248                 lastphase = ahc_inb(ahc, LASTPHASE);
1249                 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1250                 saved_lun = ahc_inb(ahc, SAVED_LUN);
1251                 target = SCSIID_TARGET(ahc, saved_scsiid);
1252                 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1253                 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1254                 ahc_compile_devinfo(&devinfo, initiator_role_id,
1255                                     target, saved_lun, channel, ROLE_INITIATOR);
1256                 printerror = 1;
1257
1258                 if (lastphase == P_MESGOUT) {
1259                         u_int tag;
1260
1261                         tag = SCB_LIST_NULL;
1262                         if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1263                          || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1264                                 if (ahc->msgout_buf[ahc->msgout_index - 1]
1265                                  == MSG_ABORT_TAG)
1266                                         tag = scb->hscb->tag;
1267                                 ahc_print_path(ahc, scb);
1268                                 kprintf("SCB %d - Abort%s Completed.\n",
1269                                        scb->hscb->tag, tag == SCB_LIST_NULL ?
1270                                        "" : " Tag");
1271                                 ahc_abort_scbs(ahc, target, channel,
1272                                                saved_lun, tag,
1273                                                ROLE_INITIATOR,
1274                                                CAM_REQ_ABORTED);
1275                                 printerror = 0;
1276                         } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1277                                                 MSG_BUS_DEV_RESET, TRUE)) {
1278 #if defined(__DragonFly__) || defined(__FreeBSD__)
1279                                 /*
1280                                  * Don't mark the user's request for this BDR
1281                                  * as completing with CAM_BDR_SENT.  CAM3
1282                                  * specifies CAM_REQ_CMP.
1283                                  */
1284                                 if (scb != NULL
1285                                  && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1286                                  && ahc_match_scb(ahc, scb, target, channel,
1287                                                   CAM_LUN_WILDCARD,
1288                                                   SCB_LIST_NULL,
1289                                                   ROLE_INITIATOR)) {
1290                                         aic_set_transaction_status(scb, CAM_REQ_CMP);
1291                                 }
1292 #endif
1293                                 ahc_compile_devinfo(&devinfo,
1294                                                     initiator_role_id,
1295                                                     target,
1296                                                     CAM_LUN_WILDCARD,
1297                                                     channel,
1298                                                     ROLE_INITIATOR);
1299                                 ahc_handle_devreset(ahc, &devinfo,
1300                                                     CAM_BDR_SENT,
1301                                                     "Bus Device Reset",
1302                                                     /*verbose_level*/0);
1303                                 printerror = 0;
1304                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1305                                                 MSG_EXT_PPR, FALSE)) {
1306                                 struct ahc_initiator_tinfo *tinfo;
1307                                 struct ahc_tmode_tstate *tstate;
1308
1309                                 /*
1310                                  * PPR Rejected.  Try non-ppr negotiation
1311                                  * and retry command.
1312                                  */
1313                                 tinfo = ahc_fetch_transinfo(ahc,
1314                                                             devinfo.channel,
1315                                                             devinfo.our_scsiid,
1316                                                             devinfo.target,
1317                                                             &tstate);
1318                                 tinfo->curr.transport_version = 2;
1319                                 tinfo->goal.transport_version = 2;
1320                                 tinfo->goal.ppr_options = 0;
1321                                 ahc_qinfifo_requeue_tail(ahc, scb);
1322                                 printerror = 0;
1323                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1324                                                 MSG_EXT_WDTR, FALSE)) {
1325                                 /*
1326                                  * Negotiation Rejected.  Go-narrow and
1327                                  * retry command.
1328                                  */
1329                                 ahc_set_width(ahc, &devinfo,
1330                                               MSG_EXT_WDTR_BUS_8_BIT,
1331                                               AHC_TRANS_CUR|AHC_TRANS_GOAL,
1332                                               /*paused*/TRUE);
1333                                 ahc_qinfifo_requeue_tail(ahc, scb);
1334                                 printerror = 0;
1335                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1336                                                 MSG_EXT_SDTR, FALSE)) {
1337                                 /*
1338                                  * Negotiation Rejected.  Go-async and
1339                                  * retry command.
1340                                  */
1341                                 ahc_set_syncrate(ahc, &devinfo,
1342                                                 /*syncrate*/NULL,
1343                                                 /*period*/0, /*offset*/0,
1344                                                 /*ppr_options*/0,
1345                                                 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1346                                                 /*paused*/TRUE);
1347                                 ahc_qinfifo_requeue_tail(ahc, scb);
1348                                 printerror = 0;
1349                         }
1350                 }
1351                 if (printerror != 0) {
1352                         u_int i;
1353
1354                         if (scb != NULL) {
1355                                 u_int tag;
1356
1357                                 if ((scb->hscb->control & TAG_ENB) != 0)
1358                                         tag = scb->hscb->tag;
1359                                 else
1360                                         tag = SCB_LIST_NULL;
1361                                 ahc_print_path(ahc, scb);
1362                                 ahc_abort_scbs(ahc, target, channel,
1363                                                SCB_GET_LUN(scb), tag,
1364                                                ROLE_INITIATOR,
1365                                                CAM_UNEXP_BUSFREE);
1366                         } else {
1367                                 /*
1368                                  * We had not fully identified this connection,
1369                                  * so we cannot abort anything.
1370                                  */
1371                                 kprintf("%s: ", ahc_name(ahc));
1372                         }
1373                         for (i = 0; i < num_phases; i++) {
1374                                 if (lastphase == ahc_phase_table[i].phase)
1375                                         break;
1376                         }
1377                         if (lastphase != P_BUSFREE) {
1378                                 /*
1379                                  * Renegotiate with this device at the
1380                                  * next oportunity just in case this busfree
1381                                  * is due to a negotiation mismatch with the
1382                                  * device.
1383                                  */
1384                                 ahc_force_renegotiation(ahc, &devinfo);
1385                         }
1386                         kprintf("Unexpected busfree %s\n"
1387                                "SEQADDR == 0x%x\n",
1388                                ahc_phase_table[i].phasemsg,
1389                                ahc_inb(ahc, SEQADDR0)
1390                                 | (ahc_inb(ahc, SEQADDR1) << 8));
1391                 }
1392                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1393                 ahc_restart(ahc);
1394         } else {
1395                 kprintf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1396                        ahc_name(ahc), status);
1397                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1398         }
1399 }
1400
1401 /*
1402  * Force renegotiation to occur the next time we initiate
1403  * a command to the current device.
1404  */
1405 static void
1406 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1407 {
1408         struct  ahc_initiator_tinfo *targ_info;
1409         struct  ahc_tmode_tstate *tstate;
1410
1411         targ_info = ahc_fetch_transinfo(ahc,
1412                                         devinfo->channel,
1413                                         devinfo->our_scsiid,
1414                                         devinfo->target,
1415                                         &tstate);
1416         ahc_update_neg_request(ahc, devinfo, tstate,
1417                                targ_info, AHC_NEG_IF_NON_ASYNC);
1418 }
1419
1420 #define AHC_MAX_STEPS 2000
1421 void
1422 ahc_clear_critical_section(struct ahc_softc *ahc)
1423 {
1424         int     stepping;
1425         int     steps;
1426         u_int   simode0;
1427         u_int   simode1;
1428
1429         if (ahc->num_critical_sections == 0)
1430                 return;
1431
1432         stepping = FALSE;
1433         steps = 0;
1434         simode0 = 0;
1435         simode1 = 0;
1436         for (;;) {
1437                 struct  cs *cs;
1438                 u_int   seqaddr;
1439                 u_int   i;
1440
1441                 seqaddr = ahc_inb(ahc, SEQADDR0)
1442                         | (ahc_inb(ahc, SEQADDR1) << 8);
1443
1444                 /*
1445                  * Seqaddr represents the next instruction to execute, 
1446                  * so we are really executing the instruction just
1447                  * before it.
1448                  */
1449                 cs = ahc->critical_sections;
1450                 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1451                         
1452                         if (cs->begin < seqaddr && cs->end >= seqaddr)
1453                                 break;
1454                 }
1455
1456                 if (i == ahc->num_critical_sections)
1457                         break;
1458
1459                 if (steps > AHC_MAX_STEPS) {
1460                         kprintf("%s: Infinite loop in critical section\n",
1461                                ahc_name(ahc));
1462                         ahc_dump_card_state(ahc);
1463                         panic("critical section loop");
1464                 }
1465
1466                 steps++;
1467                 if (stepping == FALSE) {
1468
1469                         /*
1470                          * Disable all interrupt sources so that the
1471                          * sequencer will not be stuck by a pausing
1472                          * interrupt condition while we attempt to
1473                          * leave a critical section.
1474                          */
1475                         simode0 = ahc_inb(ahc, SIMODE0);
1476                         ahc_outb(ahc, SIMODE0, 0);
1477                         simode1 = ahc_inb(ahc, SIMODE1);
1478                         if ((ahc->features & AHC_DT) != 0)
1479                                 /*
1480                                  * On DT class controllers, we
1481                                  * use the enhanced busfree logic.
1482                                  * Unfortunately we cannot re-enable
1483                                  * busfree detection within the
1484                                  * current connection, so we must
1485                                  * leave it on while single stepping.
1486                                  */
1487                                 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1488                         else
1489                                 ahc_outb(ahc, SIMODE1, 0);
1490                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1491                         ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1492                         stepping = TRUE;
1493                 }
1494                 if ((ahc->features & AHC_DT) != 0) {
1495                         ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1496                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1497                 }
1498                 ahc_outb(ahc, HCNTRL, ahc->unpause);
1499                 while (!ahc_is_paused(ahc))
1500                         aic_delay(200);
1501         }
1502         if (stepping) {
1503                 ahc_outb(ahc, SIMODE0, simode0);
1504                 ahc_outb(ahc, SIMODE1, simode1);
1505                 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1506         }
1507 }
1508
1509 /*
1510  * Clear any pending interrupt status.
1511  */
1512 void
1513 ahc_clear_intstat(struct ahc_softc *ahc)
1514 {
1515         /* Clear any interrupt conditions this may have caused */
1516         ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1517                                 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1518                                 CLRREQINIT);
1519         ahc_flush_device_writes(ahc);
1520         ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1521         ahc_flush_device_writes(ahc);
1522         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1523         ahc_flush_device_writes(ahc);
1524 }
1525
1526 /**************************** Debugging Routines ******************************/
1527 #ifdef AHC_DEBUG
1528 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1529 #endif
1530
1531 void
1532 ahc_print_scb(struct scb *scb)
1533 {
1534         int i;
1535
1536         struct hardware_scb *hscb = scb->hscb;
1537
1538         kprintf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1539                (void *)scb,
1540                hscb->control,
1541                hscb->scsiid,
1542                hscb->lun,
1543                hscb->cdb_len);
1544         kprintf("Shared Data: ");
1545         for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1546                 kprintf("%#02x", hscb->shared_data.cdb[i]);
1547         kprintf("        dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1548                 aic_le32toh(hscb->dataptr),
1549                 aic_le32toh(hscb->datacnt),
1550                 aic_le32toh(hscb->sgptr),
1551                 hscb->tag);
1552         if (scb->sg_count > 0) {
1553                 for (i = 0; i < scb->sg_count; i++) {
1554                         kprintf("sg[%d] - Addr 0x%x%x : Length %d\n",
1555                                i,
1556                                (aic_le32toh(scb->sg_list[i].len) >> 24
1557                                 & SG_HIGH_ADDR_BITS),
1558                                aic_le32toh(scb->sg_list[i].addr),
1559                                aic_le32toh(scb->sg_list[i].len));
1560                 }
1561         }
1562 }
1563
1564 /************************* Transfer Negotiation *******************************/
1565 /*
1566  * Allocate per target mode instance (ID we respond to as a target)
1567  * transfer negotiation data structures.
1568  */
1569 static struct ahc_tmode_tstate *
1570 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1571 {
1572         struct ahc_tmode_tstate *master_tstate;
1573         struct ahc_tmode_tstate *tstate;
1574         int i;
1575
1576         master_tstate = ahc->enabled_targets[ahc->our_id];
1577         if (channel == 'B') {
1578                 scsi_id += 8;
1579                 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1580         }
1581         if (ahc->enabled_targets[scsi_id] != NULL
1582          && ahc->enabled_targets[scsi_id] != master_tstate)
1583                 panic("%s: ahc_alloc_tstate - Target already allocated",
1584                       ahc_name(ahc));
1585         tstate = kmalloc(sizeof(*tstate), M_DEVBUF, M_INTWAIT);
1586
1587         /*
1588          * If we have allocated a master tstate, copy user settings from
1589          * the master tstate (taken from SRAM or the EEPROM) for this
1590          * channel, but reset our current and goal settings to async/narrow
1591          * until an initiator talks to us.
1592          */
1593         if (master_tstate != NULL) {
1594                 memcpy(tstate, master_tstate, sizeof(*tstate));
1595                 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1596                 tstate->ultraenb = 0;
1597                 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1598                         memset(&tstate->transinfo[i].curr, 0,
1599                               sizeof(tstate->transinfo[i].curr));
1600                         memset(&tstate->transinfo[i].goal, 0,
1601                               sizeof(tstate->transinfo[i].goal));
1602                 }
1603         } else
1604                 memset(tstate, 0, sizeof(*tstate));
1605         ahc->enabled_targets[scsi_id] = tstate;
1606         return (tstate);
1607 }
1608
1609 #ifdef AHC_TARGET_MODE
1610 /*
1611  * Free per target mode instance (ID we respond to as a target)
1612  * transfer negotiation data structures.
1613  */
1614 static void
1615 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1616 {
1617         struct ahc_tmode_tstate *tstate;
1618
1619         /*
1620          * Don't clean up our "master" tstate.
1621          * It has our default user settings.
1622          */
1623         if (((channel == 'B' && scsi_id == ahc->our_id_b)
1624           || (channel == 'A' && scsi_id == ahc->our_id))
1625          && force == FALSE)
1626                 return;
1627
1628         if (channel == 'B')
1629                 scsi_id += 8;
1630         tstate = ahc->enabled_targets[scsi_id];
1631         if (tstate != NULL)
1632                 kfree(tstate, M_DEVBUF);
1633         ahc->enabled_targets[scsi_id] = NULL;
1634 }
1635 #endif
1636
1637 /*
1638  * Called when we have an active connection to a target on the bus,
1639  * this function finds the nearest syncrate to the input period limited
1640  * by the capabilities of the bus connectivity of and sync settings for
1641  * the target.
1642  */
1643 struct ahc_syncrate *
1644 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1645                         struct ahc_initiator_tinfo *tinfo,
1646                         u_int *period, u_int *ppr_options, role_t role)
1647 {
1648         struct  ahc_transinfo *transinfo;
1649         u_int   maxsync;
1650
1651         if ((ahc->features & AHC_ULTRA2) != 0) {
1652                 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1653                  && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1654                         maxsync = AHC_SYNCRATE_DT;
1655                 } else {
1656                         maxsync = AHC_SYNCRATE_ULTRA;
1657                         /* Can't do DT on an SE bus */
1658                         *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1659                 }
1660         } else if ((ahc->features & AHC_ULTRA) != 0) {
1661                 maxsync = AHC_SYNCRATE_ULTRA;
1662         } else {
1663                 maxsync = AHC_SYNCRATE_FAST;
1664         }
1665         /*
1666          * Never allow a value higher than our current goal
1667          * period otherwise we may allow a target initiated
1668          * negotiation to go above the limit as set by the
1669          * user.  In the case of an initiator initiated
1670          * sync negotiation, we limit based on the user
1671          * setting.  This allows the system to still accept
1672          * incoming negotiations even if target initiated
1673          * negotiation is not performed.
1674          */
1675         if (role == ROLE_TARGET)
1676                 transinfo = &tinfo->user;
1677         else 
1678                 transinfo = &tinfo->goal;
1679         *ppr_options &= transinfo->ppr_options;
1680         if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1681                 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1682                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1683         }
1684         if (transinfo->period == 0) {
1685                 *period = 0;
1686                 *ppr_options = 0;
1687                 return (NULL);
1688         }
1689         *period = MAX(*period, transinfo->period);
1690         return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1691 }
1692
1693 /*
1694  * Look up the valid period to SCSIRATE conversion in our table.
1695  * Return the period and offset that should be sent to the target
1696  * if this was the beginning of an SDTR.
1697  */
1698 struct ahc_syncrate *
1699 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1700                   u_int *ppr_options, u_int maxsync)
1701 {
1702         struct ahc_syncrate *syncrate;
1703
1704         if ((ahc->features & AHC_DT) == 0)
1705                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1706
1707         /* Skip all DT only entries if DT is not available */
1708         if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1709          && maxsync < AHC_SYNCRATE_ULTRA2)
1710                 maxsync = AHC_SYNCRATE_ULTRA2;
1711         
1712         for (syncrate = &ahc_syncrates[maxsync];
1713              syncrate->rate != NULL;
1714              syncrate++) {
1715
1716                 /*
1717                  * The Ultra2 table doesn't go as low
1718                  * as for the Fast/Ultra cards.
1719                  */
1720                 if ((ahc->features & AHC_ULTRA2) != 0
1721                  && (syncrate->sxfr_u2 == 0))
1722                         break;
1723
1724                 if (*period <= syncrate->period) {
1725                         /*
1726                          * When responding to a target that requests
1727                          * sync, the requested rate may fall between
1728                          * two rates that we can output, but still be
1729                          * a rate that we can receive.  Because of this,
1730                          * we want to respond to the target with
1731                          * the same rate that it sent to us even
1732                          * if the period we use to send data to it
1733                          * is lower.  Only lower the response period
1734                          * if we must.
1735                          */
1736                         if (syncrate == &ahc_syncrates[maxsync])
1737                                 *period = syncrate->period;
1738
1739                         /*
1740                          * At some speeds, we only support
1741                          * ST transfers.
1742                          */
1743                         if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1744                                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1745                         break;
1746                 }
1747         }
1748
1749         if ((*period == 0)
1750          || (syncrate->rate == NULL)
1751          || ((ahc->features & AHC_ULTRA2) != 0
1752           && (syncrate->sxfr_u2 == 0))) {
1753                 /* Use asynchronous transfers. */
1754                 *period = 0;
1755                 syncrate = NULL;
1756                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1757         }
1758         return (syncrate);
1759 }
1760
1761 /*
1762  * Convert from an entry in our syncrate table to the SCSI equivalent
1763  * sync "period" factor.
1764  */
1765 u_int
1766 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1767 {
1768         struct ahc_syncrate *syncrate;
1769
1770         if ((ahc->features & AHC_ULTRA2) != 0)
1771                 scsirate &= SXFR_ULTRA2;
1772         else
1773                 scsirate &= SXFR;
1774
1775         syncrate = &ahc_syncrates[maxsync];
1776         while (syncrate->rate != NULL) {
1777
1778                 if ((ahc->features & AHC_ULTRA2) != 0) {
1779                         if (syncrate->sxfr_u2 == 0)
1780                                 break;
1781                         else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1782                                 return (syncrate->period);
1783                 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1784                                 return (syncrate->period);
1785                 }
1786                 syncrate++;
1787         }
1788         return (0); /* async */
1789 }
1790
1791 /*
1792  * Truncate the given synchronous offset to a value the
1793  * current adapter type and syncrate are capable of.
1794  */
1795 void
1796 ahc_validate_offset(struct ahc_softc *ahc,
1797                     struct ahc_initiator_tinfo *tinfo,
1798                     struct ahc_syncrate *syncrate,
1799                     u_int *offset, int wide, role_t role)
1800 {
1801         u_int maxoffset;
1802
1803         /* Limit offset to what we can do */
1804         if (syncrate == NULL) {
1805                 maxoffset = 0;
1806         } else if ((ahc->features & AHC_ULTRA2) != 0) {
1807                 maxoffset = MAX_OFFSET_ULTRA2;
1808         } else {
1809                 if (wide)
1810                         maxoffset = MAX_OFFSET_16BIT;
1811                 else
1812                         maxoffset = MAX_OFFSET_8BIT;
1813         }
1814         *offset = MIN(*offset, maxoffset);
1815         if (tinfo != NULL) {
1816                 if (role == ROLE_TARGET)
1817                         *offset = MIN(*offset, tinfo->user.offset);
1818                 else
1819                         *offset = MIN(*offset, tinfo->goal.offset);
1820         }
1821 }
1822
1823 /*
1824  * Truncate the given transfer width parameter to a value the
1825  * current adapter type is capable of.
1826  */
1827 void
1828 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1829                    u_int *bus_width, role_t role)
1830 {
1831         switch (*bus_width) {
1832         default:
1833                 if (ahc->features & AHC_WIDE) {
1834                         /* Respond Wide */
1835                         *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1836                         break;
1837                 }
1838                 /* FALLTHROUGH */
1839         case MSG_EXT_WDTR_BUS_8_BIT:
1840                 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1841                 break;
1842         }
1843         if (tinfo != NULL) {
1844                 if (role == ROLE_TARGET)
1845                         *bus_width = MIN(tinfo->user.width, *bus_width);
1846                 else
1847                         *bus_width = MIN(tinfo->goal.width, *bus_width);
1848         }
1849 }
1850
1851 /*
1852  * Update the bitmask of targets for which the controller should
1853  * negotiate with at the next convenient oportunity.  This currently
1854  * means the next time we send the initial identify messages for
1855  * a new transaction.
1856  */
1857 int
1858 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1859                        struct ahc_tmode_tstate *tstate,
1860                        struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1861 {
1862         u_int auto_negotiate_orig;
1863
1864         auto_negotiate_orig = tstate->auto_negotiate;
1865         if (neg_type == AHC_NEG_ALWAYS) {
1866                 /*
1867                  * Force our "current" settings to be
1868                  * unknown so that unless a bus reset
1869                  * occurs the need to renegotiate is
1870                  * recorded persistently.
1871                  */
1872                 if ((ahc->features & AHC_WIDE) != 0)
1873                         tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1874                 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1875                 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1876         }
1877         if (tinfo->curr.period != tinfo->goal.period
1878          || tinfo->curr.width != tinfo->goal.width
1879          || tinfo->curr.offset != tinfo->goal.offset
1880          || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1881          || (neg_type == AHC_NEG_IF_NON_ASYNC
1882           && (tinfo->goal.offset != 0
1883            || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1884            || tinfo->goal.ppr_options != 0)))
1885                 tstate->auto_negotiate |= devinfo->target_mask;
1886         else
1887                 tstate->auto_negotiate &= ~devinfo->target_mask;
1888
1889         return (auto_negotiate_orig != tstate->auto_negotiate);
1890 }
1891
1892 /*
1893  * Update the user/goal/curr tables of synchronous negotiation
1894  * parameters as well as, in the case of a current or active update,
1895  * any data structures on the host controller.  In the case of an
1896  * active update, the specified target is currently talking to us on
1897  * the bus, so the transfer parameter update must take effect
1898  * immediately.
1899  */
1900 void
1901 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1902                  struct ahc_syncrate *syncrate, u_int period,
1903                  u_int offset, u_int ppr_options, u_int type, int paused)
1904 {
1905         struct  ahc_initiator_tinfo *tinfo;
1906         struct  ahc_tmode_tstate *tstate;
1907         u_int   old_period;
1908         u_int   old_offset;
1909         u_int   old_ppr;
1910         int     active;
1911         int     update_needed;
1912
1913         active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1914         update_needed = 0;
1915
1916         if (syncrate == NULL) {
1917                 period = 0;
1918                 offset = 0;
1919         }
1920
1921         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1922                                     devinfo->target, &tstate);
1923
1924         if ((type & AHC_TRANS_USER) != 0) {
1925                 tinfo->user.period = period;
1926                 tinfo->user.offset = offset;
1927                 tinfo->user.ppr_options = ppr_options;
1928         }
1929
1930         if ((type & AHC_TRANS_GOAL) != 0) {
1931                 tinfo->goal.period = period;
1932                 tinfo->goal.offset = offset;
1933                 tinfo->goal.ppr_options = ppr_options;
1934         }
1935
1936         old_period = tinfo->curr.period;
1937         old_offset = tinfo->curr.offset;
1938         old_ppr    = tinfo->curr.ppr_options;
1939
1940         if ((type & AHC_TRANS_CUR) != 0
1941          && (old_period != period
1942           || old_offset != offset
1943           || old_ppr != ppr_options)) {
1944                 u_int   scsirate;
1945
1946                 update_needed++;
1947                 scsirate = tinfo->scsirate;
1948                 if ((ahc->features & AHC_ULTRA2) != 0) {
1949
1950                         scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1951                         if (syncrate != NULL) {
1952                                 scsirate |= syncrate->sxfr_u2;
1953                                 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1954                                         scsirate |= ENABLE_CRC;
1955                                 else
1956                                         scsirate |= SINGLE_EDGE;
1957                         }
1958                 } else {
1959
1960                         scsirate &= ~(SXFR|SOFS);
1961                         /*
1962                          * Ensure Ultra mode is set properly for
1963                          * this target.
1964                          */
1965                         tstate->ultraenb &= ~devinfo->target_mask;
1966                         if (syncrate != NULL) {
1967                                 if (syncrate->sxfr & ULTRA_SXFR) {
1968                                         tstate->ultraenb |=
1969                                                 devinfo->target_mask;
1970                                 }
1971                                 scsirate |= syncrate->sxfr & SXFR;
1972                                 scsirate |= offset & SOFS;
1973                         }
1974                         if (active) {
1975                                 u_int sxfrctl0;
1976
1977                                 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1978                                 sxfrctl0 &= ~FAST20;
1979                                 if (tstate->ultraenb & devinfo->target_mask)
1980                                         sxfrctl0 |= FAST20;
1981                                 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1982                         }
1983                 }
1984                 if (active) {
1985                         ahc_outb(ahc, SCSIRATE, scsirate);
1986                         if ((ahc->features & AHC_ULTRA2) != 0)
1987                                 ahc_outb(ahc, SCSIOFFSET, offset);
1988                 }
1989
1990                 tinfo->scsirate = scsirate;
1991                 tinfo->curr.period = period;
1992                 tinfo->curr.offset = offset;
1993                 tinfo->curr.ppr_options = ppr_options;
1994
1995                 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1996                                CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1997                 if (bootverbose) {
1998                         if (offset != 0) {
1999                                 kprintf("%s: target %d synchronous at %sMHz%s, "
2000                                        "offset = 0x%x\n", ahc_name(ahc),
2001                                        devinfo->target, syncrate->rate,
2002                                        (ppr_options & MSG_EXT_PPR_DT_REQ)
2003                                        ? " DT" : "", offset);
2004                         } else {
2005                                 kprintf("%s: target %d using "
2006                                        "asynchronous transfers\n",
2007                                        ahc_name(ahc), devinfo->target);
2008                         }
2009                 }
2010         }
2011
2012         update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2013                                                 tinfo, AHC_NEG_TO_GOAL);
2014
2015         if (update_needed)
2016                 ahc_update_pending_scbs(ahc);
2017 }
2018
2019 /*
2020  * Update the user/goal/curr tables of wide negotiation
2021  * parameters as well as, in the case of a current or active update,
2022  * any data structures on the host controller.  In the case of an
2023  * active update, the specified target is currently talking to us on
2024  * the bus, so the transfer parameter update must take effect
2025  * immediately.
2026  */
2027 void
2028 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2029               u_int width, u_int type, int paused)
2030 {
2031         struct  ahc_initiator_tinfo *tinfo;
2032         struct  ahc_tmode_tstate *tstate;
2033         u_int   oldwidth;
2034         int     active;
2035         int     update_needed;
2036
2037         active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2038         update_needed = 0;
2039         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2040                                     devinfo->target, &tstate);
2041
2042         if ((type & AHC_TRANS_USER) != 0)
2043                 tinfo->user.width = width;
2044
2045         if ((type & AHC_TRANS_GOAL) != 0)
2046                 tinfo->goal.width = width;
2047
2048         oldwidth = tinfo->curr.width;
2049         if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2050                 u_int   scsirate;
2051
2052                 update_needed++;
2053                 scsirate =  tinfo->scsirate;
2054                 scsirate &= ~WIDEXFER;
2055                 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2056                         scsirate |= WIDEXFER;
2057
2058                 tinfo->scsirate = scsirate;
2059
2060                 if (active)
2061                         ahc_outb(ahc, SCSIRATE, scsirate);
2062
2063                 tinfo->curr.width = width;
2064
2065                 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2066                                CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2067                 if (bootverbose) {
2068                         kprintf("%s: target %d using %dbit transfers\n",
2069                                ahc_name(ahc), devinfo->target,
2070                                8 * (0x01 << width));
2071                 }
2072         }
2073
2074         update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2075                                                 tinfo, AHC_NEG_TO_GOAL);
2076         if (update_needed)
2077                 ahc_update_pending_scbs(ahc);
2078 }
2079
2080 /*
2081  * Update the current state of tagged queuing for a given target.
2082  */
2083 void
2084 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2085              ahc_queue_alg alg)
2086 {
2087         ahc_platform_set_tags(ahc, devinfo, alg);
2088         ahc_send_async(ahc, devinfo->channel, devinfo->target,
2089                        devinfo->lun, AC_TRANSFER_NEG, &alg);
2090 }
2091
2092 /*
2093  * When the transfer settings for a connection change, update any
2094  * in-transit SCBs to contain the new data so the hardware will
2095  * be set correctly during future (re)selections.
2096  */
2097 static void
2098 ahc_update_pending_scbs(struct ahc_softc *ahc)
2099 {
2100         struct  scb *pending_scb;
2101         int     pending_scb_count;
2102         int     i;
2103         int     paused;
2104         u_int   saved_scbptr;
2105
2106         /*
2107          * Traverse the pending SCB list and ensure that all of the
2108          * SCBs there have the proper settings.
2109          */
2110         pending_scb_count = 0;
2111         LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2112                 struct ahc_devinfo devinfo;
2113                 struct hardware_scb *pending_hscb;
2114                 struct ahc_initiator_tinfo *tinfo;
2115                 struct ahc_tmode_tstate *tstate;
2116
2117                 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2118                 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2119                                             devinfo.our_scsiid,
2120                                             devinfo.target, &tstate);
2121                 pending_hscb = pending_scb->hscb;
2122                 pending_hscb->control &= ~ULTRAENB;
2123                 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2124                         pending_hscb->control |= ULTRAENB;
2125                 pending_hscb->scsirate = tinfo->scsirate;
2126                 pending_hscb->scsioffset = tinfo->curr.offset;
2127                 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2128                  && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2129                         pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2130                         pending_hscb->control &= ~MK_MESSAGE;
2131                 }
2132                 ahc_sync_scb(ahc, pending_scb,
2133                              BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2134                 pending_scb_count++;
2135         }
2136
2137         if (pending_scb_count == 0)
2138                 return;
2139
2140         if (ahc_is_paused(ahc)) {
2141                 paused = 1;
2142         } else {
2143                 paused = 0;
2144                 ahc_pause(ahc);
2145         }
2146
2147         saved_scbptr = ahc_inb(ahc, SCBPTR);
2148         /* Ensure that the hscbs down on the card match the new information */
2149         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2150                 struct  hardware_scb *pending_hscb;
2151                 u_int   control;
2152                 u_int   scb_tag;
2153
2154                 ahc_outb(ahc, SCBPTR, i);
2155                 scb_tag = ahc_inb(ahc, SCB_TAG);
2156                 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2157                 if (pending_scb == NULL)
2158                         continue;
2159
2160                 pending_hscb = pending_scb->hscb;
2161                 control = ahc_inb(ahc, SCB_CONTROL);
2162                 control &= ~(ULTRAENB|MK_MESSAGE);
2163                 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2164                 ahc_outb(ahc, SCB_CONTROL, control);
2165                 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2166                 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2167         }
2168         ahc_outb(ahc, SCBPTR, saved_scbptr);
2169
2170         if (paused == 0)
2171                 ahc_unpause(ahc);
2172 }
2173
2174 /**************************** Pathing Information *****************************/
2175 static void
2176 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2177 {
2178         u_int   saved_scsiid;
2179         role_t  role;
2180         int     our_id;
2181
2182         if (ahc_inb(ahc, SSTAT0) & TARGET)
2183                 role = ROLE_TARGET;
2184         else
2185                 role = ROLE_INITIATOR;
2186
2187         if (role == ROLE_TARGET
2188          && (ahc->features & AHC_MULTI_TID) != 0
2189          && (ahc_inb(ahc, SEQ_FLAGS)
2190            & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2191                 /* We were selected, so pull our id from TARGIDIN */
2192                 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2193         } else if ((ahc->features & AHC_ULTRA2) != 0)
2194                 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2195         else
2196                 our_id = ahc_inb(ahc, SCSIID) & OID;
2197
2198         saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2199         ahc_compile_devinfo(devinfo,
2200                             our_id,
2201                             SCSIID_TARGET(ahc, saved_scsiid),
2202                             ahc_inb(ahc, SAVED_LUN),
2203                             SCSIID_CHANNEL(ahc, saved_scsiid),
2204                             role);
2205 }
2206
2207 struct ahc_phase_table_entry*
2208 ahc_lookup_phase_entry(int phase)
2209 {
2210         struct ahc_phase_table_entry *entry;
2211         struct ahc_phase_table_entry *last_entry;
2212
2213         /*
2214          * num_phases doesn't include the default entry which
2215          * will be returned if the phase doesn't match.
2216          */
2217         last_entry = &ahc_phase_table[num_phases];
2218         for (entry = ahc_phase_table; entry < last_entry; entry++) {
2219                 if (phase == entry->phase)
2220                         break;
2221         }
2222         return (entry);
2223 }
2224
2225 void
2226 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2227                     u_int lun, char channel, role_t role)
2228 {
2229         devinfo->our_scsiid = our_id;
2230         devinfo->target = target;
2231         devinfo->lun = lun;
2232         devinfo->target_offset = target;
2233         devinfo->channel = channel;
2234         devinfo->role = role;
2235         if (channel == 'B')
2236                 devinfo->target_offset += 8;
2237         devinfo->target_mask = (0x01 << devinfo->target_offset);
2238 }
2239
2240 void
2241 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2242 {
2243         kprintf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2244                devinfo->target, devinfo->lun);
2245 }
2246
2247 static void
2248 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2249                 struct scb *scb)
2250 {
2251         role_t  role;
2252         int     our_id;
2253
2254         our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2255         role = ROLE_INITIATOR;
2256         if ((scb->flags & SCB_TARGET_SCB) != 0)
2257                 role = ROLE_TARGET;
2258         ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2259                             SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2260 }
2261
2262
2263 /************************ Message Phase Processing ****************************/
2264 static void
2265 ahc_assert_atn(struct ahc_softc *ahc)
2266 {
2267         u_int scsisigo;
2268
2269         scsisigo = ATNO;
2270         if ((ahc->features & AHC_DT) == 0)
2271                 scsisigo |= ahc_inb(ahc, SCSISIGI);
2272         ahc_outb(ahc, SCSISIGO, scsisigo);
2273 }
2274
2275 /*
2276  * When an initiator transaction with the MK_MESSAGE flag either reconnects
2277  * or enters the initial message out phase, we are interrupted.  Fill our
2278  * outgoing message buffer with the appropriate message and beging handing
2279  * the message phase(s) manually.
2280  */
2281 static void
2282 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2283                            struct scb *scb)
2284 {
2285         /*
2286          * To facilitate adding multiple messages together,
2287          * each routine should increment the index and len
2288          * variables instead of setting them explicitly.
2289          */
2290         ahc->msgout_index = 0;
2291         ahc->msgout_len = 0;
2292
2293         if ((scb->flags & SCB_DEVICE_RESET) == 0
2294          && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2295                 u_int identify_msg;
2296
2297                 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2298                 if ((scb->hscb->control & DISCENB) != 0)
2299                         identify_msg |= MSG_IDENTIFY_DISCFLAG;
2300                 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2301                 ahc->msgout_len++;
2302
2303                 if ((scb->hscb->control & TAG_ENB) != 0) {
2304                         ahc->msgout_buf[ahc->msgout_index++] =
2305                             scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2306                         ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2307                         ahc->msgout_len += 2;
2308                 }
2309         }
2310
2311         if (scb->flags & SCB_DEVICE_RESET) {
2312                 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2313                 ahc->msgout_len++;
2314                 ahc_print_path(ahc, scb);
2315                 kprintf("Bus Device Reset Message Sent\n");
2316                 /*
2317                  * Clear our selection hardware in advance of
2318                  * the busfree.  We may have an entry in the waiting
2319                  * Q for this target, and we don't want to go about
2320                  * selecting while we handle the busfree and blow it
2321                  * away.
2322                  */
2323                 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2324         } else if ((scb->flags & SCB_ABORT) != 0) {
2325                 if ((scb->hscb->control & TAG_ENB) != 0)
2326                         ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2327                 else
2328                         ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2329                 ahc->msgout_len++;
2330                 ahc_print_path(ahc, scb);
2331                 kprintf("Abort%s Message Sent\n",
2332                        (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2333                 /*
2334                  * Clear our selection hardware in advance of
2335                  * the busfree.  We may have an entry in the waiting
2336                  * Q for this target, and we don't want to go about
2337                  * selecting while we handle the busfree and blow it
2338                  * away.
2339                  */
2340                 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2341         } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2342                 ahc_build_transfer_msg(ahc, devinfo);
2343         } else {
2344                 kprintf("ahc_intr: AWAITING_MSG for an SCB that "
2345                        "does not have a waiting message\n");
2346                 kprintf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2347                        devinfo->target_mask);
2348                 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2349                       "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2350                       ahc_inb(ahc, MSG_OUT), scb->flags);
2351         }
2352
2353         /*
2354          * Clear the MK_MESSAGE flag from the SCB so we aren't
2355          * asked to send this message again.
2356          */
2357         ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2358         scb->hscb->control &= ~MK_MESSAGE;
2359         ahc->msgout_index = 0;
2360         ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2361 }
2362
2363 /*
2364  * Build an appropriate transfer negotiation message for the
2365  * currently active target.
2366  */
2367 static void
2368 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2369 {
2370         /*
2371          * We need to initiate transfer negotiations.
2372          * If our current and goal settings are identical,
2373          * we want to renegotiate due to a check condition.
2374          */
2375         struct  ahc_initiator_tinfo *tinfo;
2376         struct  ahc_tmode_tstate *tstate;
2377         struct  ahc_syncrate *rate;
2378         int     dowide;
2379         int     dosync;
2380         int     doppr;
2381         u_int   period;
2382         u_int   ppr_options;
2383         u_int   offset;
2384
2385         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2386                                     devinfo->target, &tstate);
2387         /*
2388          * Filter our period based on the current connection.
2389          * If we can't perform DT transfers on this segment (not in LVD
2390          * mode for instance), then our decision to issue a PPR message
2391          * may change.
2392          */
2393         period = tinfo->goal.period;
2394         offset = tinfo->goal.offset;
2395         ppr_options = tinfo->goal.ppr_options;
2396         /* Target initiated PPR is not allowed in the SCSI spec */
2397         if (devinfo->role == ROLE_TARGET)
2398                 ppr_options = 0;
2399         rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2400                                        &ppr_options, devinfo->role);
2401         dowide = tinfo->curr.width != tinfo->goal.width;
2402         dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2403         /*
2404          * Only use PPR if we have options that need it, even if the device
2405          * claims to support it.  There might be an expander in the way
2406          * that doesn't.
2407          */
2408         doppr = ppr_options != 0;
2409
2410         if (!dowide && !dosync && !doppr) {
2411                 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2412                 dosync = tinfo->goal.offset != 0;
2413         }
2414
2415         if (!dowide && !dosync && !doppr) {
2416                 /*
2417                  * Force async with a WDTR message if we have a wide bus,
2418                  * or just issue an SDTR with a 0 offset.
2419                  */
2420                 if ((ahc->features & AHC_WIDE) != 0)
2421                         dowide = 1;
2422                 else
2423                         dosync = 1;
2424
2425                 if (bootverbose) {
2426                         ahc_print_devinfo(ahc, devinfo);
2427                         kprintf("Ensuring async\n");
2428                 }
2429         }
2430
2431         /* Target initiated PPR is not allowed in the SCSI spec */
2432         if (devinfo->role == ROLE_TARGET)
2433                 doppr = 0;
2434
2435         /*
2436          * Both the PPR message and SDTR message require the
2437          * goal syncrate to be limited to what the target device
2438          * is capable of handling (based on whether an LVD->SE
2439          * expander is on the bus), so combine these two cases.
2440          * Regardless, guarantee that if we are using WDTR and SDTR
2441          * messages that WDTR comes first.
2442          */
2443         if (doppr || (dosync && !dowide)) {
2444
2445                 offset = tinfo->goal.offset;
2446                 ahc_validate_offset(ahc, tinfo, rate, &offset,
2447                                     doppr ? tinfo->goal.width
2448                                           : tinfo->curr.width,
2449                                     devinfo->role);
2450                 if (doppr) {
2451                         ahc_construct_ppr(ahc, devinfo, period, offset,
2452                                           tinfo->goal.width, ppr_options);
2453                 } else {
2454                         ahc_construct_sdtr(ahc, devinfo, period, offset);
2455                 }
2456         } else {
2457                 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2458         }
2459 }
2460
2461 /*
2462  * Build a synchronous negotiation message in our message
2463  * buffer based on the input parameters.
2464  */
2465 static void
2466 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2467                    u_int period, u_int offset)
2468 {
2469         if (offset == 0)
2470                 period = AHC_ASYNC_XFER_PERIOD;
2471         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2472         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2473         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2474         ahc->msgout_buf[ahc->msgout_index++] = period;
2475         ahc->msgout_buf[ahc->msgout_index++] = offset;
2476         ahc->msgout_len += 5;
2477         if (bootverbose) {
2478                 kprintf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2479                        ahc_name(ahc), devinfo->channel, devinfo->target,
2480                        devinfo->lun, period, offset);
2481         }
2482 }
2483
2484 /*
2485  * Build a wide negotiation message in our message
2486  * buffer based on the input parameters.
2487  */
2488 static void
2489 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2490                    u_int bus_width)
2491 {
2492         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2493         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2494         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2495         ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2496         ahc->msgout_len += 4;
2497         if (bootverbose) {
2498                 kprintf("(%s:%c:%d:%d): Sending WDTR %x\n",
2499                        ahc_name(ahc), devinfo->channel, devinfo->target,
2500                        devinfo->lun, bus_width);
2501         }
2502 }
2503
2504 /*
2505  * Build a parallel protocol request message in our message
2506  * buffer based on the input parameters.
2507  */
2508 static void
2509 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2510                   u_int period, u_int offset, u_int bus_width,
2511                   u_int ppr_options)
2512 {
2513         if (offset == 0)
2514                 period = AHC_ASYNC_XFER_PERIOD;
2515         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2516         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2517         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2518         ahc->msgout_buf[ahc->msgout_index++] = period;
2519         ahc->msgout_buf[ahc->msgout_index++] = 0;
2520         ahc->msgout_buf[ahc->msgout_index++] = offset;
2521         ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2522         ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2523         ahc->msgout_len += 8;
2524         if (bootverbose) {
2525                 kprintf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2526                        "offset %x, ppr_options %x\n", ahc_name(ahc),
2527                        devinfo->channel, devinfo->target, devinfo->lun,
2528                        bus_width, period, offset, ppr_options);
2529         }
2530 }
2531
2532 /*
2533  * Clear any active message state.
2534  */
2535 static void
2536 ahc_clear_msg_state(struct ahc_softc *ahc)
2537 {
2538         ahc->msgout_len = 0;
2539         ahc->msgin_index = 0;
2540         ahc->msg_type = MSG_TYPE_NONE;
2541         if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2542                 /*
2543                  * The target didn't care to respond to our
2544                  * message request, so clear ATN.
2545                  */
2546                 ahc_outb(ahc, CLRSINT1, CLRATNO);
2547         }
2548         ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2549         ahc_outb(ahc, SEQ_FLAGS2,
2550                  ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2551 }
2552
2553 static void
2554 ahc_handle_proto_violation(struct ahc_softc *ahc)
2555 {
2556         struct  ahc_devinfo devinfo;
2557         struct  scb *scb;
2558         u_int   scbid;
2559         u_int   seq_flags;
2560         u_int   curphase;
2561         u_int   lastphase;
2562         int     found;
2563
2564         ahc_fetch_devinfo(ahc, &devinfo);
2565         scbid = ahc_inb(ahc, SCB_TAG);
2566         scb = ahc_lookup_scb(ahc, scbid);
2567         seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2568         curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2569         lastphase = ahc_inb(ahc, LASTPHASE);
2570         if ((seq_flags & NOT_IDENTIFIED) != 0) {
2571
2572                 /*
2573                  * The reconnecting target either did not send an
2574                  * identify message, or did, but we didn't find an SCB
2575                  * to match.
2576                  */
2577                 ahc_print_devinfo(ahc, &devinfo);
2578                 kprintf("Target did not send an IDENTIFY message. "
2579                        "LASTPHASE = 0x%x.\n", lastphase);
2580                 scb = NULL;
2581         } else if (scb == NULL) {
2582                 /*
2583                  * We don't seem to have an SCB active for this
2584                  * transaction.  Print an error and reset the bus.
2585                  */
2586                 ahc_print_devinfo(ahc, &devinfo);
2587                 kprintf("No SCB found during protocol violation\n");
2588                 goto proto_violation_reset;
2589         } else {
2590                 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2591                 if ((seq_flags & NO_CDB_SENT) != 0) {
2592                         ahc_print_path(ahc, scb);
2593                         kprintf("No or incomplete CDB sent to device.\n");
2594                 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2595                         /*
2596                          * The target never bothered to provide status to
2597                          * us prior to completing the command.  Since we don't
2598                          * know the disposition of this command, we must attempt
2599                          * to abort it.  Assert ATN and prepare to send an abort
2600                          * message.
2601                          */
2602                         ahc_print_path(ahc, scb);
2603                         kprintf("Completed command without status.\n");
2604                 } else {
2605                         ahc_print_path(ahc, scb);
2606                         kprintf("Unknown protocol violation.\n");
2607                         ahc_dump_card_state(ahc);
2608                 }
2609         }
2610         if ((lastphase & ~P_DATAIN_DT) == 0
2611          || lastphase == P_COMMAND) {
2612 proto_violation_reset:
2613                 /*
2614                  * Target either went directly to data/command
2615                  * phase or didn't respond to our ATN.
2616                  * The only safe thing to do is to blow
2617                  * it away with a bus reset.
2618                  */
2619                 found = ahc_reset_channel(ahc, 'A', TRUE);
2620                 kprintf("%s: Issued Channel %c Bus Reset. "
2621                        "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2622         } else {
2623                 /*
2624                  * Leave the selection hardware off in case
2625                  * this abort attempt will affect yet to
2626                  * be sent commands.
2627                  */
2628                 ahc_outb(ahc, SCSISEQ,
2629                          ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2630                 ahc_assert_atn(ahc);
2631                 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2632                 if (scb == NULL) {
2633                         ahc_print_devinfo(ahc, &devinfo);
2634                         ahc->msgout_buf[0] = MSG_ABORT_TASK;
2635                         ahc->msgout_len = 1;
2636                         ahc->msgout_index = 0;
2637                         ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2638                 } else {
2639                         ahc_print_path(ahc, scb);
2640                         scb->flags |= SCB_ABORT;
2641                 }
2642                 kprintf("Protocol violation %s.  Attempting to abort.\n",
2643                        ahc_lookup_phase_entry(curphase)->phasemsg);
2644         }
2645 }
2646
2647 /*
2648  * Manual message loop handler.
2649  */
2650 static void
2651 ahc_handle_message_phase(struct ahc_softc *ahc)
2652
2653         struct  ahc_devinfo devinfo;
2654         u_int   bus_phase;
2655         int     end_session;
2656
2657         ahc_fetch_devinfo(ahc, &devinfo);
2658         end_session = FALSE;
2659         bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2660
2661 reswitch:
2662         switch (ahc->msg_type) {
2663         case MSG_TYPE_INITIATOR_MSGOUT:
2664         {
2665                 int lastbyte;
2666                 int phasemis;
2667                 int msgdone;
2668
2669                 if (ahc->msgout_len == 0)
2670                         panic("HOST_MSG_LOOP interrupt with no active message");
2671
2672 #ifdef AHC_DEBUG
2673                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2674                         ahc_print_devinfo(ahc, &devinfo);
2675                         kprintf("INITIATOR_MSG_OUT");
2676                 }
2677 #endif
2678                 phasemis = bus_phase != P_MESGOUT;
2679                 if (phasemis) {
2680 #ifdef AHC_DEBUG
2681                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2682                                 kprintf(" PHASEMIS %s\n",
2683                                        ahc_lookup_phase_entry(bus_phase)
2684                                                              ->phasemsg);
2685                         }
2686 #endif
2687                         if (bus_phase == P_MESGIN) {
2688                                 /*
2689                                  * Change gears and see if
2690                                  * this messages is of interest to
2691                                  * us or should be passed back to
2692                                  * the sequencer.
2693                                  */
2694                                 ahc_outb(ahc, CLRSINT1, CLRATNO);
2695                                 ahc->send_msg_perror = FALSE;
2696                                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2697                                 ahc->msgin_index = 0;
2698                                 goto reswitch;
2699                         }
2700                         end_session = TRUE;
2701                         break;
2702                 }
2703
2704                 if (ahc->send_msg_perror) {
2705                         ahc_outb(ahc, CLRSINT1, CLRATNO);
2706                         ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2707 #ifdef AHC_DEBUG
2708                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2709                                 kprintf(" byte 0x%x\n", ahc->send_msg_perror);
2710 #endif
2711                         ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2712                         break;
2713                 }
2714
2715                 msgdone = ahc->msgout_index == ahc->msgout_len;
2716                 if (msgdone) {
2717                         /*
2718                          * The target has requested a retry.
2719                          * Re-assert ATN, reset our message index to
2720                          * 0, and try again.
2721                          */
2722                         ahc->msgout_index = 0;
2723                         ahc_assert_atn(ahc);
2724                 }
2725
2726                 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2727                 if (lastbyte) {
2728                         /* Last byte is signified by dropping ATN */
2729                         ahc_outb(ahc, CLRSINT1, CLRATNO);
2730                 }
2731
2732                 /*
2733                  * Clear our interrupt status and present
2734                  * the next byte on the bus.
2735                  */
2736                 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2737 #ifdef AHC_DEBUG
2738                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2739                         kprintf(" byte 0x%x\n",
2740                                ahc->msgout_buf[ahc->msgout_index]);
2741 #endif
2742                 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2743                 break;
2744         }
2745         case MSG_TYPE_INITIATOR_MSGIN:
2746         {
2747                 int phasemis;
2748                 int message_done;
2749
2750 #ifdef AHC_DEBUG
2751                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2752                         ahc_print_devinfo(ahc, &devinfo);
2753                         kprintf("INITIATOR_MSG_IN");
2754                 }
2755 #endif
2756                 phasemis = bus_phase != P_MESGIN;
2757                 if (phasemis) {
2758 #ifdef AHC_DEBUG
2759                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2760                                 kprintf(" PHASEMIS %s\n",
2761                                        ahc_lookup_phase_entry(bus_phase)
2762                                                              ->phasemsg);
2763                         }
2764 #endif
2765                         ahc->msgin_index = 0;
2766                         if (bus_phase == P_MESGOUT
2767                          && (ahc->send_msg_perror == TRUE
2768                           || (ahc->msgout_len != 0
2769                            && ahc->msgout_index == 0))) {
2770                                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2771                                 goto reswitch;
2772                         }
2773                         end_session = TRUE;
2774                         break;
2775                 }
2776
2777                 /* Pull the byte in without acking it */
2778                 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2779 #ifdef AHC_DEBUG
2780                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2781                         kprintf(" byte 0x%x\n",
2782                                ahc->msgin_buf[ahc->msgin_index]);
2783 #endif
2784
2785                 message_done = ahc_parse_msg(ahc, &devinfo);
2786
2787                 if (message_done) {
2788                         /*
2789                          * Clear our incoming message buffer in case there
2790                          * is another message following this one.
2791                          */
2792                         ahc->msgin_index = 0;
2793
2794                         /*
2795                          * If this message illicited a response,
2796                          * assert ATN so the target takes us to the
2797                          * message out phase.
2798                          */
2799                         if (ahc->msgout_len != 0) {
2800 #ifdef AHC_DEBUG
2801                                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2802                                         ahc_print_devinfo(ahc, &devinfo);
2803                                         kprintf("Asserting ATN for response\n");
2804                                 }
2805 #endif
2806                                 ahc_assert_atn(ahc);
2807                         }
2808                 } else 
2809                         ahc->msgin_index++;
2810
2811                 if (message_done == MSGLOOP_TERMINATED) {
2812                         end_session = TRUE;
2813                 } else {
2814                         /* Ack the byte */
2815                         ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2816                         ahc_inb(ahc, SCSIDATL);
2817                 }
2818                 break;
2819         }
2820         case MSG_TYPE_TARGET_MSGIN:
2821         {
2822                 int msgdone;
2823
2824                 if (ahc->msgout_len == 0)
2825                         panic("Target MSGIN with no active message");
2826
2827 #ifdef AHC_DEBUG
2828                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2829                         ahc_print_devinfo(ahc, &devinfo);
2830                         kprintf("TARGET_MSG_IN");
2831                 }
2832 #endif
2833
2834                 /*
2835                  * If we interrupted a mesgout session, the initiator
2836                  * will not know this until our first REQ.  So, we
2837                  * only honor mesgout requests after we've sent our
2838                  * first byte.
2839                  */
2840                 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2841                  && ahc->msgout_index > 0) {
2842
2843                         /*
2844                          * Change gears and see if this messages is
2845                          * of interest to us or should be passed back
2846                          * to the sequencer.
2847                          */
2848 #ifdef AHC_DEBUG
2849                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2850                                 kprintf(" Honoring ATN Request.\n");
2851 #endif
2852                         ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2853
2854                         /*
2855                          * Disable SCSI Programmed I/O during the
2856                          * phase change so as to avoid phantom REQs.
2857                          */
2858                         ahc_outb(ahc, SXFRCTL0,
2859                                  ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2860
2861                         /*
2862                          * Since SPIORDY asserts when ACK is asserted
2863                          * for P_MSGOUT, and SPIORDY's assertion triggered
2864                          * our entry into this routine, wait for ACK to
2865                          * *de-assert* before changing phases.
2866                          */
2867                         while ((ahc_inb(ahc, SCSISIGI) & ACKI) != 0)
2868                                 ;
2869
2870                         ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2871
2872                         /*
2873                          * All phase line changes require a bus
2874                          * settle delay before REQ is asserted.
2875                          * [SCSI SPI4 10.7.1]
2876                          */
2877                         ahc_flush_device_writes(ahc);
2878                         aic_delay(AHC_BUSSETTLE_DELAY);
2879
2880                         ahc->msgin_index = 0;
2881                         /* Enable SCSI Programmed I/O to REQ for first byte */
2882                         ahc_outb(ahc, SXFRCTL0,
2883                                  ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2884                         break;
2885                 }
2886
2887                 msgdone = ahc->msgout_index == ahc->msgout_len;
2888                 if (msgdone) {
2889                         ahc_outb(ahc, SXFRCTL0,
2890                                  ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2891                         end_session = TRUE;
2892                         break;
2893                 }
2894
2895                 /*
2896                  * Present the next byte on the bus.
2897                  */
2898 #ifdef AHC_DEBUG
2899                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2900                         kprintf(" byte 0x%x\n",
2901                                ahc->msgout_buf[ahc->msgout_index]);
2902 #endif
2903                 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2904                 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2905                 break;
2906         }
2907         case MSG_TYPE_TARGET_MSGOUT:
2908         {
2909                 int lastbyte;
2910                 int msgdone;
2911
2912 #ifdef AHC_DEBUG
2913                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2914                         ahc_print_devinfo(ahc, &devinfo);
2915                         kprintf("TARGET_MSG_OUT");
2916                 }
2917 #endif
2918                 /*
2919                  * The initiator signals that this is
2920                  * the last byte by dropping ATN.
2921                  */
2922                 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2923
2924                 /*
2925                  * Read the latched byte, but turn off SPIOEN first
2926                  * so that we don't inadvertently cause a REQ for the
2927                  * next byte.
2928                  */
2929                 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2930                 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2931
2932 #ifdef AHC_DEBUG
2933                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2934                         kprintf(" byte 0x%x\n",
2935                                ahc->msgin_buf[ahc->msgin_index]);
2936 #endif
2937
2938                 msgdone = ahc_parse_msg(ahc, &devinfo);
2939                 if (msgdone == MSGLOOP_TERMINATED) {
2940                         /*
2941                          * The message is *really* done in that it caused
2942                          * us to go to bus free.  The sequencer has already
2943                          * been reset at this point, so pull the ejection
2944                          * handle.
2945                          */
2946                         return;
2947                 }
2948                 
2949                 ahc->msgin_index++;
2950
2951                 /*
2952                  * XXX Read spec about initiator dropping ATN too soon
2953                  *     and use msgdone to detect it.
2954                  */
2955                 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2956                         ahc->msgin_index = 0;
2957
2958                         /*
2959                          * If this message illicited a response, transition
2960                          * to the Message in phase and send it.
2961                          */
2962                         if (ahc->msgout_len != 0) {
2963 #ifdef AHC_DEBUG
2964                                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2965                                         ahc_print_devinfo(ahc, &devinfo);
2966                                         kprintf(" preparing response.\n");
2967                                 }
2968 #endif
2969                                 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2970
2971                                 /*
2972                                  * All phase line changes require a bus
2973                                  * settle delay before REQ is asserted.
2974                                  * [SCSI SPI4 10.7.1]  When transitioning
2975                                  * from an OUT to an IN phase, we must
2976                                  * also wait a data release delay to allow
2977                                  * the initiator time to release the data
2978                                  * lines. [SCSI SPI4 10.12]
2979                                  */
2980                                 ahc_flush_device_writes(ahc);
2981                                 aic_delay(AHC_BUSSETTLE_DELAY
2982                                         + AHC_DATARELEASE_DELAY);
2983
2984                                 /*
2985                                  * Enable SCSI Programmed I/O.  This will
2986                                  * immediately cause SPIORDY to assert,
2987                                  * and the sequencer will call our message
2988                                  * loop again.
2989                                  */
2990                                 ahc_outb(ahc, SXFRCTL0,
2991                                          ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2992                                 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2993                                 ahc->msgin_index = 0;
2994                                 break;
2995                         }
2996                 }
2997
2998                 if (lastbyte)
2999                         end_session = TRUE;
3000                 else {
3001                         /* Ask for the next byte. */
3002                         ahc_outb(ahc, SXFRCTL0,
3003                                  ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3004                 }
3005
3006                 break;
3007         }
3008         default:
3009                 panic("Unknown REQINIT message type");
3010         }
3011
3012         if (end_session) {
3013                 ahc_clear_msg_state(ahc);
3014                 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
3015         } else
3016                 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
3017 }
3018
3019 /*
3020  * See if we sent a particular extended message to the target.
3021  * If "full" is true, return true only if the target saw the full
3022  * message.  If "full" is false, return true if the target saw at
3023  * least the first byte of the message.
3024  */
3025 static int
3026 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
3027 {
3028         int found;
3029         u_int index;
3030
3031         found = FALSE;
3032         index = 0;
3033
3034         while (index < ahc->msgout_len) {
3035                 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
3036                         u_int end_index;
3037
3038                         end_index = index + 1 + ahc->msgout_buf[index + 1];
3039                         if (ahc->msgout_buf[index+2] == msgval
3040                          && type == AHCMSG_EXT) {
3041
3042                                 if (full) {
3043                                         if (ahc->msgout_index > end_index)
3044                                                 found = TRUE;
3045                                 } else if (ahc->msgout_index > index)
3046                                         found = TRUE;
3047                         }
3048                         index = end_index;
3049                 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
3050                         && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3051
3052                         /* Skip tag type and tag id or residue param*/
3053                         index += 2;
3054                 } else {
3055                         /* Single byte message */
3056                         if (type == AHCMSG_1B
3057                          && ahc->msgout_buf[index] == msgval
3058                          && ahc->msgout_index > index)
3059                                 found = TRUE;
3060                         index++;
3061                 }
3062
3063                 if (found)
3064                         break;
3065         }
3066         return (found);
3067 }
3068
3069 /*
3070  * Wait for a complete incoming message, parse it, and respond accordingly.
3071  */
3072 static int
3073 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3074 {
3075         struct  ahc_initiator_tinfo *tinfo;
3076         struct  ahc_tmode_tstate *tstate;
3077         int     reject;
3078         int     done;
3079         int     response;
3080         u_int   targ_scsirate;
3081
3082         done = MSGLOOP_IN_PROG;
3083         response = FALSE;
3084         reject = FALSE;
3085         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3086                                     devinfo->target, &tstate);
3087         targ_scsirate = tinfo->scsirate;
3088
3089         /*
3090          * Parse as much of the message as is available,
3091          * rejecting it if we don't support it.  When
3092          * the entire message is available and has been
3093          * handled, return MSGLOOP_MSGCOMPLETE, indicating
3094          * that we have parsed an entire message.
3095          *
3096          * In the case of extended messages, we accept the length
3097          * byte outright and perform more checking once we know the
3098          * extended message type.
3099          */
3100         switch (ahc->msgin_buf[0]) {
3101         case MSG_DISCONNECT:
3102         case MSG_SAVEDATAPOINTER:
3103         case MSG_CMDCOMPLETE:
3104         case MSG_RESTOREPOINTERS:
3105         case MSG_IGN_WIDE_RESIDUE:
3106                 /*
3107                  * End our message loop as these are messages
3108                  * the sequencer handles on its own.
3109                  */
3110                 done = MSGLOOP_TERMINATED;
3111                 break;
3112         case MSG_MESSAGE_REJECT:
3113                 response = ahc_handle_msg_reject(ahc, devinfo);
3114                 /* FALLTHROUGH */
3115         case MSG_NOOP:
3116                 done = MSGLOOP_MSGCOMPLETE;
3117                 break;
3118         case MSG_EXTENDED:
3119         {
3120                 /* Wait for enough of the message to begin validation */
3121                 if (ahc->msgin_index < 2)
3122                         break;
3123                 switch (ahc->msgin_buf[2]) {
3124                 case MSG_EXT_SDTR:
3125                 {
3126                         struct   ahc_syncrate *syncrate;
3127                         u_int    period;
3128                         u_int    ppr_options;
3129                         u_int    offset;
3130                         u_int    saved_offset;
3131                         
3132                         if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3133                                 reject = TRUE;
3134                                 break;
3135                         }
3136
3137                         /*
3138                          * Wait until we have both args before validating
3139                          * and acting on this message.
3140                          *
3141                          * Add one to MSG_EXT_SDTR_LEN to account for
3142                          * the extended message preamble.
3143                          */
3144                         if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3145                                 break;
3146
3147                         period = ahc->msgin_buf[3];
3148                         ppr_options = 0;
3149                         saved_offset = offset = ahc->msgin_buf[4];
3150                         syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3151                                                            &ppr_options,
3152                                                            devinfo->role);
3153                         ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3154                                             targ_scsirate & WIDEXFER,
3155                                             devinfo->role);
3156                         if (bootverbose) {
3157                                 kprintf("(%s:%c:%d:%d): Received "
3158                                        "SDTR period %x, offset %x\n\t"
3159                                        "Filtered to period %x, offset %x\n",
3160                                        ahc_name(ahc), devinfo->channel,
3161                                        devinfo->target, devinfo->lun,
3162                                        ahc->msgin_buf[3], saved_offset,
3163                                        period, offset);
3164                         }
3165                         ahc_set_syncrate(ahc, devinfo, 
3166                                          syncrate, period,
3167                                          offset, ppr_options,
3168                                          AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3169                                          /*paused*/TRUE);
3170
3171                         /*
3172                          * See if we initiated Sync Negotiation
3173                          * and didn't have to fall down to async
3174                          * transfers.
3175                          */
3176                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3177                                 /* We started it */
3178                                 if (saved_offset != offset) {
3179                                         /* Went too low - force async */
3180                                         reject = TRUE;
3181                                 }
3182                         } else {
3183                                 /*
3184                                  * Send our own SDTR in reply
3185                                  */
3186                                 if (bootverbose
3187                                  && devinfo->role == ROLE_INITIATOR) {
3188                                         kprintf("(%s:%c:%d:%d): Target "
3189                                                "Initiated SDTR\n",
3190                                                ahc_name(ahc), devinfo->channel,
3191                                                devinfo->target, devinfo->lun);
3192                                 }
3193                                 ahc->msgout_index = 0;
3194                                 ahc->msgout_len = 0;
3195                                 ahc_construct_sdtr(ahc, devinfo,
3196                                                    period, offset);
3197                                 ahc->msgout_index = 0;
3198                                 response = TRUE;
3199                         }
3200                         done = MSGLOOP_MSGCOMPLETE;
3201                         break;
3202                 }
3203                 case MSG_EXT_WDTR:
3204                 {
3205                         u_int bus_width;
3206                         u_int saved_width;
3207                         u_int sending_reply;
3208
3209                         sending_reply = FALSE;
3210                         if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3211                                 reject = TRUE;
3212                                 break;
3213                         }
3214
3215                         /*
3216                          * Wait until we have our arg before validating
3217                          * and acting on this message.
3218                          *
3219                          * Add one to MSG_EXT_WDTR_LEN to account for
3220                          * the extended message preamble.
3221                          */
3222                         if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3223                                 break;
3224
3225                         bus_width = ahc->msgin_buf[3];
3226                         saved_width = bus_width;
3227                         ahc_validate_width(ahc, tinfo, &bus_width,
3228                                            devinfo->role);
3229                         if (bootverbose) {
3230                                 kprintf("(%s:%c:%d:%d): Received WDTR "
3231                                        "%x filtered to %x\n",
3232                                        ahc_name(ahc), devinfo->channel,
3233                                        devinfo->target, devinfo->lun,
3234                                        saved_width, bus_width);
3235                         }
3236
3237                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3238                                 /*
3239                                  * Don't send a WDTR back to the
3240                                  * target, since we asked first.
3241                                  * If the width went higher than our
3242                                  * request, reject it.
3243                                  */
3244                                 if (saved_width > bus_width) {
3245                                         reject = TRUE;
3246                                         kprintf("(%s:%c:%d:%d): requested %dBit "
3247                                                "transfers.  Rejecting...\n",
3248                                                ahc_name(ahc), devinfo->channel,
3249                                                devinfo->target, devinfo->lun,
3250                                                8 * (0x01 << bus_width));
3251                                         bus_width = 0;
3252                                 }
3253                         } else {
3254                                 /*
3255                                  * Send our own WDTR in reply
3256                                  */
3257                                 if (bootverbose
3258                                  && devinfo->role == ROLE_INITIATOR) {
3259                                         kprintf("(%s:%c:%d:%d): Target "
3260                                                "Initiated WDTR\n",
3261                                                ahc_name(ahc), devinfo->channel,
3262                                                devinfo->target, devinfo->lun);
3263                                 }
3264                                 ahc->msgout_index = 0;
3265                                 ahc->msgout_len = 0;
3266                                 ahc_construct_wdtr(ahc, devinfo, bus_width);
3267                                 ahc->msgout_index = 0;
3268                                 response = TRUE;
3269                                 sending_reply = TRUE;
3270                         }
3271                         /*
3272                          * After a wide message, we are async, but
3273                          * some devices don't seem to honor this portion
3274                          * of the spec.  Force a renegotiation of the
3275                          * sync component of our transfer agreement even
3276                          * if our goal is async.  By updating our width
3277                          * after forcing the negotiation, we avoid
3278                          * renegotiating for width.
3279                          */
3280                         ahc_update_neg_request(ahc, devinfo, tstate,
3281                                                tinfo, AHC_NEG_ALWAYS);
3282                         ahc_set_width(ahc, devinfo, bus_width,
3283                                       AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3284                                       /*paused*/TRUE);
3285                         if (sending_reply == FALSE && reject == FALSE) {
3286
3287                                 /*
3288                                  * We will always have an SDTR to send.
3289                                  */
3290                                 ahc->msgout_index = 0;
3291                                 ahc->msgout_len = 0;
3292                                 ahc_build_transfer_msg(ahc, devinfo);
3293                                 ahc->msgout_index = 0;
3294                                 response = TRUE;
3295                         }
3296                         done = MSGLOOP_MSGCOMPLETE;
3297                         break;
3298                 }
3299                 case MSG_EXT_PPR:
3300                 {
3301                         struct  ahc_syncrate *syncrate;
3302                         u_int   period;
3303                         u_int   offset;
3304                         u_int   bus_width;
3305                         u_int   ppr_options;
3306                         u_int   saved_width;
3307                         u_int   saved_offset;
3308                         u_int   saved_ppr_options;
3309
3310                         if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3311                                 reject = TRUE;
3312                                 break;
3313                         }
3314
3315                         /*
3316                          * Wait until we have all args before validating
3317                          * and acting on this message.
3318                          *
3319                          * Add one to MSG_EXT_PPR_LEN to account for
3320                          * the extended message preamble.
3321                          */
3322                         if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3323                                 break;
3324
3325                         period = ahc->msgin_buf[3];
3326                         offset = ahc->msgin_buf[5];
3327                         bus_width = ahc->msgin_buf[6];
3328                         saved_width = bus_width;
3329                         ppr_options = ahc->msgin_buf[7];
3330                         /*
3331                          * According to the spec, a DT only
3332                          * period factor with no DT option
3333                          * set implies async.
3334                          */
3335                         if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3336                          && period == 9)
3337                                 offset = 0;
3338                         saved_ppr_options = ppr_options;
3339                         saved_offset = offset;
3340
3341                         /*
3342                          * Mask out any options we don't support
3343                          * on any controller.  Transfer options are
3344                          * only available if we are negotiating wide.
3345                          */
3346                         ppr_options &= MSG_EXT_PPR_DT_REQ;
3347                         if (bus_width == 0)
3348                                 ppr_options = 0;
3349
3350                         ahc_validate_width(ahc, tinfo, &bus_width,
3351                                            devinfo->role);
3352                         syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3353                                                            &ppr_options,
3354                                                            devinfo->role);
3355                         ahc_validate_offset(ahc, tinfo, syncrate,
3356                                             &offset, bus_width,
3357                                             devinfo->role);
3358
3359                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3360                                 /*
3361                                  * If we are unable to do any of the
3362                                  * requested options (we went too low),
3363                                  * then we'll have to reject the message.
3364                                  */
3365                                 if (saved_width > bus_width
3366                                  || saved_offset != offset
3367                                  || saved_ppr_options != ppr_options) {
3368                                         reject = TRUE;
3369                                         period = 0;
3370                                         offset = 0;
3371                                         bus_width = 0;
3372                                         ppr_options = 0;
3373                                         syncrate = NULL;
3374                                 }
3375                         } else {
3376                                 if (devinfo->role != ROLE_TARGET)
3377                                         kprintf("(%s:%c:%d:%d): Target "
3378                                                "Initiated PPR\n",
3379                                                ahc_name(ahc), devinfo->channel,
3380                                                devinfo->target, devinfo->lun);
3381                                 else
3382                                         kprintf("(%s:%c:%d:%d): Initiator "
3383                                                "Initiated PPR\n",
3384                                                ahc_name(ahc), devinfo->channel,
3385                                                devinfo->target, devinfo->lun);
3386                                 ahc->msgout_index = 0;
3387                                 ahc->msgout_len = 0;
3388                                 ahc_construct_ppr(ahc, devinfo, period, offset,
3389                                                   bus_width, ppr_options);
3390                                 ahc->msgout_index = 0;
3391                                 response = TRUE;
3392                         }