2 * Copyright (c) 2001-2011, Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 #include "opt_ifpoll.h"
35 #include <sys/param.h>
37 #include <sys/endian.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
44 #include <sys/serialize.h>
45 #include <sys/serialize2.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
52 #include <net/ethernet.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
58 #include <net/toeplitz.h>
59 #include <net/toeplitz2.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 #include <net/if_poll.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
68 #include <bus/pci/pcivar.h>
69 #include <bus/pci/pcireg.h>
71 #include <dev/netif/ig_hal/e1000_api.h>
72 #include <dev/netif/ig_hal/e1000_82575.h>
73 #include <dev/netif/igb/if_igb.h>
76 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
78 if (sc->rss_debug >= lvl) \
79 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
81 #else /* !IGB_RSS_DEBUG */
82 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
83 #endif /* IGB_RSS_DEBUG */
85 #define IGB_NAME "Intel(R) PRO/1000 "
86 #define IGB_DEVICE(id) \
87 { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
88 #define IGB_DEVICE_NULL { 0, 0, NULL }
90 static struct igb_device {
95 IGB_DEVICE(82575EB_COPPER),
96 IGB_DEVICE(82575EB_FIBER_SERDES),
97 IGB_DEVICE(82575GB_QUAD_COPPER),
100 IGB_DEVICE(82576_NS_SERDES),
101 IGB_DEVICE(82576_FIBER),
102 IGB_DEVICE(82576_SERDES),
103 IGB_DEVICE(82576_SERDES_QUAD),
104 IGB_DEVICE(82576_QUAD_COPPER),
105 IGB_DEVICE(82576_QUAD_COPPER_ET2),
106 IGB_DEVICE(82576_VF),
107 IGB_DEVICE(82580_COPPER),
108 IGB_DEVICE(82580_FIBER),
109 IGB_DEVICE(82580_SERDES),
110 IGB_DEVICE(82580_SGMII),
111 IGB_DEVICE(82580_COPPER_DUAL),
112 IGB_DEVICE(82580_QUAD_FIBER),
113 IGB_DEVICE(DH89XXCC_SERDES),
114 IGB_DEVICE(DH89XXCC_SGMII),
115 IGB_DEVICE(DH89XXCC_SFP),
116 IGB_DEVICE(DH89XXCC_BACKPLANE),
117 IGB_DEVICE(I350_COPPER),
118 IGB_DEVICE(I350_FIBER),
119 IGB_DEVICE(I350_SERDES),
120 IGB_DEVICE(I350_SGMII),
122 IGB_DEVICE(I210_COPPER),
123 IGB_DEVICE(I210_COPPER_IT),
124 IGB_DEVICE(I210_COPPER_OEM1),
125 IGB_DEVICE(I210_COPPER_FLASHLESS),
126 IGB_DEVICE(I210_SERDES_FLASHLESS),
127 IGB_DEVICE(I210_FIBER),
128 IGB_DEVICE(I210_SERDES),
129 IGB_DEVICE(I210_SGMII),
130 IGB_DEVICE(I211_COPPER),
131 IGB_DEVICE(I354_BACKPLANE_1GBPS),
132 IGB_DEVICE(I354_SGMII),
134 /* required last entry */
138 static int igb_probe(device_t);
139 static int igb_attach(device_t);
140 static int igb_detach(device_t);
141 static int igb_shutdown(device_t);
142 static int igb_suspend(device_t);
143 static int igb_resume(device_t);
145 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
146 static void igb_setup_ifp(struct igb_softc *);
147 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
148 static int igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
149 static void igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
150 static void igb_add_sysctl(struct igb_softc *);
151 static int igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
152 static int igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
153 static int igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
154 static int igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
155 static int igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
156 static void igb_set_ring_inuse(struct igb_softc *, boolean_t);
157 static int igb_get_rxring_inuse(const struct igb_softc *, boolean_t);
158 static int igb_get_txring_inuse(const struct igb_softc *, boolean_t);
159 static void igb_set_timer_cpuid(struct igb_softc *, boolean_t);
161 static int igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
162 static int igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
165 static void igb_vf_init_stats(struct igb_softc *);
166 static void igb_reset(struct igb_softc *);
167 static void igb_update_stats_counters(struct igb_softc *);
168 static void igb_update_vf_stats_counters(struct igb_softc *);
169 static void igb_update_link_status(struct igb_softc *);
170 static void igb_init_tx_unit(struct igb_softc *);
171 static void igb_init_rx_unit(struct igb_softc *);
173 static void igb_set_vlan(struct igb_softc *);
174 static void igb_set_multi(struct igb_softc *);
175 static void igb_set_promisc(struct igb_softc *);
176 static void igb_disable_promisc(struct igb_softc *);
178 static int igb_alloc_rings(struct igb_softc *);
179 static void igb_free_rings(struct igb_softc *);
180 static int igb_create_tx_ring(struct igb_tx_ring *);
181 static int igb_create_rx_ring(struct igb_rx_ring *);
182 static void igb_free_tx_ring(struct igb_tx_ring *);
183 static void igb_free_rx_ring(struct igb_rx_ring *);
184 static void igb_destroy_tx_ring(struct igb_tx_ring *, int);
185 static void igb_destroy_rx_ring(struct igb_rx_ring *, int);
186 static void igb_init_tx_ring(struct igb_tx_ring *);
187 static int igb_init_rx_ring(struct igb_rx_ring *);
188 static int igb_newbuf(struct igb_rx_ring *, int, boolean_t);
189 static int igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
190 static void igb_rx_refresh(struct igb_rx_ring *, int);
191 static void igb_setup_serializer(struct igb_softc *);
193 static void igb_stop(struct igb_softc *);
194 static void igb_init(void *);
195 static int igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
196 static void igb_media_status(struct ifnet *, struct ifmediareq *);
197 static int igb_media_change(struct ifnet *);
198 static void igb_timer(void *);
199 static void igb_watchdog(struct ifaltq_subque *);
200 static void igb_start(struct ifnet *, struct ifaltq_subque *);
202 static void igb_npoll(struct ifnet *, struct ifpoll_info *);
203 static void igb_npoll_rx(struct ifnet *, void *, int);
204 static void igb_npoll_tx(struct ifnet *, void *, int);
205 static void igb_npoll_status(struct ifnet *);
207 static void igb_serialize(struct ifnet *, enum ifnet_serialize);
208 static void igb_deserialize(struct ifnet *, enum ifnet_serialize);
209 static int igb_tryserialize(struct ifnet *, enum ifnet_serialize);
211 static void igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
215 static void igb_intr(void *);
216 static void igb_intr_shared(void *);
217 static void igb_rxeof(struct igb_rx_ring *, int);
218 static void igb_txeof(struct igb_tx_ring *);
219 static void igb_set_eitr(struct igb_softc *, int, int);
220 static void igb_enable_intr(struct igb_softc *);
221 static void igb_disable_intr(struct igb_softc *);
222 static void igb_init_unshared_intr(struct igb_softc *);
223 static void igb_init_intr(struct igb_softc *);
224 static int igb_setup_intr(struct igb_softc *);
225 static void igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
226 static void igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
227 static void igb_set_intr_mask(struct igb_softc *);
228 static int igb_alloc_intr(struct igb_softc *);
229 static void igb_free_intr(struct igb_softc *);
230 static void igb_teardown_intr(struct igb_softc *);
231 static void igb_msix_try_alloc(struct igb_softc *);
232 static void igb_msix_rx_conf(struct igb_softc *, int, int *, int);
233 static void igb_msix_tx_conf(struct igb_softc *, int, int *, int);
234 static void igb_msix_free(struct igb_softc *, boolean_t);
235 static int igb_msix_setup(struct igb_softc *);
236 static void igb_msix_teardown(struct igb_softc *, int);
237 static void igb_msix_rx(void *);
238 static void igb_msix_tx(void *);
239 static void igb_msix_status(void *);
240 static void igb_msix_rxtx(void *);
242 /* Management and WOL Support */
243 static void igb_get_mgmt(struct igb_softc *);
244 static void igb_rel_mgmt(struct igb_softc *);
245 static void igb_get_hw_control(struct igb_softc *);
246 static void igb_rel_hw_control(struct igb_softc *);
247 static void igb_enable_wol(device_t);
249 static device_method_t igb_methods[] = {
250 /* Device interface */
251 DEVMETHOD(device_probe, igb_probe),
252 DEVMETHOD(device_attach, igb_attach),
253 DEVMETHOD(device_detach, igb_detach),
254 DEVMETHOD(device_shutdown, igb_shutdown),
255 DEVMETHOD(device_suspend, igb_suspend),
256 DEVMETHOD(device_resume, igb_resume),
260 static driver_t igb_driver = {
263 sizeof(struct igb_softc),
266 static devclass_t igb_devclass;
268 DECLARE_DUMMY_MODULE(if_igb);
269 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
270 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
272 static int igb_rxd = IGB_DEFAULT_RXD;
273 static int igb_txd = IGB_DEFAULT_TXD;
274 static int igb_rxr = 0;
275 static int igb_txr = 0;
276 static int igb_msi_enable = 1;
277 static int igb_msix_enable = 1;
278 static int igb_eee_disabled = 1; /* Energy Efficient Ethernet */
279 static int igb_fc_setting = e1000_fc_full;
282 * DMA Coalescing, only for i350 - default to off,
283 * this feature is for power savings
285 static int igb_dma_coalesce = 0;
287 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
288 TUNABLE_INT("hw.igb.txd", &igb_txd);
289 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
290 TUNABLE_INT("hw.igb.txr", &igb_txr);
291 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
292 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
293 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
296 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
297 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
300 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
302 /* Ignore Checksum bit is set */
303 if (staterr & E1000_RXD_STAT_IXSM)
306 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
308 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
310 if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
311 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
312 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
313 CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
314 mp->m_pkthdr.csum_data = htons(0xffff);
319 static __inline struct pktinfo *
320 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
321 uint32_t hash, uint32_t hashtype, uint32_t staterr)
324 case E1000_RXDADV_RSSTYPE_IPV4_TCP:
325 pi->pi_netisr = NETISR_IP;
327 pi->pi_l3proto = IPPROTO_TCP;
330 case E1000_RXDADV_RSSTYPE_IPV4:
331 if (staterr & E1000_RXD_STAT_IXSM)
335 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
336 E1000_RXD_STAT_TCPCS) {
337 pi->pi_netisr = NETISR_IP;
339 pi->pi_l3proto = IPPROTO_UDP;
347 m->m_flags |= M_HASH;
348 m->m_pkthdr.hash = toeplitz_hash(hash);
353 igb_probe(device_t dev)
355 const struct igb_device *d;
358 vid = pci_get_vendor(dev);
359 did = pci_get_device(dev);
361 for (d = igb_devices; d->desc != NULL; ++d) {
362 if (vid == d->vid && did == d->did) {
363 device_set_desc(dev, d->desc);
371 igb_attach(device_t dev)
373 struct igb_softc *sc = device_get_softc(dev);
374 uint16_t eeprom_data;
375 int error = 0, ring_max;
377 int offset, offset_def;
382 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
383 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
384 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
385 igb_sysctl_nvm_info, "I", "NVM Information");
386 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
387 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
388 OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
389 adapter, 0, igb_set_flowcntl, "I", "Flow Control");
392 callout_init_mp(&sc->timer);
393 lwkt_serialize_init(&sc->main_serialize);
395 if_initname(&sc->arpcom.ac_if, device_get_name(dev),
396 device_get_unit(dev));
397 sc->dev = sc->osdep.dev = dev;
400 * Determine hardware and mac type
402 sc->hw.vendor_id = pci_get_vendor(dev);
403 sc->hw.device_id = pci_get_device(dev);
404 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
405 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
406 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
408 if (e1000_set_mac_type(&sc->hw))
411 /* Are we a VF device? */
412 if (sc->hw.mac.type == e1000_vfadapt ||
413 sc->hw.mac.type == e1000_vfadapt_i350)
419 * Configure total supported RX/TX ring count
421 switch (sc->hw.mac.type) {
423 ring_max = IGB_MAX_RING_82575;
427 ring_max = IGB_MAX_RING_82576;
431 ring_max = IGB_MAX_RING_82580;
435 ring_max = IGB_MAX_RING_I350;
439 ring_max = IGB_MAX_RING_I354;
443 ring_max = IGB_MAX_RING_I210;
447 ring_max = IGB_MAX_RING_I211;
451 ring_max = IGB_MIN_RING;
455 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
456 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
458 sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
460 sc->rx_ring_inuse = sc->rx_ring_cnt;
462 sc->tx_ring_cnt = device_getenv_int(dev, "txr", igb_txr);
463 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, ring_max);
465 sc->tx_ring_cnt = device_getenv_int(dev, "txr_debug", sc->tx_ring_cnt);
467 sc->tx_ring_inuse = sc->tx_ring_cnt;
469 /* Enable bus mastering */
470 pci_enable_busmaster(dev);
475 sc->mem_rid = PCIR_BAR(0);
476 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
478 if (sc->mem_res == NULL) {
479 device_printf(dev, "Unable to allocate bus resource: memory\n");
483 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
484 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
486 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
488 /* Save PCI command register for Shared Code */
489 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
490 sc->hw.back = &sc->osdep;
492 /* Do Shared Code initialization */
493 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
494 device_printf(dev, "Setup of Shared code failed\n");
499 e1000_get_bus_info(&sc->hw);
501 sc->hw.mac.autoneg = DO_AUTO_NEG;
502 sc->hw.phy.autoneg_wait_to_complete = FALSE;
503 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
506 if (sc->hw.phy.media_type == e1000_media_type_copper) {
507 sc->hw.phy.mdix = AUTO_ALL_MODES;
508 sc->hw.phy.disable_polarity_correction = FALSE;
509 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
512 /* Set the frame limits assuming standard ethernet sized frames. */
513 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
515 /* Allocate RX/TX rings */
516 error = igb_alloc_rings(sc);
522 * NPOLLING RX CPU offset
524 if (sc->rx_ring_cnt == ncpus2) {
527 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
528 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
529 if (offset >= ncpus2 ||
530 offset % sc->rx_ring_cnt != 0) {
531 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
536 sc->rx_npoll_off = offset;
539 * NPOLLING TX CPU offset
541 if (sc->tx_ring_cnt == ncpus2) {
544 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
545 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
546 if (offset >= ncpus2 ||
547 offset % sc->tx_ring_cnt != 0) {
548 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
553 sc->tx_npoll_off = offset;
556 /* Allocate interrupt */
557 error = igb_alloc_intr(sc);
561 /* Setup serializers */
562 igb_setup_serializer(sc);
564 /* Allocate the appropriate stats memory */
566 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
568 igb_vf_init_stats(sc);
570 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
574 /* Allocate multicast array memory. */
575 sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
578 /* Some adapter-specific advanced features */
579 if (sc->hw.mac.type >= e1000_i350) {
581 igb_set_sysctl_value(adapter, "dma_coalesce",
582 "configure dma coalesce",
583 &adapter->dma_coalesce, igb_dma_coalesce);
584 igb_set_sysctl_value(adapter, "eee_disabled",
585 "enable Energy Efficient Ethernet",
586 &adapter->hw.dev_spec._82575.eee_disable,
589 sc->dma_coalesce = igb_dma_coalesce;
590 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
592 if (sc->hw.phy.media_type == e1000_media_type_copper) {
593 if (sc->hw.mac.type == e1000_i354)
594 e1000_set_eee_i354(&sc->hw);
596 e1000_set_eee_i350(&sc->hw);
601 * Start from a known state, this is important in reading the nvm and
604 e1000_reset_hw(&sc->hw);
606 /* Make sure we have a good EEPROM before we read from it */
607 if (sc->hw.mac.type != e1000_i210 && sc->hw.mac.type != e1000_i211 &&
608 e1000_validate_nvm_checksum(&sc->hw) < 0) {
610 * Some PCI-E parts fail the first check due to
611 * the link being in sleep state, call it again,
612 * if it fails a second time its a real issue.
614 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
616 "The EEPROM Checksum Is Not Valid\n");
622 /* Copy the permanent MAC address out of the EEPROM */
623 if (e1000_read_mac_addr(&sc->hw) < 0) {
624 device_printf(dev, "EEPROM read error while reading MAC"
629 if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
630 device_printf(dev, "Invalid MAC address\n");
635 /* Setup OS specific network interface */
638 /* Add sysctl tree, must after igb_setup_ifp() */
641 /* Now get a good starting state */
644 /* Initialize statistics */
645 igb_update_stats_counters(sc);
647 sc->hw.mac.get_link_status = 1;
648 igb_update_link_status(sc);
650 /* Indicate SOL/IDER usage */
651 if (e1000_check_reset_block(&sc->hw)) {
653 "PHY reset is blocked due to SOL/IDER session.\n");
656 /* Determine if we have to control management hardware */
657 if (e1000_enable_mng_pass_thru(&sc->hw))
658 sc->flags |= IGB_FLAG_HAS_MGMT;
663 /* APME bit in EEPROM is mapped to WUC.APME */
664 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
666 sc->wol = E1000_WUFC_MAG;
667 /* XXX disable WOL */
671 /* Register for VLAN events */
672 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
673 igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
674 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
675 igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
679 igb_add_hw_stats(adapter);
683 * Disable interrupt to prevent spurious interrupts (line based
684 * interrupt, MSI or even MSI-X), which had been observed on
685 * several types of LOMs, from being handled.
687 igb_disable_intr(sc);
689 error = igb_setup_intr(sc);
691 ether_ifdetach(&sc->arpcom.ac_if);
702 igb_detach(device_t dev)
704 struct igb_softc *sc = device_get_softc(dev);
706 if (device_is_attached(dev)) {
707 struct ifnet *ifp = &sc->arpcom.ac_if;
709 ifnet_serialize_all(ifp);
713 e1000_phy_hw_reset(&sc->hw);
715 /* Give control back to firmware */
717 igb_rel_hw_control(sc);
720 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
721 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
725 igb_teardown_intr(sc);
727 ifnet_deserialize_all(ifp);
730 } else if (sc->mem_res != NULL) {
731 igb_rel_hw_control(sc);
733 bus_generic_detach(dev);
735 if (sc->sysctl_tree != NULL)
736 sysctl_ctx_free(&sc->sysctl_ctx);
740 if (sc->msix_mem_res != NULL) {
741 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
744 if (sc->mem_res != NULL) {
745 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
752 kfree(sc->mta, M_DEVBUF);
753 if (sc->stats != NULL)
754 kfree(sc->stats, M_DEVBUF);
755 if (sc->serializes != NULL)
756 kfree(sc->serializes, M_DEVBUF);
762 igb_shutdown(device_t dev)
764 return igb_suspend(dev);
768 igb_suspend(device_t dev)
770 struct igb_softc *sc = device_get_softc(dev);
771 struct ifnet *ifp = &sc->arpcom.ac_if;
773 ifnet_serialize_all(ifp);
778 igb_rel_hw_control(sc);
781 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
782 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
786 ifnet_deserialize_all(ifp);
788 return bus_generic_suspend(dev);
792 igb_resume(device_t dev)
794 struct igb_softc *sc = device_get_softc(dev);
795 struct ifnet *ifp = &sc->arpcom.ac_if;
798 ifnet_serialize_all(ifp);
803 for (i = 0; i < sc->tx_ring_inuse; ++i)
804 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
806 ifnet_deserialize_all(ifp);
808 return bus_generic_resume(dev);
812 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
814 struct igb_softc *sc = ifp->if_softc;
815 struct ifreq *ifr = (struct ifreq *)data;
816 int max_frame_size, mask, reinit;
819 ASSERT_IFNET_SERIALIZED_ALL(ifp);
823 max_frame_size = 9234;
824 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
830 ifp->if_mtu = ifr->ifr_mtu;
831 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
834 if (ifp->if_flags & IFF_RUNNING)
839 if (ifp->if_flags & IFF_UP) {
840 if (ifp->if_flags & IFF_RUNNING) {
841 if ((ifp->if_flags ^ sc->if_flags) &
842 (IFF_PROMISC | IFF_ALLMULTI)) {
843 igb_disable_promisc(sc);
849 } else if (ifp->if_flags & IFF_RUNNING) {
852 sc->if_flags = ifp->if_flags;
857 if (ifp->if_flags & IFF_RUNNING) {
858 igb_disable_intr(sc);
861 if (!(ifp->if_flags & IFF_NPOLLING))
868 /* Check SOL/IDER usage */
869 if (e1000_check_reset_block(&sc->hw)) {
870 if_printf(ifp, "Media change is "
871 "blocked due to SOL/IDER session.\n");
877 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
882 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
883 if (mask & IFCAP_RXCSUM) {
884 ifp->if_capenable ^= IFCAP_RXCSUM;
887 if (mask & IFCAP_VLAN_HWTAGGING) {
888 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
891 if (mask & IFCAP_TXCSUM) {
892 ifp->if_capenable ^= IFCAP_TXCSUM;
893 if (ifp->if_capenable & IFCAP_TXCSUM)
894 ifp->if_hwassist |= IGB_CSUM_FEATURES;
896 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
898 if (mask & IFCAP_TSO) {
899 ifp->if_capenable ^= IFCAP_TSO;
900 if (ifp->if_capenable & IFCAP_TSO)
901 ifp->if_hwassist |= CSUM_TSO;
903 ifp->if_hwassist &= ~CSUM_TSO;
905 if (mask & IFCAP_RSS)
906 ifp->if_capenable ^= IFCAP_RSS;
907 if (reinit && (ifp->if_flags & IFF_RUNNING))
912 error = ether_ioctl(ifp, command, data);
921 struct igb_softc *sc = xsc;
922 struct ifnet *ifp = &sc->arpcom.ac_if;
926 ASSERT_IFNET_SERIALIZED_ALL(ifp);
930 /* Get the latest mac address, User can use a LAA */
931 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
933 /* Put the address into the Receive Address Array */
934 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
937 igb_update_link_status(sc);
939 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
941 /* Configure for OS presence */
946 if (ifp->if_flags & IFF_NPOLLING)
950 /* Configured used RX/TX rings */
951 igb_set_ring_inuse(sc, polling);
952 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
954 /* Initialize interrupt */
957 /* Prepare transmit descriptors and buffers */
958 for (i = 0; i < sc->tx_ring_inuse; ++i)
959 igb_init_tx_ring(&sc->tx_rings[i]);
960 igb_init_tx_unit(sc);
962 /* Setup Multicast table */
967 * Figure out the desired mbuf pool
968 * for doing jumbo/packetsplit
970 if (adapter->max_frame_size <= 2048)
971 adapter->rx_mbuf_sz = MCLBYTES;
972 else if (adapter->max_frame_size <= 4096)
973 adapter->rx_mbuf_sz = MJUMPAGESIZE;
975 adapter->rx_mbuf_sz = MJUM9BYTES;
978 /* Prepare receive descriptors and buffers */
979 for (i = 0; i < sc->rx_ring_inuse; ++i) {
982 error = igb_init_rx_ring(&sc->rx_rings[i]);
984 if_printf(ifp, "Could not setup receive structures\n");
989 igb_init_rx_unit(sc);
991 /* Enable VLAN support */
992 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
995 /* Don't lose promiscuous settings */
998 ifp->if_flags |= IFF_RUNNING;
999 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1000 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
1001 ifsq_watchdog_start(&sc->tx_rings[i].tx_watchdog);
1004 igb_set_timer_cpuid(sc, polling);
1005 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1006 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1008 /* This clears any pending interrupts */
1009 E1000_READ_REG(&sc->hw, E1000_ICR);
1012 * Only enable interrupts if we are not polling, make sure
1013 * they are off otherwise.
1016 igb_disable_intr(sc);
1018 igb_enable_intr(sc);
1019 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1022 /* Set Energy Efficient Ethernet */
1023 if (sc->hw.phy.media_type == e1000_media_type_copper) {
1024 if (sc->hw.mac.type == e1000_i354)
1025 e1000_set_eee_i354(&sc->hw);
1027 e1000_set_eee_i350(&sc->hw);
1032 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1034 struct igb_softc *sc = ifp->if_softc;
1036 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1038 if ((ifp->if_flags & IFF_RUNNING) == 0)
1039 sc->hw.mac.get_link_status = 1;
1040 igb_update_link_status(sc);
1042 ifmr->ifm_status = IFM_AVALID;
1043 ifmr->ifm_active = IFM_ETHER;
1045 if (!sc->link_active)
1048 ifmr->ifm_status |= IFM_ACTIVE;
1050 switch (sc->link_speed) {
1052 ifmr->ifm_active |= IFM_10_T;
1057 * Support for 100Mb SFP - these are Fiber
1058 * but the media type appears as serdes
1060 if (sc->hw.phy.media_type == e1000_media_type_internal_serdes)
1061 ifmr->ifm_active |= IFM_100_FX;
1063 ifmr->ifm_active |= IFM_100_TX;
1067 ifmr->ifm_active |= IFM_1000_T;
1071 if (sc->link_duplex == FULL_DUPLEX)
1072 ifmr->ifm_active |= IFM_FDX;
1074 ifmr->ifm_active |= IFM_HDX;
1078 igb_media_change(struct ifnet *ifp)
1080 struct igb_softc *sc = ifp->if_softc;
1081 struct ifmedia *ifm = &sc->media;
1083 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1085 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1088 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1090 sc->hw.mac.autoneg = DO_AUTO_NEG;
1091 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1097 sc->hw.mac.autoneg = DO_AUTO_NEG;
1098 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1102 sc->hw.mac.autoneg = FALSE;
1103 sc->hw.phy.autoneg_advertised = 0;
1104 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1105 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1107 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1111 sc->hw.mac.autoneg = FALSE;
1112 sc->hw.phy.autoneg_advertised = 0;
1113 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1114 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1116 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1120 if_printf(ifp, "Unsupported media type\n");
1130 igb_set_promisc(struct igb_softc *sc)
1132 struct ifnet *ifp = &sc->arpcom.ac_if;
1133 struct e1000_hw *hw = &sc->hw;
1137 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1141 reg = E1000_READ_REG(hw, E1000_RCTL);
1142 if (ifp->if_flags & IFF_PROMISC) {
1143 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1144 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1145 } else if (ifp->if_flags & IFF_ALLMULTI) {
1146 reg |= E1000_RCTL_MPE;
1147 reg &= ~E1000_RCTL_UPE;
1148 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1153 igb_disable_promisc(struct igb_softc *sc)
1155 struct e1000_hw *hw = &sc->hw;
1156 struct ifnet *ifp = &sc->arpcom.ac_if;
1161 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1164 reg = E1000_READ_REG(hw, E1000_RCTL);
1165 reg &= ~E1000_RCTL_UPE;
1166 if (ifp->if_flags & IFF_ALLMULTI) {
1167 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1169 struct ifmultiaddr *ifma;
1170 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1171 if (ifma->ifma_addr->sa_family != AF_LINK)
1173 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1178 /* Don't disable if in MAX groups */
1179 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1180 reg &= ~E1000_RCTL_MPE;
1181 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1185 igb_set_multi(struct igb_softc *sc)
1187 struct ifnet *ifp = &sc->arpcom.ac_if;
1188 struct ifmultiaddr *ifma;
1189 uint32_t reg_rctl = 0;
1194 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1196 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1197 if (ifma->ifma_addr->sa_family != AF_LINK)
1200 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1203 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1204 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1208 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1209 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1210 reg_rctl |= E1000_RCTL_MPE;
1211 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1213 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1218 igb_timer(void *xsc)
1220 struct igb_softc *sc = xsc;
1222 lwkt_serialize_enter(&sc->main_serialize);
1224 igb_update_link_status(sc);
1225 igb_update_stats_counters(sc);
1227 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1229 lwkt_serialize_exit(&sc->main_serialize);
1233 igb_update_link_status(struct igb_softc *sc)
1235 struct ifnet *ifp = &sc->arpcom.ac_if;
1236 struct e1000_hw *hw = &sc->hw;
1237 uint32_t link_check, thstat, ctrl;
1239 link_check = thstat = ctrl = 0;
1241 /* Get the cached link value or read for real */
1242 switch (hw->phy.media_type) {
1243 case e1000_media_type_copper:
1244 if (hw->mac.get_link_status) {
1245 /* Do the work to read phy */
1246 e1000_check_for_link(hw);
1247 link_check = !hw->mac.get_link_status;
1253 case e1000_media_type_fiber:
1254 e1000_check_for_link(hw);
1255 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1258 case e1000_media_type_internal_serdes:
1259 e1000_check_for_link(hw);
1260 link_check = hw->mac.serdes_has_link;
1263 /* VF device is type_unknown */
1264 case e1000_media_type_unknown:
1265 e1000_check_for_link(hw);
1266 link_check = !hw->mac.get_link_status;
1272 /* Check for thermal downshift or shutdown */
1273 if (hw->mac.type == e1000_i350) {
1274 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1275 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1278 /* Now we check if a transition has happened */
1279 if (link_check && sc->link_active == 0) {
1280 e1000_get_speed_and_duplex(hw,
1281 &sc->link_speed, &sc->link_duplex);
1283 const char *flowctl;
1285 /* Get the flow control for display */
1286 switch (hw->fc.current_mode) {
1287 case e1000_fc_rx_pause:
1291 case e1000_fc_tx_pause:
1304 if_printf(ifp, "Link is up %d Mbps %s, "
1305 "Flow control: %s\n",
1307 sc->link_duplex == FULL_DUPLEX ?
1308 "Full Duplex" : "Half Duplex",
1311 sc->link_active = 1;
1313 ifp->if_baudrate = sc->link_speed * 1000000;
1314 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1315 (thstat & E1000_THSTAT_LINK_THROTTLE))
1316 if_printf(ifp, "Link: thermal downshift\n");
1317 /* Delay Link Up for Phy update */
1318 if ((hw->mac.type == e1000_i210 ||
1319 hw->mac.type == e1000_i211) &&
1320 hw->phy.id == I210_I_PHY_ID)
1321 msec_delay(IGB_I210_LINK_DELAY);
1322 /* This can sleep */
1323 ifp->if_link_state = LINK_STATE_UP;
1324 if_link_state_change(ifp);
1325 } else if (!link_check && sc->link_active == 1) {
1326 ifp->if_baudrate = sc->link_speed = 0;
1327 sc->link_duplex = 0;
1329 if_printf(ifp, "Link is Down\n");
1330 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1331 (thstat & E1000_THSTAT_PWR_DOWN))
1332 if_printf(ifp, "Link: thermal shutdown\n");
1333 sc->link_active = 0;
1334 /* This can sleep */
1335 ifp->if_link_state = LINK_STATE_DOWN;
1336 if_link_state_change(ifp);
1341 igb_stop(struct igb_softc *sc)
1343 struct ifnet *ifp = &sc->arpcom.ac_if;
1346 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1348 igb_disable_intr(sc);
1350 callout_stop(&sc->timer);
1352 ifp->if_flags &= ~IFF_RUNNING;
1353 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1354 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
1355 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
1356 sc->tx_rings[i].tx_flags &= ~IGB_TXFLAG_ENABLED;
1359 e1000_reset_hw(&sc->hw);
1360 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1362 e1000_led_off(&sc->hw);
1363 e1000_cleanup_led(&sc->hw);
1365 for (i = 0; i < sc->tx_ring_cnt; ++i)
1366 igb_free_tx_ring(&sc->tx_rings[i]);
1367 for (i = 0; i < sc->rx_ring_cnt; ++i)
1368 igb_free_rx_ring(&sc->rx_rings[i]);
1372 igb_reset(struct igb_softc *sc)
1374 struct ifnet *ifp = &sc->arpcom.ac_if;
1375 struct e1000_hw *hw = &sc->hw;
1376 struct e1000_fc_info *fc = &hw->fc;
1380 /* Let the firmware know the OS is in control */
1381 igb_get_hw_control(sc);
1384 * Packet Buffer Allocation (PBA)
1385 * Writing PBA sets the receive portion of the buffer
1386 * the remainder is used for the transmit buffer.
1388 switch (hw->mac.type) {
1390 pba = E1000_PBA_32K;
1395 pba = E1000_READ_REG(hw, E1000_RXPBS);
1396 pba &= E1000_RXPBS_SIZE_MASK_82576;
1402 case e1000_vfadapt_i350:
1403 pba = E1000_READ_REG(hw, E1000_RXPBS);
1404 pba = e1000_rxpbs_adjust_82580(pba);
1409 pba = E1000_PBA_34K;
1416 /* Special needs in case of Jumbo frames */
1417 if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1418 uint32_t tx_space, min_tx, min_rx;
1420 pba = E1000_READ_REG(hw, E1000_PBA);
1421 tx_space = pba >> 16;
1424 min_tx = (sc->max_frame_size +
1425 sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1426 min_tx = roundup2(min_tx, 1024);
1428 min_rx = sc->max_frame_size;
1429 min_rx = roundup2(min_rx, 1024);
1431 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1432 pba = pba - (min_tx - tx_space);
1434 * if short on rx space, rx wins
1435 * and must trump tx adjustment
1440 E1000_WRITE_REG(hw, E1000_PBA, pba);
1444 * These parameters control the automatic generation (Tx) and
1445 * response (Rx) to Ethernet PAUSE frames.
1446 * - High water mark should allow for at least two frames to be
1447 * received after sending an XOFF.
1448 * - Low water mark works best when it is very near the high water mark.
1449 * This allows the receiver to restart by sending XON when it has
1452 hwm = min(((pba << 10) * 9 / 10),
1453 ((pba << 10) - 2 * sc->max_frame_size));
1455 if (hw->mac.type < e1000_82576) {
1456 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1457 fc->low_water = fc->high_water - 8;
1459 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1460 fc->low_water = fc->high_water - 16;
1462 fc->pause_time = IGB_FC_PAUSE_TIME;
1463 fc->send_xon = TRUE;
1464 fc->requested_mode = e1000_fc_default;
1466 /* Issue a global reset */
1468 E1000_WRITE_REG(hw, E1000_WUC, 0);
1470 if (e1000_init_hw(hw) < 0)
1471 if_printf(ifp, "Hardware Initialization Failed\n");
1473 /* Setup DMA Coalescing */
1474 if (hw->mac.type > e1000_82580 && hw->mac.type != e1000_i211) {
1478 if (sc->dma_coalesce == 0) {
1482 reg = E1000_READ_REG(hw, E1000_DMACR);
1483 reg &= ~E1000_DMACR_DMAC_EN;
1484 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1488 /* Set starting thresholds */
1489 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
1490 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1492 hwm = 64 * pba - sc->max_frame_size / 16;
1493 if (hwm < 64 * (pba - 6))
1494 hwm = 64 * (pba - 6);
1495 reg = E1000_READ_REG(hw, E1000_FCRTC);
1496 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
1497 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
1498 & E1000_FCRTC_RTH_COAL_MASK);
1499 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
1501 dmac = pba - sc->max_frame_size / 512;
1502 if (dmac < pba - 10)
1504 reg = E1000_READ_REG(hw, E1000_DMACR);
1505 reg &= ~E1000_DMACR_DMACTHR_MASK;
1506 reg = ((dmac << E1000_DMACR_DMACTHR_SHIFT)
1507 & E1000_DMACR_DMACTHR_MASK);
1508 /* Transition to L0x or L1 if available.. */
1509 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1510 /* timer = value in sc->dma_coalesce in 32usec intervals */
1511 reg |= (sc->dma_coalesce >> 5);
1512 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1514 /* Set the interval before transition */
1515 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1517 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1519 /* Free space in tx packet buffer to wake from DMA coal */
1520 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1521 (20480 - (2 * sc->max_frame_size)) >> 6);
1523 /* Make low power state decision controlled by DMA coal */
1524 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1525 reg &= ~E1000_PCIEMISC_LX_DECISION;
1526 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
1527 if_printf(ifp, "DMA Coalescing enabled\n");
1528 } else if (hw->mac.type == e1000_82580) {
1529 uint32_t reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1531 E1000_WRITE_REG(hw, E1000_DMACR, 0);
1532 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1533 reg & ~E1000_PCIEMISC_LX_DECISION);
1537 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1538 e1000_get_phy_info(hw);
1539 e1000_check_for_link(hw);
1543 igb_setup_ifp(struct igb_softc *sc)
1545 struct ifnet *ifp = &sc->arpcom.ac_if;
1549 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1550 ifp->if_init = igb_init;
1551 ifp->if_ioctl = igb_ioctl;
1552 ifp->if_start = igb_start;
1553 ifp->if_serialize = igb_serialize;
1554 ifp->if_deserialize = igb_deserialize;
1555 ifp->if_tryserialize = igb_tryserialize;
1557 ifp->if_serialize_assert = igb_serialize_assert;
1559 #ifdef IFPOLL_ENABLE
1560 ifp->if_npoll = igb_npoll;
1563 ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1564 ifq_set_ready(&ifp->if_snd);
1565 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
1567 ifp->if_mapsubq = ifq_mapsubq_mask;
1568 ifq_set_subq_mask(&ifp->if_snd, 0);
1570 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1572 ifp->if_capabilities =
1573 IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1574 if (IGB_ENABLE_HWRSS(sc))
1575 ifp->if_capabilities |= IFCAP_RSS;
1576 ifp->if_capenable = ifp->if_capabilities;
1577 ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1580 * Tell the upper layer(s) we support long frames
1582 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1584 /* Setup TX rings and subqueues */
1585 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1586 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
1587 struct igb_tx_ring *txr = &sc->tx_rings[i];
1589 ifsq_set_cpuid(ifsq, txr->tx_intr_cpuid);
1590 ifsq_set_priv(ifsq, txr);
1591 ifsq_set_hw_serialize(ifsq, &txr->tx_serialize);
1594 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, igb_watchdog);
1598 * Specify the media types supported by this adapter and register
1599 * callbacks to update media and link information
1601 ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1602 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1603 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1604 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1606 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1608 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1609 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1611 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1612 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1614 if (sc->hw.phy.type != e1000_phy_ife) {
1615 ifmedia_add(&sc->media,
1616 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1617 ifmedia_add(&sc->media,
1618 IFM_ETHER | IFM_1000_T, 0, NULL);
1621 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1622 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1626 igb_add_sysctl(struct igb_softc *sc)
1631 sysctl_ctx_init(&sc->sysctl_ctx);
1632 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1633 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1634 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1635 if (sc->sysctl_tree == NULL) {
1636 device_printf(sc->dev, "can't add sysctl node\n");
1640 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1641 OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1642 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1643 OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1644 "# of RX rings used");
1645 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1646 OID_AUTO, "txr", CTLFLAG_RD, &sc->tx_ring_cnt, 0, "# of TX rings");
1647 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1648 OID_AUTO, "txr_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
1649 "# of TX rings used");
1650 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1651 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1653 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1654 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1657 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1658 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1659 SYSCTL_CHILDREN(sc->sysctl_tree),
1660 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1661 sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1663 for (i = 0; i < sc->msix_cnt; ++i) {
1664 struct igb_msix_data *msix = &sc->msix_data[i];
1666 ksnprintf(node, sizeof(node), "msix%d_rate", i);
1667 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1668 SYSCTL_CHILDREN(sc->sysctl_tree),
1669 OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1670 msix, 0, igb_sysctl_msix_rate, "I",
1671 msix->msix_rate_desc);
1675 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1676 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1677 sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1678 "# of segments per TX interrupt");
1680 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1681 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1682 sc, 0, igb_sysctl_tx_wreg_nsegs, "I",
1683 "# of segments sent before write to hardware register");
1685 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1686 OID_AUTO, "rx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1687 sc, 0, igb_sysctl_rx_wreg_nsegs, "I",
1688 "# of segments received before write to hardware register");
1690 #ifdef IFPOLL_ENABLE
1691 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1692 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1693 sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1694 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1695 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1696 sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1699 #ifdef IGB_RSS_DEBUG
1700 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1701 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1703 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1704 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1705 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1706 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1707 CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1710 #ifdef IGB_TSS_DEBUG
1711 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1712 ksnprintf(node, sizeof(node), "tx%d_pkt", i);
1713 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1714 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1715 CTLFLAG_RW, &sc->tx_rings[i].tx_packets, "TXed packets");
1721 igb_alloc_rings(struct igb_softc *sc)
1726 * Create top level busdma tag
1728 error = bus_dma_tag_create(NULL, 1, 0,
1729 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1730 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1733 device_printf(sc->dev, "could not create top level DMA tag\n");
1738 * Allocate TX descriptor rings and buffers
1740 sc->tx_rings = kmalloc_cachealign(
1741 sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1742 M_DEVBUF, M_WAITOK | M_ZERO);
1743 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1744 struct igb_tx_ring *txr = &sc->tx_rings[i];
1746 /* Set up some basics */
1749 lwkt_serialize_init(&txr->tx_serialize);
1751 error = igb_create_tx_ring(txr);
1757 * Allocate RX descriptor rings and buffers
1759 sc->rx_rings = kmalloc_cachealign(
1760 sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1761 M_DEVBUF, M_WAITOK | M_ZERO);
1762 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1763 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1765 /* Set up some basics */
1768 lwkt_serialize_init(&rxr->rx_serialize);
1770 error = igb_create_rx_ring(rxr);
1779 igb_free_rings(struct igb_softc *sc)
1783 if (sc->tx_rings != NULL) {
1784 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1785 struct igb_tx_ring *txr = &sc->tx_rings[i];
1787 igb_destroy_tx_ring(txr, txr->num_tx_desc);
1789 kfree(sc->tx_rings, M_DEVBUF);
1792 if (sc->rx_rings != NULL) {
1793 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1794 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1796 igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1798 kfree(sc->rx_rings, M_DEVBUF);
1803 igb_create_tx_ring(struct igb_tx_ring *txr)
1805 int tsize, error, i, ntxd;
1808 * Validate number of transmit descriptors. It must not exceed
1809 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1811 ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1812 if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1813 ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1814 device_printf(txr->sc->dev,
1815 "Using %d TX descriptors instead of %d!\n",
1816 IGB_DEFAULT_TXD, ntxd);
1817 txr->num_tx_desc = IGB_DEFAULT_TXD;
1819 txr->num_tx_desc = ntxd;
1823 * Allocate TX descriptor ring
1825 tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1827 txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1828 IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1829 &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1830 if (txr->txdma.dma_vaddr == NULL) {
1831 device_printf(txr->sc->dev,
1832 "Unable to allocate TX Descriptor memory\n");
1835 txr->tx_base = txr->txdma.dma_vaddr;
1836 bzero(txr->tx_base, tsize);
1838 tsize = __VM_CACHELINE_ALIGN(
1839 sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1840 txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1843 * Allocate TX head write-back buffer
1845 txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1846 __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1847 &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1848 if (txr->tx_hdr == NULL) {
1849 device_printf(txr->sc->dev,
1850 "Unable to allocate TX head write-back buffer\n");
1855 * Create DMA tag for TX buffers
1857 error = bus_dma_tag_create(txr->sc->parent_tag,
1858 1, 0, /* alignment, bounds */
1859 BUS_SPACE_MAXADDR, /* lowaddr */
1860 BUS_SPACE_MAXADDR, /* highaddr */
1861 NULL, NULL, /* filter, filterarg */
1862 IGB_TSO_SIZE, /* maxsize */
1863 IGB_MAX_SCATTER, /* nsegments */
1864 PAGE_SIZE, /* maxsegsize */
1865 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1866 BUS_DMA_ONEBPAGE, /* flags */
1869 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1870 kfree(txr->tx_buf, M_DEVBUF);
1876 * Create DMA maps for TX buffers
1878 for (i = 0; i < txr->num_tx_desc; ++i) {
1879 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1881 error = bus_dmamap_create(txr->tx_tag,
1882 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1884 device_printf(txr->sc->dev,
1885 "Unable to create TX DMA map\n");
1886 igb_destroy_tx_ring(txr, i);
1891 if (txr->sc->hw.mac.type == e1000_82575)
1892 txr->tx_flags |= IGB_TXFLAG_TSO_IPLEN0;
1895 * Initialize various watermark
1897 txr->spare_desc = IGB_TX_SPARE;
1898 txr->intr_nsegs = txr->num_tx_desc / 16;
1899 txr->wreg_nsegs = IGB_DEF_TXWREG_NSEGS;
1900 txr->oact_hi_desc = txr->num_tx_desc / 2;
1901 txr->oact_lo_desc = txr->num_tx_desc / 8;
1902 if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1903 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1904 if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1905 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1911 igb_free_tx_ring(struct igb_tx_ring *txr)
1915 for (i = 0; i < txr->num_tx_desc; ++i) {
1916 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1918 if (txbuf->m_head != NULL) {
1919 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1920 m_freem(txbuf->m_head);
1921 txbuf->m_head = NULL;
1927 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1931 if (txr->txdma.dma_vaddr != NULL) {
1932 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1933 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1934 txr->txdma.dma_map);
1935 bus_dma_tag_destroy(txr->txdma.dma_tag);
1936 txr->txdma.dma_vaddr = NULL;
1939 if (txr->tx_hdr != NULL) {
1940 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1941 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1943 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1947 if (txr->tx_buf == NULL)
1950 for (i = 0; i < ndesc; ++i) {
1951 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1953 KKASSERT(txbuf->m_head == NULL);
1954 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1956 bus_dma_tag_destroy(txr->tx_tag);
1958 kfree(txr->tx_buf, M_DEVBUF);
1963 igb_init_tx_ring(struct igb_tx_ring *txr)
1965 /* Clear the old descriptor contents */
1967 sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1969 /* Clear TX head write-back buffer */
1973 txr->next_avail_desc = 0;
1974 txr->next_to_clean = 0;
1977 /* Set number of descriptors available */
1978 txr->tx_avail = txr->num_tx_desc;
1980 /* Enable this TX ring */
1981 txr->tx_flags |= IGB_TXFLAG_ENABLED;
1985 igb_init_tx_unit(struct igb_softc *sc)
1987 struct e1000_hw *hw = &sc->hw;
1991 /* Setup the Tx Descriptor Rings */
1992 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1993 struct igb_tx_ring *txr = &sc->tx_rings[i];
1994 uint64_t bus_addr = txr->txdma.dma_paddr;
1995 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1996 uint32_t txdctl = 0;
1997 uint32_t dca_txctrl;
1999 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2000 txr->num_tx_desc * sizeof(struct e1000_tx_desc));
2001 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2002 (uint32_t)(bus_addr >> 32));
2003 E1000_WRITE_REG(hw, E1000_TDBAL(i),
2004 (uint32_t)bus_addr);
2006 /* Setup the HW Tx Head and Tail descriptor pointers */
2007 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2008 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2010 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
2011 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
2012 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
2015 * Don't set WB_on_EITR:
2016 * - 82575 does not have it
2017 * - It almost has no effect on 82576, see:
2018 * 82576 specification update errata #26
2019 * - It causes unnecessary bus traffic
2021 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
2022 (uint32_t)(hdr_paddr >> 32));
2023 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
2024 ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
2027 * WTHRESH is ignored by the hardware, since header
2028 * write back mode is used.
2030 txdctl |= IGB_TX_PTHRESH;
2031 txdctl |= IGB_TX_HTHRESH << 8;
2032 txdctl |= IGB_TX_WTHRESH << 16;
2033 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2034 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2040 e1000_config_collision_dist(hw);
2042 /* Program the Transmit Control Register */
2043 tctl = E1000_READ_REG(hw, E1000_TCTL);
2044 tctl &= ~E1000_TCTL_CT;
2045 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2046 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2048 /* This write will effectively turn on the transmit unit. */
2049 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2053 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
2055 struct e1000_adv_tx_context_desc *TXD;
2056 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
2057 int ehdrlen, ctxd, ip_hlen = 0;
2058 boolean_t offload = TRUE;
2060 if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
2063 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
2065 ctxd = txr->next_avail_desc;
2066 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
2069 * In advanced descriptors the vlan tag must
2070 * be placed into the context descriptor, thus
2071 * we need to be here just for that setup.
2073 if (mp->m_flags & M_VLANTAG) {
2076 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
2077 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
2078 } else if (!offload) {
2082 ehdrlen = mp->m_pkthdr.csum_lhlen;
2083 KASSERT(ehdrlen > 0, ("invalid ether hlen"));
2085 /* Set the ether header length */
2086 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
2087 if (mp->m_pkthdr.csum_flags & CSUM_IP) {
2088 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
2089 ip_hlen = mp->m_pkthdr.csum_iphlen;
2090 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
2092 vlan_macip_lens |= ip_hlen;
2094 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
2095 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
2096 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
2097 else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
2098 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
2101 * 82575 needs the TX context index added; the queue
2102 * index is used as TX context index here.
2104 if (txr->sc->hw.mac.type == e1000_82575)
2105 mss_l4len_idx = txr->me << 4;
2107 /* Now copy bits into descriptor */
2108 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
2109 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
2110 TXD->seqnum_seed = htole32(0);
2111 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
2113 /* We've consumed the first desc, adjust counters */
2114 if (++ctxd == txr->num_tx_desc)
2116 txr->next_avail_desc = ctxd;
2123 igb_txeof(struct igb_tx_ring *txr)
2125 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
2126 int first, hdr, avail;
2128 if (txr->tx_avail == txr->num_tx_desc)
2131 first = txr->next_to_clean;
2132 hdr = *(txr->tx_hdr);
2137 avail = txr->tx_avail;
2138 while (first != hdr) {
2139 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
2142 if (txbuf->m_head) {
2143 bus_dmamap_unload(txr->tx_tag, txbuf->map);
2144 m_freem(txbuf->m_head);
2145 txbuf->m_head = NULL;
2146 IFNET_STAT_INC(ifp, opackets, 1);
2148 if (++first == txr->num_tx_desc)
2151 txr->next_to_clean = first;
2152 txr->tx_avail = avail;
2155 * If we have a minimum free, clear OACTIVE
2156 * to tell the stack that it is OK to send packets.
2158 if (IGB_IS_NOT_OACTIVE(txr)) {
2159 ifsq_clr_oactive(txr->ifsq);
2162 * We have enough TX descriptors, turn off
2163 * the watchdog. We allow small amount of
2164 * packets (roughly intr_nsegs) pending on
2165 * the transmit ring.
2167 txr->tx_watchdog.wd_timer = 0;
2172 igb_create_rx_ring(struct igb_rx_ring *rxr)
2174 int rsize, i, error, nrxd;
2177 * Validate number of receive descriptors. It must not exceed
2178 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2180 nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2181 if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2182 nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2183 device_printf(rxr->sc->dev,
2184 "Using %d RX descriptors instead of %d!\n",
2185 IGB_DEFAULT_RXD, nrxd);
2186 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2188 rxr->num_rx_desc = nrxd;
2192 * Allocate RX descriptor ring
2194 rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2196 rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2197 IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2198 &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2199 &rxr->rxdma.dma_paddr);
2200 if (rxr->rxdma.dma_vaddr == NULL) {
2201 device_printf(rxr->sc->dev,
2202 "Unable to allocate RxDescriptor memory\n");
2205 rxr->rx_base = rxr->rxdma.dma_vaddr;
2206 bzero(rxr->rx_base, rsize);
2208 rsize = __VM_CACHELINE_ALIGN(
2209 sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2210 rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2213 * Create DMA tag for RX buffers
2215 error = bus_dma_tag_create(rxr->sc->parent_tag,
2216 1, 0, /* alignment, bounds */
2217 BUS_SPACE_MAXADDR, /* lowaddr */
2218 BUS_SPACE_MAXADDR, /* highaddr */
2219 NULL, NULL, /* filter, filterarg */
2220 MCLBYTES, /* maxsize */
2222 MCLBYTES, /* maxsegsize */
2223 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2226 device_printf(rxr->sc->dev,
2227 "Unable to create RX payload DMA tag\n");
2228 kfree(rxr->rx_buf, M_DEVBUF);
2234 * Create spare DMA map for RX buffers
2236 error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2239 device_printf(rxr->sc->dev,
2240 "Unable to create spare RX DMA maps\n");
2241 bus_dma_tag_destroy(rxr->rx_tag);
2242 kfree(rxr->rx_buf, M_DEVBUF);
2248 * Create DMA maps for RX buffers
2250 for (i = 0; i < rxr->num_rx_desc; i++) {
2251 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2253 error = bus_dmamap_create(rxr->rx_tag,
2254 BUS_DMA_WAITOK, &rxbuf->map);
2256 device_printf(rxr->sc->dev,
2257 "Unable to create RX DMA maps\n");
2258 igb_destroy_rx_ring(rxr, i);
2264 * Initialize various watermark
2266 rxr->wreg_nsegs = IGB_DEF_RXWREG_NSEGS;
2272 igb_free_rx_ring(struct igb_rx_ring *rxr)
2276 for (i = 0; i < rxr->num_rx_desc; ++i) {
2277 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2279 if (rxbuf->m_head != NULL) {
2280 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2281 m_freem(rxbuf->m_head);
2282 rxbuf->m_head = NULL;
2286 if (rxr->fmp != NULL)
2293 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2297 if (rxr->rxdma.dma_vaddr != NULL) {
2298 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2299 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2300 rxr->rxdma.dma_map);
2301 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2302 rxr->rxdma.dma_vaddr = NULL;
2305 if (rxr->rx_buf == NULL)
2308 for (i = 0; i < ndesc; ++i) {
2309 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2311 KKASSERT(rxbuf->m_head == NULL);
2312 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2314 bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2315 bus_dma_tag_destroy(rxr->rx_tag);
2317 kfree(rxr->rx_buf, M_DEVBUF);
2322 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2324 rxd->read.pkt_addr = htole64(rxbuf->paddr);
2325 rxd->wb.upper.status_error = 0;
2329 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2332 bus_dma_segment_t seg;
2334 struct igb_rx_buf *rxbuf;
2337 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2340 if_printf(&rxr->sc->arpcom.ac_if,
2341 "Unable to allocate RX mbuf\n");
2345 m->m_len = m->m_pkthdr.len = MCLBYTES;
2347 if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2348 m_adj(m, ETHER_ALIGN);
2350 error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2351 rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2355 if_printf(&rxr->sc->arpcom.ac_if,
2356 "Unable to load RX mbuf\n");
2361 rxbuf = &rxr->rx_buf[i];
2362 if (rxbuf->m_head != NULL)
2363 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2366 rxbuf->map = rxr->rx_sparemap;
2367 rxr->rx_sparemap = map;
2370 rxbuf->paddr = seg.ds_addr;
2372 igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2377 igb_init_rx_ring(struct igb_rx_ring *rxr)
2381 /* Clear the ring contents */
2383 rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2385 /* Now replenish the ring mbufs */
2386 for (i = 0; i < rxr->num_rx_desc; ++i) {
2389 error = igb_newbuf(rxr, i, TRUE);
2394 /* Setup our descriptor indices */
2395 rxr->next_to_check = 0;
2399 rxr->discard = FALSE;
2405 igb_init_rx_unit(struct igb_softc *sc)
2407 struct ifnet *ifp = &sc->arpcom.ac_if;
2408 struct e1000_hw *hw = &sc->hw;
2409 uint32_t rctl, rxcsum, srrctl = 0;
2413 * Make sure receives are disabled while setting
2414 * up the descriptor ring
2416 rctl = E1000_READ_REG(hw, E1000_RCTL);
2417 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2421 ** Set up for header split
2423 if (igb_header_split) {
2424 /* Use a standard mbuf for the header */
2425 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2426 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2429 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2432 ** Set up for jumbo frames
2434 if (ifp->if_mtu > ETHERMTU) {
2435 rctl |= E1000_RCTL_LPE;
2437 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2438 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2439 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2440 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2441 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2442 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2444 /* Set maximum packet len */
2445 psize = adapter->max_frame_size;
2446 /* are we on a vlan? */
2447 if (adapter->ifp->if_vlantrunk != NULL)
2448 psize += VLAN_TAG_SIZE;
2449 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2451 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2452 rctl |= E1000_RCTL_SZ_2048;
2455 rctl &= ~E1000_RCTL_LPE;
2456 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2457 rctl |= E1000_RCTL_SZ_2048;
2460 /* Setup the Base and Length of the Rx Descriptor Rings */
2461 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2462 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2463 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2466 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2467 rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2468 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2469 (uint32_t)(bus_addr >> 32));
2470 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2471 (uint32_t)bus_addr);
2472 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2473 /* Enable this Queue */
2474 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2475 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2476 rxdctl &= 0xFFF00000;
2477 rxdctl |= IGB_RX_PTHRESH;
2478 rxdctl |= IGB_RX_HTHRESH << 8;
2480 * Don't set WTHRESH to a value above 1 on 82576, see:
2481 * 82576 specification update errata #26
2483 rxdctl |= IGB_RX_WTHRESH << 16;
2484 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2487 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2488 rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2491 * Receive Checksum Offload for TCP and UDP
2493 * Checksum offloading is also enabled if multiple receive
2494 * queue is to be supported, since we need it to figure out
2497 if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2500 * PCSD must be enabled to enable multiple
2503 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2506 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2509 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2511 if (IGB_ENABLE_HWRSS(sc)) {
2512 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2513 uint32_t reta_shift;
2518 * When we reach here, RSS has already been disabled
2519 * in igb_stop(), so we could safely configure RSS key
2520 * and redirect table.
2526 toeplitz_get_key(key, sizeof(key));
2527 for (i = 0; i < IGB_NRSSRK; ++i) {
2530 rssrk = IGB_RSSRK_VAL(key, i);
2531 IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2533 E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2537 * Configure RSS redirect table in following fashion:
2538 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2540 reta_shift = IGB_RETA_SHIFT;
2541 if (hw->mac.type == e1000_82575)
2542 reta_shift = IGB_RETA_SHIFT_82575;
2545 for (j = 0; j < IGB_NRETA; ++j) {
2548 for (i = 0; i < IGB_RETA_SIZE; ++i) {
2551 q = (r % sc->rx_ring_inuse) << reta_shift;
2552 reta |= q << (8 * i);
2555 IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2556 E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2560 * Enable multiple receive queues.
2561 * Enable IPv4 RSS standard hash functions.
2562 * Disable RSS interrupt on 82575
2564 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2565 E1000_MRQC_ENABLE_RSS_4Q |
2566 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2567 E1000_MRQC_RSS_FIELD_IPV4);
2570 /* Setup the Receive Control Register */
2571 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2572 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2573 E1000_RCTL_RDMTS_HALF |
2574 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2575 /* Strip CRC bytes. */
2576 rctl |= E1000_RCTL_SECRC;
2577 /* Make sure VLAN Filters are off */
2578 rctl &= ~E1000_RCTL_VFE;
2579 /* Don't store bad packets */
2580 rctl &= ~E1000_RCTL_SBP;
2582 /* Enable Receives */
2583 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2586 * Setup the HW Rx Head and Tail Descriptor Pointers
2587 * - needs to be after enable
2589 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2590 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2592 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2593 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2598 igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2601 i = rxr->num_rx_desc - 1;
2602 E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2606 igb_rxeof(struct igb_rx_ring *rxr, int count)
2608 struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2609 union e1000_adv_rx_desc *cur;
2613 i = rxr->next_to_check;
2614 cur = &rxr->rx_base[i];
2615 staterr = le32toh(cur->wb.upper.status_error);
2617 if ((staterr & E1000_RXD_STAT_DD) == 0)
2620 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2621 struct pktinfo *pi = NULL, pi0;
2622 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2623 struct mbuf *m = NULL;
2626 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2631 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2633 struct mbuf *mp = rxbuf->m_head;
2634 uint32_t hash, hashtype;
2638 len = le16toh(cur->wb.upper.length);
2639 if ((rxr->sc->hw.mac.type == e1000_i350 ||
2640 rxr->sc->hw.mac.type == e1000_i354) &&
2641 (staterr & E1000_RXDEXT_STATERR_LB))
2642 vlan = be16toh(cur->wb.upper.vlan);
2644 vlan = le16toh(cur->wb.upper.vlan);
2646 hash = le32toh(cur->wb.lower.hi_dword.rss);
2647 hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2648 E1000_RXDADV_RSSTYPE_MASK;
2650 IGB_RSS_DPRINTF(rxr->sc, 10,
2651 "ring%d, hash 0x%08x, hashtype %u\n",
2652 rxr->me, hash, hashtype);
2654 bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2655 BUS_DMASYNC_POSTREAD);
2657 if (igb_newbuf(rxr, i, FALSE) != 0) {
2658 IFNET_STAT_INC(ifp, iqdrops, 1);
2663 if (rxr->fmp == NULL) {
2664 mp->m_pkthdr.len = len;
2668 rxr->lmp->m_next = mp;
2669 rxr->lmp = rxr->lmp->m_next;
2670 rxr->fmp->m_pkthdr.len += len;
2678 m->m_pkthdr.rcvif = ifp;
2679 IFNET_STAT_INC(ifp, ipackets, 1);
2681 if (ifp->if_capenable & IFCAP_RXCSUM)
2682 igb_rxcsum(staterr, m);
2684 if (staterr & E1000_RXD_STAT_VP) {
2685 m->m_pkthdr.ether_vlantag = vlan;
2686 m->m_flags |= M_VLANTAG;
2689 if (ifp->if_capenable & IFCAP_RSS) {
2690 pi = igb_rssinfo(m, &pi0,
2691 hash, hashtype, staterr);
2693 #ifdef IGB_RSS_DEBUG
2698 IFNET_STAT_INC(ifp, ierrors, 1);
2700 igb_setup_rxdesc(cur, rxbuf);
2702 rxr->discard = TRUE;
2704 rxr->discard = FALSE;
2705 if (rxr->fmp != NULL) {
2714 ether_input_pkt(ifp, m, pi);
2716 /* Advance our pointers to the next descriptor. */
2717 if (++i == rxr->num_rx_desc)
2720 if (ncoll >= rxr->wreg_nsegs) {
2721 igb_rx_refresh(rxr, i);
2725 cur = &rxr->rx_base[i];
2726 staterr = le32toh(cur->wb.upper.status_error);
2728 rxr->next_to_check = i;
2731 igb_rx_refresh(rxr, i);
2736 igb_set_vlan(struct igb_softc *sc)
2738 struct e1000_hw *hw = &sc->hw;
2741 struct ifnet *ifp = sc->arpcom.ac_if;
2745 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2749 reg = E1000_READ_REG(hw, E1000_CTRL);
2750 reg |= E1000_CTRL_VME;
2751 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2754 /* Enable the Filter Table */
2755 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2756 reg = E1000_READ_REG(hw, E1000_RCTL);
2757 reg &= ~E1000_RCTL_CFIEN;
2758 reg |= E1000_RCTL_VFE;
2759 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2763 /* Update the frame size */
2764 E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2765 sc->max_frame_size + VLAN_TAG_SIZE);
2768 /* Don't bother with table if no vlans */
2769 if ((adapter->num_vlans == 0) ||
2770 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2773 ** A soft reset zero's out the VFTA, so
2774 ** we need to repopulate it now.
2776 for (int i = 0; i < IGB_VFTA_SIZE; i++)
2777 if (adapter->shadow_vfta[i] != 0) {
2778 if (adapter->vf_ifp)
2779 e1000_vfta_set_vf(hw,
2780 adapter->shadow_vfta[i], TRUE);
2782 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2783 i, adapter->shadow_vfta[i]);
2789 igb_enable_intr(struct igb_softc *sc)
2791 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2792 lwkt_serialize_handler_enable(&sc->main_serialize);
2796 for (i = 0; i < sc->msix_cnt; ++i) {
2797 lwkt_serialize_handler_enable(
2798 sc->msix_data[i].msix_serialize);
2802 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2803 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2804 E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2806 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2807 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2808 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2809 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2811 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2813 E1000_WRITE_FLUSH(&sc->hw);
2817 igb_disable_intr(struct igb_softc *sc)
2819 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2820 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2821 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2823 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2824 E1000_WRITE_FLUSH(&sc->hw);
2826 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2827 lwkt_serialize_handler_disable(&sc->main_serialize);
2831 for (i = 0; i < sc->msix_cnt; ++i) {
2832 lwkt_serialize_handler_disable(
2833 sc->msix_data[i].msix_serialize);
2839 * Bit of a misnomer, what this really means is
2840 * to enable OS management of the system... aka
2841 * to disable special hardware management features
2844 igb_get_mgmt(struct igb_softc *sc)
2846 if (sc->flags & IGB_FLAG_HAS_MGMT) {
2847 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2848 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2850 /* disable hardware interception of ARP */
2851 manc &= ~E1000_MANC_ARP_EN;
2853 /* enable receiving management packets to the host */
2854 manc |= E1000_MANC_EN_MNG2HOST;
2855 manc2h |= 1 << 5; /* Mng Port 623 */
2856 manc2h |= 1 << 6; /* Mng Port 664 */
2857 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2858 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2863 * Give control back to hardware management controller
2867 igb_rel_mgmt(struct igb_softc *sc)
2869 if (sc->flags & IGB_FLAG_HAS_MGMT) {
2870 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2872 /* Re-enable hardware interception of ARP */
2873 manc |= E1000_MANC_ARP_EN;
2874 manc &= ~E1000_MANC_EN_MNG2HOST;
2876 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2881 * Sets CTRL_EXT:DRV_LOAD bit.
2883 * For ASF and Pass Through versions of f/w this means that
2884 * the driver is loaded.
2887 igb_get_hw_control(struct igb_softc *sc)
2894 /* Let firmware know the driver has taken over */
2895 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2896 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2897 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2901 * Resets CTRL_EXT:DRV_LOAD bit.
2903 * For ASF and Pass Through versions of f/w this means that the
2904 * driver is no longer loaded.
2907 igb_rel_hw_control(struct igb_softc *sc)
2914 /* Let firmware taken over control of h/w */
2915 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2916 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2917 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2921 igb_is_valid_ether_addr(const uint8_t *addr)
2923 uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2925 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2931 * Enable PCI Wake On Lan capability
2934 igb_enable_wol(device_t dev)
2936 uint16_t cap, status;
2939 /* First find the capabilities pointer*/
2940 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2942 /* Read the PM Capabilities */
2943 id = pci_read_config(dev, cap, 1);
2944 if (id != PCIY_PMG) /* Something wrong */
2948 * OK, we have the power capabilities,
2949 * so now get the status register
2951 cap += PCIR_POWER_STATUS;
2952 status = pci_read_config(dev, cap, 2);
2953 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2954 pci_write_config(dev, cap, status, 2);
2958 igb_update_stats_counters(struct igb_softc *sc)
2960 struct e1000_hw *hw = &sc->hw;
2961 struct e1000_hw_stats *stats;
2962 struct ifnet *ifp = &sc->arpcom.ac_if;
2965 * The virtual function adapter has only a
2966 * small controlled set of stats, do only
2970 igb_update_vf_stats_counters(sc);
2975 if (sc->hw.phy.media_type == e1000_media_type_copper ||
2976 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2978 E1000_READ_REG(hw,E1000_SYMERRS);
2979 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2982 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2983 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2984 stats->scc += E1000_READ_REG(hw, E1000_SCC);
2985 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2987 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2988 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2989 stats->colc += E1000_READ_REG(hw, E1000_COLC);
2990 stats->dc += E1000_READ_REG(hw, E1000_DC);
2991 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2992 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2993 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2996 * For watchdog management we need to know if we have been
2997 * paused during the last interval, so capture that here.
2999 sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
3000 stats->xoffrxc += sc->pause_frames;
3001 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
3002 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
3003 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
3004 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
3005 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
3006 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
3007 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
3008 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
3009 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
3010 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
3011 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
3012 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
3014 /* For the 64-bit byte counters the low dword must be read first. */
3015 /* Both registers clear on the read of the high dword */
3017 stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
3018 ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
3019 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
3020 ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
3022 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
3023 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
3024 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
3025 stats->roc += E1000_READ_REG(hw, E1000_ROC);
3026 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
3028 stats->tor += E1000_READ_REG(hw, E1000_TORH);
3029 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
3031 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
3032 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
3033 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
3034 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
3035 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
3036 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
3037 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
3038 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
3039 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
3040 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
3042 /* Interrupt Counts */
3044 stats->iac += E1000_READ_REG(hw, E1000_IAC);
3045 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
3046 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
3047 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
3048 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
3049 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
3050 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
3051 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
3052 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
3054 /* Host to Card Statistics */
3056 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
3057 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
3058 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
3059 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
3060 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
3061 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
3062 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
3063 stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
3064 ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
3065 stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
3066 ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
3067 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
3068 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
3069 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
3071 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
3072 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
3073 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
3074 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
3075 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
3076 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
3078 IFNET_STAT_SET(ifp, collisions, stats->colc);
3081 IFNET_STAT_SET(ifp, ierrors,
3082 stats->rxerrc + stats->crcerrs + stats->algnerrc +
3083 stats->ruc + stats->roc + stats->mpc + stats->cexterr);
3086 IFNET_STAT_SET(ifp, oerrors,
3087 stats->ecol + stats->latecol + sc->watchdog_events);
3089 /* Driver specific counters */
3090 sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
3091 sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
3092 sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
3093 sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
3094 sc->packet_buf_alloc_tx =
3095 ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
3096 sc->packet_buf_alloc_rx =
3097 (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
3101 igb_vf_init_stats(struct igb_softc *sc)
3103 struct e1000_hw *hw = &sc->hw;
3104 struct e1000_vf_stats *stats;
3107 stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
3108 stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
3109 stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
3110 stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
3111 stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
3115 igb_update_vf_stats_counters(struct igb_softc *sc)
3117 struct e1000_hw *hw = &sc->hw;
3118 struct e1000_vf_stats *stats;
3120 if (sc->link_speed == 0)
3124 UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
3125 UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
3126 UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
3127 UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
3128 UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
3131 #ifdef IFPOLL_ENABLE
3134 igb_npoll_status(struct ifnet *ifp)
3136 struct igb_softc *sc = ifp->if_softc;
3139 ASSERT_SERIALIZED(&sc->main_serialize);
3141 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3142 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3143 sc->hw.mac.get_link_status = 1;
3144 igb_update_link_status(sc);
3149 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3151 struct igb_tx_ring *txr = arg;
3153 ASSERT_SERIALIZED(&txr->tx_serialize);
3156 if (!ifsq_is_empty(txr->ifsq))
3157 ifsq_devstart(txr->ifsq);
3161 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3163 struct igb_rx_ring *rxr = arg;
3165 ASSERT_SERIALIZED(&rxr->rx_serialize);
3167 igb_rxeof(rxr, cycle);
3171 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3173 struct igb_softc *sc = ifp->if_softc;
3174 int i, txr_cnt, rxr_cnt;
3176 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3181 info->ifpi_status.status_func = igb_npoll_status;
3182 info->ifpi_status.serializer = &sc->main_serialize;
3184 txr_cnt = igb_get_txring_inuse(sc, TRUE);
3185 off = sc->tx_npoll_off;
3186 for (i = 0; i < txr_cnt; ++i) {
3187 struct igb_tx_ring *txr = &sc->tx_rings[i];
3190 KKASSERT(idx < ncpus2);
3191 info->ifpi_tx[idx].poll_func = igb_npoll_tx;
3192 info->ifpi_tx[idx].arg = txr;
3193 info->ifpi_tx[idx].serializer = &txr->tx_serialize;
3194 ifsq_set_cpuid(txr->ifsq, idx);
3197 rxr_cnt = igb_get_rxring_inuse(sc, TRUE);
3198 off = sc->rx_npoll_off;
3199 for (i = 0; i < rxr_cnt; ++i) {
3200 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3203 KKASSERT(idx < ncpus2);
3204 info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3205 info->ifpi_rx[idx].arg = rxr;
3206 info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3209 if (ifp->if_flags & IFF_RUNNING) {
3210 if (rxr_cnt == sc->rx_ring_inuse &&
3211 txr_cnt == sc->tx_ring_inuse) {
3212 igb_set_timer_cpuid(sc, TRUE);
3213 igb_disable_intr(sc);
3219 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3220 struct igb_tx_ring *txr = &sc->tx_rings[i];
3222 ifsq_set_cpuid(txr->ifsq, txr->tx_intr_cpuid);
3225 if (ifp->if_flags & IFF_RUNNING) {
3226 txr_cnt = igb_get_txring_inuse(sc, FALSE);
3227 rxr_cnt = igb_get_rxring_inuse(sc, FALSE);
3229 if (rxr_cnt == sc->rx_ring_inuse &&
3230 txr_cnt == sc->tx_ring_inuse) {
3231 igb_set_timer_cpuid(sc, FALSE);
3232 igb_enable_intr(sc);
3240 #endif /* IFPOLL_ENABLE */
3245 struct igb_softc *sc = xsc;
3246 struct ifnet *ifp = &sc->arpcom.ac_if;
3249 ASSERT_SERIALIZED(&sc->main_serialize);
3251 eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3256 if (ifp->if_flags & IFF_RUNNING) {
3257 struct igb_tx_ring *txr = &sc->tx_rings[0];
3260 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3261 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3263 if (eicr & rxr->rx_intr_mask) {
3264 lwkt_serialize_enter(&rxr->rx_serialize);
3266 lwkt_serialize_exit(&rxr->rx_serialize);
3270 if (eicr & txr->tx_intr_mask) {
3271 lwkt_serialize_enter(&txr->tx_serialize);
3273 if (!ifsq_is_empty(txr->ifsq))
3274 ifsq_devstart(txr->ifsq);
3275 lwkt_serialize_exit(&txr->tx_serialize);
3279 if (eicr & E1000_EICR_OTHER) {
3280 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3282 /* Link status change */
3283 if (icr & E1000_ICR_LSC) {
3284 sc->hw.mac.get_link_status = 1;
3285 igb_update_link_status(sc);
3290 * Reading EICR has the side effect to clear interrupt mask,
3291 * so all interrupts need to be enabled here.
3293 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3297 igb_intr_shared(void *xsc)
3299 struct igb_softc *sc = xsc;
3300 struct ifnet *ifp = &sc->arpcom.ac_if;
3303 ASSERT_SERIALIZED(&sc->main_serialize);
3305 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3308 if (reg_icr == 0xffffffff)
3311 /* Definitely not our interrupt. */
3315 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3318 if (ifp->if_flags & IFF_RUNNING) {
3320 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3323 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3324 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3326 lwkt_serialize_enter(&rxr->rx_serialize);
3328 lwkt_serialize_exit(&rxr->rx_serialize);
3332 if (reg_icr & E1000_ICR_TXDW) {
3333 struct igb_tx_ring *txr = &sc->tx_rings[0];
3335 lwkt_serialize_enter(&txr->tx_serialize);
3337 if (!ifsq_is_empty(txr->ifsq))
3338 ifsq_devstart(txr->ifsq);
3339 lwkt_serialize_exit(&txr->tx_serialize);
3343 /* Link status change */
3344 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3345 sc->hw.mac.get_link_status = 1;
3346 igb_update_link_status(sc);
3349 if (reg_icr & E1000_ICR_RXO)
3354 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3355 int *segs_used, int *idx)
3357 bus_dma_segment_t segs[IGB_MAX_SCATTER];
3359 struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3360 union e1000_adv_tx_desc *txd = NULL;
3361 struct mbuf *m_head = *m_headp;
3362 uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3363 int maxsegs, nsegs, i, j, error;
3364 uint32_t hdrlen = 0;
3366 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3367 error = igb_tso_pullup(txr, m_headp);
3373 /* Set basic descriptor constants */
3374 cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3375 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3376 if (m_head->m_flags & M_VLANTAG)
3377 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3380 * Map the packet for DMA.
3382 tx_buf = &txr->tx_buf[txr->next_avail_desc];
3383 tx_buf_mapped = tx_buf;
3386 maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3387 KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3388 if (maxsegs > IGB_MAX_SCATTER)
3389 maxsegs = IGB_MAX_SCATTER;
3391 error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3392 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3394 if (error == ENOBUFS)
3395 txr->sc->mbuf_defrag_failed++;
3397 txr->sc->no_tx_dma_setup++;
3403 bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3408 * Set up the TX context descriptor, if any hardware offloading is
3409 * needed. This includes CSUM, VLAN, and TSO. It will consume one
3412 * Unlike these chips' predecessors (em/emx), TX context descriptor
3413 * will _not_ interfere TX data fetching pipelining.
3415 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3416 igb_tso_ctx(txr, m_head, &hdrlen);
3417 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3418 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3419 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3422 } else if (igb_txcsum_ctx(txr, m_head)) {
3423 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3424 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3425 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3426 olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3431 *segs_used += nsegs;
3432 txr->tx_nsegs += nsegs;
3433 if (txr->tx_nsegs >= txr->intr_nsegs) {
3435 * Report Status (RS) is turned on every intr_nsegs
3436 * descriptors (roughly).
3439 cmd_rs = E1000_ADVTXD_DCMD_RS;
3442 /* Calculate payload length */
3443 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3444 << E1000_ADVTXD_PAYLEN_SHIFT);
3447 * 82575 needs the TX context index added; the queue
3448 * index is used as TX context index here.
3450 if (txr->sc->hw.mac.type == e1000_82575)
3451 olinfo_status |= txr->me << 4;
3453 /* Set up our transmit descriptors */
3454 i = txr->next_avail_desc;
3455 for (j = 0; j < nsegs; j++) {
3457 bus_addr_t seg_addr;
3459 tx_buf = &txr->tx_buf[i];
3460 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3461 seg_addr = segs[j].ds_addr;
3462 seg_len = segs[j].ds_len;
3464 txd->read.buffer_addr = htole64(seg_addr);
3465 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3466 txd->read.olinfo_status = htole32(olinfo_status);
3467 if (++i == txr->num_tx_desc)
3469 tx_buf->m_head = NULL;
3472 KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3473 txr->next_avail_desc = i;
3474 txr->tx_avail -= nsegs;
3476 tx_buf->m_head = m_head;
3477 tx_buf_mapped->map = tx_buf->map;
3481 * Last Descriptor of Packet needs End Of Packet (EOP)
3483 txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3486 * Defer TDT updating, until enough descrptors are setup
3489 #ifdef IGB_TSS_DEBUG
3497 igb_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3499 struct igb_softc *sc = ifp->if_softc;
3500 struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3501 struct mbuf *m_head;
3502 int idx = -1, nsegs = 0;
3504 KKASSERT(txr->ifsq == ifsq);
3505 ASSERT_SERIALIZED(&txr->tx_serialize);
3507 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3510 if (!sc->link_active || (txr->tx_flags & IGB_TXFLAG_ENABLED) == 0) {
3515 if (!IGB_IS_NOT_OACTIVE(txr))
3518 while (!ifsq_is_empty(ifsq)) {
3519 if (IGB_IS_OACTIVE(txr)) {
3520 ifsq_set_oactive(ifsq);
3521 /* Set watchdog on */
3522 txr->tx_watchdog.wd_timer = 5;
3526 m_head = ifsq_dequeue(ifsq);
3530 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3531 IFNET_STAT_INC(ifp, oerrors, 1);
3535 if (nsegs >= txr->wreg_nsegs) {
3536 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3541 /* Send a copy of the frame to the BPF listener */
3542 ETHER_BPF_MTAP(ifp, m_head);
3545 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3549 igb_watchdog(struct ifaltq_subque *ifsq)
3551 struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3552 struct ifnet *ifp = ifsq_get_ifp(ifsq);
3553 struct igb_softc *sc = ifp->if_softc;
3556 KKASSERT(txr->ifsq == ifsq);
3557 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3560 * If flow control has paused us since last checking
3561 * it invalidates the watchdog timing, so dont run it.
3563 if (sc->pause_frames) {
3564 sc->pause_frames = 0;
3565 txr->tx_watchdog.wd_timer = 5;
3569 if_printf(ifp, "Watchdog timeout -- resetting\n");
3570 if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3571 E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3572 E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3573 if_printf(ifp, "TX(%d) desc avail = %d, "
3574 "Next TX to Clean = %d\n",
3575 txr->me, txr->tx_avail, txr->next_to_clean);
3577 IFNET_STAT_INC(ifp, oerrors, 1);
3578 sc->watchdog_events++;
3581 for (i = 0; i < sc->tx_ring_inuse; ++i)
3582 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
3586 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3591 if (sc->hw.mac.type == e1000_82575) {
3592 eitr = 1000000000 / 256 / rate;
3595 * Document is wrong on the 2 bits left shift
3598 eitr = 1000000 / rate;
3599 eitr <<= IGB_EITR_INTVL_SHIFT;
3603 /* Don't disable it */
3604 eitr = 1 << IGB_EITR_INTVL_SHIFT;
3605 } else if (eitr > IGB_EITR_INTVL_MASK) {
3606 /* Don't allow it to be too large */
3607 eitr = IGB_EITR_INTVL_MASK;
3610 if (sc->hw.mac.type == e1000_82575)
3613 eitr |= E1000_EITR_CNT_IGNR;
3614 E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3618 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3620 struct igb_softc *sc = (void *)arg1;
3621 struct ifnet *ifp = &sc->arpcom.ac_if;
3622 int error, intr_rate;
3624 intr_rate = sc->intr_rate;
3625 error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3626 if (error || req->newptr == NULL)
3631 ifnet_serialize_all(ifp);
3633 sc->intr_rate = intr_rate;
3634 if (ifp->if_flags & IFF_RUNNING)
3635 igb_set_eitr(sc, 0, sc->intr_rate);
3638 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3640 ifnet_deserialize_all(ifp);
3646 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3648 struct igb_msix_data *msix = (void *)arg1;
3649 struct igb_softc *sc = msix->msix_sc;
3650 struct ifnet *ifp = &sc->arpcom.ac_if;
3651 int error, msix_rate;
3653 msix_rate = msix->msix_rate;
3654 error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3655 if (error || req->newptr == NULL)
3660 lwkt_serialize_enter(msix->msix_serialize);
3662 msix->msix_rate = msix_rate;
3663 if (ifp->if_flags & IFF_RUNNING)
3664 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3667 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3671 lwkt_serialize_exit(msix->msix_serialize);
3677 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3679 struct igb_softc *sc = (void *)arg1;
3680 struct ifnet *ifp = &sc->arpcom.ac_if;
3681 struct igb_tx_ring *txr = &sc->tx_rings[0];
3684 nsegs = txr->intr_nsegs;
3685 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3686 if (error || req->newptr == NULL)
3691 ifnet_serialize_all(ifp);
3693 if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3694 nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3700 for (i = 0; i < sc->tx_ring_cnt; ++i)
3701 sc->tx_rings[i].intr_nsegs = nsegs;
3704 ifnet_deserialize_all(ifp);
3710 igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3712 struct igb_softc *sc = (void *)arg1;
3713 struct ifnet *ifp = &sc->arpcom.ac_if;
3714 int error, nsegs, i;
3716 nsegs = sc->rx_rings[0].wreg_nsegs;
3717 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3718 if (error || req->newptr == NULL)
3721 ifnet_serialize_all(ifp);
3722 for (i = 0; i < sc->rx_ring_cnt; ++i)
3723 sc->rx_rings[i].wreg_nsegs =nsegs;
3724 ifnet_deserialize_all(ifp);
3730 igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3732 struct igb_softc *sc = (void *)arg1;
3733 struct ifnet *ifp = &sc->arpcom.ac_if;
3734 int error, nsegs, i;
3736 nsegs = sc->tx_rings[0].wreg_nsegs;
3737 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3738 if (error || req->newptr == NULL)
3741 ifnet_serialize_all(ifp);
3742 for (i = 0; i < sc->tx_ring_cnt; ++i)
3743 sc->tx_rings[i].wreg_nsegs =nsegs;
3744 ifnet_deserialize_all(ifp);
3749 #ifdef IFPOLL_ENABLE
3752 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3754 struct igb_softc *sc = (void *)arg1;
3755 struct ifnet *ifp = &sc->arpcom.ac_if;
3758 off = sc->rx_npoll_off;
3759 error = sysctl_handle_int(oidp, &off, 0, req);
3760 if (error || req->newptr == NULL)
3765 ifnet_serialize_all(ifp);
3766 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3770 sc->rx_npoll_off = off;
3772 ifnet_deserialize_all(ifp);
3778 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3780 struct igb_softc *sc = (void *)arg1;
3781 struct ifnet *ifp = &sc->arpcom.ac_if;
3784 off = sc->tx_npoll_off;
3785 error = sysctl_handle_int(oidp, &off, 0, req);
3786 if (error || req->newptr == NULL)
3791 ifnet_serialize_all(ifp);
3792 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3796 sc->tx_npoll_off = off;
3798 ifnet_deserialize_all(ifp);
3803 #endif /* IFPOLL_ENABLE */
3806 igb_init_intr(struct igb_softc *sc)
3808 igb_set_intr_mask(sc);
3810 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3811 igb_init_unshared_intr(sc);
3813 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3814 igb_set_eitr(sc, 0, sc->intr_rate);
3818 for (i = 0; i < sc->msix_cnt; ++i)
3819 igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3824 igb_init_unshared_intr(struct igb_softc *sc)
3826 struct e1000_hw *hw = &sc->hw;
3827 const struct igb_rx_ring *rxr;
3828 const struct igb_tx_ring *txr;
3829 uint32_t ivar, index;
3833 * Enable extended mode
3835 if (sc->hw.mac.type != e1000_82575) {
3839 gpie = E1000_GPIE_NSICR;
3840 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3841 gpie |= E1000_GPIE_MSIX_MODE |
3845 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3850 switch (sc->hw.mac.type) {
3852 ivar_max = IGB_MAX_IVAR_82576;
3856 ivar_max = IGB_MAX_IVAR_82580;
3860 ivar_max = IGB_MAX_IVAR_I350;
3864 ivar_max = IGB_MAX_IVAR_I354;
3868 case e1000_vfadapt_i350:
3869 ivar_max = IGB_MAX_IVAR_VF;
3873 ivar_max = IGB_MAX_IVAR_I210;
3877 ivar_max = IGB_MAX_IVAR_I211;
3881 panic("unknown mac type %d\n", sc->hw.mac.type);
3883 for (i = 0; i < ivar_max; ++i)
3884 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3885 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3889 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3890 ("82575 w/ MSI-X"));
3891 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3892 tmp |= E1000_CTRL_EXT_IRCA;
3893 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3897 * Map TX/RX interrupts to EICR
3899 switch (sc->hw.mac.type) {
3904 case e1000_vfadapt_i350:
3908 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3909 rxr = &sc->rx_rings[i];
3912 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3917 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3921 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3923 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3926 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3927 txr = &sc->tx_rings[i];
3930 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3935 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3939 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3941 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3943 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3944 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3945 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3951 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3952 rxr = &sc->rx_rings[i];
3954 index = i & 0x7; /* Each IVAR has two entries */
3955 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3960 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3964 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3966 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3969 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3970 txr = &sc->tx_rings[i];
3972 index = i & 0x7; /* Each IVAR has two entries */
3973 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3978 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3982 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3984 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3986 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3987 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3988 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3994 * Enable necessary interrupt bits.
3996 * The name of the register is confusing; in addition to
3997 * configuring the first vector of MSI-X, it also configures
3998 * which bits of EICR could be set by the hardware even when
3999 * MSI or line interrupt is used; it thus controls interrupt
4000 * generation. It MUST be configured explicitly; the default
4001 * value mentioned in the datasheet is wrong: RX queue0 and
4002 * TX queue0 are NOT enabled by default.
4004 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
4008 panic("unknown mac type %d\n", sc->hw.mac.type);
4013 igb_setup_intr(struct igb_softc *sc)
4017 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
4018 return igb_msix_setup(sc);
4020 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
4021 (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
4022 sc, &sc->intr_tag, &sc->main_serialize);
4024 device_printf(sc->dev, "Failed to register interrupt handler");
4031 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
4033 if (txr->sc->hw.mac.type == e1000_82575) {
4034 txr->tx_intr_bit = 0; /* unused */
4037 txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
4040 txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
4043 txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
4046 txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
4049 panic("unsupported # of TX ring, %d\n", txr->me);
4052 int intr_bit = *intr_bit0;
4054 txr->tx_intr_bit = intr_bit % intr_bitmax;
4055 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
4057 *intr_bit0 = intr_bit + 1;
4062 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
4064 if (rxr->sc->hw.mac.type == e1000_82575) {
4065 rxr->rx_intr_bit = 0; /* unused */
4068 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
4071 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
4074 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
4077 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
4080 panic("unsupported # of RX ring, %d\n", rxr->me);
4083 int intr_bit = *intr_bit0;
4085 rxr->rx_intr_bit = intr_bit % intr_bitmax;
4086 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
4088 *intr_bit0 = intr_bit + 1;
4093 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
4095 struct igb_softc *sc = ifp->if_softc;
4097 ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt, slz);
4101 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4103 struct igb_softc *sc = ifp->if_softc;
4105 ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt, slz);
4109 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4111 struct igb_softc *sc = ifp->if_softc;
4113 return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
4120 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
4121 boolean_t serialized)
4123 struct igb_softc *sc = ifp->if_softc;
4125 ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
4129 #endif /* INVARIANTS */
4132 igb_set_intr_mask(struct igb_softc *sc)
4136 sc->intr_mask = sc->sts_intr_mask;
4137 for (i = 0; i < sc->rx_ring_inuse; ++i)
4138 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
4139 for (i = 0; i < sc->tx_ring_inuse; ++i)
4140 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
4142 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
4148 igb_alloc_intr(struct igb_softc *sc)
4150 int i, intr_bit, intr_bitmax;
4153 igb_msix_try_alloc(sc);
4154 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
4158 * Allocate MSI/legacy interrupt resource
4160 sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
4161 &sc->intr_rid, &intr_flags);
4163 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
4166 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
4168 sc->flags |= IGB_FLAG_SHARED_INTR;
4170 device_printf(sc->dev, "IRQ shared\n");
4172 intr_flags &= ~RF_SHAREABLE;
4174 device_printf(sc->dev, "IRQ unshared\n");
4178 sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4179 &sc->intr_rid, intr_flags);
4180 if (sc->intr_res == NULL) {
4181 device_printf(sc->dev, "Unable to allocate bus resource: "
4186 for (i = 0; i < sc->tx_ring_cnt; ++i)
4187 sc->tx_rings[i].tx_intr_cpuid = rman_get_cpuid(sc->intr_res);
4190 * Setup MSI/legacy interrupt mask
4192 switch (sc->hw.mac.type) {
4194 intr_bitmax = IGB_MAX_TXRXINT_82575;
4198 intr_bitmax = IGB_MAX_TXRXINT_82576;
4202 intr_bitmax = IGB_MAX_TXRXINT_82580;
4206 intr_bitmax = IGB_MAX_TXRXINT_I350;
4210 intr_bitmax = IGB_MAX_TXRXINT_I354;
4214 intr_bitmax = IGB_MAX_TXRXINT_I210;
4218 intr_bitmax = IGB_MAX_TXRXINT_I211;
4222 intr_bitmax = IGB_MIN_TXRXINT;
4226 for (i = 0; i < sc->tx_ring_cnt; ++i)
4227 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
4228 for (i = 0; i < sc->rx_ring_cnt; ++i)
4229 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
4230 sc->sts_intr_bit = 0;
4231 sc->sts_intr_mask = E1000_EICR_OTHER;
4233 /* Initialize interrupt rate */
4234 sc->intr_rate = IGB_INTR_RATE;
4236 igb_set_ring_inuse(sc, FALSE);
4237 igb_set_intr_mask(sc);
4242 igb_free_intr(struct igb_softc *sc)
4244 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
4245 if (sc->intr_res != NULL) {
4246 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
4249 if (sc->intr_type == PCI_INTR_TYPE_MSI)
4250 pci_release_msi(sc->dev);
4252 igb_msix_free(sc, TRUE);
4257 igb_teardown_intr(struct igb_softc *sc)
4259 if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4260 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
4262 igb_msix_teardown(sc, sc->msix_cnt);
4266 igb_msix_try_alloc(struct igb_softc *sc)
4268 int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
4270 int offset, offset_def;
4271 struct igb_msix_data *msix;
4272 boolean_t aggregate, setup = FALSE;
4275 * Don't enable MSI-X on 82575, see:
4276 * 82575 specification update errata #25
4278 if (sc->hw.mac.type == e1000_82575)
4281 /* Don't enable MSI-X on VF */
4285 msix_enable = device_getenv_int(sc->dev, "msix.enable",
4290 msix_cnt = pci_msix_count(sc->dev);
4291 #ifdef IGB_MSIX_DEBUG
4292 msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
4294 if (msix_cnt <= 1) {
4295 /* One MSI-X model does not make sense */
4300 while ((1 << (i + 1)) <= msix_cnt)
4305 device_printf(sc->dev, "MSI-X count %d/%d\n",
4306 msix_cnt2, msix_cnt);
4309 KKASSERT(msix_cnt2 <= msix_cnt);
4310 if (msix_cnt == msix_cnt2) {
4311 /* We need at least one MSI-X for link status */
4313 if (msix_cnt2 <= 1) {
4314 /* One MSI-X for RX/TX does not make sense */
4315 device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4316 "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4319 KKASSERT(msix_cnt > msix_cnt2);
4322 device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4323 msix_cnt2, msix_cnt);
4327 sc->rx_ring_msix = sc->rx_ring_cnt;
4328 if (sc->rx_ring_msix > msix_cnt2)
4329 sc->rx_ring_msix = msix_cnt2;
4331 sc->tx_ring_msix = sc->tx_ring_cnt;
4332 if (sc->tx_ring_msix > msix_cnt2)
4333 sc->tx_ring_msix = msix_cnt2;
4335 if (msix_cnt >= sc->tx_ring_msix + sc->rx_ring_msix + 1) {
4337 * Independent TX/RX MSI-X
4341 device_printf(sc->dev, "independent TX/RX MSI-X\n");
4342 alloc_cnt = sc->tx_ring_msix + sc->rx_ring_msix;
4345 * Aggregate TX/RX MSI-X
4349 device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4350 alloc_cnt = msix_cnt2;
4351 if (alloc_cnt > ncpus2)
4353 if (sc->rx_ring_msix > alloc_cnt)
4354 sc->rx_ring_msix = alloc_cnt;
4355 if (sc->tx_ring_msix > alloc_cnt)
4356 sc->tx_ring_msix = alloc_cnt;
4358 ++alloc_cnt; /* For link status */
4361 device_printf(sc->dev, "MSI-X alloc %d, "
4362 "RX ring %d, TX ring %d\n", alloc_cnt,
4363 sc->rx_ring_msix, sc->tx_ring_msix);
4366 sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4367 sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4368 &sc->msix_mem_rid, RF_ACTIVE);
4369 if (sc->msix_mem_res == NULL) {
4370 device_printf(sc->dev, "Unable to map MSI-X table\n");
4374 sc->msix_cnt = alloc_cnt;
4375 sc->msix_data = kmalloc_cachealign(
4376 sizeof(struct igb_msix_data) * sc->msix_cnt,
4377 M_DEVBUF, M_WAITOK | M_ZERO);
4378 for (x = 0; x < sc->msix_cnt; ++x) {
4379 msix = &sc->msix_data[x];
4381 lwkt_serialize_init(&msix->msix_serialize0);
4383 msix->msix_rid = -1;
4384 msix->msix_vector = x;
4385 msix->msix_mask = 1 << msix->msix_vector;
4386 msix->msix_rate = IGB_INTR_RATE;
4394 if (sc->rx_ring_msix == ncpus2) {
4397 offset_def = (sc->rx_ring_msix *
4398 device_get_unit(sc->dev)) % ncpus2;
4400 offset = device_getenv_int(sc->dev,
4401 "msix.rxoff", offset_def);
4402 if (offset >= ncpus2 ||
4403 offset % sc->rx_ring_msix != 0) {
4404 device_printf(sc->dev,
4405 "invalid msix.rxoff %d, use %d\n",
4406 offset, offset_def);
4407 offset = offset_def;
4410 igb_msix_rx_conf(sc, 0, &x, offset);
4415 if (sc->tx_ring_msix == ncpus2) {
4418 offset_def = (sc->tx_ring_msix *
4419 device_get_unit(sc->dev)) % ncpus2;
4421 offset = device_getenv_int(sc->dev,
4422 "msix.txoff", offset_def);
4423 if (offset >= ncpus2 ||
4424 offset % sc->tx_ring_msix != 0) {
4425 device_printf(sc->dev,
4426 "invalid msix.txoff %d, use %d\n",
4427 offset, offset_def);
4428 offset = offset_def;
4431 igb_msix_tx_conf(sc, 0, &x, offset);
4433 int ring_agg, ring_max;
4435 ring_agg = sc->rx_ring_msix;
4436 if (ring_agg > sc->tx_ring_msix)
4437 ring_agg = sc->tx_ring_msix;
4439 ring_max = sc->rx_ring_msix;
4440 if (ring_max < sc->tx_ring_msix)
4441 ring_max = sc->tx_ring_msix;
4443 if (ring_max == ncpus2) {
4446 offset_def = (ring_max * device_get_unit(sc->dev)) %
4449 offset = device_getenv_int(sc->dev, "msix.off",
4451 if (offset >= ncpus2 || offset % ring_max != 0) {
4452 device_printf(sc->dev,
4453 "invalid msix.off %d, use %d\n",
4454 offset, offset_def);
4455 offset = offset_def;
4459 for (i = 0; i < ring_agg; ++i) {
4460 struct igb_tx_ring *txr = &sc->tx_rings[i];
4461 struct igb_rx_ring *rxr = &sc->rx_rings[i];
4463 KKASSERT(x < sc->msix_cnt);
4464 msix = &sc->msix_data[x++];
4466 txr->tx_intr_bit = msix->msix_vector;
4467 txr->tx_intr_mask = msix->msix_mask;
4468 rxr->rx_intr_bit = msix->msix_vector;
4469 rxr->rx_intr_mask = msix->msix_mask;
4471 msix->msix_serialize = &msix->msix_serialize0;
4472 msix->msix_func = igb_msix_rxtx;
4473 msix->msix_arg = msix;
4474 msix->msix_rx = rxr;
4475 msix->msix_tx = txr;
4477 msix->msix_cpuid = i + offset;
4478 KKASSERT(msix->msix_cpuid < ncpus2);
4479 txr->tx_intr_cpuid = msix->msix_cpuid;
4481 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4482 "%s rxtx%d", device_get_nameunit(sc->dev), i);
4483 msix->msix_rate = IGB_MSIX_RX_RATE;
4484 ksnprintf(msix->msix_rate_desc,
4485 sizeof(msix->msix_rate_desc),
4486 "RXTX%d interrupt rate", i);
4489 if (ring_agg != ring_max) {
4490 if (ring_max == sc->tx_ring_msix)
4491 igb_msix_tx_conf(sc, i, &x, offset);
4493 igb_msix_rx_conf(sc, i, &x, offset);
4500 KKASSERT(x < sc->msix_cnt);
4501 msix = &sc->msix_data[x++];
4502 sc->sts_intr_bit = msix->msix_vector;
4503 sc->sts_intr_mask = msix->msix_mask;
4505 msix->msix_serialize = &sc->main_serialize;
4506 msix->msix_func = igb_msix_status;
4507 msix->msix_arg = sc;
4508 msix->msix_cpuid = 0;
4509 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4510 device_get_nameunit(sc->dev));
4511 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4512 "status interrupt rate");
4514 KKASSERT(x == sc->msix_cnt);
4516 error = pci_setup_msix(sc->dev);
4518 device_printf(sc->dev, "Setup MSI-X failed\n");
4523 for (i = 0; i < sc->msix_cnt; ++i) {
4524 msix = &sc->msix_data[i];
4526 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4527 &msix->msix_rid, msix->msix_cpuid);
4529 device_printf(sc->dev,
4530 "Unable to allocate MSI-X %d on cpu%d\n",
4531 msix->msix_vector, msix->msix_cpuid);
4535 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4536 &msix->msix_rid, RF_ACTIVE);
4537 if (msix->msix_res == NULL) {
4538 device_printf(sc->dev,
4539 "Unable to allocate MSI-X %d resource\n",
4546 pci_enable_msix(sc->dev);
4547 sc->intr_type = PCI_INTR_TYPE_MSIX;
4550 igb_msix_free(sc, setup);
4554 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4558 KKASSERT(sc->msix_cnt > 1);
4560 for (i = 0; i < sc->msix_cnt; ++i) {
4561 struct igb_msix_data *msix = &sc->msix_data[i];
4563 if (msix->msix_res != NULL) {
4564 bus_release_resource(sc->dev, SYS_RES_IRQ,
4565 msix->msix_rid, msix->msix_res);
4567 if (msix->msix_rid >= 0)
4568 pci_release_msix_vector(sc->dev, msix->msix_rid);
4571 pci_teardown_msix(sc->dev);
4574 kfree(sc->msix_data, M_DEVBUF);
4575 sc->msix_data = NULL;
4579 igb_msix_setup(struct igb_softc *sc)
4583 for (i = 0; i < sc->msix_cnt; ++i) {
4584 struct igb_msix_data *msix = &sc->msix_data[i];
4587 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4588 INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4589 &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4591 device_printf(sc->dev, "could not set up %s "
4592 "interrupt handler.\n", msix->msix_desc);
4593 igb_msix_teardown(sc, i);
4601 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4605 for (i = 0; i < msix_cnt; ++i) {
4606 struct igb_msix_data *msix = &sc->msix_data[i];
4608 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4613 igb_msix_rx(void *arg)
4615 struct igb_rx_ring *rxr = arg;
4617 ASSERT_SERIALIZED(&rxr->rx_serialize);
4620 E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4624 igb_msix_tx(void *arg)
4626 struct igb_tx_ring *txr = arg;
4628 ASSERT_SERIALIZED(&txr->tx_serialize);
4631 if (!ifsq_is_empty(txr->ifsq))
4632 ifsq_devstart(txr->ifsq);
4634 E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4638 igb_msix_status(void *arg)
4640 struct igb_softc *sc = arg;
4643 ASSERT_SERIALIZED(&sc->main_serialize);
4645 icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4646 if (icr & E1000_ICR_LSC) {
4647 sc->hw.mac.get_link_status = 1;
4648 igb_update_link_status(sc);
4651 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4655 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4657 sc->rx_ring_inuse = igb_get_rxring_inuse(sc, polling);
4658 sc->tx_ring_inuse = igb_get_txring_inuse(sc, polling);
4660 if_printf(&sc->arpcom.ac_if, "RX rings %d/%d, TX rings %d/%d\n",
4661 sc->rx_ring_inuse, sc->rx_ring_cnt,
4662 sc->tx_ring_inuse, sc->tx_ring_cnt);
4667 igb_get_rxring_inuse(const struct igb_softc *sc, boolean_t polling)
4669 if (!IGB_ENABLE_HWRSS(sc))
4673 return sc->rx_ring_cnt;
4674 else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4675 return IGB_MIN_RING_RSS;
4677 return sc->rx_ring_msix;
4681 igb_get_txring_inuse(const struct igb_softc *sc, boolean_t polling)
4683 if (!IGB_ENABLE_HWTSS(sc))
4687 return sc->tx_ring_cnt;
4688 else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4689 return IGB_MIN_RING;
4691 return sc->tx_ring_msix;
4695 igb_tso_pullup(struct igb_tx_ring *txr, struct mbuf **mp)
4697 int hoff, iphlen, thoff;
4701 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4703 iphlen = m->m_pkthdr.csum_iphlen;
4704 thoff = m->m_pkthdr.csum_thlen;
4705 hoff = m->m_pkthdr.csum_lhlen;
4707 KASSERT(iphlen > 0, ("invalid ip hlen"));
4708 KASSERT(thoff > 0, ("invalid tcp hlen"));
4709 KASSERT(hoff > 0, ("invalid ether hlen"));
4711 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4712 m = m_pullup(m, hoff + iphlen + thoff);
4719 if (txr->tx_flags & IGB_TXFLAG_TSO_IPLEN0) {
4722 ip = mtodoff(m, struct ip *, hoff);
4730 igb_tso_ctx(struct igb_tx_ring *txr, struct mbuf *m, uint32_t *hlen)
4732 struct e1000_adv_tx_context_desc *TXD;
4733 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
4734 int hoff, ctxd, iphlen, thoff;
4736 iphlen = m->m_pkthdr.csum_iphlen;
4737 thoff = m->m_pkthdr.csum_thlen;
4738 hoff = m->m_pkthdr.csum_lhlen;
4740 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
4742 ctxd = txr->next_avail_desc;
4743 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
4745 if (m->m_flags & M_VLANTAG) {
4748 vlantag = htole16(m->m_pkthdr.ether_vlantag);
4749 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
4752 vlan_macip_lens |= (hoff << E1000_ADVTXD_MACLEN_SHIFT);
4753 vlan_macip_lens |= iphlen;
4755 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4756 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
4757 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
4759 mss_l4len_idx |= (m->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT);
4760 mss_l4len_idx |= (thoff << E1000_ADVTXD_L4LEN_SHIFT);
4763 * 82575 needs the TX context index added; the queue
4764 * index is used as TX context index here.
4766 if (txr->sc->hw.mac.type == e1000_82575)
4767 mss_l4len_idx |= txr->me << 4;
4769 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
4770 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
4771 TXD->seqnum_seed = htole32(0);
4772 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
4774 /* We've consumed the first desc, adjust counters */
4775 if (++ctxd == txr->num_tx_desc)
4777 txr->next_avail_desc = ctxd;
4780 *hlen = hoff + iphlen + thoff;
4784 igb_setup_serializer(struct igb_softc *sc)
4786 const struct igb_msix_data *msix;
4790 * Allocate serializer array
4793 /* Main + TX + RX */
4794 sc->serialize_cnt = 1 + sc->tx_ring_cnt + sc->rx_ring_cnt;
4796 /* Aggregate TX/RX MSI-X */
4797 for (i = 0; i < sc->msix_cnt; ++i) {
4798 msix = &sc->msix_data[i];
4799 if (msix->msix_serialize == &msix->msix_serialize0)
4800 sc->serialize_cnt++;
4804 kmalloc(sc->serialize_cnt * sizeof(struct lwkt_serialize *),
4805 M_DEVBUF, M_WAITOK | M_ZERO);
4810 * NOTE: Order is critical
4815 KKASSERT(i < sc->serialize_cnt);
4816 sc->serializes[i++] = &sc->main_serialize;
4818 for (j = 0; j < sc->msix_cnt; ++j) {
4819 msix = &sc->msix_data[j];
4820 if (msix->msix_serialize == &msix->msix_serialize0) {
4821 KKASSERT(i < sc->serialize_cnt);
4822 sc->serializes[i++] = msix->msix_serialize;
4826 for (j = 0; j < sc->tx_ring_cnt; ++j) {
4827 KKASSERT(i < sc->serialize_cnt);
4828 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
4831 for (j = 0; j < sc->rx_ring_cnt; ++j) {
4832 KKASSERT(i < sc->serialize_cnt);
4833 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
4836 KKASSERT(i == sc->serialize_cnt);
4840 igb_msix_rx_conf(struct igb_softc *sc, int i, int *x0, int offset)
4844 for (; i < sc->rx_ring_msix; ++i) {
4845 struct igb_rx_ring *rxr = &sc->rx_rings[i];
4846 struct igb_msix_data *msix;
4848 KKASSERT(x < sc->msix_cnt);
4849 msix = &sc->msix_data[x++];
4851 rxr->rx_intr_bit = msix->msix_vector;
4852 rxr->rx_intr_mask = msix->msix_mask;
4854 msix->msix_serialize = &rxr->rx_serialize;
4855 msix->msix_func = igb_msix_rx;
4856 msix->msix_arg = rxr;
4858 msix->msix_cpuid = i + offset;
4859 KKASSERT(msix->msix_cpuid < ncpus2);
4861 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s rx%d",
4862 device_get_nameunit(sc->dev), i);
4864 msix->msix_rate = IGB_MSIX_RX_RATE;
4865 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4866 "RX%d interrupt rate", i);
4872 igb_msix_tx_conf(struct igb_softc *sc, int i, int *x0, int offset)
4876 for (; i < sc->tx_ring_msix; ++i) {
4877 struct igb_tx_ring *txr = &sc->tx_rings[i];
4878 struct igb_msix_data *msix;
4880 KKASSERT(x < sc->msix_cnt);
4881 msix = &sc->msix_data[x++];
4883 txr->tx_intr_bit = msix->msix_vector;
4884 txr->tx_intr_mask = msix->msix_mask;
4886 msix->msix_serialize = &txr->tx_serialize;
4887 msix->msix_func = igb_msix_tx;
4888 msix->msix_arg = txr;
4890 msix->msix_cpuid = i + offset;
4891 KKASSERT(msix->msix_cpuid < ncpus2);
4892 txr->tx_intr_cpuid = msix->msix_cpuid;
4894 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s tx%d",
4895 device_get_nameunit(sc->dev), i);
4897 msix->msix_rate = IGB_MSIX_TX_RATE;
4898 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4899 "TX%d interrupt rate", i);
4905 igb_msix_rxtx(void *arg)
4907 struct igb_msix_data *msix = arg;
4908 struct igb_rx_ring *rxr = msix->msix_rx;
4909 struct igb_tx_ring *txr = msix->msix_tx;
4911 ASSERT_SERIALIZED(&msix->msix_serialize0);
4913 lwkt_serialize_enter(&rxr->rx_serialize);
4915 lwkt_serialize_exit(&rxr->rx_serialize);
4917 lwkt_serialize_enter(&txr->tx_serialize);
4919 if (!ifsq_is_empty(txr->ifsq))
4920 ifsq_devstart(txr->ifsq);
4921 lwkt_serialize_exit(&txr->tx_serialize);
4923 E1000_WRITE_REG(&msix->msix_sc->hw, E1000_EIMS, msix->msix_mask);
4927 igb_set_timer_cpuid(struct igb_softc *sc, boolean_t polling)
4929 if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
4930 sc->timer_cpuid = 0; /* XXX fixed */
4932 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);