bd6e97915898df08dc169bc6be0fb4c9a4e2710e
[dragonfly.git] / sys / dev / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include <drm/drmP.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/drm_fb_helper.h>
32 #include <drm/drm_legacy.h>
33 #include "intel_drv.h"
34 #include <drm/i915_drm.h>
35 #include "i915_drv.h"
36 #include "i915_vgpu.h"
37
38
39 static int i915_getparam(struct drm_device *dev, void *data,
40                          struct drm_file *file_priv)
41 {
42         struct drm_i915_private *dev_priv = dev->dev_private;
43         drm_i915_getparam_t *param = data;
44         int value;
45
46         switch (param->param) {
47         case I915_PARAM_IRQ_ACTIVE:
48         case I915_PARAM_ALLOW_BATCHBUFFER:
49         case I915_PARAM_LAST_DISPATCH:
50                 /* Reject all old ums/dri params. */
51                 return -ENODEV;
52         case I915_PARAM_CHIPSET_ID:
53                 value = dev->pdev->device;
54                 break;
55         case I915_PARAM_REVISION:
56                 value = dev->pdev->revision;
57                 break;
58         case I915_PARAM_HAS_GEM:
59                 value = 1;
60                 break;
61         case I915_PARAM_NUM_FENCES_AVAIL:
62                 value = dev_priv->num_fence_regs;
63                 break;
64         case I915_PARAM_HAS_OVERLAY:
65                 value = dev_priv->overlay ? 1 : 0;
66                 break;
67         case I915_PARAM_HAS_PAGEFLIPPING:
68                 value = 1;
69                 break;
70         case I915_PARAM_HAS_EXECBUF2:
71                 /* depends on GEM */
72                 value = 1;
73                 break;
74         case I915_PARAM_HAS_BSD:
75                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
76                 break;
77         case I915_PARAM_HAS_BLT:
78                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
79                 break;
80         case I915_PARAM_HAS_VEBOX:
81                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
82                 break;
83         case I915_PARAM_HAS_BSD2:
84                 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
85                 break;
86         case I915_PARAM_HAS_RELAXED_FENCING:
87                 value = 1;
88                 break;
89         case I915_PARAM_HAS_COHERENT_RINGS:
90                 value = 1;
91                 break;
92         case I915_PARAM_HAS_EXEC_CONSTANTS:
93                 value = INTEL_INFO(dev)->gen >= 4;
94                 break;
95         case I915_PARAM_HAS_RELAXED_DELTA:
96                 value = 1;
97                 break;
98         case I915_PARAM_HAS_GEN7_SOL_RESET:
99                 value = 1;
100                 break;
101         case I915_PARAM_HAS_LLC:
102                 value = HAS_LLC(dev);
103                 break;
104         case I915_PARAM_HAS_WT:
105                 value = HAS_WT(dev);
106                 break;
107         case I915_PARAM_HAS_ALIASING_PPGTT:
108                 value = USES_PPGTT(dev);
109                 break;
110         case I915_PARAM_HAS_WAIT_TIMEOUT:
111                 value = 1;
112                 break;
113         case I915_PARAM_HAS_SEMAPHORES:
114                 value = i915_semaphore_is_enabled(dev);
115                 break;
116         case I915_PARAM_HAS_PINNED_BATCHES:
117                 value = 1;
118                 break;
119         case I915_PARAM_HAS_EXEC_NO_RELOC:
120                 value = 1;
121                 break;
122         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
123                 value = 1;
124                 break;
125         case I915_PARAM_CMD_PARSER_VERSION:
126                 value = i915_cmd_parser_get_version();
127                 break;
128         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
129                 value = 1;
130                 break;
131         case I915_PARAM_SUBSLICE_TOTAL:
132                 value = INTEL_INFO(dev)->subslice_total;
133                 if (!value)
134                         return -ENODEV;
135                 break;
136         case I915_PARAM_EU_TOTAL:
137                 value = INTEL_INFO(dev)->eu_total;
138                 if (!value)
139                         return -ENODEV;
140                 break;
141         case I915_PARAM_HAS_GPU_RESET:
142                 value = i915.enable_hangcheck &&
143                         intel_has_gpu_reset(dev);
144                 break;
145         case I915_PARAM_HAS_RESOURCE_STREAMER:
146                 value = HAS_RESOURCE_STREAMER(dev);
147                 break;
148         case I915_PARAM_HAS_EXEC_SOFTPIN:
149                 value = 1;
150                 break;
151         default:
152                 DRM_DEBUG("Unknown parameter %d\n", param->param);
153                 return -EINVAL;
154         }
155
156         if (copy_to_user(param->value, &value, sizeof(int))) {
157                 DRM_ERROR("copy_to_user failed\n");
158                 return -EFAULT;
159         }
160
161         return 0;
162 }
163
164 static int i915_get_bridge_dev(struct drm_device *dev)
165 {
166         struct drm_i915_private *dev_priv = dev->dev_private;
167         static struct pci_dev i915_bridge_dev;
168
169         i915_bridge_dev.dev.bsddev = pci_find_dbsf(0, 0, 0, 0);
170         if (!i915_bridge_dev.dev.bsddev) {
171                 DRM_ERROR("bridge device not found\n");
172                 return -1;
173         }
174
175         dev_priv->bridge_dev = &i915_bridge_dev;
176         return 0;
177 }
178
179 #define MCHBAR_I915 0x44
180 #define MCHBAR_I965 0x48
181 #define MCHBAR_SIZE (4*4096)
182
183 #define DEVEN_REG 0x54
184 #define   DEVEN_MCHBAR_EN (1 << 28)
185
186 /* Allocate space for the MCH regs if needed, return nonzero on error */
187 static int
188 intel_alloc_mchbar_resource(struct drm_device *dev)
189 {
190         struct drm_i915_private *dev_priv = dev->dev_private;
191         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
192         device_t vga;
193         u32 temp_lo, temp_hi = 0;
194         u64 mchbar_addr;
195
196         if (INTEL_INFO(dev)->gen >= 4)
197                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
198         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
199         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
200
201         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
202 #ifdef CONFIG_PNP
203         if (mchbar_addr &&
204             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
205                 return 0;
206 #endif
207
208         /* Get some space for it */
209         vga = device_get_parent(dev->dev->bsddev);
210         dev_priv->mch_res_rid = 0x100;
211         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
212             dev->dev->bsddev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
213             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
214         if (dev_priv->mch_res == NULL) {
215                 DRM_ERROR("failed mchbar resource alloc\n");
216                 return (-ENOMEM);
217         }
218
219         if (INTEL_INFO(dev)->gen >= 4)
220                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
221                                        upper_32_bits(rman_get_start(dev_priv->mch_res)));
222
223         pci_write_config_dword(dev_priv->bridge_dev, reg,
224                                lower_32_bits(rman_get_start(dev_priv->mch_res)));
225         return 0;
226 }
227
228 /* Setup MCHBAR if possible, return true if we should disable it again */
229 static void
230 intel_setup_mchbar(struct drm_device *dev)
231 {
232         struct drm_i915_private *dev_priv = dev->dev_private;
233         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
234         u32 temp;
235         bool enabled;
236
237         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
238                 return;
239
240         dev_priv->mchbar_need_disable = false;
241
242         if (IS_I915G(dev) || IS_I915GM(dev)) {
243                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
244                 enabled = !!(temp & DEVEN_MCHBAR_EN);
245         } else {
246                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
247                 enabled = temp & 1;
248         }
249
250         /* If it's already enabled, don't have to do anything */
251         if (enabled)
252                 return;
253
254         if (intel_alloc_mchbar_resource(dev))
255                 return;
256
257         dev_priv->mchbar_need_disable = true;
258
259         /* Space is allocated or reserved, so enable it. */
260         if (IS_I915G(dev) || IS_I915GM(dev)) {
261                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
262                                        temp | DEVEN_MCHBAR_EN);
263         } else {
264                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
265                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
266         }
267 }
268
269 static void
270 intel_teardown_mchbar(struct drm_device *dev)
271 {
272         struct drm_i915_private *dev_priv = dev->dev_private;
273         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
274         device_t vga;
275         u32 temp;
276
277         if (dev_priv->mchbar_need_disable) {
278                 if (IS_I915G(dev) || IS_I915GM(dev)) {
279                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
280                         temp &= ~DEVEN_MCHBAR_EN;
281                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
282                 } else {
283                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
284                         temp &= ~1;
285                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
286                 }
287         }
288
289         if (dev_priv->mch_res != NULL) {
290                 vga = device_get_parent(dev->dev->bsddev);
291                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev->bsddev,
292                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
293                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev->bsddev,
294                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
295                 dev_priv->mch_res = NULL;
296         }
297 }
298
299 #if 0
300 /* true = enable decode, false = disable decoder */
301 static unsigned int i915_vga_set_decode(void *cookie, bool state)
302 {
303         struct drm_device *dev = cookie;
304
305         intel_modeset_vga_set_state(dev, state);
306         if (state)
307                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
308                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
309         else
310                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
311 }
312
313 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
314 {
315         struct drm_device *dev = pci_get_drvdata(pdev);
316         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
317
318         if (state == VGA_SWITCHEROO_ON) {
319                 pr_info("switched on\n");
320                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
321                 /* i915 resume handler doesn't set to D0 */
322                 pci_set_power_state(dev->pdev, PCI_D0);
323                 i915_resume_switcheroo(dev);
324                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
325         } else {
326                 pr_info("switched off\n");
327                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
328                 i915_suspend_switcheroo(dev, pmm);
329                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
330         }
331 }
332
333 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
334 {
335         struct drm_device *dev = pci_get_drvdata(pdev);
336
337         /*
338          * FIXME: open_count is protected by drm_global_mutex but that would lead to
339          * locking inversion with the driver load path. And the access here is
340          * completely racy anyway. So don't bother with locking for now.
341          */
342         return dev->open_count == 0;
343 }
344
345 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
346         .set_gpu_state = i915_switcheroo_set_state,
347         .reprobe = NULL,
348         .can_switch = i915_switcheroo_can_switch,
349 };
350 #endif
351
352 static int i915_load_modeset_init(struct drm_device *dev)
353 {
354         struct drm_i915_private *dev_priv = dev->dev_private;
355         int ret;
356
357         ret = intel_bios_init(dev_priv);
358         if (ret)
359                 DRM_INFO("failed to find VBIOS tables\n");
360
361 #if 0
362         /* If we have > 1 VGA cards, then we need to arbitrate access
363          * to the common VGA resources.
364          *
365          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
366          * then we do not take part in VGA arbitration and the
367          * vga_client_register() fails with -ENODEV.
368          */
369         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
370         if (ret && ret != -ENODEV)
371                 goto out;
372
373         intel_register_dsm_handler();
374
375         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
376         if (ret)
377                 goto cleanup_vga_client;
378
379         /* Initialise stolen first so that we may reserve preallocated
380          * objects for the BIOS to KMS transition.
381          */
382         ret = i915_gem_init_stolen(dev);
383         if (ret)
384                 goto cleanup_vga_switcheroo;
385 #endif
386
387         intel_power_domains_init_hw(dev_priv, false);
388
389         intel_csr_ucode_init(dev_priv);
390
391         ret = intel_irq_install(dev_priv);
392         if (ret)
393                 goto cleanup_gem_stolen;
394
395         intel_setup_gmbus(dev);
396
397         /* Important: The output setup functions called by modeset_init need
398          * working irqs for e.g. gmbus and dp aux transfers. */
399         intel_modeset_init(dev);
400
401         intel_guc_ucode_init(dev);
402
403         ret = i915_gem_init(dev);
404         if (ret)
405                 goto cleanup_irq;
406
407         intel_modeset_gem_init(dev);
408
409         /* Always safe in the mode setting case. */
410         /* FIXME: do pre/post-mode set stuff in core KMS code */
411         dev->vblank_disable_allowed = 1;
412         if (INTEL_INFO(dev)->num_pipes == 0)
413                 return 0;
414
415         ret = intel_fbdev_init(dev);
416         if (ret)
417                 goto cleanup_gem;
418
419         /* Only enable hotplug handling once the fbdev is fully set up. */
420         intel_hpd_init(dev_priv);
421
422         /*
423          * Some ports require correctly set-up hpd registers for detection to
424          * work properly (leading to ghost connected connector status), e.g. VGA
425          * on gm45.  Hence we can only set up the initial fbdev config after hpd
426          * irqs are fully enabled. Now we should scan for the initial config
427          * only once hotplug handling is enabled, but due to screwed-up locking
428          * around kms/fbdev init we can't protect the fdbev initial config
429          * scanning against hotplug events. Hence do this first and ignore the
430          * tiny window where we will loose hotplug notifactions.
431          */
432         intel_fbdev_initial_config_async(dev);
433
434         drm_kms_helper_poll_init(dev);
435
436         return 0;
437
438 cleanup_gem:
439         mutex_lock(&dev->struct_mutex);
440         i915_gem_cleanup_ringbuffer(dev);
441         i915_gem_context_fini(dev);
442         mutex_unlock(&dev->struct_mutex);
443 cleanup_irq:
444         intel_guc_ucode_fini(dev);
445         drm_irq_uninstall(dev);
446         intel_teardown_gmbus(dev);
447 cleanup_gem_stolen:
448         i915_gem_cleanup_stolen(dev);
449 #if 0
450 cleanup_vga_switcheroo:
451         vga_switcheroo_unregister_client(dev->pdev);
452 cleanup_vga_client:
453         vga_client_register(dev->pdev, NULL, NULL, NULL);
454 out:
455 #endif
456         return ret;
457 }
458
459 #if IS_ENABLED(CONFIG_FB)
460 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
461 {
462         struct apertures_struct *ap;
463         struct pci_dev *pdev = dev_priv->dev->pdev;
464         bool primary;
465         int ret;
466
467         ap = alloc_apertures(1);
468         if (!ap)
469                 return -ENOMEM;
470
471         ap->ranges[0].base = dev_priv->gtt.mappable_base;
472         ap->ranges[0].size = dev_priv->gtt.mappable_end;
473
474         primary =
475                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
476
477         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
478
479         kfree(ap);
480
481         return ret;
482 }
483 #else
484 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
485 {
486         return 0;
487 }
488 #endif
489
490 #if !defined(CONFIG_VGA_CONSOLE)
491 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
492 {
493         return 0;
494 }
495 #elif !defined(CONFIG_DUMMY_CONSOLE)
496 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
497 {
498         return -ENODEV;
499 }
500 #else
501 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
502 {
503         int ret = 0;
504
505         DRM_INFO("Replacing VGA console driver\n");
506
507         console_lock();
508         if (con_is_bound(&vga_con))
509                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
510         if (ret == 0) {
511                 ret = do_unregister_con_driver(&vga_con);
512
513                 /* Ignore "already unregistered". */
514                 if (ret == -ENODEV)
515                         ret = 0;
516         }
517         console_unlock();
518
519         return ret;
520 }
521 #endif
522
523 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
524 {
525 #if 0
526         const struct intel_device_info *info = &dev_priv->info;
527
528 #define PRINT_S(name) "%s"
529 #define SEP_EMPTY
530 #define PRINT_FLAG(name) info->name ? #name "," : ""
531 #define SEP_COMMA ,
532         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
533                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
534                          info->gen,
535                          dev_priv->dev->pdev->device,
536                          dev_priv->dev->pdev->revision,
537                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
538 #undef PRINT_S
539 #undef SEP_EMPTY
540 #undef PRINT_FLAG
541 #undef SEP_COMMA
542 #endif
543 }
544
545 static void cherryview_sseu_info_init(struct drm_device *dev)
546 {
547         struct drm_i915_private *dev_priv = dev->dev_private;
548         struct intel_device_info *info;
549         u32 fuse, eu_dis;
550
551         info = (struct intel_device_info *)&dev_priv->info;
552         fuse = I915_READ(CHV_FUSE_GT);
553
554         info->slice_total = 1;
555
556         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
557                 info->subslice_per_slice++;
558                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
559                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
560                 info->eu_total += 8 - hweight32(eu_dis);
561         }
562
563         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
564                 info->subslice_per_slice++;
565                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
566                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
567                 info->eu_total += 8 - hweight32(eu_dis);
568         }
569
570         info->subslice_total = info->subslice_per_slice;
571         /*
572          * CHV expected to always have a uniform distribution of EU
573          * across subslices.
574         */
575         info->eu_per_subslice = info->subslice_total ?
576                                 info->eu_total / info->subslice_total :
577                                 0;
578         /*
579          * CHV supports subslice power gating on devices with more than
580          * one subslice, and supports EU power gating on devices with
581          * more than one EU pair per subslice.
582         */
583         info->has_slice_pg = 0;
584         info->has_subslice_pg = (info->subslice_total > 1);
585         info->has_eu_pg = (info->eu_per_subslice > 2);
586 }
587
588 static void gen9_sseu_info_init(struct drm_device *dev)
589 {
590         struct drm_i915_private *dev_priv = dev->dev_private;
591         struct intel_device_info *info;
592         int s_max = 3, ss_max = 4, eu_max = 8;
593         int s, ss;
594         u32 fuse2, s_enable, ss_disable, eu_disable;
595         u8 eu_mask = 0xff;
596
597         info = (struct intel_device_info *)&dev_priv->info;
598         fuse2 = I915_READ(GEN8_FUSE2);
599         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
600                    GEN8_F2_S_ENA_SHIFT;
601         ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
602                      GEN9_F2_SS_DIS_SHIFT;
603
604         info->slice_total = hweight32(s_enable);
605         /*
606          * The subslice disable field is global, i.e. it applies
607          * to each of the enabled slices.
608         */
609         info->subslice_per_slice = ss_max - hweight32(ss_disable);
610         info->subslice_total = info->slice_total *
611                                info->subslice_per_slice;
612
613         /*
614          * Iterate through enabled slices and subslices to
615          * count the total enabled EU.
616         */
617         for (s = 0; s < s_max; s++) {
618                 if (!(s_enable & (0x1 << s)))
619                         /* skip disabled slice */
620                         continue;
621
622                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
623                 for (ss = 0; ss < ss_max; ss++) {
624                         int eu_per_ss;
625
626                         if (ss_disable & (0x1 << ss))
627                                 /* skip disabled subslice */
628                                 continue;
629
630                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
631                                                       eu_mask);
632
633                         /*
634                          * Record which subslice(s) has(have) 7 EUs. we
635                          * can tune the hash used to spread work among
636                          * subslices if they are unbalanced.
637                          */
638                         if (eu_per_ss == 7)
639                                 info->subslice_7eu[s] |= 1 << ss;
640
641                         info->eu_total += eu_per_ss;
642                 }
643         }
644
645         /*
646          * SKL is expected to always have a uniform distribution
647          * of EU across subslices with the exception that any one
648          * EU in any one subslice may be fused off for die
649          * recovery. BXT is expected to be perfectly uniform in EU
650          * distribution.
651         */
652         info->eu_per_subslice = info->subslice_total ?
653                                 DIV_ROUND_UP(info->eu_total,
654                                              info->subslice_total) : 0;
655         /*
656          * SKL supports slice power gating on devices with more than
657          * one slice, and supports EU power gating on devices with
658          * more than one EU pair per subslice. BXT supports subslice
659          * power gating on devices with more than one subslice, and
660          * supports EU power gating on devices with more than one EU
661          * pair per subslice.
662         */
663         info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
664                                (info->slice_total > 1));
665         info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
666         info->has_eu_pg = (info->eu_per_subslice > 2);
667 }
668
669 static void broadwell_sseu_info_init(struct drm_device *dev)
670 {
671         struct drm_i915_private *dev_priv = dev->dev_private;
672         struct intel_device_info *info;
673         const int s_max = 3, ss_max = 3, eu_max = 8;
674         int s, ss;
675         u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
676
677         fuse2 = I915_READ(GEN8_FUSE2);
678         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
679         ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
680
681         eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
682         eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
683                         ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
684                          (32 - GEN8_EU_DIS0_S1_SHIFT));
685         eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
686                         ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
687                          (32 - GEN8_EU_DIS1_S2_SHIFT));
688
689
690         info = (struct intel_device_info *)&dev_priv->info;
691         info->slice_total = hweight32(s_enable);
692
693         /*
694          * The subslice disable field is global, i.e. it applies
695          * to each of the enabled slices.
696          */
697         info->subslice_per_slice = ss_max - hweight32(ss_disable);
698         info->subslice_total = info->slice_total * info->subslice_per_slice;
699
700         /*
701          * Iterate through enabled slices and subslices to
702          * count the total enabled EU.
703          */
704         for (s = 0; s < s_max; s++) {
705                 if (!(s_enable & (0x1 << s)))
706                         /* skip disabled slice */
707                         continue;
708
709                 for (ss = 0; ss < ss_max; ss++) {
710                         u32 n_disabled;
711
712                         if (ss_disable & (0x1 << ss))
713                                 /* skip disabled subslice */
714                                 continue;
715
716                         n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
717
718                         /*
719                          * Record which subslices have 7 EUs.
720                          */
721                         if (eu_max - n_disabled == 7)
722                                 info->subslice_7eu[s] |= 1 << ss;
723
724                         info->eu_total += eu_max - n_disabled;
725                 }
726         }
727
728         /*
729          * BDW is expected to always have a uniform distribution of EU across
730          * subslices with the exception that any one EU in any one subslice may
731          * be fused off for die recovery.
732          */
733         info->eu_per_subslice = info->subslice_total ?
734                 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
735
736         /*
737          * BDW supports slice power gating on devices with more than
738          * one slice.
739          */
740         info->has_slice_pg = (info->slice_total > 1);
741         info->has_subslice_pg = 0;
742         info->has_eu_pg = 0;
743 }
744
745 /*
746  * Determine various intel_device_info fields at runtime.
747  *
748  * Use it when either:
749  *   - it's judged too laborious to fill n static structures with the limit
750  *     when a simple if statement does the job,
751  *   - run-time checks (eg read fuse/strap registers) are needed.
752  *
753  * This function needs to be called:
754  *   - after the MMIO has been setup as we are reading registers,
755  *   - after the PCH has been detected,
756  *   - before the first usage of the fields it can tweak.
757  */
758 static void intel_device_info_runtime_init(struct drm_device *dev)
759 {
760         struct drm_i915_private *dev_priv = dev->dev_private;
761         struct intel_device_info *info;
762         enum i915_pipe pipe;
763
764         info = (struct intel_device_info *)&dev_priv->info;
765
766         /*
767          * Skylake and Broxton currently don't expose the topmost plane as its
768          * use is exclusive with the legacy cursor and we only want to expose
769          * one of those, not both. Until we can safely expose the topmost plane
770          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
771          * we don't expose the topmost plane at all to prevent ABI breakage
772          * down the line.
773          */
774         if (IS_BROXTON(dev)) {
775                 info->num_sprites[PIPE_A] = 2;
776                 info->num_sprites[PIPE_B] = 2;
777                 info->num_sprites[PIPE_C] = 1;
778         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
779                 for_each_pipe(dev_priv, pipe)
780                         info->num_sprites[pipe] = 2;
781         else
782                 for_each_pipe(dev_priv, pipe)
783                         info->num_sprites[pipe] = 1;
784
785         if (i915.disable_display) {
786                 DRM_INFO("Display disabled (module parameter)\n");
787                 info->num_pipes = 0;
788         } else if (info->num_pipes > 0 &&
789                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
790                    HAS_PCH_SPLIT(dev)) {
791                 u32 fuse_strap = I915_READ(FUSE_STRAP);
792                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
793
794                 /*
795                  * SFUSE_STRAP is supposed to have a bit signalling the display
796                  * is fused off. Unfortunately it seems that, at least in
797                  * certain cases, fused off display means that PCH display
798                  * reads don't land anywhere. In that case, we read 0s.
799                  *
800                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
801                  * should be set when taking over after the firmware.
802                  */
803                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
804                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
805                     (dev_priv->pch_type == PCH_CPT &&
806                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
807                         DRM_INFO("Display fused off, disabling\n");
808                         info->num_pipes = 0;
809                 }
810         }
811
812         /* Initialize slice/subslice/EU info */
813         if (IS_CHERRYVIEW(dev))
814                 cherryview_sseu_info_init(dev);
815         else if (IS_BROADWELL(dev))
816                 broadwell_sseu_info_init(dev);
817         else if (INTEL_INFO(dev)->gen >= 9)
818                 gen9_sseu_info_init(dev);
819
820         DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
821         DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
822         DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
823         DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
824         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
825         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
826                          info->has_slice_pg ? "y" : "n");
827         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
828                          info->has_subslice_pg ? "y" : "n");
829         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
830                          info->has_eu_pg ? "y" : "n");
831 }
832
833 static void intel_init_dpio(struct drm_i915_private *dev_priv)
834 {
835         /*
836          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
837          * CHV x1 PHY (DP/HDMI D)
838          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
839          */
840         if (IS_CHERRYVIEW(dev_priv)) {
841                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
842                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
843         } else if (IS_VALLEYVIEW(dev_priv)) {
844                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
845         }
846 }
847
848 /**
849  * i915_driver_load - setup chip and create an initial config
850  * @dev: DRM device
851  * @flags: startup flags
852  *
853  * The driver load routine has to do several things:
854  *   - drive output discovery via intel_modeset_init()
855  *   - initialize the memory manager
856  *   - allocate initial config memory
857  *   - setup the DRM framebuffer with the allocated memory
858  */
859 int i915_driver_load(struct drm_device *dev, unsigned long flags)
860 {
861         struct drm_i915_private *dev_priv;
862         struct intel_device_info *info, *device_info;
863         int ret = 0, mmio_bar, mmio_size;
864         uint32_t aperture_size;
865
866         /* XXX: struct pci_dev */
867         info = i915_get_device_id(dev->pdev->device);
868
869         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
870         if (dev_priv == NULL)
871                 return -ENOMEM;
872
873         dev->dev_private = dev_priv;
874         dev_priv->dev = dev;
875
876         /* Setup the write-once "constant" device info */
877         device_info = (struct intel_device_info *)&dev_priv->info;
878         memcpy(device_info, info, sizeof(dev_priv->info));
879         device_info->device_id = dev->pdev->device;
880
881         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
882         lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
883         lockinit(&dev_priv->backlight_lock, "i915bl", 0, LK_CANRECURSE);
884         lockinit(&dev_priv->uncore.lock, "915gt", 0, LK_CANRECURSE);
885         spin_init(&dev_priv->mm.object_stat_lock, "i915osl");
886         spin_init(&dev_priv->mmio_flip_lock, "i915mfl");
887         lockinit(&dev_priv->sb_lock, "i915sbl", 0, LK_CANRECURSE);
888         lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
889         lockinit(&dev_priv->av_mutex, "i915am", 0, LK_CANRECURSE);
890
891         intel_pm_setup(dev);
892
893         intel_runtime_pm_get(dev_priv);
894
895         intel_display_crc_init(dev);
896
897         i915_dump_device_info(dev_priv);
898
899         /* Not all pre-production machines fall into this category, only the
900          * very first ones. Almost everything should work, except for maybe
901          * suspend/resume. And we don't implement workarounds that affect only
902          * pre-production machines. */
903         if (IS_HSW_EARLY_SDV(dev))
904                 DRM_INFO("This is an early pre-production Haswell machine. "
905                          "It may not be fully functional.\n");
906
907         if (i915_get_bridge_dev(dev)) {
908                 ret = -EIO;
909                 goto free_priv;
910         }
911
912         mmio_bar = IS_GEN2(dev) ? 1 : 0;
913         /* Before gen4, the registers and the GTT are behind different BARs.
914          * However, from gen4 onwards, the registers and the GTT are shared
915          * in the same BAR, so we want to restrict this ioremap from
916          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
917          * the register BAR remains the same size for all the earlier
918          * generations up to Ironlake.
919          */
920         if (info->gen < 5)
921                 mmio_size = 512*1024;
922         else
923                 mmio_size = 2*1024*1024;
924
925         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
926         if (!dev_priv->regs) {
927                 DRM_ERROR("failed to map registers\n");
928                 ret = -EIO;
929                 goto put_bridge;
930         }
931
932         /* This must be called before any calls to HAS_PCH_* */
933         intel_detect_pch(dev);
934
935         intel_uncore_init(dev);
936
937         ret = i915_gem_gtt_init(dev);
938         if (ret)
939                 goto out_freecsr;
940
941         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
942          * otherwise the vga fbdev driver falls over. */
943         ret = i915_kick_out_firmware_fb(dev_priv);
944         if (ret) {
945                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
946                 goto out_gtt;
947         }
948
949         ret = i915_kick_out_vgacon(dev_priv);
950         if (ret) {
951                 DRM_ERROR("failed to remove conflicting VGA console\n");
952                 goto out_gtt;
953         }
954
955 #if 0
956         pci_set_master(dev->pdev);
957
958         /* overlay on gen2 is broken and can't address above 1G */
959         if (IS_GEN2(dev))
960                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
961
962         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
963          * using 32bit addressing, overwriting memory if HWS is located
964          * above 4GB.
965          *
966          * The documentation also mentions an issue with undefined
967          * behaviour if any general state is accessed within a page above 4GB,
968          * which also needs to be handled carefully.
969          */
970         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
971                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
972 #endif
973
974         aperture_size = dev_priv->gtt.mappable_end;
975
976         dev_priv->gtt.mappable =
977                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
978                                      aperture_size);
979         if (dev_priv->gtt.mappable == NULL) {
980                 ret = -EIO;
981                 goto out_gtt;
982         }
983
984         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
985                                               aperture_size);
986
987         /* The i915 workqueue is primarily used for batched retirement of
988          * requests (and thus managing bo) once the task has been completed
989          * by the GPU. i915_gem_retire_requests() is called directly when we
990          * need high-priority retirement, such as waiting for an explicit
991          * bo.
992          *
993          * It is also used for periodic low-priority events, such as
994          * idle-timers and recording error state.
995          *
996          * All tasks on the workqueue are expected to acquire the dev mutex
997          * so there is no point in running more than one instance of the
998          * workqueue at any time.  Use an ordered one.
999          */
1000         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1001         if (dev_priv->wq == NULL) {
1002                 DRM_ERROR("Failed to create our workqueue.\n");
1003                 ret = -ENOMEM;
1004                 goto out_mtrrfree;
1005         }
1006
1007         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1008         if (dev_priv->hotplug.dp_wq == NULL) {
1009                 DRM_ERROR("Failed to create our dp workqueue.\n");
1010                 ret = -ENOMEM;
1011                 goto out_freewq;
1012         }
1013
1014         dev_priv->gpu_error.hangcheck_wq =
1015                 alloc_ordered_workqueue("i915-hangcheck", 0);
1016         if (dev_priv->gpu_error.hangcheck_wq == NULL) {
1017                 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
1018                 ret = -ENOMEM;
1019                 goto out_freedpwq;
1020         }
1021
1022         intel_irq_init(dev_priv);
1023         intel_uncore_sanitize(dev);
1024
1025         /* Try to make sure MCHBAR is enabled before poking at it */
1026         intel_setup_mchbar(dev);
1027         intel_opregion_setup(dev);
1028
1029         i915_gem_load(dev);
1030
1031         /* On the 945G/GM, the chipset reports the MSI capability on the
1032          * integrated graphics even though the support isn't actually there
1033          * according to the published specs.  It doesn't appear to function
1034          * correctly in testing on 945G.
1035          * This may be a side effect of MSI having been made available for PEG
1036          * and the registers being closely associated.
1037          *
1038          * According to chipset errata, on the 965GM, MSI interrupts may
1039          * be lost or delayed, but we use them anyways to avoid
1040          * stuck interrupts on some machines.
1041          */
1042 #if 0
1043         if (!IS_I945G(dev) && !IS_I945GM(dev))
1044                 pci_enable_msi(dev->pdev);
1045 #endif
1046
1047         intel_device_info_runtime_init(dev);
1048
1049         intel_init_dpio(dev_priv);
1050
1051         if (INTEL_INFO(dev)->num_pipes) {
1052                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1053                 if (ret)
1054                         goto out_gem_unload;
1055         }
1056
1057         intel_power_domains_init(dev_priv);
1058
1059         ret = i915_load_modeset_init(dev);
1060         if (ret < 0) {
1061                 DRM_ERROR("failed to init modeset\n");
1062                 goto out_power_well;
1063         }
1064
1065         /*
1066          * Notify a valid surface after modesetting,
1067          * when running inside a VM.
1068          */
1069         if (intel_vgpu_active(dev))
1070                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1071
1072         i915_setup_sysfs(dev);
1073
1074         if (INTEL_INFO(dev)->num_pipes) {
1075                 /* Must be done after probing outputs */
1076                 intel_opregion_init(dev);
1077 #if 0
1078                 acpi_video_register();
1079 #endif
1080         }
1081
1082         if (IS_GEN5(dev))
1083                 intel_gpu_ips_init(dev_priv);
1084
1085         intel_runtime_pm_enable(dev_priv);
1086
1087         i915_audio_component_init(dev_priv);
1088
1089         intel_runtime_pm_put(dev_priv);
1090
1091         return 0;
1092
1093 out_power_well:
1094         intel_power_domains_fini(dev_priv);
1095         drm_vblank_cleanup(dev);
1096 out_gem_unload:
1097
1098         intel_teardown_mchbar(dev);
1099         pm_qos_remove_request(&dev_priv->pm_qos);
1100         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1101 out_freedpwq:
1102         destroy_workqueue(dev_priv->hotplug.dp_wq);
1103 out_freewq:
1104         destroy_workqueue(dev_priv->wq);
1105 out_mtrrfree:
1106         arch_phys_wc_del(dev_priv->gtt.mtrr);
1107 #if 0
1108         io_mapping_free(dev_priv->gtt.mappable);
1109 #endif
1110 out_gtt:
1111         i915_global_gtt_cleanup(dev);
1112 out_freecsr:
1113         intel_csr_ucode_fini(dev_priv);
1114         intel_uncore_fini(dev);
1115 #if 0
1116         pci_iounmap(dev->pdev, dev_priv->regs);
1117 #endif
1118 put_bridge:
1119         pci_dev_put(dev_priv->bridge_dev);
1120 free_priv:
1121
1122         intel_runtime_pm_put(dev_priv);
1123
1124         kfree(dev_priv);
1125         return ret;
1126 }
1127
1128 int i915_driver_unload(struct drm_device *dev)
1129 {
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131         int ret;
1132
1133         intel_fbdev_fini(dev);
1134
1135         i915_audio_component_cleanup(dev_priv);
1136
1137         ret = i915_gem_suspend(dev);
1138         if (ret) {
1139                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1140                 return ret;
1141         }
1142
1143         intel_power_domains_fini(dev_priv);
1144
1145         intel_gpu_ips_teardown();
1146
1147         i915_teardown_sysfs(dev);
1148
1149 #if 0
1150         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1151         unregister_shrinker(&dev_priv->mm.shrinker);
1152
1153         io_mapping_free(dev_priv->gtt.mappable);
1154 #endif
1155         arch_phys_wc_del(dev_priv->gtt.mtrr);
1156
1157 #if 0
1158         acpi_video_unregister();
1159 #endif
1160
1161         drm_vblank_cleanup(dev);
1162
1163         intel_modeset_cleanup(dev);
1164
1165         /*
1166          * free the memory space allocated for the child device
1167          * config parsed from VBT
1168          */
1169         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1170                 kfree(dev_priv->vbt.child_dev);
1171                 dev_priv->vbt.child_dev = NULL;
1172                 dev_priv->vbt.child_dev_num = 0;
1173         }
1174         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1175         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1176         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1177         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1178
1179 #if 0
1180         vga_switcheroo_unregister_client(dev->pdev);
1181         vga_client_register(dev->pdev, NULL, NULL, NULL);
1182 #endif
1183
1184         /* Free error state after interrupts are fully disabled. */
1185         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1186 #if 0
1187         i915_destroy_error_state(dev);
1188
1189         if (dev->pdev->msi_enabled)
1190                 pci_disable_msi(dev->pdev);
1191 #endif
1192
1193         intel_opregion_fini(dev);
1194
1195         /* Flush any outstanding unpin_work. */
1196         flush_workqueue(dev_priv->wq);
1197
1198         intel_guc_ucode_fini(dev);
1199         mutex_lock(&dev->struct_mutex);
1200         i915_gem_cleanup_ringbuffer(dev);
1201         i915_gem_context_fini(dev);
1202         mutex_unlock(&dev->struct_mutex);
1203         intel_fbc_cleanup_cfb(dev_priv);
1204         i915_gem_cleanup_stolen(dev);
1205
1206         intel_csr_ucode_fini(dev_priv);
1207
1208         intel_teardown_mchbar(dev);
1209
1210         destroy_workqueue(dev_priv->hotplug.dp_wq);
1211         destroy_workqueue(dev_priv->wq);
1212         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1213         pm_qos_remove_request(&dev_priv->pm_qos);
1214
1215         i915_global_gtt_cleanup(dev);
1216
1217         intel_uncore_fini(dev);
1218 #if 0
1219         if (dev_priv->regs != NULL)
1220                 pci_iounmap(dev->pdev, dev_priv->regs);
1221 #endif
1222
1223         pci_dev_put(dev_priv->bridge_dev);
1224         kfree(dev_priv);
1225
1226         return 0;
1227 }
1228
1229 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1230 {
1231         int ret;
1232
1233         ret = i915_gem_open(dev, file);
1234         if (ret)
1235                 return ret;
1236
1237         return 0;
1238 }
1239
1240 /**
1241  * i915_driver_lastclose - clean up after all DRM clients have exited
1242  * @dev: DRM device
1243  *
1244  * Take care of cleaning up after all DRM clients have exited.  In the
1245  * mode setting case, we want to restore the kernel's initial mode (just
1246  * in case the last client left us in a bad state).
1247  *
1248  * Additionally, in the non-mode setting case, we'll tear down the GTT
1249  * and DMA structures, since the kernel won't be using them, and clea
1250  * up any GEM state.
1251  */
1252 void i915_driver_lastclose(struct drm_device *dev)
1253 {
1254         intel_fbdev_restore_mode(dev);
1255 #if 0
1256         vga_switcheroo_process_delayed_switch();
1257 #endif
1258 }
1259
1260 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1261 {
1262         mutex_lock(&dev->struct_mutex);
1263         i915_gem_context_close(dev, file);
1264         i915_gem_release(dev, file);
1265         mutex_unlock(&dev->struct_mutex);
1266
1267         intel_modeset_preclose(dev, file);
1268 }
1269
1270 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1271 {
1272         struct drm_i915_file_private *file_priv = file->driver_priv;
1273
1274         kfree(file_priv);
1275 }
1276
1277 static int
1278 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1279                           struct drm_file *file)
1280 {
1281         return -ENODEV;
1282 }
1283
1284 const struct drm_ioctl_desc i915_ioctls[] = {
1285         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1286         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1287         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1288         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1289         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1290         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1291         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1292         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1293         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1294         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1295         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1296         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1297         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1298         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1299         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1300         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1301         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1302         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1303         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1304         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1305         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1306         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1307         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1308         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1309         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1310         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1311         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1312         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1313         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1314         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1315         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1316         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1317         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1318         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1319         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1320         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1321         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1322         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1323         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1324         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1325         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1326         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1327         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1328         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1329         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1330         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1331         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1332         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1333         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1334 #if 0
1335         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1336 #endif
1337         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1338         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1339 };
1340
1341 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);