2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.10 2005/02/15 19:39:40 joerg Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
45 #include <net/ifq_var.h>
46 #include <net/if_arp.h>
47 #include <net/ethernet.h>
48 #include <net/if_dl.h>
49 #include <net/if_media.h>
53 #include <net/if_types.h>
54 #include <net/vlan/if_vlan_var.h>
56 #include <netinet/in_systm.h>
57 #include <netinet/in.h>
58 #include <netinet/ip.h>
60 #include <machine/bus_memio.h>
61 #include <machine/bus.h>
62 #include <machine/resource.h>
66 #include <bus/pci/pcireg.h>
67 #include <bus/pci/pcivar.h>
68 #include <bus/pci/pcidevs.h>
70 #include <dev/netif/mii_layer/mii.h>
71 #include <dev/netif/mii_layer/miivar.h>
73 #include "if_bfereg.h"
75 MODULE_DEPEND(bfe, pci, 1, 1, 1);
76 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
78 /* "controller miibus0" required. See GENERIC if you get errors here. */
79 #include "miibus_if.h"
81 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
83 static struct bfe_type bfe_devs[] = {
84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
85 "Broadcom BCM4401 Fast Ethernet" },
89 static int bfe_probe(device_t);
90 static int bfe_attach(device_t);
91 static int bfe_detach(device_t);
92 static void bfe_release_resources(struct bfe_softc *);
93 static void bfe_intr(void *);
94 static void bfe_start(struct ifnet *);
95 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
96 static void bfe_init(void *);
97 static void bfe_stop(struct bfe_softc *);
98 static void bfe_watchdog(struct ifnet *);
99 static void bfe_shutdown(device_t);
100 static void bfe_tick(void *);
101 static void bfe_txeof(struct bfe_softc *);
102 static void bfe_rxeof(struct bfe_softc *);
103 static void bfe_set_rx_mode(struct bfe_softc *);
104 static int bfe_list_rx_init(struct bfe_softc *);
105 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*);
106 static void bfe_rx_ring_free(struct bfe_softc *);
108 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
109 static int bfe_ifmedia_upd(struct ifnet *);
110 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
111 static int bfe_miibus_readreg(device_t, int, int);
112 static int bfe_miibus_writereg(device_t, int, int, int);
113 static void bfe_miibus_statchg(device_t);
114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
116 static void bfe_get_config(struct bfe_softc *sc);
117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
118 static void bfe_stats_update(struct bfe_softc *);
119 static void bfe_clear_stats (struct bfe_softc *);
120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
122 static int bfe_resetphy(struct bfe_softc *);
123 static int bfe_setupphy(struct bfe_softc *);
124 static void bfe_chip_reset(struct bfe_softc *);
125 static void bfe_chip_halt(struct bfe_softc *);
126 static void bfe_core_reset(struct bfe_softc *);
127 static void bfe_core_disable(struct bfe_softc *);
128 static int bfe_dma_alloc(device_t);
129 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int);
130 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
131 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
133 static device_method_t bfe_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, bfe_probe),
136 DEVMETHOD(device_attach, bfe_attach),
137 DEVMETHOD(device_detach, bfe_detach),
138 DEVMETHOD(device_shutdown, bfe_shutdown),
141 DEVMETHOD(bus_print_child, bus_generic_print_child),
142 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
147 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
152 static driver_t bfe_driver = {
155 sizeof(struct bfe_softc)
158 static devclass_t bfe_devclass;
160 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
164 * Probe for a Broadcom 4401 chip.
167 bfe_probe(device_t dev)
170 struct bfe_softc *sc;
174 sc = device_get_softc(dev);
175 bzero(sc, sizeof(struct bfe_softc));
176 sc->bfe_unit = device_get_unit(dev);
179 while (t->bfe_name != NULL) {
180 if ((pci_get_vendor(dev) == t->bfe_vid) &&
181 (pci_get_device(dev) == t->bfe_did)) {
182 device_set_desc_copy(dev, t->bfe_name);
192 bfe_dma_alloc(device_t dev)
194 struct bfe_softc *sc;
197 sc = device_get_softc(dev);
200 error = bus_dma_tag_create(NULL, /* parent */
201 PAGE_SIZE, 0, /* alignment, boundary */
202 BUS_SPACE_MAXADDR, /* lowaddr */
203 BUS_SPACE_MAXADDR_32BIT, /* highaddr */
204 NULL, NULL, /* filter, filterarg */
205 MAXBSIZE, /* maxsize */
206 BUS_SPACE_UNRESTRICTED, /* num of segments */
207 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
208 BUS_DMA_ALLOCNOW, /* flags */
209 &sc->bfe_parent_tag);
212 device_printf(dev, "could not allocate dma tag\n");
217 /* tag for TX ring */
218 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE,
219 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
220 NULL, NULL, BFE_TX_LIST_SIZE, 1,
221 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag);
224 device_printf(dev, "could not allocate dma tag\n");
228 /* tag for RX ring */
229 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE,
230 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
231 NULL, NULL, BFE_RX_LIST_SIZE, 1,
232 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag);
235 device_printf(dev, "could not allocate dma tag\n");
240 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
241 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
242 1, BUS_SPACE_MAXSIZE_32BIT, 0,
246 device_printf(dev, "could not allocate dma tag\n");
250 /* pre allocate dmamaps for RX list */
251 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
252 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map);
254 device_printf(dev, "cannot create DMA map for RX\n");
259 /* pre allocate dmamaps for TX list */
260 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
261 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map);
263 device_printf(dev, "cannot create DMA map for TX\n");
268 /* Alloc dma for rx ring */
269 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
270 BUS_DMA_WAITOK, &sc->bfe_rx_map);
275 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
276 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
277 sc->bfe_rx_list, sizeof(struct bfe_desc),
278 bfe_dma_map, &sc->bfe_rx_dma, 0);
283 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
285 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
286 BUS_DMA_WAITOK, &sc->bfe_tx_map);
290 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
291 sc->bfe_tx_list, sizeof(struct bfe_desc),
292 bfe_dma_map, &sc->bfe_tx_dma, 0);
296 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
297 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
303 bfe_attach(device_t dev)
306 struct bfe_softc *sc;
307 int unit, error = 0, rid;
309 sc = device_get_softc(dev);
311 unit = device_get_unit(dev);
314 callout_init(&sc->bfe_stat_timer);
317 * Handle power management nonsense.
319 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
320 uint32_t membase, irq;
322 /* Save important PCI config data. */
323 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
324 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
326 /* Reset the power state. */
327 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n",
328 sc->bfe_unit, pci_get_powerstate(dev));
330 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
332 /* Restore PCI config data. */
333 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
334 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
338 * Map control/status registers.
340 pci_enable_busmaster(dev);
343 sc->bfe_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1,
345 if (sc->bfe_res == NULL) {
346 printf ("bfe%d: couldn't map memory\n", unit);
351 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
352 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
354 /* Allocate interrupt */
357 sc->bfe_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
358 RF_SHAREABLE | RF_ACTIVE);
359 if (sc->bfe_irq == NULL) {
360 printf("bfe%d: couldn't map interrupt\n", unit);
365 if (bfe_dma_alloc(dev)) {
366 printf("bfe%d: failed to allocate DMA resources\n", sc->bfe_unit);
367 bfe_release_resources(sc);
372 /* Set up ifnet structure */
373 ifp = &sc->arpcom.ac_if;
375 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
376 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
377 ifp->if_ioctl = bfe_ioctl;
378 ifp->if_start = bfe_start;
379 ifp->if_watchdog = bfe_watchdog;
380 ifp->if_init = bfe_init;
381 ifp->if_mtu = ETHERMTU;
382 ifp->if_baudrate = 10000000;
383 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
384 ifq_set_ready(&ifp->if_snd);
388 /* Reset the chip and turn on the PHY */
391 if (mii_phy_probe(dev, &sc->bfe_miibus,
392 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
393 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit);
398 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
401 * Hook interrupt last to avoid having to lock softc
403 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET,
404 bfe_intr, sc, &sc->bfe_intrhand);
407 bfe_release_resources(sc);
408 printf("bfe%d: couldn't set up irq\n", unit);
413 bfe_release_resources(sc);
418 bfe_detach(device_t dev)
420 struct bfe_softc *sc;
424 sc = device_get_softc(dev);
428 ifp = &sc->arpcom.ac_if;
430 if (device_is_attached(dev)) {
437 bus_generic_detach(dev);
438 if (sc->bfe_miibus != NULL)
439 device_delete_child(dev, sc->bfe_miibus);
441 bfe_release_resources(sc);
448 * Stop all chip I/O so that the kernel's probe routines don't
449 * get confused by errant DMAs when rebooting.
452 bfe_shutdown(device_t dev)
454 struct bfe_softc *sc;
457 sc = device_get_softc(dev);
467 bfe_miibus_readreg(device_t dev, int phy, int reg)
469 struct bfe_softc *sc;
472 sc = device_get_softc(dev);
473 if (phy != sc->bfe_phyaddr)
475 bfe_readphy(sc, reg, &ret);
481 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
483 struct bfe_softc *sc;
485 sc = device_get_softc(dev);
486 if (phy != sc->bfe_phyaddr)
488 bfe_writephy(sc, reg, val);
494 bfe_miibus_statchg(device_t dev)
500 bfe_tx_ring_free(struct bfe_softc *sc)
504 for (i = 0; i < BFE_TX_LIST_CNT; i++)
505 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
506 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
507 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
508 bus_dmamap_unload(sc->bfe_tag,
509 sc->bfe_tx_ring[i].bfe_map);
510 bus_dmamap_destroy(sc->bfe_tag,
511 sc->bfe_tx_ring[i].bfe_map);
513 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
514 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
518 bfe_rx_ring_free(struct bfe_softc *sc)
522 for (i = 0; i < BFE_RX_LIST_CNT; i++)
523 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
524 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
525 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
526 bus_dmamap_unload(sc->bfe_tag,
527 sc->bfe_rx_ring[i].bfe_map);
528 bus_dmamap_destroy(sc->bfe_tag,
529 sc->bfe_rx_ring[i].bfe_map);
531 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
532 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
537 bfe_list_rx_init(struct bfe_softc *sc)
541 for (i = 0; i < BFE_RX_LIST_CNT; i++)
542 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
545 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
546 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
554 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
556 struct bfe_rxheader *rx_header;
561 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
565 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
568 m->m_len = m->m_pkthdr.len = MCLBYTES;
571 m->m_data = m->m_ext.ext_buf;
573 rx_header = mtod(m, struct bfe_rxheader *);
575 rx_header->flags = 0;
577 /* Map the mbuf into DMA */
579 d = &sc->bfe_rx_list[c];
580 r = &sc->bfe_rx_ring[c];
581 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
582 MCLBYTES, bfe_dma_map_desc, d, 0);
583 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
585 ctrl = ETHER_MAX_LEN + 32;
587 if(c == BFE_RX_LIST_CNT - 1)
588 ctrl |= BFE_DESC_EOT;
592 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
597 bfe_get_config(struct bfe_softc *sc)
601 bfe_read_eeprom(sc, eeprom);
603 sc->arpcom.ac_enaddr[0] = eeprom[79];
604 sc->arpcom.ac_enaddr[1] = eeprom[78];
605 sc->arpcom.ac_enaddr[2] = eeprom[81];
606 sc->arpcom.ac_enaddr[3] = eeprom[80];
607 sc->arpcom.ac_enaddr[4] = eeprom[83];
608 sc->arpcom.ac_enaddr[5] = eeprom[82];
610 sc->bfe_phyaddr = eeprom[90] & 0x1f;
611 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
613 sc->bfe_core_unit = 0;
614 sc->bfe_dma_offset = BFE_PCI_DMA;
618 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
620 uint32_t bar_orig, pci_rev, val;
622 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
623 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
624 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
626 val = CSR_READ_4(sc, BFE_SBINTVEC);
628 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
630 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
631 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
632 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
634 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
638 bfe_clear_stats(struct bfe_softc *sc)
645 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
646 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
648 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
655 bfe_resetphy(struct bfe_softc *sc)
661 bfe_writephy(sc, 0, BMCR_RESET);
663 bfe_readphy(sc, 0, &val);
664 if (val & BMCR_RESET) {
665 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit);
674 bfe_chip_halt(struct bfe_softc *sc)
679 /* disable interrupts - not that it actually does..*/
680 CSR_WRITE_4(sc, BFE_IMASK, 0);
681 CSR_READ_4(sc, BFE_IMASK);
683 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
684 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
686 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
687 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
694 bfe_chip_reset(struct bfe_softc *sc)
701 /* Set the interrupt vector for the enet core */
702 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
705 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
706 if (val == BFE_CLOCK) {
707 /* It is, so shut it down */
708 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
709 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
710 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
711 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
712 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
713 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
714 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
715 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
716 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
723 * We want the phy registers to be accessible even when
724 * the driver is "downed" so initialize MDC preamble, frequency,
725 * and whether internal or external phy here.
728 /* 4402 has 62.5Mhz SB clock and internal phy */
729 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
731 /* Internal or external PHY? */
732 val = CSR_READ_4(sc, BFE_DEVCTRL);
733 if (!(val & BFE_IPP))
734 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
735 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
736 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
740 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB);
741 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
745 * We don't want lazy interrupts, so just send them at the end of a
748 BFE_OR(sc, BFE_RCV_LAZY, 0);
750 /* Set max lengths, accounting for VLAN tags */
751 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
752 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
754 /* Set watermark XXX - magic */
755 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
758 * Initialise DMA channels - not forgetting dma addresses need to be
759 * added to BFE_PCI_DMA
761 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
762 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
764 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
766 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
775 bfe_core_disable(struct bfe_softc *sc)
777 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
781 * Set reject, wait for it set, then wait for the core to stop being busy
782 * Then set reset and reject and enable the clocks
784 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
785 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
786 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
787 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
789 CSR_READ_4(sc, BFE_SBTMSLOW);
791 /* Leave reset and reject set */
792 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
797 bfe_core_reset(struct bfe_softc *sc)
801 /* Disable the core */
802 bfe_core_disable(sc);
804 /* and bring it back up */
805 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
806 CSR_READ_4(sc, BFE_SBTMSLOW);
809 /* Chip bug, clear SERR, IB and TO if they are set. */
810 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
811 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
812 val = CSR_READ_4(sc, BFE_SBIMSTATE);
813 if (val & (BFE_IBE | BFE_TO))
814 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
816 /* Clear reset and allow it to move through the core */
817 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
818 CSR_READ_4(sc, BFE_SBTMSLOW);
821 /* Leave the clock set */
822 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
823 CSR_READ_4(sc, BFE_SBTMSLOW);
828 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
832 val = ((uint32_t) data[2]) << 24;
833 val |= ((uint32_t) data[3]) << 16;
834 val |= ((uint32_t) data[4]) << 8;
835 val |= ((uint32_t) data[5]);
836 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
837 val = (BFE_CAM_HI_VALID |
838 (((uint32_t) data[0]) << 8) |
839 (((uint32_t) data[1])));
840 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
841 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
842 (index << BFE_CAM_INDEX_SHIFT)));
843 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
847 bfe_set_rx_mode(struct bfe_softc *sc)
849 struct ifnet *ifp = &sc->arpcom.ac_if;
853 val = CSR_READ_4(sc, BFE_RXCONF);
855 if (ifp->if_flags & IFF_PROMISC)
856 val |= BFE_RXCONF_PROMISC;
858 val &= ~BFE_RXCONF_PROMISC;
860 if (ifp->if_flags & IFF_BROADCAST)
861 val &= ~BFE_RXCONF_DBCAST;
863 val |= BFE_RXCONF_DBCAST;
866 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
867 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
869 CSR_WRITE_4(sc, BFE_RXCONF, val);
870 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
874 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
879 *ptr = segs->ds_addr;
883 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
888 /* The chip needs all addresses to be added to BFE_PCI_DMA */
889 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
893 bfe_release_resources(struct bfe_softc *sc)
900 if (sc->bfe_intrhand != NULL)
901 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
903 if (sc->bfe_irq != NULL)
904 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
906 if (sc->bfe_res != NULL)
907 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res);
909 if (sc->bfe_tx_tag != NULL) {
910 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
911 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, sc->bfe_tx_map);
912 bus_dma_tag_destroy(sc->bfe_tx_tag);
913 sc->bfe_tx_tag = NULL;
916 if (sc->bfe_rx_tag != NULL) {
917 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
918 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, sc->bfe_rx_map);
919 bus_dma_tag_destroy(sc->bfe_rx_tag);
920 sc->bfe_rx_tag = NULL;
923 if (sc->bfe_tag != NULL) {
924 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
925 bus_dmamap_destroy(sc->bfe_tag,
926 sc->bfe_tx_ring[i].bfe_map);
928 bus_dma_tag_destroy(sc->bfe_tag);
932 if (sc->bfe_parent_tag != NULL)
933 bus_dma_tag_destroy(sc->bfe_parent_tag);
937 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
940 uint16_t *ptr = (uint16_t *)data;
942 for (i = 0; i < 128; i += 2)
943 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
947 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
948 u_long timeout, const int clear)
952 for (i = 0; i < timeout; i++) {
953 uint32_t val = CSR_READ_4(sc, reg);
955 if (clear && !(val & bit))
957 if (!clear && (val & bit))
962 printf("bfe%d: BUG! Timeout waiting for bit %08x of register "
963 "%x to %s.\n", sc->bfe_unit, bit, reg,
964 (clear ? "clear" : "set"));
971 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
978 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
979 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
980 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
981 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
982 (reg << BFE_MDIO_RA_SHIFT) |
983 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
984 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
985 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
992 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
998 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
999 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1000 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1001 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1002 (reg << BFE_MDIO_RA_SHIFT) |
1003 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1004 (val & BFE_MDIO_DATA_DATA)));
1005 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1013 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1017 bfe_setupphy(struct bfe_softc *sc)
1024 /* Enable activity LED */
1025 bfe_readphy(sc, 26, &val);
1026 bfe_writephy(sc, 26, val & 0x7fff);
1027 bfe_readphy(sc, 26, &val);
1029 /* Enable traffic meter LED mode */
1030 bfe_readphy(sc, 27, &val);
1031 bfe_writephy(sc, 27, val | (1 << 6));
1038 bfe_stats_update(struct bfe_softc *sc)
1043 val = &sc->bfe_hwstats.tx_good_octets;
1044 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1045 *val++ += CSR_READ_4(sc, reg);
1046 val = &sc->bfe_hwstats.rx_good_octets;
1047 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1048 *val++ += CSR_READ_4(sc, reg);
1052 bfe_txeof(struct bfe_softc *sc)
1056 uint32_t i, chipidx;
1060 ifp = &sc->arpcom.ac_if;
1062 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1063 chipidx /= sizeof(struct bfe_desc);
1065 i = sc->bfe_tx_cons;
1066 /* Go through the mbufs and free those that have been transmitted */
1067 while (i != chipidx) {
1068 struct bfe_data *r = &sc->bfe_tx_ring[i];
1069 if (r->bfe_mbuf != NULL) {
1071 m_freem(r->bfe_mbuf);
1073 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1076 BFE_INC(i, BFE_TX_LIST_CNT);
1079 if (i != sc->bfe_tx_cons) {
1080 /* we freed up some mbufs */
1081 sc->bfe_tx_cons = i;
1082 ifp->if_flags &= ~IFF_OACTIVE;
1084 if (sc->bfe_tx_cnt == 0)
1092 /* Pass a received packet up the stack */
1094 bfe_rxeof(struct bfe_softc *sc)
1098 struct bfe_rxheader *rxheader;
1100 uint32_t cons, status, current, len, flags;
1104 cons = sc->bfe_rx_cons;
1105 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1106 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1108 ifp = &sc->arpcom.ac_if;
1110 while (current != cons) {
1111 r = &sc->bfe_rx_ring[cons];
1113 rxheader = mtod(m, struct bfe_rxheader*);
1114 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE);
1115 len = rxheader->len;
1118 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1119 flags = rxheader->flags;
1121 len -= ETHER_CRC_LEN;
1123 /* flag an error and try again */
1124 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1126 if (flags & BFE_RX_FLAG_SERR)
1127 ifp->if_collisions++;
1128 bfe_list_newbuf(sc, cons, m);
1129 BFE_INC(cons, BFE_RX_LIST_CNT);
1133 /* Go past the rx header */
1134 if (bfe_list_newbuf(sc, cons, NULL) != 0) {
1135 bfe_list_newbuf(sc, cons, m);
1136 BFE_INC(cons, BFE_RX_LIST_CNT);
1141 m_adj(m, BFE_RX_OFFSET);
1142 m->m_len = m->m_pkthdr.len = len;
1145 m->m_pkthdr.rcvif = ifp;
1147 (*ifp->if_input)(ifp, m);
1148 BFE_INC(cons, BFE_RX_LIST_CNT);
1150 sc->bfe_rx_cons = cons;
1157 struct bfe_softc *sc = xsc;
1159 uint32_t istat, imask, flag;
1162 ifp = &sc->arpcom.ac_if;
1166 istat = CSR_READ_4(sc, BFE_ISTAT);
1167 imask = CSR_READ_4(sc, BFE_IMASK);
1170 * Defer unsolicited interrupts - This is necessary because setting the
1171 * chips interrupt mask register to 0 doesn't actually stop the
1175 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1176 CSR_READ_4(sc, BFE_ISTAT);
1178 /* not expecting this interrupt, disregard it */
1184 if (istat & BFE_ISTAT_ERRORS) {
1185 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1186 if (flag & BFE_STAT_EMASK)
1189 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1190 if (flag & BFE_RX_FLAG_ERRORS)
1193 ifp->if_flags &= ~IFF_RUNNING;
1197 /* A packet was received */
1198 if (istat & BFE_ISTAT_RX)
1201 /* A packet was sent */
1202 if (istat & BFE_ISTAT_TX)
1205 /* We have packets pending, fire them out */
1206 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1213 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1215 struct bfe_desc *d = NULL;
1216 struct bfe_data *r = NULL;
1218 uint32_t frag, cur, cnt = 0;
1220 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2)
1224 * Start packing the mbufs in this chain into
1225 * the fragment pointers. Stop when we run out
1226 * of fragments or hit the end of the mbuf chain.
1229 cur = frag = *txidx;
1232 for (m = m_head; m != NULL; m = m->m_next) {
1233 if (m->m_len != 0) {
1234 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2)
1237 d = &sc->bfe_tx_list[cur];
1238 r = &sc->bfe_tx_ring[cur];
1239 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1240 /* always intterupt on completion */
1241 d->bfe_ctrl |= BFE_DESC_IOC;
1243 /* Set start of frame */
1244 d->bfe_ctrl |= BFE_DESC_SOF;
1245 if (cur == BFE_TX_LIST_CNT - 1)
1247 * Tell the chip to wrap to the start of the
1250 d->bfe_ctrl |= BFE_DESC_EOT;
1252 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*),
1253 m->m_len, bfe_dma_map_desc, d, 0);
1254 bus_dmamap_sync(sc->bfe_tag, r->bfe_map,
1255 BUS_DMASYNC_PREREAD);
1258 BFE_INC(cur, BFE_TX_LIST_CNT);
1266 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1267 sc->bfe_tx_ring[frag].bfe_mbuf = m_head;
1268 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
1271 sc->bfe_tx_cnt += cnt;
1276 * Set up to transmit a packet
1279 bfe_start(struct ifnet *ifp)
1281 struct bfe_softc *sc;
1282 struct mbuf *m_head = NULL;
1287 idx = sc->bfe_tx_prod;
1292 * not much point trying to send if the link is down or we have nothing to
1295 if (!sc->bfe_link) {
1300 if (ifp->if_flags & IFF_OACTIVE) {
1305 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1306 m_head = ifq_poll(&ifp->if_snd);
1311 * Pack the data into the tx ring. If we dont have enough room, let
1312 * the chip drain the ring
1314 if (bfe_encap(sc, m_head, &idx)) {
1315 ifp->if_flags |= IFF_OACTIVE;
1318 m_head = ifq_dequeue(&ifp->if_snd);
1321 * If there's a BPF listener, bounce a copy of this frame
1324 BPF_MTAP(ifp, m_head);
1327 sc->bfe_tx_prod = idx;
1328 /* Transmit - twice due to apparent hardware bug */
1329 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1330 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1333 * Set a timeout in case the chip goes out to lunch.
1342 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1343 struct ifnet *ifp = &sc->arpcom.ac_if;
1348 if (ifp->if_flags & IFF_RUNNING) {
1356 if (bfe_list_rx_init(sc) == ENOBUFS) {
1357 printf("bfe%d: bfe_init failed. Not enough memory for list buffers\n",
1363 bfe_set_rx_mode(sc);
1365 /* Enable the chip and core */
1366 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1367 /* Enable interrupts */
1368 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1370 bfe_ifmedia_upd(ifp);
1371 ifp->if_flags |= IFF_RUNNING;
1372 ifp->if_flags &= ~IFF_OACTIVE;
1374 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1379 * Set media options.
1382 bfe_ifmedia_upd(struct ifnet *ifp)
1384 struct bfe_softc *sc;
1385 struct mii_data *mii;
1392 mii = device_get_softc(sc->bfe_miibus);
1394 if (mii->mii_instance) {
1395 struct mii_softc *miisc;
1396 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1397 miisc = LIST_NEXT(miisc, mii_list))
1398 mii_phy_reset(miisc);
1407 * Report current media status.
1410 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1412 struct bfe_softc *sc = ifp->if_softc;
1413 struct mii_data *mii;
1418 mii = device_get_softc(sc->bfe_miibus);
1420 ifmr->ifm_active = mii->mii_media_active;
1421 ifmr->ifm_status = mii->mii_media_status;
1427 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1429 struct bfe_softc *sc = ifp->if_softc;
1430 struct ifreq *ifr = (struct ifreq *) data;
1431 struct mii_data *mii;
1439 if (ifp->if_flags & IFF_UP)
1440 if (ifp->if_flags & IFF_RUNNING)
1441 bfe_set_rx_mode(sc);
1444 else if (ifp->if_flags & IFF_RUNNING)
1449 if (ifp->if_flags & IFF_RUNNING)
1450 bfe_set_rx_mode(sc);
1454 mii = device_get_softc(sc->bfe_miibus);
1455 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1461 error = ether_ioctl(ifp, command, data);
1474 bfe_watchdog(struct ifnet *ifp)
1476 struct bfe_softc *sc;
1483 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit);
1485 ifp->if_flags &= ~IFF_RUNNING;
1496 struct bfe_softc *sc = xsc;
1497 struct mii_data *mii;
1505 mii = device_get_softc(sc->bfe_miibus);
1507 bfe_stats_update(sc);
1508 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1516 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1517 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1527 * Stop the adapter and free any mbufs allocated to the
1531 bfe_stop(struct bfe_softc *sc)
1538 callout_stop(&sc->bfe_stat_timer);
1540 ifp = &sc->arpcom.ac_if;
1543 bfe_tx_ring_free(sc);
1544 bfe_rx_ring_free(sc);
1546 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);