2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.20 2005/02/21 18:40:37 joerg Exp $
37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
38 * available from http://www.sis.com.tw.
40 * This driver also supports the NatSemi DP83815. Datasheets are
41 * available from http://www.national.com.
43 * Written by Bill Paul <wpaul@ee.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
57 * The only downside to this chipset is that RX descriptors must be
61 #include <sys/param.h>
62 #include <sys/systm.h>
63 #include <sys/sockio.h>
65 #include <sys/malloc.h>
66 #include <sys/kernel.h>
67 #include <sys/socket.h>
68 #include <sys/sysctl.h>
71 #include <net/ifq_var.h>
72 #include <net/if_arp.h>
73 #include <net/ethernet.h>
74 #include <net/if_dl.h>
75 #include <net/if_media.h>
76 #include <net/if_types.h>
77 #include <net/vlan/if_vlan_var.h>
81 #include <machine/bus_pio.h>
82 #include <machine/bus_memio.h>
83 #include <machine/bus.h>
84 #include <machine/resource.h>
88 #include <dev/netif/mii_layer/mii.h>
89 #include <dev/netif/mii_layer/miivar.h>
91 #include <bus/pci/pcireg.h>
92 #include <bus/pci/pcivar.h>
94 #define SIS_USEIOSPACE
96 #include "if_sisreg.h"
98 /* "controller miibus0" required. See GENERIC if you get errors here. */
99 #include "miibus_if.h"
102 * Various supported device vendors/types and their names.
104 static struct sis_type sis_devs[] = {
105 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
106 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
107 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
111 static int sis_probe(device_t);
112 static int sis_attach(device_t);
113 static int sis_detach(device_t);
115 static int sis_newbuf(struct sis_softc *, struct sis_desc *,
117 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *);
118 static void sis_rxeof(struct sis_softc *);
119 static void sis_rxeoc(struct sis_softc *);
120 static void sis_txeof(struct sis_softc *);
121 static void sis_intr(void *);
122 static void sis_tick(void *);
123 static void sis_start(struct ifnet *);
124 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
125 static void sis_init(void *);
126 static void sis_stop(struct sis_softc *);
127 static void sis_watchdog(struct ifnet *);
128 static void sis_shutdown(device_t);
129 static int sis_ifmedia_upd(struct ifnet *);
130 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
132 static uint16_t sis_reverse(uint16_t);
133 static void sis_delay(struct sis_softc *);
134 static void sis_eeprom_idle(struct sis_softc *);
135 static void sis_eeprom_putbyte(struct sis_softc *, int);
136 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
137 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
139 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
140 static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
141 static device_t sis_find_bridge(device_t);
144 static void sis_mii_sync(struct sis_softc *);
145 static void sis_mii_send(struct sis_softc *, uint32_t, int);
146 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
147 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
148 static int sis_miibus_readreg(device_t, int, int);
149 static int sis_miibus_writereg(device_t, int, int, int);
150 static void sis_miibus_statchg(device_t);
152 static void sis_setmulti_sis(struct sis_softc *);
153 static void sis_setmulti_ns(struct sis_softc *);
154 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
155 static void sis_reset(struct sis_softc *);
156 static int sis_list_rx_init(struct sis_softc *);
157 static int sis_list_tx_init(struct sis_softc *);
159 static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int);
160 static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int);
161 static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int);
162 #ifdef SIS_USEIOSPACE
163 #define SIS_RES SYS_RES_IOPORT
164 #define SIS_RID SIS_PCI_LOIO
166 #define SIS_RES SYS_RES_MEMORY
167 #define SIS_RID SIS_PCI_LOMEM
170 static device_method_t sis_methods[] = {
171 /* Device interface */
172 DEVMETHOD(device_probe, sis_probe),
173 DEVMETHOD(device_attach, sis_attach),
174 DEVMETHOD(device_detach, sis_detach),
175 DEVMETHOD(device_shutdown, sis_shutdown),
178 DEVMETHOD(bus_print_child, bus_generic_print_child),
179 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
182 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
183 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
184 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
189 static driver_t sis_driver = {
192 sizeof(struct sis_softc)
195 static devclass_t sis_devclass;
197 DECLARE_DUMMY_MODULE(if_sis);
198 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0);
199 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
201 #define SIS_SETBIT(sc, reg, x) \
202 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
204 #define SIS_CLRBIT(sc, reg, x) \
205 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
208 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
211 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
214 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error)
219 r->sis_next = segs->ds_addr;
223 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
228 r->sis_ptr = segs->ds_addr;
232 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error)
241 * Routine to reverse the bits in a word. Stolen almost
242 * verbatim from /usr/games/fortune.
245 sis_reverse(uint16_t n)
247 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
248 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
249 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
250 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
256 sis_delay(struct sis_softc *sc)
260 for (idx = (300 / 33) + 1; idx > 0; idx--)
261 CSR_READ_4(sc, SIS_CSR);
265 sis_eeprom_idle(struct sis_softc *sc)
269 SIO_SET(SIS_EECTL_CSEL);
271 SIO_SET(SIS_EECTL_CLK);
274 for (i = 0; i < 25; i++) {
275 SIO_CLR(SIS_EECTL_CLK);
277 SIO_SET(SIS_EECTL_CLK);
281 SIO_CLR(SIS_EECTL_CLK);
283 SIO_CLR(SIS_EECTL_CSEL);
285 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
289 * Send a read command and address to the EEPROM, check for ACK.
292 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
296 d = addr | SIS_EECMD_READ;
299 * Feed in each bit and stobe the clock.
301 for (i = 0x400; i; i >>= 1) {
303 SIO_SET(SIS_EECTL_DIN);
305 SIO_CLR(SIS_EECTL_DIN);
307 SIO_SET(SIS_EECTL_CLK);
309 SIO_CLR(SIS_EECTL_CLK);
315 * Read a word of data stored in the EEPROM at address 'addr.'
318 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
323 /* Force EEPROM to idle state. */
326 /* Enter EEPROM access mode. */
328 SIO_CLR(SIS_EECTL_CLK);
330 SIO_SET(SIS_EECTL_CSEL);
334 * Send address of word we want to read.
336 sis_eeprom_putbyte(sc, addr);
339 * Start reading bits from EEPROM.
341 for (i = 0x8000; i; i >>= 1) {
342 SIO_SET(SIS_EECTL_CLK);
344 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
347 SIO_CLR(SIS_EECTL_CLK);
351 /* Turn off EEPROM access mode. */
358 * Read a sequence of words from the EEPROM.
361 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
364 uint16_t word = 0, *ptr;
366 for (i = 0; i < cnt; i++) {
367 sis_eeprom_getword(sc, off + i, &word);
368 ptr = (uint16_t *)(dest + (i * 2));
378 sis_find_bridge(device_t dev)
380 devclass_t pci_devclass;
381 device_t *pci_devices;
383 device_t *pci_children;
384 int pci_childcount = 0;
385 device_t *busp, *childp;
386 device_t child = NULL;
389 if ((pci_devclass = devclass_find("pci")) == NULL)
392 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
394 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
396 device_get_children(*busp, &pci_children, &pci_childcount);
397 for (j = 0, childp = pci_children; j < pci_childcount;
399 if (pci_get_vendor(*childp) == SIS_VENDORID &&
400 pci_get_device(*childp) == 0x0008) {
408 free(pci_devices, M_TEMP);
409 free(pci_children, M_TEMP);
414 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
420 bus_space_tag_t btag;
422 bridge = sis_find_bridge(dev);
425 reg = pci_read_config(bridge, 0x48, 1);
426 pci_write_config(bridge, 0x48, reg|0x40, 1);
429 btag = I386_BUS_SPACE_IO;
431 for (i = 0; i < cnt; i++) {
432 bus_space_write_1(btag, 0x0, 0x70, i + off);
433 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
436 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
440 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
442 uint32_t filtsave, csrsave;
444 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
445 csrsave = CSR_READ_4(sc, SIS_CSR);
447 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
448 CSR_WRITE_4(sc, SIS_CSR, 0);
450 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
452 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
453 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
454 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
455 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
456 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
457 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
459 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
460 CSR_WRITE_4(sc, SIS_CSR, csrsave);
465 * Sync the PHYs by setting data bit and strobing the clock 32 times.
468 sis_mii_sync(struct sis_softc *sc)
472 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
474 for (i = 0; i < 32; i++) {
475 SIO_SET(SIS_MII_CLK);
477 SIO_CLR(SIS_MII_CLK);
483 * Clock a series of bits through the MII.
486 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
490 SIO_CLR(SIS_MII_CLK);
492 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
494 SIO_SET(SIS_MII_DATA);
496 SIO_CLR(SIS_MII_DATA);
498 SIO_CLR(SIS_MII_CLK);
500 SIO_SET(SIS_MII_CLK);
505 * Read an PHY register through the MII.
508 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
515 * Set up frame for RX.
517 frame->mii_stdelim = SIS_MII_STARTDELIM;
518 frame->mii_opcode = SIS_MII_READOP;
519 frame->mii_turnaround = 0;
525 SIO_SET(SIS_MII_DIR);
530 * Send command/address info.
532 sis_mii_send(sc, frame->mii_stdelim, 2);
533 sis_mii_send(sc, frame->mii_opcode, 2);
534 sis_mii_send(sc, frame->mii_phyaddr, 5);
535 sis_mii_send(sc, frame->mii_regaddr, 5);
538 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
540 SIO_SET(SIS_MII_CLK);
544 SIO_CLR(SIS_MII_DIR);
547 SIO_CLR(SIS_MII_CLK);
549 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
550 SIO_SET(SIS_MII_CLK);
554 * Now try reading data bits. If the ack failed, we still
555 * need to clock through 16 cycles to keep the PHY(s) in sync.
558 for(i = 0; i < 16; i++) {
559 SIO_CLR(SIS_MII_CLK);
561 SIO_SET(SIS_MII_CLK);
567 for (i = 0x8000; i; i >>= 1) {
568 SIO_CLR(SIS_MII_CLK);
571 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
572 frame->mii_data |= i;
575 SIO_SET(SIS_MII_CLK);
581 SIO_CLR(SIS_MII_CLK);
583 SIO_SET(SIS_MII_CLK);
594 * Write to a PHY register through the MII.
597 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
603 * Set up frame for TX.
606 frame->mii_stdelim = SIS_MII_STARTDELIM;
607 frame->mii_opcode = SIS_MII_WRITEOP;
608 frame->mii_turnaround = SIS_MII_TURNAROUND;
611 * Turn on data output.
613 SIO_SET(SIS_MII_DIR);
617 sis_mii_send(sc, frame->mii_stdelim, 2);
618 sis_mii_send(sc, frame->mii_opcode, 2);
619 sis_mii_send(sc, frame->mii_phyaddr, 5);
620 sis_mii_send(sc, frame->mii_regaddr, 5);
621 sis_mii_send(sc, frame->mii_turnaround, 2);
622 sis_mii_send(sc, frame->mii_data, 16);
625 SIO_SET(SIS_MII_CLK);
627 SIO_CLR(SIS_MII_CLK);
633 SIO_CLR(SIS_MII_DIR);
641 sis_miibus_readreg(device_t dev, int phy, int reg)
643 struct sis_softc *sc;
644 struct sis_mii_frame frame;
646 sc = device_get_softc(dev);
648 if (sc->sis_type == SIS_TYPE_83815) {
652 * The NatSemi chip can take a while after
653 * a reset to come ready, during which the BMSR
654 * returns a value of 0. This is *never* supposed
655 * to happen: some of the BMSR bits are meant to
656 * be hardwired in the on position, and this can
657 * confuse the miibus code a bit during the probe
658 * and attach phase. So we make an effort to check
659 * for this condition and wait for it to clear.
661 if (!CSR_READ_4(sc, NS_BMSR))
663 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
666 * Chipsets < SIS_635 seem not to be able to read/write
667 * through mdio. Use the enhanced PHY access register
670 if (sc->sis_type == SIS_TYPE_900 &&
671 sc->sis_rev < SIS_REV_635) {
677 CSR_WRITE_4(sc, SIS_PHYCTL,
678 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
679 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
681 for (i = 0; i < SIS_TIMEOUT; i++) {
682 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
686 if (i == SIS_TIMEOUT) {
687 device_printf(dev, "PHY failed to come ready\n");
691 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
698 bzero((char *)&frame, sizeof(frame));
700 frame.mii_phyaddr = phy;
701 frame.mii_regaddr = reg;
702 sis_mii_readreg(sc, &frame);
704 return(frame.mii_data);
709 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
711 struct sis_softc *sc;
712 struct sis_mii_frame frame;
714 sc = device_get_softc(dev);
716 if (sc->sis_type == SIS_TYPE_83815) {
719 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
723 if (sc->sis_type == SIS_TYPE_900 &&
724 sc->sis_rev < SIS_REV_635) {
730 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
731 (reg << 6) | SIS_PHYOP_WRITE);
732 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
734 for (i = 0; i < SIS_TIMEOUT; i++) {
735 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
739 if (i == SIS_TIMEOUT)
740 device_printf(dev, "PHY failed to come ready\n");
742 bzero((char *)&frame, sizeof(frame));
744 frame.mii_phyaddr = phy;
745 frame.mii_regaddr = reg;
746 frame.mii_data = data;
747 sis_mii_writereg(sc, &frame);
752 static void sis_miibus_statchg(device_t dev)
754 struct sis_softc *sc;
756 sc = device_get_softc(dev);
761 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
767 /* Compute CRC for the address value. */
768 crc = 0xFFFFFFFF; /* initial value */
770 for (i = 0; i < 6; i++) {
772 for (j = 0; j < 8; j++) {
773 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
777 crc = (crc ^ 0x04c11db6) | carry;
782 * return the filter bit position
784 * The NatSemi chip has a 512-bit filter, which is
785 * different than the SiS, so we special-case it.
787 if (sc->sis_type == SIS_TYPE_83815)
789 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
796 sis_setmulti_ns(struct sis_softc *sc)
799 struct ifmultiaddr *ifma;
800 uint32_t h = 0, i, filtsave;
803 ifp = &sc->arpcom.ac_if;
805 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
806 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
807 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
812 * We have to explicitly enable the multicast hash table
813 * on the NatSemi chip if we want to use it, which we do.
815 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
816 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
818 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
820 /* first, zot all the existing hash bits */
821 for (i = 0; i < 32; i++) {
822 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
823 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
826 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
827 if (ifma->ifma_addr->sa_family != AF_LINK)
830 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
833 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
836 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
839 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
843 sis_setmulti_sis(struct sis_softc *sc)
846 struct ifmultiaddr *ifma;
847 uint32_t h, i, n, ctl;
850 ifp = &sc->arpcom.ac_if;
852 /* hash table size */
853 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
858 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
860 if (ifp->if_flags & IFF_BROADCAST)
861 ctl |= SIS_RXFILTCTL_BROAD;
863 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
864 ctl |= SIS_RXFILTCTL_ALLMULTI;
865 if (ifp->if_flags & IFF_PROMISC)
866 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
867 for (i = 0; i < n; i++)
870 for (i = 0; i < n; i++)
873 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
874 if (ifma->ifma_addr->sa_family != AF_LINK)
877 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
878 hashes[h >> 4] |= 1 << (h & 0xf);
882 ctl |= SIS_RXFILTCTL_ALLMULTI;
883 for (i = 0; i < n; i++)
888 for (i = 0; i < n; i++) {
889 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
890 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
893 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
897 sis_reset(struct sis_softc *sc)
899 struct ifnet *ifp = &sc->arpcom.ac_if;
902 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
904 for (i = 0; i < SIS_TIMEOUT; i++) {
905 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
909 if (i == SIS_TIMEOUT)
910 if_printf(ifp, "reset never completed\n");
912 /* Wait a little while for the chip to get its brains in order. */
916 * If this is a NetSemi chip, make sure to clear
919 if (sc->sis_type == SIS_TYPE_83815) {
920 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
921 CSR_WRITE_4(sc, NS_CLKRUN, 0);
926 * Probe for an SiS chip. Check the PCI vendor and device
927 * IDs against our list and return a device name if we find a match.
930 sis_probe(device_t dev)
936 while(t->sis_name != NULL) {
937 if ((pci_get_vendor(dev) == t->sis_vid) &&
938 (pci_get_device(dev) == t->sis_did)) {
939 device_set_desc(dev, t->sis_name);
949 * Attach the interface. Allocate softc structures, do ifmedia
950 * setup and ethernet/BPF attach.
953 sis_attach(device_t dev)
955 uint8_t eaddr[ETHER_ADDR_LEN];
957 struct sis_softc *sc;
959 int error, rid, waittime;
961 error = waittime = 0;
962 sc = device_get_softc(dev);
963 bzero(sc, sizeof(struct sis_softc));
965 if (pci_get_device(dev) == SIS_DEVICEID_900)
966 sc->sis_type = SIS_TYPE_900;
967 if (pci_get_device(dev) == SIS_DEVICEID_7016)
968 sc->sis_type = SIS_TYPE_7016;
969 if (pci_get_vendor(dev) == NS_VENDORID)
970 sc->sis_type = SIS_TYPE_83815;
972 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
975 * Handle power management nonsense.
978 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
979 if (command == 0x01) {
981 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
982 if (command & SIS_PSTATE_MASK) {
983 uint32_t iobase, membase, irq;
985 /* Save important PCI config data. */
986 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
987 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
988 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
990 /* Reset the power state. */
991 device_printf(dev, "chip is in D%d power mode "
992 "-- setting to D0\n", command & SIS_PSTATE_MASK);
993 command &= 0xFFFFFFFC;
994 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
996 /* Restore PCI config data. */
997 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
998 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
999 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
1004 * Map control/status registers.
1006 command = pci_read_config(dev, PCIR_COMMAND, 4);
1007 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1008 pci_write_config(dev, PCIR_COMMAND, command, 4);
1009 command = pci_read_config(dev, PCIR_COMMAND, 4);
1011 #ifdef SIS_USEIOSPACE
1012 if (!(command & PCIM_CMD_PORTEN)) {
1013 device_printf(dev, "failed to enable I/O ports!\n");
1018 if (!(command & PCIM_CMD_MEMEN)) {
1019 device_printf(dev, "failed to enable memory mapping!\n");
1026 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid,
1027 0, ~0, 1, RF_ACTIVE);
1029 if (sc->sis_res == NULL) {
1030 device_printf(dev, "couldn't map ports/memory\n");
1035 sc->sis_btag = rman_get_bustag(sc->sis_res);
1036 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1038 /* Allocate interrupt */
1040 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1041 RF_SHAREABLE | RF_ACTIVE);
1043 if (sc->sis_irq == NULL) {
1044 device_printf(dev, "couldn't map interrupt\n");
1049 /* Reset the adapter. */
1052 if (sc->sis_type == SIS_TYPE_900 &&
1053 (sc->sis_rev == SIS_REV_635 ||
1054 sc->sis_rev == SIS_REV_900B)) {
1055 SIO_SET(SIS_CFG_RND_CNT);
1056 SIO_SET(SIS_CFG_PERR_DETECT);
1060 * Get station address from the EEPROM.
1062 switch (pci_get_vendor(dev)) {
1065 * Reading the MAC address out of the EEPROM on
1066 * the NatSemi chip takes a bit more work than
1067 * you'd expect. The address spans 4 16-bit words,
1068 * with the first word containing only a single bit.
1069 * You have to shift everything over one bit to
1070 * get it aligned properly. Also, the bits are
1071 * stored backwards (the LSB is really the MSB,
1072 * and so on) so you have to reverse them in order
1073 * to get the MAC address into the form we want.
1074 * Why? Who the hell knows.
1079 sis_read_eeprom(sc, (caddr_t)&tmp,
1080 NS_EE_NODEADDR, 4, 0);
1082 /* Shift everything over one bit. */
1083 tmp[3] = tmp[3] >> 1;
1084 tmp[3] |= tmp[2] << 15;
1085 tmp[2] = tmp[2] >> 1;
1086 tmp[2] |= tmp[1] << 15;
1087 tmp[1] = tmp[1] >> 1;
1088 tmp[1] |= tmp[0] << 15;
1090 /* Now reverse all the bits. */
1091 tmp[3] = sis_reverse(tmp[3]);
1092 tmp[2] = sis_reverse(tmp[2]);
1093 tmp[1] = sis_reverse(tmp[1]);
1095 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1102 * If this is a SiS 630E chipset with an embedded
1103 * SiS 900 controller, we have to read the MAC address
1104 * from the APC CMOS RAM. Our method for doing this
1105 * is very ugly since we have to reach out and grab
1106 * ahold of hardware for which we cannot properly
1107 * allocate resources. This code is only compiled on
1108 * the i386 architecture since the SiS 630E chipset
1109 * is for x86 motherboards only. Note that there are
1110 * a lot of magic numbers in this hack. These are
1111 * taken from SiS's Linux driver. I'd like to replace
1112 * them with proper symbolic definitions, but that
1113 * requires some datasheets that I don't have access
1116 if (sc->sis_rev == SIS_REV_630S ||
1117 sc->sis_rev == SIS_REV_630E ||
1118 sc->sis_rev == SIS_REV_630EA1)
1119 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1121 else if (sc->sis_rev == SIS_REV_635 ||
1122 sc->sis_rev == SIS_REV_630ET)
1123 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1124 else if (sc->sis_rev == SIS_REV_96x) {
1126 * Allow to read EEPROM from LAN. It is shared
1127 * between a 1394 controller and the NIC and each
1128 * time we access it, we need to set SIS_EECMD_REQ.
1130 SIO_SET(SIS_EECMD_REQ);
1131 for (waittime = 0; waittime < SIS_TIMEOUT;
1133 /* Force EEPROM to idle state. */
1134 sis_eeprom_idle(sc);
1135 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1136 sis_read_eeprom(sc, (caddr_t)&eaddr,
1137 SIS_EE_NODEADDR, 3, 0);
1143 * Set SIS_EECTL_CLK to high, so a other master
1144 * can operate on the i2c bus.
1146 SIO_SET(SIS_EECTL_CLK);
1147 /* Refuse EEPROM access by LAN */
1148 SIO_SET(SIS_EECMD_DONE);
1151 sis_read_eeprom(sc, (caddr_t)&eaddr,
1152 SIS_EE_NODEADDR, 3, 0);
1156 callout_init(&sc->sis_timer);
1159 * Allocate the parent bus DMA tag appropriate for PCI.
1161 #define SIS_NSEG_NEW 32
1162 error = bus_dma_tag_create(NULL, /* parent */
1163 1, 0, /* alignment, boundary */
1164 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1165 BUS_SPACE_MAXADDR, /* highaddr */
1166 NULL, NULL, /* filter, filterarg */
1167 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
1168 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1169 BUS_DMA_ALLOCNOW, /* flags */
1170 &sc->sis_parent_tag);
1175 * Now allocate a tag for the DMA descriptor lists and a chunk
1176 * of DMA-able memory based on the tag. Also obtain the physical
1177 * addresses of the RX and TX ring, which we'll need later.
1178 * All of our lists are allocated as a contiguous block of memory.
1180 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1181 1, 0, /* alignment, boundary */
1182 BUS_SPACE_MAXADDR, /* lowaddr */
1183 BUS_SPACE_MAXADDR, /* highaddr */
1184 NULL, NULL, /* filter, filterarg */
1185 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */
1186 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1188 &sc->sis_ldata.sis_rx_tag);
1192 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag,
1193 (void **)&sc->sis_ldata.sis_rx_list,
1194 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1195 &sc->sis_ldata.sis_rx_dmamap);
1198 device_printf(dev, "no memory for rx list buffers!\n");
1199 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1200 sc->sis_ldata.sis_rx_tag = NULL;
1204 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1205 sc->sis_ldata.sis_rx_dmamap,
1206 sc->sis_ldata.sis_rx_list,
1207 sizeof(struct sis_desc), sis_dma_map_ring,
1208 &sc->sis_cdata.sis_rx_paddr, 0);
1211 device_printf(dev, "cannot get address of the rx ring!\n");
1212 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1213 sc->sis_ldata.sis_rx_list,
1214 sc->sis_ldata.sis_rx_dmamap);
1215 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1216 sc->sis_ldata.sis_rx_tag = NULL;
1220 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1221 1, 0, /* alignment, boundary */
1222 BUS_SPACE_MAXADDR, /* lowaddr */
1223 BUS_SPACE_MAXADDR, /* highaddr */
1224 NULL, NULL, /* filter, filterarg */
1225 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */
1226 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1228 &sc->sis_ldata.sis_tx_tag);
1232 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag,
1233 (void **)&sc->sis_ldata.sis_tx_list,
1234 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1235 &sc->sis_ldata.sis_tx_dmamap);
1238 device_printf(dev, "no memory for tx list buffers!\n");
1239 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1240 sc->sis_ldata.sis_tx_tag = NULL;
1244 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1245 sc->sis_ldata.sis_tx_dmamap,
1246 sc->sis_ldata.sis_tx_list,
1247 sizeof(struct sis_desc), sis_dma_map_ring,
1248 &sc->sis_cdata.sis_tx_paddr, 0);
1251 device_printf(dev, "cannot get address of the tx ring!\n");
1252 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1253 sc->sis_ldata.sis_tx_list,
1254 sc->sis_ldata.sis_tx_dmamap);
1255 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1256 sc->sis_ldata.sis_tx_tag = NULL;
1260 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1261 1, 0, /* alignment, boundary */
1262 BUS_SPACE_MAXADDR, /* lowaddr */
1263 BUS_SPACE_MAXADDR, /* highaddr */
1264 NULL, NULL, /* filter, filterarg */
1265 MCLBYTES, 1, /* maxsize, nsegments */
1266 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1272 ifp = &sc->arpcom.ac_if;
1274 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1275 ifp->if_mtu = ETHERMTU;
1276 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1277 ifp->if_ioctl = sis_ioctl;
1278 ifp->if_start = sis_start;
1279 ifp->if_watchdog = sis_watchdog;
1280 ifp->if_init = sis_init;
1281 ifp->if_baudrate = 10000000;
1282 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1283 ifq_set_ready(&ifp->if_snd);
1284 #ifdef DEVICE_POLLING
1285 ifp->if_capabilities |= IFCAP_POLLING;
1287 ifp->if_capenable = ifp->if_capabilities;
1292 if (mii_phy_probe(dev, &sc->sis_miibus,
1293 sis_ifmedia_upd, sis_ifmedia_sts)) {
1294 device_printf(dev, "MII without any PHY!\n");
1300 * Call MI attach routine.
1302 ether_ifattach(ifp, eaddr);
1305 * Tell the upper layer(s) we support long frames.
1307 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1309 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET,
1310 sis_intr, sc, &sc->sis_intrhand);
1313 device_printf(dev, "couldn't set up irq\n");
1314 ether_ifdetach(ifp);
1326 * Shutdown hardware and free up resources. It is called in both the error case
1327 * and the normal detach case so it needs to be careful about only freeing
1328 * resources that have actually been allocated.
1331 sis_detach(device_t dev)
1333 struct sis_softc *sc;
1339 sc = device_get_softc(dev);
1340 ifp = &sc->arpcom.ac_if;
1342 if (device_is_attached(dev)) {
1345 ether_ifdetach(ifp);
1348 device_delete_child(dev, sc->sis_miibus);
1349 bus_generic_detach(dev);
1351 if (sc->sis_intrhand)
1352 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1354 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1356 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1358 if (sc->sis_ldata.sis_rx_tag) {
1359 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag,
1360 sc->sis_ldata.sis_rx_dmamap);
1361 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1362 sc->sis_ldata.sis_rx_list,
1363 sc->sis_ldata.sis_rx_dmamap);
1364 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1367 if (sc->sis_ldata.sis_tx_tag) {
1368 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag,
1369 sc->sis_ldata.sis_tx_dmamap);
1370 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1371 sc->sis_ldata.sis_tx_list,
1372 sc->sis_ldata.sis_tx_dmamap);
1373 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1376 bus_dma_tag_destroy(sc->sis_tag);
1377 if (sc->sis_parent_tag)
1378 bus_dma_tag_destroy(sc->sis_parent_tag);
1386 * Initialize the transmit descriptors.
1389 sis_list_tx_init(struct sis_softc *sc)
1391 struct sis_list_data *ld;
1392 struct sis_ring_data *cd;
1395 cd = &sc->sis_cdata;
1396 ld = &sc->sis_ldata;
1398 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1399 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1400 ld->sis_tx_list[i].sis_nextdesc =
1401 &ld->sis_tx_list[nexti];
1402 bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1403 sc->sis_ldata.sis_tx_dmamap,
1404 &ld->sis_tx_list[nexti],
1405 sizeof(struct sis_desc), sis_dma_map_desc_next,
1406 &ld->sis_tx_list[i], 0);
1407 ld->sis_tx_list[i].sis_mbuf = NULL;
1408 ld->sis_tx_list[i].sis_ptr = 0;
1409 ld->sis_tx_list[i].sis_ctl = 0;
1412 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1414 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap,
1415 BUS_DMASYNC_PREWRITE);
1421 * Initialize the RX descriptors and allocate mbufs for them. Note that
1422 * we arrange the descriptors in a closed ring, so that the last descriptor
1423 * points back to the first.
1426 sis_list_rx_init(struct sis_softc *sc)
1428 struct sis_list_data *ld;
1429 struct sis_ring_data *cd;
1432 ld = &sc->sis_ldata;
1433 cd = &sc->sis_cdata;
1435 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1436 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS)
1438 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1439 ld->sis_rx_list[i].sis_nextdesc =
1440 &ld->sis_rx_list[nexti];
1441 bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1442 sc->sis_ldata.sis_rx_dmamap,
1443 &ld->sis_rx_list[nexti],
1444 sizeof(struct sis_desc), sis_dma_map_desc_next,
1445 &ld->sis_rx_list[i], 0);
1448 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap,
1449 BUS_DMASYNC_PREWRITE);
1451 cd->sis_rx_prod = 0;
1457 * Initialize an RX descriptor and attach an MBUF cluster.
1460 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m)
1463 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1467 m->m_data = m->m_ext.ext_buf;
1471 c->sis_ctl = SIS_RXLEN;
1473 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
1474 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES,
1475 sis_dma_map_desc_ptr, c, 0);
1476 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE);
1482 * A frame has been uploaded: pass the resulting mbuf chain up to
1483 * the higher level protocols.
1486 sis_rxeof(struct sis_softc *sc)
1490 struct sis_desc *cur_rx;
1491 int i, total_len = 0;
1494 ifp = &sc->arpcom.ac_if;
1495 i = sc->sis_cdata.sis_rx_prod;
1497 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
1499 #ifdef DEVICE_POLLING
1500 if (ifp->if_flags & IFF_POLLING) {
1501 if (sc->rxcycles <= 0)
1505 #endif /* DEVICE_POLLING */
1506 cur_rx = &sc->sis_ldata.sis_rx_list[i];
1507 rxstat = cur_rx->sis_rxstat;
1508 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map,
1509 BUS_DMASYNC_POSTWRITE);
1510 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
1511 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
1512 m = cur_rx->sis_mbuf;
1513 cur_rx->sis_mbuf = NULL;
1514 total_len = SIS_RXBYTES(cur_rx);
1515 SIS_INC(i, SIS_RX_LIST_CNT);
1518 * If an error occurs, update stats, clear the
1519 * status word and leave the mbuf cluster in place:
1520 * it should simply get re-used next time this descriptor
1521 * comes up in the ring.
1523 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1525 if (rxstat & SIS_RXSTAT_COLL)
1526 ifp->if_collisions++;
1527 sis_newbuf(sc, cur_rx, m);
1531 /* No errors; receive the packet. */
1534 * On the x86 we do not have alignment problems, so try to
1535 * allocate a new buffer for the receive ring, and pass up
1536 * the one where the packet is already, saving the expensive
1537 * copy done in m_devget().
1538 * If we are on an architecture with alignment problems, or
1539 * if the allocation fails, then use m_devget and leave the
1540 * existing buffer in the receive ring.
1542 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1543 m->m_pkthdr.len = m->m_len = total_len;
1548 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1549 total_len + ETHER_ALIGN, 0, ifp, NULL);
1550 sis_newbuf(sc, cur_rx, m);
1555 m_adj(m0, ETHER_ALIGN);
1560 (*ifp->if_input)(ifp, m);
1563 sc->sis_cdata.sis_rx_prod = i;
1567 sis_rxeoc(struct sis_softc *sc)
1574 * A frame was downloaded to the chip. It's safe for us to clean up
1579 sis_txeof(struct sis_softc *sc)
1581 struct sis_desc *cur_tx;
1585 ifp = &sc->arpcom.ac_if;
1588 * Go through our tx list and free mbufs for those
1589 * frames that have been transmitted.
1591 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1592 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1593 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
1595 if (SIS_OWNDESC(cur_tx))
1598 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1601 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1603 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1604 ifp->if_collisions++;
1605 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1606 ifp->if_collisions++;
1609 ifp->if_collisions +=
1610 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1613 if (cur_tx->sis_mbuf != NULL) {
1614 m_freem(cur_tx->sis_mbuf);
1615 cur_tx->sis_mbuf = NULL;
1616 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
1617 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
1621 if (idx != sc->sis_cdata.sis_tx_cons) {
1622 /* we freed up some buffers */
1623 sc->sis_cdata.sis_tx_cons = idx;
1624 ifp->if_flags &= ~IFF_OACTIVE;
1627 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5;
1633 struct sis_softc *sc;
1634 struct mii_data *mii;
1641 ifp = &sc->arpcom.ac_if;
1643 mii = device_get_softc(sc->sis_miibus);
1646 if (!sc->sis_link) {
1648 if (mii->mii_media_status & IFM_ACTIVE &&
1649 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1651 if (!ifq_is_empty(&ifp->if_snd))
1655 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
1660 #ifdef DEVICE_POLLING
1661 static poll_handler_t sis_poll;
1664 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1666 struct sis_softc *sc = ifp->if_softc;
1668 if ((ifp->if_capenable & IFCAP_POLLING) == 0) {
1669 ether_poll_deregister(ifp);
1670 cmd = POLL_DEREGISTER;
1672 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1673 CSR_WRITE_4(sc, SIS_IER, 1);
1678 * On the sis, reading the status register also clears it.
1679 * So before returning to intr mode we must make sure that all
1680 * possible pending sources of interrupts have been served.
1681 * In practice this means run to completion the *eof routines,
1682 * and then call the interrupt routine
1684 sc->rxcycles = count;
1687 if (!ifq_is_empty(&ifp->if_snd))
1690 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1693 /* Reading the ISR register clears all interrupts. */
1694 status = CSR_READ_4(sc, SIS_ISR);
1696 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1699 if (status & (SIS_ISR_RX_IDLE))
1700 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1702 if (status & SIS_ISR_SYSERR) {
1708 #endif /* DEVICE_POLLING */
1713 struct sis_softc *sc;
1718 ifp = &sc->arpcom.ac_if;
1720 #ifdef DEVICE_POLLING
1721 if (ifp->if_flags & IFF_POLLING)
1723 if ((ifp->if_capenable & IFCAP_POLLING) &&
1724 ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */
1725 CSR_WRITE_4(sc, SIS_IER, 0);
1726 sis_poll(ifp, 0, 1);
1729 #endif /* DEVICE_POLLING */
1731 /* Supress unwanted interrupts */
1732 if (!(ifp->if_flags & IFF_UP)) {
1737 /* Disable interrupts. */
1738 CSR_WRITE_4(sc, SIS_IER, 0);
1741 /* Reading the ISR register clears all interrupts. */
1742 status = CSR_READ_4(sc, SIS_ISR);
1744 if ((status & SIS_INTRS) == 0)
1748 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1753 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
1756 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1759 if (status & (SIS_ISR_RX_IDLE))
1760 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1762 if (status & SIS_ISR_SYSERR) {
1768 /* Re-enable interrupts. */
1769 CSR_WRITE_4(sc, SIS_IER, 1);
1771 if (!ifq_is_empty(&ifp->if_snd))
1776 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1777 * pointers to the fragment pointers.
1780 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1782 struct sis_desc *f = NULL;
1784 int frag, cur, cnt = 0;
1787 * If there's no way we can send any packets, return now.
1789 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2)
1793 * Start packing the mbufs in this chain into
1794 * the fragment pointers. Stop when we run out
1795 * of fragments or hit the end of the mbuf chain.
1798 cur = frag = *txidx;
1800 for (m = m_head; m != NULL; m = m->m_next) {
1801 if (m->m_len != 0) {
1802 if ((SIS_TX_LIST_CNT -
1803 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2)
1805 f = &sc->sis_ldata.sis_tx_list[frag];
1806 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
1807 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
1808 bus_dmamap_load(sc->sis_tag, f->sis_map,
1809 mtod(m, void *), m->m_len,
1810 sis_dma_map_desc_ptr, f, 0);
1811 bus_dmamap_sync(sc->sis_tag, f->sis_map,
1812 BUS_DMASYNC_PREREAD);
1814 f->sis_ctl |= SIS_CMDSTS_OWN;
1816 SIS_INC(frag, SIS_TX_LIST_CNT);
1824 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head;
1825 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1826 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1827 sc->sis_cdata.sis_tx_cnt += cnt;
1834 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1835 * to the mbuf data regions directly in the transmit lists. We also save a
1836 * copy of the pointers since the transmit list fragment pointers are
1837 * physical addresses.
1841 sis_start(struct ifnet *ifp)
1843 struct sis_softc *sc;
1844 struct mbuf *m_head = NULL;
1852 idx = sc->sis_cdata.sis_tx_prod;
1854 if (ifp->if_flags & IFF_OACTIVE)
1857 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) {
1858 m_head = ifq_poll(&ifp->if_snd);
1862 if (sis_encap(sc, m_head, &idx)) {
1863 ifp->if_flags |= IFF_OACTIVE;
1866 m_head = ifq_dequeue(&ifp->if_snd);
1869 * If there's a BPF listener, bounce a copy of this frame
1872 BPF_MTAP(ifp, m_head);
1876 sc->sis_cdata.sis_tx_prod = idx;
1877 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1880 * Set a timeout in case the chip goes out to lunch.
1888 struct sis_softc *sc = xsc;
1889 struct ifnet *ifp = &sc->arpcom.ac_if;
1890 struct mii_data *mii;
1896 * Cancel pending I/O and free all RX/TX buffers.
1900 mii = device_get_softc(sc->sis_miibus);
1902 /* Set MAC address */
1903 if (sc->sis_type == SIS_TYPE_83815) {
1904 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1905 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1906 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1907 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1908 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1909 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1910 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1911 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1912 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1914 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1915 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1916 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1917 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1918 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1919 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1920 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1921 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1922 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1925 /* Init circular RX list. */
1926 if (sis_list_rx_init(sc) == ENOBUFS) {
1927 if_printf(ifp, "initialization failed: "
1928 "no memory for rx buffers\n");
1935 * Init tx descriptors.
1937 sis_list_tx_init(sc);
1940 * For the NatSemi chip, we have to explicitly enable the
1941 * reception of ARP frames, as well as turn on the 'perfect
1942 * match' filter where we store the station address, otherwise
1943 * we won't receive unicasts meant for this host.
1945 if (sc->sis_type == SIS_TYPE_83815) {
1946 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1947 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1950 /* If we want promiscuous mode, set the allframes bit. */
1951 if (ifp->if_flags & IFF_PROMISC)
1952 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1954 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1957 * Set the capture broadcast bit to capture broadcast frames.
1959 if (ifp->if_flags & IFF_BROADCAST)
1960 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1962 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1965 * Load the multicast filter.
1967 if (sc->sis_type == SIS_TYPE_83815)
1968 sis_setmulti_ns(sc);
1970 sis_setmulti_sis(sc);
1972 /* Turn the receive filter on */
1973 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1976 * Load the address of the RX and TX lists.
1978 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr);
1979 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr);
1981 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1982 * the PCI bus. When this bit is set, the Max DMA Burst Size
1983 * for TX/RX DMA should be no larger than 16 double words.
1985 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
1986 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1988 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1990 /* Accept Long Packets for VLAN support */
1991 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1993 /* Set TX configuration */
1994 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
1995 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1997 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1999 /* Set full/half duplex mode. */
2000 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
2001 SIS_SETBIT(sc, SIS_TX_CFG,
2002 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
2003 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
2005 SIS_CLRBIT(sc, SIS_TX_CFG,
2006 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
2007 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
2011 * Enable interrupts.
2013 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2014 #ifdef DEVICE_POLLING
2016 * ... only enable interrupts if we are not polling, make sure
2017 * they are off otherwise.
2019 if (ifp->if_flags & IFF_POLLING)
2020 CSR_WRITE_4(sc, SIS_IER, 0);
2022 #endif /* DEVICE_POLLING */
2023 CSR_WRITE_4(sc, SIS_IER, 1);
2025 /* Enable receiver and transmitter. */
2026 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2027 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2034 * Page 75 of the DP83815 manual recommends the
2035 * following register settings "for optimum
2036 * performance." Note however that at least three
2037 * of the registers are listed as "reserved" in
2038 * the register map, so who knows what they do.
2040 if (sc->sis_type == SIS_TYPE_83815) {
2041 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2042 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2043 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2044 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2045 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2048 ifp->if_flags |= IFF_RUNNING;
2049 ifp->if_flags &= ~IFF_OACTIVE;
2053 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
2057 * Set media options.
2060 sis_ifmedia_upd(struct ifnet *ifp)
2062 struct sis_softc *sc;
2063 struct mii_data *mii;
2067 mii = device_get_softc(sc->sis_miibus);
2069 if (mii->mii_instance) {
2070 struct mii_softc *miisc;
2071 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2072 mii_phy_reset(miisc);
2080 * Report current media status.
2083 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2085 struct sis_softc *sc;
2086 struct mii_data *mii;
2090 mii = device_get_softc(sc->sis_miibus);
2092 ifmr->ifm_active = mii->mii_media_active;
2093 ifmr->ifm_status = mii->mii_media_status;
2097 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2099 struct sis_softc *sc = ifp->if_softc;
2100 struct ifreq *ifr = (struct ifreq *) data;
2101 struct mii_data *mii;
2106 if (ifp->if_flags & IFF_UP) {
2109 if (ifp->if_flags & IFF_RUNNING)
2117 if (sc->sis_type == SIS_TYPE_83815)
2118 sis_setmulti_ns(sc);
2120 sis_setmulti_sis(sc);
2126 mii = device_get_softc(sc->sis_miibus);
2128 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2132 error = ether_ioctl(ifp, command, data);
2140 sis_watchdog(struct ifnet *ifp)
2142 struct sis_softc *sc;
2147 if_printf(ifp, "watchdog timeout\n");
2153 if (!ifq_is_empty(&ifp->if_snd))
2158 * Stop the adapter and free any mbufs allocated to the
2162 sis_stop(struct sis_softc *sc)
2167 ifp = &sc->arpcom.ac_if;
2170 callout_stop(&sc->sis_timer);
2172 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2173 #ifdef DEVICE_POLLING
2174 ether_poll_deregister(ifp);
2176 CSR_WRITE_4(sc, SIS_IER, 0);
2177 CSR_WRITE_4(sc, SIS_IMR, 0);
2178 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2180 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2181 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2186 * Free data in the RX lists.
2188 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2189 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) {
2190 bus_dmamap_unload(sc->sis_tag,
2191 sc->sis_ldata.sis_rx_list[i].sis_map);
2192 bus_dmamap_destroy(sc->sis_tag,
2193 sc->sis_ldata.sis_rx_list[i].sis_map);
2194 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf);
2195 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL;
2198 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list));
2201 * Free the TX list buffers.
2203 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2204 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) {
2205 bus_dmamap_unload(sc->sis_tag,
2206 sc->sis_ldata.sis_tx_list[i].sis_map);
2207 bus_dmamap_destroy(sc->sis_tag,
2208 sc->sis_ldata.sis_tx_list[i].sis_map);
2209 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf);
2210 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL;
2214 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list));
2218 * Stop all chip I/O so that the kernel's probe routines don't
2219 * get confused by errant DMAs when rebooting.
2222 sis_shutdown(device_t dev)
2224 struct sis_softc *sc;
2226 sc = device_get_softc(dev);