2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/delay.h>
31 #include <linux/hdmi.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
41 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
45 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
47 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
48 struct drm_i915_private *dev_priv = dev->dev_private;
49 uint32_t enabled_bits;
51 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
53 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
54 "HDMI port enabled, expecting disabled\n");
57 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
59 struct intel_digital_port *intel_dig_port =
60 container_of(encoder, struct intel_digital_port, base.base);
61 return &intel_dig_port->hdmi;
64 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
66 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
69 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
72 case HDMI_INFOFRAME_TYPE_AVI:
73 return VIDEO_DIP_SELECT_AVI;
74 case HDMI_INFOFRAME_TYPE_SPD:
75 return VIDEO_DIP_SELECT_SPD;
76 case HDMI_INFOFRAME_TYPE_VENDOR:
77 return VIDEO_DIP_SELECT_VENDOR;
79 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
84 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
87 case HDMI_INFOFRAME_TYPE_AVI:
88 return VIDEO_DIP_ENABLE_AVI;
89 case HDMI_INFOFRAME_TYPE_SPD:
90 return VIDEO_DIP_ENABLE_SPD;
91 case HDMI_INFOFRAME_TYPE_VENDOR:
92 return VIDEO_DIP_ENABLE_VENDOR;
94 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
99 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
102 case HDMI_INFOFRAME_TYPE_AVI:
103 return VIDEO_DIP_ENABLE_AVI_HSW;
104 case HDMI_INFOFRAME_TYPE_SPD:
105 return VIDEO_DIP_ENABLE_SPD_HSW;
106 case HDMI_INFOFRAME_TYPE_VENDOR:
107 return VIDEO_DIP_ENABLE_VS_HSW;
109 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
114 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
115 enum transcoder cpu_transcoder,
116 struct drm_i915_private *dev_priv)
119 case HDMI_INFOFRAME_TYPE_AVI:
120 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
121 case HDMI_INFOFRAME_TYPE_SPD:
122 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
123 case HDMI_INFOFRAME_TYPE_VENDOR:
124 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
126 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
131 static void g4x_write_infoframe(struct drm_encoder *encoder,
132 enum hdmi_infoframe_type type,
133 const void *frame, ssize_t len)
135 const uint32_t *data = frame;
136 struct drm_device *dev = encoder->dev;
137 struct drm_i915_private *dev_priv = dev->dev_private;
138 u32 val = I915_READ(VIDEO_DIP_CTL);
141 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
143 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
144 val |= g4x_infoframe_index(type);
146 val &= ~g4x_infoframe_enable(type);
148 I915_WRITE(VIDEO_DIP_CTL, val);
151 for (i = 0; i < len; i += 4) {
152 I915_WRITE(VIDEO_DIP_DATA, *data);
155 /* Write every possible data byte to force correct ECC calculation. */
156 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
157 I915_WRITE(VIDEO_DIP_DATA, 0);
160 val |= g4x_infoframe_enable(type);
161 val &= ~VIDEO_DIP_FREQ_MASK;
162 val |= VIDEO_DIP_FREQ_VSYNC;
164 I915_WRITE(VIDEO_DIP_CTL, val);
165 POSTING_READ(VIDEO_DIP_CTL);
168 static void ibx_write_infoframe(struct drm_encoder *encoder,
169 enum hdmi_infoframe_type type,
170 const void *frame, ssize_t len)
172 const uint32_t *data = frame;
173 struct drm_device *dev = encoder->dev;
174 struct drm_i915_private *dev_priv = dev->dev_private;
175 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
176 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
177 u32 val = I915_READ(reg);
179 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
181 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
182 val |= g4x_infoframe_index(type);
184 val &= ~g4x_infoframe_enable(type);
186 I915_WRITE(reg, val);
189 for (i = 0; i < len; i += 4) {
190 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
193 /* Write every possible data byte to force correct ECC calculation. */
194 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
195 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
198 val |= g4x_infoframe_enable(type);
199 val &= ~VIDEO_DIP_FREQ_MASK;
200 val |= VIDEO_DIP_FREQ_VSYNC;
202 I915_WRITE(reg, val);
206 static void cpt_write_infoframe(struct drm_encoder *encoder,
207 enum hdmi_infoframe_type type,
208 const void *frame, ssize_t len)
210 const uint32_t *data = frame;
211 struct drm_device *dev = encoder->dev;
212 struct drm_i915_private *dev_priv = dev->dev_private;
213 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
214 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
215 u32 val = I915_READ(reg);
217 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
219 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
220 val |= g4x_infoframe_index(type);
222 /* The DIP control register spec says that we need to update the AVI
223 * infoframe without clearing its enable bit */
224 if (type != HDMI_INFOFRAME_TYPE_AVI)
225 val &= ~g4x_infoframe_enable(type);
227 I915_WRITE(reg, val);
230 for (i = 0; i < len; i += 4) {
231 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
234 /* Write every possible data byte to force correct ECC calculation. */
235 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
236 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
239 val |= g4x_infoframe_enable(type);
240 val &= ~VIDEO_DIP_FREQ_MASK;
241 val |= VIDEO_DIP_FREQ_VSYNC;
243 I915_WRITE(reg, val);
247 static void vlv_write_infoframe(struct drm_encoder *encoder,
248 enum hdmi_infoframe_type type,
249 const void *frame, ssize_t len)
251 const uint32_t *data = frame;
252 struct drm_device *dev = encoder->dev;
253 struct drm_i915_private *dev_priv = dev->dev_private;
254 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
255 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
256 u32 val = I915_READ(reg);
258 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
260 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
261 val |= g4x_infoframe_index(type);
263 val &= ~g4x_infoframe_enable(type);
265 I915_WRITE(reg, val);
268 for (i = 0; i < len; i += 4) {
269 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
272 /* Write every possible data byte to force correct ECC calculation. */
273 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
274 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
277 val |= g4x_infoframe_enable(type);
278 val &= ~VIDEO_DIP_FREQ_MASK;
279 val |= VIDEO_DIP_FREQ_VSYNC;
281 I915_WRITE(reg, val);
285 static void hsw_write_infoframe(struct drm_encoder *encoder,
286 enum hdmi_infoframe_type type,
287 const void *frame, ssize_t len)
289 const uint32_t *data = frame;
290 struct drm_device *dev = encoder->dev;
291 struct drm_i915_private *dev_priv = dev->dev_private;
292 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
293 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
296 u32 val = I915_READ(ctl_reg);
298 data_reg = hsw_infoframe_data_reg(type,
299 intel_crtc->config.cpu_transcoder,
304 val &= ~hsw_infoframe_enable(type);
305 I915_WRITE(ctl_reg, val);
308 for (i = 0; i < len; i += 4) {
309 I915_WRITE(data_reg + i, *data);
312 /* Write every possible data byte to force correct ECC calculation. */
313 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
314 I915_WRITE(data_reg + i, 0);
317 val |= hsw_infoframe_enable(type);
318 I915_WRITE(ctl_reg, val);
319 POSTING_READ(ctl_reg);
323 * The data we write to the DIP data buffer registers is 1 byte bigger than the
324 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
325 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
326 * used for both technologies.
328 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
329 * DW1: DB3 | DB2 | DB1 | DB0
330 * DW2: DB7 | DB6 | DB5 | DB4
333 * (HB is Header Byte, DB is Data Byte)
335 * The hdmi pack() functions don't know about that hardware specific hole so we
336 * trick them by giving an offset into the buffer and moving back the header
339 static void intel_write_infoframe(struct drm_encoder *encoder,
340 union hdmi_infoframe *frame)
342 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
343 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
346 /* see comment above for the reason for this offset */
347 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
351 /* Insert the 'hole' (see big comment above) at position 3 */
352 buffer[0] = buffer[1];
353 buffer[1] = buffer[2];
354 buffer[2] = buffer[3];
358 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
361 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
362 struct drm_display_mode *adjusted_mode)
364 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
365 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
366 union hdmi_infoframe frame;
369 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
372 DRM_ERROR("couldn't fill AVI infoframe\n");
376 if (intel_hdmi->rgb_quant_range_selectable) {
377 if (intel_crtc->config.limited_color_range)
378 frame.avi.quantization_range =
379 HDMI_QUANTIZATION_RANGE_LIMITED;
381 frame.avi.quantization_range =
382 HDMI_QUANTIZATION_RANGE_FULL;
385 intel_write_infoframe(encoder, &frame);
388 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
390 union hdmi_infoframe frame;
393 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
395 DRM_ERROR("couldn't fill SPD infoframe\n");
399 frame.spd.sdi = HDMI_SPD_SDI_PC;
401 intel_write_infoframe(encoder, &frame);
405 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
406 struct drm_display_mode *adjusted_mode)
408 union hdmi_infoframe frame;
411 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
416 intel_write_infoframe(encoder, &frame);
419 static void g4x_set_infoframes(struct drm_encoder *encoder,
421 struct drm_display_mode *adjusted_mode)
423 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
424 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
425 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
426 u32 reg = VIDEO_DIP_CTL;
427 u32 val = I915_READ(reg);
428 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
430 assert_hdmi_port_disabled(intel_hdmi);
432 /* If the registers were not initialized yet, they might be zeroes,
433 * which means we're selecting the AVI DIP and we're setting its
434 * frequency to once. This seems to really confuse the HW and make
435 * things stop working (the register spec says the AVI always needs to
436 * be sent every VSync). So here we avoid writing to the register more
437 * than we need and also explicitly select the AVI DIP and explicitly
438 * set its frequency to every VSync. Avoiding to write it twice seems to
439 * be enough to solve the problem, but being defensive shouldn't hurt us
441 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
444 if (!(val & VIDEO_DIP_ENABLE))
446 val &= ~VIDEO_DIP_ENABLE;
447 I915_WRITE(reg, val);
452 if (port != (val & VIDEO_DIP_PORT_MASK)) {
453 if (val & VIDEO_DIP_ENABLE) {
454 val &= ~VIDEO_DIP_ENABLE;
455 I915_WRITE(reg, val);
458 val &= ~VIDEO_DIP_PORT_MASK;
462 val |= VIDEO_DIP_ENABLE;
463 val &= ~VIDEO_DIP_ENABLE_VENDOR;
465 I915_WRITE(reg, val);
468 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
469 intel_hdmi_set_spd_infoframe(encoder);
470 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
473 static void ibx_set_infoframes(struct drm_encoder *encoder,
475 struct drm_display_mode *adjusted_mode)
477 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
478 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
479 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
480 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
481 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
482 u32 val = I915_READ(reg);
483 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
485 assert_hdmi_port_disabled(intel_hdmi);
487 /* See the big comment in g4x_set_infoframes() */
488 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
491 if (!(val & VIDEO_DIP_ENABLE))
493 val &= ~VIDEO_DIP_ENABLE;
494 I915_WRITE(reg, val);
499 if (port != (val & VIDEO_DIP_PORT_MASK)) {
500 if (val & VIDEO_DIP_ENABLE) {
501 val &= ~VIDEO_DIP_ENABLE;
502 I915_WRITE(reg, val);
505 val &= ~VIDEO_DIP_PORT_MASK;
509 val |= VIDEO_DIP_ENABLE;
510 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
511 VIDEO_DIP_ENABLE_GCP);
513 I915_WRITE(reg, val);
516 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
517 intel_hdmi_set_spd_infoframe(encoder);
518 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
521 static void cpt_set_infoframes(struct drm_encoder *encoder,
523 struct drm_display_mode *adjusted_mode)
525 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
526 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
527 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
528 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
529 u32 val = I915_READ(reg);
531 assert_hdmi_port_disabled(intel_hdmi);
533 /* See the big comment in g4x_set_infoframes() */
534 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
537 if (!(val & VIDEO_DIP_ENABLE))
539 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
540 I915_WRITE(reg, val);
545 /* Set both together, unset both together: see the spec. */
546 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
547 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
548 VIDEO_DIP_ENABLE_GCP);
550 I915_WRITE(reg, val);
553 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
554 intel_hdmi_set_spd_infoframe(encoder);
555 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
558 static void vlv_set_infoframes(struct drm_encoder *encoder,
560 struct drm_display_mode *adjusted_mode)
562 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
563 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
564 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
565 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
566 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
567 u32 val = I915_READ(reg);
568 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
570 assert_hdmi_port_disabled(intel_hdmi);
572 /* See the big comment in g4x_set_infoframes() */
573 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
576 if (!(val & VIDEO_DIP_ENABLE))
578 val &= ~VIDEO_DIP_ENABLE;
579 I915_WRITE(reg, val);
584 if (port != (val & VIDEO_DIP_PORT_MASK)) {
585 if (val & VIDEO_DIP_ENABLE) {
586 val &= ~VIDEO_DIP_ENABLE;
587 I915_WRITE(reg, val);
590 val &= ~VIDEO_DIP_PORT_MASK;
594 val |= VIDEO_DIP_ENABLE;
595 val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
596 VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
598 I915_WRITE(reg, val);
601 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
602 intel_hdmi_set_spd_infoframe(encoder);
603 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
606 static void hsw_set_infoframes(struct drm_encoder *encoder,
608 struct drm_display_mode *adjusted_mode)
610 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
611 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
612 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
613 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
614 u32 val = I915_READ(reg);
616 assert_hdmi_port_disabled(intel_hdmi);
624 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
625 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
627 I915_WRITE(reg, val);
630 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
631 intel_hdmi_set_spd_infoframe(encoder);
632 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
635 static void intel_hdmi_prepare(struct intel_encoder *encoder)
637 struct drm_device *dev = encoder->base.dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
640 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
641 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
644 hdmi_val = SDVO_ENCODING_HDMI;
645 if (!HAS_PCH_SPLIT(dev))
646 hdmi_val |= intel_hdmi->color_range;
647 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
648 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
649 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
650 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
652 if (crtc->config.pipe_bpp > 24)
653 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
655 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
657 if (crtc->config.has_hdmi_sink)
658 hdmi_val |= HDMI_MODE_SELECT_HDMI;
660 if (crtc->config.has_audio) {
661 WARN_ON(!crtc->config.has_hdmi_sink);
662 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
663 pipe_name(crtc->pipe));
664 hdmi_val |= SDVO_AUDIO_ENABLE;
665 intel_write_eld(&encoder->base, adjusted_mode);
668 if (HAS_PCH_CPT(dev))
669 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
670 else if (IS_CHERRYVIEW(dev))
671 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
673 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
675 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
676 POSTING_READ(intel_hdmi->hdmi_reg);
679 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
680 enum i915_pipe *pipe)
682 struct drm_device *dev = encoder->base.dev;
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
685 enum intel_display_power_domain power_domain;
688 power_domain = intel_display_port_power_domain(encoder);
689 if (!intel_display_power_enabled(dev_priv, power_domain))
692 tmp = I915_READ(intel_hdmi->hdmi_reg);
694 if (!(tmp & SDVO_ENABLE))
697 if (HAS_PCH_CPT(dev))
698 *pipe = PORT_TO_PIPE_CPT(tmp);
699 else if (IS_CHERRYVIEW(dev))
700 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
702 *pipe = PORT_TO_PIPE(tmp);
707 static void intel_hdmi_get_config(struct intel_encoder *encoder,
708 struct intel_crtc_config *pipe_config)
710 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
711 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
715 tmp = I915_READ(intel_hdmi->hdmi_reg);
717 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
718 flags |= DRM_MODE_FLAG_PHSYNC;
720 flags |= DRM_MODE_FLAG_NHSYNC;
722 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
723 flags |= DRM_MODE_FLAG_PVSYNC;
725 flags |= DRM_MODE_FLAG_NVSYNC;
727 if (tmp & HDMI_MODE_SELECT_HDMI)
728 pipe_config->has_hdmi_sink = true;
730 if (tmp & HDMI_MODE_SELECT_HDMI)
731 pipe_config->has_audio = true;
733 pipe_config->adjusted_mode.flags |= flags;
735 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
736 dotclock = pipe_config->port_clock * 2 / 3;
738 dotclock = pipe_config->port_clock;
740 if (HAS_PCH_SPLIT(dev_priv->dev))
741 ironlake_check_encoder_dotclock(pipe_config, dotclock);
743 pipe_config->adjusted_mode.crtc_clock = dotclock;
746 static void intel_enable_hdmi(struct intel_encoder *encoder)
748 struct drm_device *dev = encoder->base.dev;
749 struct drm_i915_private *dev_priv = dev->dev_private;
750 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
751 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
753 u32 enable_bits = SDVO_ENABLE;
755 if (intel_crtc->config.has_audio)
756 enable_bits |= SDVO_AUDIO_ENABLE;
758 temp = I915_READ(intel_hdmi->hdmi_reg);
760 /* HW workaround for IBX, we need to move the port to transcoder A
761 * before disabling it, so restore the transcoder select bit here. */
762 if (HAS_PCH_IBX(dev))
763 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
765 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
766 * we do this anyway which shows more stable in testing.
768 if (HAS_PCH_SPLIT(dev)) {
769 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
770 POSTING_READ(intel_hdmi->hdmi_reg);
775 I915_WRITE(intel_hdmi->hdmi_reg, temp);
776 POSTING_READ(intel_hdmi->hdmi_reg);
778 /* HW workaround, need to write this twice for issue that may result
779 * in first write getting masked.
781 if (HAS_PCH_SPLIT(dev)) {
782 I915_WRITE(intel_hdmi->hdmi_reg, temp);
783 POSTING_READ(intel_hdmi->hdmi_reg);
787 static void vlv_enable_hdmi(struct intel_encoder *encoder)
791 static void intel_disable_hdmi(struct intel_encoder *encoder)
793 struct drm_device *dev = encoder->base.dev;
794 struct drm_i915_private *dev_priv = dev->dev_private;
795 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
797 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
799 temp = I915_READ(intel_hdmi->hdmi_reg);
801 /* HW workaround for IBX, we need to move the port to transcoder A
802 * before disabling it. */
803 if (HAS_PCH_IBX(dev)) {
804 struct drm_crtc *crtc = encoder->base.crtc;
805 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
807 if (temp & SDVO_PIPE_B_SELECT) {
808 temp &= ~SDVO_PIPE_B_SELECT;
809 I915_WRITE(intel_hdmi->hdmi_reg, temp);
810 POSTING_READ(intel_hdmi->hdmi_reg);
812 /* Again we need to write this twice. */
813 I915_WRITE(intel_hdmi->hdmi_reg, temp);
814 POSTING_READ(intel_hdmi->hdmi_reg);
816 /* Transcoder selection bits only update
817 * effectively on vblank. */
819 intel_wait_for_vblank(dev, pipe);
825 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
826 * we do this anyway which shows more stable in testing.
828 if (HAS_PCH_SPLIT(dev)) {
829 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
830 POSTING_READ(intel_hdmi->hdmi_reg);
833 temp &= ~enable_bits;
835 I915_WRITE(intel_hdmi->hdmi_reg, temp);
836 POSTING_READ(intel_hdmi->hdmi_reg);
838 /* HW workaround, need to write this twice for issue that may result
839 * in first write getting masked.
841 if (HAS_PCH_SPLIT(dev)) {
842 I915_WRITE(intel_hdmi->hdmi_reg, temp);
843 POSTING_READ(intel_hdmi->hdmi_reg);
847 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
849 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
851 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
853 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
859 static enum drm_mode_status
860 intel_hdmi_mode_valid(struct drm_connector *connector,
861 struct drm_display_mode *mode)
863 if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
865 return MODE_CLOCK_HIGH;
866 if (mode->clock < 20000)
867 return MODE_CLOCK_LOW;
869 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
870 return MODE_NO_DBLESCAN;
875 static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
877 struct drm_device *dev = crtc->base.dev;
878 struct intel_encoder *encoder;
879 int count = 0, count_hdmi = 0;
881 if (!HAS_PCH_SPLIT(dev))
884 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
885 if (encoder->new_crtc != crtc)
888 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
893 * HDMI 12bpc affects the clocks, so it's only possible
894 * when not cloning with other encoder types.
896 return count_hdmi > 0 && count_hdmi == count;
899 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
900 struct intel_crtc_config *pipe_config)
902 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
903 struct drm_device *dev = encoder->base.dev;
904 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
905 int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
906 int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
909 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
911 if (intel_hdmi->color_range_auto) {
912 /* See CEA-861-E - 5.1 Default Encoding Parameters */
913 if (pipe_config->has_hdmi_sink &&
914 drm_match_cea_mode(adjusted_mode) > 1)
915 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
917 intel_hdmi->color_range = 0;
920 if (intel_hdmi->color_range)
921 pipe_config->limited_color_range = true;
923 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
924 pipe_config->has_pch_encoder = true;
926 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
927 pipe_config->has_audio = true;
930 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
931 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
932 * outputs. We also need to check that the higher clock still fits
935 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
936 clock_12bpc <= portclock_limit &&
937 hdmi_12bpc_possible(encoder->new_crtc)) {
938 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
941 /* Need to adjust the port link by 1.5x for 12bpc. */
942 pipe_config->port_clock = clock_12bpc;
944 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
948 if (!pipe_config->bw_constrained) {
949 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
950 pipe_config->pipe_bpp = desired_bpp;
953 if (adjusted_mode->crtc_clock > portclock_limit) {
954 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
961 static enum drm_connector_status
962 intel_hdmi_detect(struct drm_connector *connector, bool force)
964 struct drm_device *dev = connector->dev;
965 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
966 struct intel_digital_port *intel_dig_port =
967 hdmi_to_dig_port(intel_hdmi);
968 struct intel_encoder *intel_encoder = &intel_dig_port->base;
969 struct drm_i915_private *dev_priv = dev->dev_private;
971 enum intel_display_power_domain power_domain;
972 enum drm_connector_status status = connector_status_disconnected;
974 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
975 connector->base.id, connector->name);
977 power_domain = intel_display_port_power_domain(intel_encoder);
978 intel_display_power_get(dev_priv, power_domain);
980 intel_hdmi->has_hdmi_sink = false;
981 intel_hdmi->has_audio = false;
982 intel_hdmi->rgb_quant_range_selectable = false;
983 edid = drm_get_edid(connector,
984 intel_gmbus_get_adapter(dev_priv,
985 intel_hdmi->ddc_bus));
988 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
989 status = connector_status_connected;
990 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
991 intel_hdmi->has_hdmi_sink =
992 drm_detect_hdmi_monitor(edid);
993 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
994 intel_hdmi->rgb_quant_range_selectable =
995 drm_rgb_quant_range_selectable(edid);
1000 if (status == connector_status_connected) {
1001 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1002 intel_hdmi->has_audio =
1003 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
1004 intel_encoder->type = INTEL_OUTPUT_HDMI;
1007 intel_display_power_put(dev_priv, power_domain);
1012 static int intel_hdmi_get_modes(struct drm_connector *connector)
1014 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
1015 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1016 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1017 enum intel_display_power_domain power_domain;
1020 /* We should parse the EDID data and find out if it's an HDMI sink so
1021 * we can send audio to it.
1024 power_domain = intel_display_port_power_domain(intel_encoder);
1025 intel_display_power_get(dev_priv, power_domain);
1027 ret = intel_ddc_get_modes(connector,
1028 intel_gmbus_get_adapter(dev_priv,
1029 intel_hdmi->ddc_bus));
1031 intel_display_power_put(dev_priv, power_domain);
1037 intel_hdmi_detect_audio(struct drm_connector *connector)
1039 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
1040 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1041 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1042 enum intel_display_power_domain power_domain;
1044 bool has_audio = false;
1046 power_domain = intel_display_port_power_domain(intel_encoder);
1047 intel_display_power_get(dev_priv, power_domain);
1049 edid = drm_get_edid(connector,
1050 intel_gmbus_get_adapter(dev_priv,
1051 intel_hdmi->ddc_bus));
1053 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1054 has_audio = drm_detect_monitor_audio(edid);
1058 intel_display_power_put(dev_priv, power_domain);
1064 intel_hdmi_set_property(struct drm_connector *connector,
1065 struct drm_property *property,
1068 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1069 struct intel_digital_port *intel_dig_port =
1070 hdmi_to_dig_port(intel_hdmi);
1071 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1074 ret = drm_object_property_set_value(&connector->base, property, val);
1078 if (property == dev_priv->force_audio_property) {
1079 enum hdmi_force_audio i = val;
1082 if (i == intel_hdmi->force_audio)
1085 intel_hdmi->force_audio = i;
1087 if (i == HDMI_AUDIO_AUTO)
1088 has_audio = intel_hdmi_detect_audio(connector);
1090 has_audio = (i == HDMI_AUDIO_ON);
1092 if (i == HDMI_AUDIO_OFF_DVI)
1093 intel_hdmi->has_hdmi_sink = 0;
1095 intel_hdmi->has_audio = has_audio;
1099 if (property == dev_priv->broadcast_rgb_property) {
1100 bool old_auto = intel_hdmi->color_range_auto;
1101 uint32_t old_range = intel_hdmi->color_range;
1104 case INTEL_BROADCAST_RGB_AUTO:
1105 intel_hdmi->color_range_auto = true;
1107 case INTEL_BROADCAST_RGB_FULL:
1108 intel_hdmi->color_range_auto = false;
1109 intel_hdmi->color_range = 0;
1111 case INTEL_BROADCAST_RGB_LIMITED:
1112 intel_hdmi->color_range_auto = false;
1113 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1119 if (old_auto == intel_hdmi->color_range_auto &&
1120 old_range == intel_hdmi->color_range)
1129 if (intel_dig_port->base.base.crtc)
1130 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1135 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1137 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1138 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1139 struct drm_display_mode *adjusted_mode =
1140 &intel_crtc->config.adjusted_mode;
1142 intel_hdmi_prepare(encoder);
1144 intel_hdmi->set_infoframes(&encoder->base,
1145 intel_crtc->config.has_hdmi_sink,
1149 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1151 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1152 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1153 struct drm_device *dev = encoder->base.dev;
1154 struct drm_i915_private *dev_priv = dev->dev_private;
1155 struct intel_crtc *intel_crtc =
1156 to_intel_crtc(encoder->base.crtc);
1157 struct drm_display_mode *adjusted_mode =
1158 &intel_crtc->config.adjusted_mode;
1159 enum dpio_channel port = vlv_dport_to_channel(dport);
1160 int pipe = intel_crtc->pipe;
1163 /* Enable clock channels for this port */
1164 mutex_lock(&dev_priv->dpio_lock);
1165 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1172 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1175 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1176 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1177 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1178 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1179 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1180 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1181 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1182 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1184 /* Program lane clock */
1185 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1186 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1187 mutex_unlock(&dev_priv->dpio_lock);
1189 intel_hdmi->set_infoframes(&encoder->base,
1190 intel_crtc->config.has_hdmi_sink,
1193 intel_enable_hdmi(encoder);
1195 vlv_wait_port_ready(dev_priv, dport);
1198 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1200 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1201 struct drm_device *dev = encoder->base.dev;
1202 struct drm_i915_private *dev_priv = dev->dev_private;
1203 struct intel_crtc *intel_crtc =
1204 to_intel_crtc(encoder->base.crtc);
1205 enum dpio_channel port = vlv_dport_to_channel(dport);
1206 int pipe = intel_crtc->pipe;
1208 intel_hdmi_prepare(encoder);
1210 /* Program Tx lane resets to default */
1211 mutex_lock(&dev_priv->dpio_lock);
1212 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1213 DPIO_PCS_TX_LANE2_RESET |
1214 DPIO_PCS_TX_LANE1_RESET);
1215 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1216 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1217 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1218 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1219 DPIO_PCS_CLK_SOFT_RESET);
1221 /* Fix up inter-pair skew failure */
1222 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1223 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1224 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1226 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1227 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1228 mutex_unlock(&dev_priv->dpio_lock);
1231 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1233 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1234 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1235 struct intel_crtc *intel_crtc =
1236 to_intel_crtc(encoder->base.crtc);
1237 enum dpio_channel port = vlv_dport_to_channel(dport);
1238 int pipe = intel_crtc->pipe;
1240 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1241 mutex_lock(&dev_priv->dpio_lock);
1242 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1243 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1244 mutex_unlock(&dev_priv->dpio_lock);
1247 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1249 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1250 struct drm_device *dev = encoder->base.dev;
1251 struct drm_i915_private *dev_priv = dev->dev_private;
1252 struct intel_crtc *intel_crtc =
1253 to_intel_crtc(encoder->base.crtc);
1254 enum dpio_channel ch = vlv_dport_to_channel(dport);
1255 enum i915_pipe pipe = intel_crtc->pipe;
1258 mutex_lock(&dev_priv->dpio_lock);
1260 /* Propagate soft reset to data lane reset */
1261 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1262 val |= CHV_PCS_REQ_SOFTRESET_EN;
1263 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1265 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1266 val |= CHV_PCS_REQ_SOFTRESET_EN;
1267 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1269 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1270 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1271 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1273 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1274 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1275 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1277 mutex_unlock(&dev_priv->dpio_lock);
1280 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1282 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1283 struct drm_device *dev = encoder->base.dev;
1284 struct drm_i915_private *dev_priv = dev->dev_private;
1285 struct intel_crtc *intel_crtc =
1286 to_intel_crtc(encoder->base.crtc);
1287 enum dpio_channel ch = vlv_dport_to_channel(dport);
1288 int pipe = intel_crtc->pipe;
1292 mutex_lock(&dev_priv->dpio_lock);
1294 /* Deassert soft data lane reset*/
1295 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1296 val |= CHV_PCS_REQ_SOFTRESET_EN;
1297 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1299 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1300 val |= CHV_PCS_REQ_SOFTRESET_EN;
1301 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1303 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1304 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1305 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1307 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1308 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1309 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1311 /* Program Tx latency optimal setting */
1312 for (i = 0; i < 4; i++) {
1313 /* Set the latency optimal bit */
1314 data = (i == 1) ? 0x0 : 0x6;
1315 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1316 data << DPIO_FRC_LATENCY_SHFIT);
1318 /* Set the upar bit */
1319 data = (i == 1) ? 0x0 : 0x1;
1320 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1321 data << DPIO_UPAR_SHIFT);
1324 /* Data lane stagger programming */
1325 /* FIXME: Fix up value only after power analysis */
1327 /* Clear calc init */
1328 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1329 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1330 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1332 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1333 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1334 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1336 /* FIXME: Program the support xxx V-dB */
1338 for (i = 0; i < 4; i++) {
1339 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1340 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1341 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1342 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1345 for (i = 0; i < 4; i++) {
1346 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1347 val &= ~DPIO_SWING_MARGIN_MASK;
1348 val |= 102 << DPIO_SWING_MARGIN_SHIFT;
1349 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1352 /* Disable unique transition scale */
1353 for (i = 0; i < 4; i++) {
1354 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1355 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1356 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1359 /* Additional steps for 1200mV-0dB */
1361 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1363 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1365 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1366 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1368 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1369 vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1370 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1372 /* Start swing calculation */
1373 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1374 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1375 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1377 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1378 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1379 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1382 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1383 val |= DPIO_LRC_BYPASS;
1384 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1386 mutex_unlock(&dev_priv->dpio_lock);
1388 intel_enable_hdmi(encoder);
1390 vlv_wait_port_ready(dev_priv, dport);
1393 static void intel_hdmi_destroy(struct drm_connector *connector)
1395 drm_connector_cleanup(connector);
1399 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1400 .dpms = intel_connector_dpms,
1401 .detect = intel_hdmi_detect,
1402 .fill_modes = drm_helper_probe_single_connector_modes,
1403 .set_property = intel_hdmi_set_property,
1404 .destroy = intel_hdmi_destroy,
1407 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1408 .get_modes = intel_hdmi_get_modes,
1409 .mode_valid = intel_hdmi_mode_valid,
1410 .best_encoder = intel_best_encoder,
1413 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1414 .destroy = intel_encoder_destroy,
1418 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1420 intel_attach_force_audio_property(connector);
1421 intel_attach_broadcast_rgb_property(connector);
1422 intel_hdmi->color_range_auto = true;
1425 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1426 struct intel_connector *intel_connector)
1428 struct drm_connector *connector = &intel_connector->base;
1429 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1430 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1431 struct drm_device *dev = intel_encoder->base.dev;
1432 struct drm_i915_private *dev_priv = dev->dev_private;
1433 enum port port = intel_dig_port->port;
1435 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1436 DRM_MODE_CONNECTOR_HDMIA);
1437 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1439 connector->interlace_allowed = 1;
1440 connector->doublescan_allowed = 0;
1441 connector->stereo_allowed = 1;
1445 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1446 intel_encoder->hpd_pin = HPD_PORT_B;
1449 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1450 intel_encoder->hpd_pin = HPD_PORT_C;
1453 if (IS_CHERRYVIEW(dev))
1454 intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV;
1456 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1457 intel_encoder->hpd_pin = HPD_PORT_D;
1460 intel_encoder->hpd_pin = HPD_PORT_A;
1461 /* Internal port only for eDP. */
1466 if (IS_VALLEYVIEW(dev)) {
1467 intel_hdmi->write_infoframe = vlv_write_infoframe;
1468 intel_hdmi->set_infoframes = vlv_set_infoframes;
1469 } else if (!HAS_PCH_SPLIT(dev)) {
1470 intel_hdmi->write_infoframe = g4x_write_infoframe;
1471 intel_hdmi->set_infoframes = g4x_set_infoframes;
1472 } else if (HAS_DDI(dev)) {
1473 intel_hdmi->write_infoframe = hsw_write_infoframe;
1474 intel_hdmi->set_infoframes = hsw_set_infoframes;
1475 } else if (HAS_PCH_IBX(dev)) {
1476 intel_hdmi->write_infoframe = ibx_write_infoframe;
1477 intel_hdmi->set_infoframes = ibx_set_infoframes;
1479 intel_hdmi->write_infoframe = cpt_write_infoframe;
1480 intel_hdmi->set_infoframes = cpt_set_infoframes;
1484 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1486 intel_connector->get_hw_state = intel_connector_get_hw_state;
1487 intel_connector->unregister = intel_connector_unregister;
1489 intel_hdmi_add_properties(intel_hdmi, connector);
1491 intel_connector_attach_encoder(intel_connector, intel_encoder);
1492 drm_connector_register(connector);
1494 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1495 * 0xd. Failure to do so will result in spurious interrupts being
1496 * generated on the port when a cable is not attached.
1498 if (IS_G4X(dev) && !IS_GM45(dev)) {
1499 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1500 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1504 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1506 struct intel_digital_port *intel_dig_port;
1507 struct intel_encoder *intel_encoder;
1508 struct intel_connector *intel_connector;
1510 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1511 if (!intel_dig_port)
1514 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1515 if (!intel_connector) {
1516 kfree(intel_dig_port);
1520 intel_encoder = &intel_dig_port->base;
1522 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1523 DRM_MODE_ENCODER_TMDS);
1525 intel_encoder->compute_config = intel_hdmi_compute_config;
1526 intel_encoder->disable = intel_disable_hdmi;
1527 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1528 intel_encoder->get_config = intel_hdmi_get_config;
1529 if (IS_CHERRYVIEW(dev)) {
1530 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1531 intel_encoder->enable = vlv_enable_hdmi;
1532 intel_encoder->post_disable = chv_hdmi_post_disable;
1533 } else if (IS_VALLEYVIEW(dev)) {
1534 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1535 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1536 intel_encoder->enable = vlv_enable_hdmi;
1537 intel_encoder->post_disable = vlv_hdmi_post_disable;
1539 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1540 intel_encoder->enable = intel_enable_hdmi;
1543 intel_encoder->type = INTEL_OUTPUT_HDMI;
1544 if (IS_CHERRYVIEW(dev)) {
1546 intel_encoder->crtc_mask = 1 << 2;
1548 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1550 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1552 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1554 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1555 * to work on real hardware. And since g4x can send infoframes to
1556 * only one port anyway, nothing is lost by allowing it.
1559 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1561 intel_dig_port->port = port;
1562 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1563 intel_dig_port->dp.output_reg = 0;
1565 intel_hdmi_init_connector(intel_dig_port, intel_connector);