2 * Copyright (c) 1991 The Regents of the University of California.
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33 * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $
34 * $DragonFly: src/sys/platform/pc32/isa/intr_machdep.h,v 1.12 2005/02/01 22:41:25 dillon Exp $
37 #ifndef _I386_ISA_INTR_MACHDEP_H_
38 #define _I386_ISA_INTR_MACHDEP_H_
40 #ifndef _SYS_INTERRUPT_H_
42 #include <sys/interrupt.h>
47 * Low level interrupt code.
52 #if defined(SMP) || defined(APIC_IO)
54 * XXX FIXME: rethink location for all IPI vectors.
58 APIC TPR priority vector levels:
60 0xff (255) +-------------+
61 | | 15 (IPIs: Xspuriousint)
62 0xf0 (240) +-------------+
64 0xe0 (224) +-------------+
66 0xd0 (208) +-------------+
68 0xc0 (192) +-------------+
70 0xb0 (176) +-------------+
71 | | 10 (IPIs: Xcpustop)
72 0xa0 (160) +-------------+
73 | | 9 (IPIs: Xinvltlb)
74 0x90 (144) +-------------+
75 | | 8 (linux/BSD syscall, IGNORE FAST HW INTS)
76 0x80 (128) +-------------+
77 | | 7 (FAST_INTR 16-23)
78 0x70 (112) +-------------+
79 | | 6 (FAST_INTR 0-15)
80 0x60 (96) +-------------+
81 | | 5 (IGNORE HW INTS)
82 0x50 (80) +-------------+
84 0x40 (64) +------+------+
85 | | | 3 (upper APIC hardware INTs: PCI)
86 0x30 (48) +------+------+
87 | | 2 (start of hardware INTs: ISA)
88 0x20 (32) +-------------+
89 | | 1 (exceptions, traps, etc.)
90 0x10 (16) +-------------+
91 | | 0 (exceptions, traps, etc.)
92 0x00 (0) +-------------+
95 /* IDT vector base for regular (aka. slow) and fast interrupts */
96 #define TPR_SLOW_INTS 0x20
97 #define TPR_FAST_INTS 0x60
99 /* blocking values for local APIC Task Priority Register */
100 #define TPR_BLOCK_HWI 0x4f /* hardware INTs */
101 #define TPR_IGNORE_HWI 0x5f /* ignore INTs */
102 #define TPR_BLOCK_FHWI 0x7f /* hardware FAST INTs */
103 #define TPR_IGNORE_FHWI 0x8f /* ignore FAST INTs */
104 #define TPR_IPI_ONLY 0x8f /* ignore FAST INTs */
105 #define TPR_BLOCK_XINVLTLB 0x9f /* */
106 #define TPR_BLOCK_XCPUSTOP 0xaf /* */
107 #define TPR_BLOCK_ALL 0xff /* all INTs */
111 /* put a 'fake' HWI in top of APIC prio 0x3x, 32 + 31 = 63 = 0x3f */
112 #define XTEST1_OFFSET (ICU_OFFSET + 31)
113 #endif /** TEST_TEST1 */
116 #define XINVLTLB_OFFSET (ICU_OFFSET + 112)
118 /* unused/open (was inter-cpu clock handling) */
119 #define XUNUSED113_OFFSET (ICU_OFFSET + 113)
121 /* inter-CPU rendezvous */
122 #define XRENDEZVOUS_OFFSET (ICU_OFFSET + 114)
124 /* IPIQ rendezvous */
125 #define XIPIQ_OFFSET (ICU_OFFSET + 115)
127 /* IPI to signal CPUs to stop and wait for another CPU to restart them */
128 #define XCPUSTOP_OFFSET (ICU_OFFSET + 128)
131 * Note: this vector MUST be xxxx1111, 32 + 223 = 255 = 0xff:
133 #define XSPURIOUSINT_OFFSET (ICU_OFFSET + 223)
135 #endif /* SMP || APIC_IO */
140 * Type of the first (asm) part of an interrupt handler.
142 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
143 typedef void unpendhand_t(void);
145 #define IDTVEC(name) __CONCAT(X,name)
147 extern u_long *intr_countp[]; /* pointers into intrcnt[] */
148 extern inthand2_t *intr_handler[]; /* C entry points for FAST ints */
149 extern u_int intr_mask[]; /* sets of intrs masked during handling of 1 */
150 extern void *intr_unit[]; /* cookies to pass to intr handlers */
153 IDTVEC(fastintr0), IDTVEC(fastintr1),
154 IDTVEC(fastintr2), IDTVEC(fastintr3),
155 IDTVEC(fastintr4), IDTVEC(fastintr5),
156 IDTVEC(fastintr6), IDTVEC(fastintr7),
157 IDTVEC(fastintr8), IDTVEC(fastintr9),
158 IDTVEC(fastintr10), IDTVEC(fastintr11),
159 IDTVEC(fastintr12), IDTVEC(fastintr13),
160 IDTVEC(fastintr14), IDTVEC(fastintr15);
162 IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3),
163 IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7),
164 IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11),
165 IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15);
168 IDTVEC(fastunpend0), IDTVEC(fastunpend1),
169 IDTVEC(fastunpend2), IDTVEC(fastunpend3),
170 IDTVEC(fastunpend4), IDTVEC(fastunpend5),
171 IDTVEC(fastunpend6), IDTVEC(fastunpend7),
172 IDTVEC(fastunpend8), IDTVEC(fastunpend9),
173 IDTVEC(fastunpend10), IDTVEC(fastunpend11),
174 IDTVEC(fastunpend12), IDTVEC(fastunpend13),
175 IDTVEC(fastunpend14), IDTVEC(fastunpend15);
179 IDTVEC(fastintr16), IDTVEC(fastintr17),
180 IDTVEC(fastintr18), IDTVEC(fastintr19),
181 IDTVEC(fastintr20), IDTVEC(fastintr21),
182 IDTVEC(fastintr22), IDTVEC(fastintr23);
184 IDTVEC(intr16), IDTVEC(intr17), IDTVEC(intr18), IDTVEC(intr19),
185 IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23);
187 IDTVEC(fastunpend16), IDTVEC(fastunpend17),
188 IDTVEC(fastunpend18), IDTVEC(fastunpend19),
189 IDTVEC(fastunpend20), IDTVEC(fastunpend21),
190 IDTVEC(fastunpend22), IDTVEC(fastunpend23);
195 Xinvltlb, /* TLB shootdowns */
196 Xcpuast, /* Additional software trap on other cpu */
197 Xforward_irq, /* Forward irq to cpu holding ISR lock */
198 Xcpustop, /* CPU stops & waits for another CPU to restart it */
199 Xspuriousint, /* handle APIC "spurious INTs" */
200 Xipiq, /* handle lwkt_send_ipiq() requests */
201 Xrendezvous; /* handle CPU rendezvous */
205 Xtest1; /* 'fake' HWI at top of APIC prio 0x3x, 32+31 = 0x3f */
206 #endif /** TEST_TEST1 */
209 void call_fast_unpend(int irq);
210 void isa_defaultirq (void);
211 int isa_nmi (int cd);
212 int icu_setup (int intr, inthand2_t *func, void *arg,
213 u_int *maskptr, int flags);
214 int icu_unset (int intr, inthand2_t *handler);
215 void icu_reinit (void);
216 int update_intr_masks (void);
219 * WARNING: These are internal functions and not to be used by device drivers!
220 * They are subject to change without notice.
222 struct intrec *inthand_add(const char *name, int irq, inthand2_t handler,
223 void *arg, intrmask_t *maskptr, int flags);
225 int inthand_remove(struct intrec *idesc);
226 void forward_fastint_remote(void *arg);
232 #endif /* !_I386_ISA_INTR_MACHDEP_H_ */