2 * Copyright (c) KATO Takenori, 1997, 1998.
4 * All rights reserved. Unpublished rights reserved under the copyright
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $FreeBSD: src/sys/i386/i386/initcpu.c,v 1.19.2.9 2003/04/05 13:47:19 dwmalone Exp $
30 * $DragonFly: src/sys/platform/pc32/i386/initcpu.c,v 1.10 2006/12/23 00:27:03 swildner Exp $
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
44 void initializecpu(void);
45 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
46 void enable_K5_wt_alloc(void);
47 void enable_K6_wt_alloc(void);
48 void enable_K6_2_wt_alloc(void);
52 static void init_5x86(void);
53 static void init_bluelightning(void);
54 static void init_486dlc(void);
55 static void init_cy486dx(void);
56 #ifdef CPU_I486_ON_386
57 static void init_i486_on_386(void);
59 static void init_6x86(void);
63 static void init_6x86MX(void);
64 static void init_ppro(void);
65 static void init_mendocino(void);
68 static int hw_instruction_sse;
69 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
70 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
72 u_int via_feature_rng = 0; /* VIA RNG features */
73 u_int via_feature_xcrypt = 0; /* VIA ACE features */
75 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
76 &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU");
77 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
78 &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU");
80 #ifndef CPU_DISABLE_SSE
81 u_int cpu_fxsr; /* SSE enabled */
89 init_bluelightning(void)
93 eflags = read_eflags();
96 load_cr0(rcr0() | CR0_CD | CR0_NW);
99 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
100 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
102 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
104 /* Enables 13MB and 0-640KB cache. */
105 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
106 #ifdef CPU_BLUELIGHTNING_3X
107 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
109 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
112 /* Enable caching in CR0. */
113 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
115 write_eflags(eflags);
119 * Cyrix 486SLC/DLC/SR/DR series
127 eflags = read_eflags();
131 ccr0 = read_cyrix_reg(CCR0);
132 #ifndef CYRIX_CACHE_WORKS
133 ccr0 |= CCR0_NC1 | CCR0_BARB;
134 write_cyrix_reg(CCR0, ccr0);
138 #ifndef CYRIX_CACHE_REALLY_WORKS
139 ccr0 |= CCR0_NC1 | CCR0_BARB;
143 #ifdef CPU_DIRECT_MAPPED_CACHE
144 ccr0 |= CCR0_CO; /* Direct mapped mode. */
146 write_cyrix_reg(CCR0, ccr0);
148 /* Clear non-cacheable region. */
149 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
150 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
151 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
152 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
154 write_cyrix_reg(0, 0); /* dummy write */
156 /* Enable caching in CR0. */
157 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
159 #endif /* !CYRIX_CACHE_WORKS */
160 write_eflags(eflags);
165 * Cyrix 486S/DX series
173 eflags = read_eflags();
177 ccr2 = read_cyrix_reg(CCR2);
179 ccr2 |= CCR2_SUSP_HLT;
182 write_cyrix_reg(CCR2, ccr2);
183 write_eflags(eflags);
194 u_char ccr2, ccr3, ccr4, pcr0;
196 eflags = read_eflags();
199 load_cr0(rcr0() | CR0_CD | CR0_NW);
202 read_cyrix_reg(CCR3); /* dummy */
204 /* Initialize CCR2. */
205 ccr2 = read_cyrix_reg(CCR2);
208 ccr2 |= CCR2_SUSP_HLT;
210 ccr2 &= ~CCR2_SUSP_HLT;
213 write_cyrix_reg(CCR2, ccr2);
215 /* Initialize CCR4. */
216 ccr3 = read_cyrix_reg(CCR3);
217 write_cyrix_reg(CCR3, CCR3_MAPEN0);
219 ccr4 = read_cyrix_reg(CCR4);
222 #ifdef CPU_FASTER_5X86_FPU
223 ccr4 |= CCR4_FASTFPE;
225 ccr4 &= ~CCR4_FASTFPE;
227 ccr4 &= ~CCR4_IOMASK;
228 /********************************************************************
229 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
230 * should be 0 for errata fix.
231 ********************************************************************/
233 ccr4 |= CPU_IORT & CCR4_IOMASK;
235 write_cyrix_reg(CCR4, ccr4);
237 /* Initialize PCR0. */
238 /****************************************************************
239 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
240 * BTB_EN might make your system unstable.
241 ****************************************************************/
242 pcr0 = read_cyrix_reg(PCR0);
259 /****************************************************************
260 * WARNING: if you use a memory mapped I/O device, don't use
261 * DISABLE_5X86_LSSER option, which may reorder memory mapped
263 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
264 ****************************************************************/
265 #ifdef CPU_DISABLE_5X86_LSSER
270 write_cyrix_reg(PCR0, pcr0);
273 write_cyrix_reg(CCR3, ccr3);
275 read_cyrix_reg(0x80); /* dummy */
277 /* Unlock NW bit in CR0. */
278 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
279 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
280 /* Lock NW bit in CR0. */
281 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
283 write_eflags(eflags);
286 #ifdef CPU_I486_ON_386
288 * There are i486 based upgrade products for i386 machines.
289 * In this case, BIOS doesn't enables CPU cache.
292 init_i486_on_386(void)
296 eflags = read_eflags();
299 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
301 write_eflags(eflags);
308 * XXX - What should I do here? Please let me know.
316 eflags = read_eflags();
319 load_cr0(rcr0() | CR0_CD | CR0_NW);
322 /* Initialize CCR0. */
323 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
325 /* Initialize CCR1. */
326 #ifdef CPU_CYRIX_NO_LOCK
327 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
329 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
332 /* Initialize CCR2. */
334 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
336 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
339 ccr3 = read_cyrix_reg(CCR3);
340 write_cyrix_reg(CCR3, CCR3_MAPEN0);
342 /* Initialize CCR4. */
343 ccr4 = read_cyrix_reg(CCR4);
345 ccr4 &= ~CCR4_IOMASK;
347 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
349 write_cyrix_reg(CCR4, ccr4 | 7);
352 /* Initialize CCR5. */
354 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
358 write_cyrix_reg(CCR3, ccr3);
360 /* Unlock NW bit in CR0. */
361 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
364 * Earlier revision of the 6x86 CPU could crash the system if
365 * L1 cache is in write-back mode.
367 if ((cyrix_did & 0xff00) > 0x1600)
368 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
370 /* Revision 2.6 and lower. */
371 #ifdef CYRIX_CACHE_REALLY_WORKS
372 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
374 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
378 /* Lock NW bit in CR0. */
379 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
381 write_eflags(eflags);
383 #endif /* I486_CPU */
387 * Cyrix 6x86MX (code-named M2)
389 * XXX - What should I do here? Please let me know.
397 eflags = read_eflags();
400 load_cr0(rcr0() | CR0_CD | CR0_NW);
403 /* Initialize CCR0. */
404 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
406 /* Initialize CCR1. */
407 #ifdef CPU_CYRIX_NO_LOCK
408 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
410 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
413 /* Initialize CCR2. */
415 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
417 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
420 ccr3 = read_cyrix_reg(CCR3);
421 write_cyrix_reg(CCR3, CCR3_MAPEN0);
423 /* Initialize CCR4. */
424 ccr4 = read_cyrix_reg(CCR4);
425 ccr4 &= ~CCR4_IOMASK;
427 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
429 write_cyrix_reg(CCR4, ccr4 | 7);
432 /* Initialize CCR5. */
434 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
438 write_cyrix_reg(CCR3, ccr3);
440 /* Unlock NW bit in CR0. */
441 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
443 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
445 /* Lock NW bit in CR0. */
446 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
448 write_eflags(eflags);
458 * Local APIC should be diabled in UP kernel.
460 apicbase = rdmsr(0x1b);
461 apicbase &= ~0x800LL;
462 wrmsr(0x1b, apicbase);
467 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
473 #ifdef CPU_PPRO2CELERON
475 u_int64_t bbl_cr_ctl3;
477 eflags = read_eflags();
480 load_cr0(rcr0() | CR0_CD | CR0_NW);
483 bbl_cr_ctl3 = rdmsr(0x11e);
485 /* If the L2 cache is configured, do nothing. */
486 if (!(bbl_cr_ctl3 & 1)) {
487 bbl_cr_ctl3 = 0x134052bLL;
489 /* Set L2 Cache Latency (Default: 5). */
490 #ifdef CPU_CELERON_L2_LATENCY
491 #if CPU_L2_LATENCY > 15
492 #error invalid CPU_L2_LATENCY.
494 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
496 bbl_cr_ctl3 |= 5 << 1;
498 wrmsr(0x11e, bbl_cr_ctl3);
501 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
502 write_eflags(eflags);
503 #endif /* CPU_PPRO2CELERON */
507 * Initialize special VIA C3/C7 features
515 do_cpuid(0xc0000000, regs);
517 if (val >= 0xc0000001) {
518 do_cpuid(0xc0000001, regs);
523 /* Enable RNG if present and disabled */
524 if (val & VIA_CPUID_HAS_RNG) {
525 if (!(val & VIA_CPUID_DO_RNG)) {
526 msreg = rdmsr(0x110B);
528 wrmsr(0x110B, msreg);
530 via_feature_rng = VIA_HAS_RNG;
532 /* Enable AES engine if present and disabled */
533 if (val & VIA_CPUID_HAS_ACE) {
534 if (!(val & VIA_CPUID_DO_ACE)) {
535 msreg = rdmsr(0x1107);
536 msreg |= (0x01 << 28);
537 wrmsr(0x1107, msreg);
539 via_feature_xcrypt |= VIA_HAS_AES;
541 /* Enable ACE2 engine if present and disabled */
542 if (val & VIA_CPUID_HAS_ACE2) {
543 if (!(val & VIA_CPUID_DO_ACE2)) {
544 msreg = rdmsr(0x1107);
545 msreg |= (0x01 << 28);
546 wrmsr(0x1107, msreg);
548 via_feature_xcrypt |= VIA_HAS_AESCTR;
550 /* Enable SHA engine if present and disabled */
551 if (val & VIA_CPUID_HAS_PHE) {
552 if (!(val & VIA_CPUID_DO_PHE)) {
553 msreg = rdmsr(0x1107);
554 msreg |= (0x01 << 28/**/);
555 wrmsr(0x1107, msreg);
557 via_feature_xcrypt |= VIA_HAS_SHA;
559 /* Enable MM engine if present and disabled */
560 if (val & VIA_CPUID_HAS_PMM) {
561 if (!(val & VIA_CPUID_DO_PMM)) {
562 msreg = rdmsr(0x1107);
563 msreg |= (0x01 << 28/**/);
564 wrmsr(0x1107, msreg);
566 via_feature_xcrypt |= VIA_HAS_MM;
570 #endif /* I686_CPU */
573 * Initialize CR4 (Control register 4) to enable SSE instructions.
578 #ifndef CPU_DISABLE_SSE
579 if ((cpu_feature & CPUID_SSE) && (cpu_feature & CPUID_FXSR)) {
580 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
581 cpu_fxsr = hw_instruction_sse = 1;
590 #if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
592 * Sometimes the BIOS doesn't enable SSE instructions.
593 * According to AMD document 20734, the mobile
594 * Duron, the (mobile) Athlon 4 and the Athlon MP
595 * support SSE. These correspond to cpu_id 0x66X
598 if ((cpu_feature & CPUID_XMM) == 0 &&
599 ((cpu_id & ~0xf) == 0x660 ||
600 (cpu_id & ~0xf) == 0x670 ||
601 (cpu_id & ~0xf) == 0x680)) {
603 wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
605 cpu_feature = regs[3];
608 #if defined(I686_CPU) && defined(CPU_AMD64X2_INTR_SPAM)
610 * Set the LINTEN bit in the HyperTransport Transaction
613 * This will cause EXTINT and NMI interrupts routed over the
614 * hypertransport bus to be fed into the LAPIC LINT0/LINT1. If
615 * the bit isn't set, the interrupts will go to the general cpu
616 * INTR/NMI pins. On a dual-core cpu the interrupt winds up
617 * going to BOTH cpus. The first cpu that does the interrupt ack
618 * cycle will get the correct interrupt. The second cpu that does
619 * it will get a spurious interrupt vector (typically IRQ 7).
621 if ((cpu_id & 0xff0) == 0xf30) {
624 (1 << 31) | /* enable */
625 (0 << 16) | /* bus */
626 (24 << 11) | /* dev (cpu + 24) */
627 (0 << 8) | /* func */
631 if ((tcr & 0x00010000) == 0) {
632 outl(0xcfc, tcr|0x00010000);
633 additional_cpu_info("AMD: Rerouting HyperTransport "
634 "EXTINT/NMI to APIC");
647 init_bluelightning();
658 #ifdef CPU_I486_ON_386
666 #endif /* I486_CPU */
672 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
673 switch (cpu_id & 0xff0) {
681 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
683 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
684 switch (cpu_id & 0xff0) {
686 if ((cpu_id & 0xf) < 3)
706 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
708 * Enable write allocate feature of AMD processors.
709 * Following two functions require the Maxmem variable being set.
712 enable_K5_wt_alloc(void)
717 * Write allocate is supported only on models 1, 2, and 3, with
718 * a stepping of 4 or greater.
720 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
722 msr = rdmsr(0x83); /* HWCR */
723 wrmsr(0x83, msr & !(0x10));
726 * We have to tell the chip where the top of memory is,
727 * since video cards could have frame bufferes there,
728 * memory-mapped I/O could be there, etc.
734 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
737 * There is no way to know wheter 15-16M hole exists or not.
738 * Therefore, we disable write allocate for this range.
740 wrmsr(0x86, 0x0ff00f0);
741 msr |= AMD_WT_ALLOC_PRE;
745 wrmsr(0x83, msr|0x10); /* enable write allocate */
752 enable_K6_wt_alloc(void)
758 eflags = read_eflags();
762 #ifdef CPU_DISABLE_CACHE
764 * Certain K6-2 box becomes unstable when write allocation is
768 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
769 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
770 * All other bits in TR12 have no effect on the processer's operation.
771 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
774 wrmsr(0x0000000e, (u_int64_t)0x0008);
776 /* Don't assume that memory size is aligned with 4M. */
778 size = ((Maxmem >> 8) + 3) >> 2;
782 /* Limit is 508M bytes. */
785 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
787 #if defined(NO_MEMORY_HOLE)
788 if (whcr & (0x7fLL << 1))
792 * There is no way to know wheter 15-16M hole exists or not.
793 * Therefore, we disable write allocate for this range.
797 wrmsr(0x0c0000082, whcr);
799 write_eflags(eflags);
803 enable_K6_2_wt_alloc(void)
809 eflags = read_eflags();
813 #ifdef CPU_DISABLE_CACHE
815 * Certain K6-2 box becomes unstable when write allocation is
819 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
820 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
821 * All other bits in TR12 have no effect on the processer's operation.
822 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
825 wrmsr(0x0000000e, (u_int64_t)0x0008);
827 /* Don't assume that memory size is aligned with 4M. */
829 size = ((Maxmem >> 8) + 3) >> 2;
833 /* Limit is 4092M bytes. */
836 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
838 #if defined(NO_MEMORY_HOLE)
839 if (whcr & (0x3ffLL << 22))
843 * There is no way to know wheter 15-16M hole exists or not.
844 * Therefore, we disable write allocate for this range.
846 whcr &= ~(1LL << 16);
848 wrmsr(0x0c0000082, whcr);
850 write_eflags(eflags);
852 #endif /* I585_CPU && CPU_WT_ALLOC */
858 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
862 u_char ccr1, ccr2, ccr3;
863 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
866 if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
867 eflags = read_eflags();
871 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
872 ccr0 = read_cyrix_reg(CCR0);
874 ccr1 = read_cyrix_reg(CCR1);
875 ccr2 = read_cyrix_reg(CCR2);
876 ccr3 = read_cyrix_reg(CCR3);
877 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
878 write_cyrix_reg(CCR3, CCR3_MAPEN0);
879 ccr4 = read_cyrix_reg(CCR4);
880 if ((cpu == CPU_M1) || (cpu == CPU_M2))
881 ccr5 = read_cyrix_reg(CCR5);
883 pcr0 = read_cyrix_reg(PCR0);
884 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
886 write_eflags(eflags);
888 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
889 kprintf("CCR0=%x, ", (u_int)ccr0);
891 kprintf("CCR1=%x, CCR2=%x, CCR3=%x",
892 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
893 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
894 kprintf(", CCR4=%x, ", (u_int)ccr4);
896 kprintf("PCR0=%x\n", pcr0);
898 kprintf("CCR5=%x\n", ccr5);
901 kprintf("CR0=%x\n", cr0);